if_wm.c revision 1.84
1 /* $NetBSD: if_wm.c,v 1.84 2004/11/22 19:28:37 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.84 2004/11/22 19:28:37 thorpej Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA ETHER_MAX_LEN_JUMBO 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make serveral things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 280 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 281 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 282 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 283 284 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 285 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 286 287 struct evcnt sc_ev_tu; /* Tx underrun */ 288 289 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 290 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 291 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 292 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 293 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 294 #endif /* WM_EVENT_COUNTERS */ 295 296 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 297 298 int sc_txfree; /* number of free Tx descriptors */ 299 int sc_txnext; /* next ready Tx descriptor */ 300 301 int sc_txsfree; /* number of free Tx jobs */ 302 int sc_txsnext; /* next free Tx job */ 303 int sc_txsdirty; /* dirty Tx jobs */ 304 305 /* These 5 variables are used only on the 82547. */ 306 int sc_txfifo_size; /* Tx FIFO size */ 307 int sc_txfifo_head; /* current head of FIFO */ 308 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 309 int sc_txfifo_stall; /* Tx FIFO is stalled */ 310 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 311 312 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 313 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 314 315 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 316 317 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 318 int sc_rxdiscard; 319 int sc_rxlen; 320 struct mbuf *sc_rxhead; 321 struct mbuf *sc_rxtail; 322 struct mbuf **sc_rxtailp; 323 324 uint32_t sc_ctrl; /* prototype CTRL register */ 325 #if 0 326 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 327 #endif 328 uint32_t sc_icr; /* prototype interrupt bits */ 329 uint32_t sc_tctl; /* prototype TCTL register */ 330 uint32_t sc_rctl; /* prototype RCTL register */ 331 uint32_t sc_txcw; /* prototype TXCW register */ 332 uint32_t sc_tipg; /* prototype TIPG register */ 333 uint32_t sc_fcrtl; /* prototype FCRTL register */ 334 uint32_t sc_pba; /* prototype PBA register */ 335 336 int sc_tbi_linkup; /* TBI link status */ 337 int sc_tbi_anstate; /* autonegotiation state */ 338 339 int sc_mchash_type; /* multicast filter offset */ 340 341 #if NRND > 0 342 rndsource_element_t rnd_source; /* random source */ 343 #endif 344 }; 345 346 #define WM_RXCHAIN_RESET(sc) \ 347 do { \ 348 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 349 *(sc)->sc_rxtailp = NULL; \ 350 (sc)->sc_rxlen = 0; \ 351 } while (/*CONSTCOND*/0) 352 353 #define WM_RXCHAIN_LINK(sc, m) \ 354 do { \ 355 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 356 (sc)->sc_rxtailp = &(m)->m_next; \ 357 } while (/*CONSTCOND*/0) 358 359 /* sc_flags */ 360 #define WM_F_HAS_MII 0x01 /* has MII */ 361 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 362 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 363 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 364 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 365 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 366 #define WM_F_CSA 0x80 /* bus is CSA */ 367 368 #ifdef WM_EVENT_COUNTERS 369 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 370 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 371 #else 372 #define WM_EVCNT_INCR(ev) /* nothing */ 373 #define WM_EVCNT_ADD(ev, val) /* nothing */ 374 #endif 375 376 #define CSR_READ(sc, reg) \ 377 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 378 #define CSR_WRITE(sc, reg, val) \ 379 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 380 #define CSR_WRITE_FLUSH(sc) \ 381 (void) CSR_READ((sc), WMREG_STATUS) 382 383 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 384 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 385 386 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 387 #define WM_CDTXADDR_HI(sc, x) \ 388 (sizeof(bus_addr_t) == 8 ? \ 389 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 390 391 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 392 #define WM_CDRXADDR_HI(sc, x) \ 393 (sizeof(bus_addr_t) == 8 ? \ 394 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 395 396 #define WM_CDTXSYNC(sc, x, n, ops) \ 397 do { \ 398 int __x, __n; \ 399 \ 400 __x = (x); \ 401 __n = (n); \ 402 \ 403 /* If it will wrap around, sync to the end of the ring. */ \ 404 if ((__x + __n) > WM_NTXDESC(sc)) { \ 405 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 406 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 407 (WM_NTXDESC(sc) - __x), (ops)); \ 408 __n -= (WM_NTXDESC(sc) - __x); \ 409 __x = 0; \ 410 } \ 411 \ 412 /* Now sync whatever is left. */ \ 413 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 414 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 415 } while (/*CONSTCOND*/0) 416 417 #define WM_CDRXSYNC(sc, x, ops) \ 418 do { \ 419 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 420 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 421 } while (/*CONSTCOND*/0) 422 423 #define WM_INIT_RXDESC(sc, x) \ 424 do { \ 425 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 426 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 427 struct mbuf *__m = __rxs->rxs_mbuf; \ 428 \ 429 /* \ 430 * Note: We scoot the packet forward 2 bytes in the buffer \ 431 * so that the payload after the Ethernet header is aligned \ 432 * to a 4-byte boundary. \ 433 * \ 434 * XXX BRAINDAMAGE ALERT! \ 435 * The stupid chip uses the same size for every buffer, which \ 436 * is set in the Receive Control register. We are using the 2K \ 437 * size option, but what we REALLY want is (2K - 2)! For this \ 438 * reason, we can't "scoot" packets longer than the standard \ 439 * Ethernet MTU. On strict-alignment platforms, if the total \ 440 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 441 * the upper layer copy the headers. \ 442 */ \ 443 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 444 \ 445 wm_set_dma_addr(&__rxd->wrx_addr, \ 446 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 447 __rxd->wrx_len = 0; \ 448 __rxd->wrx_cksum = 0; \ 449 __rxd->wrx_status = 0; \ 450 __rxd->wrx_errors = 0; \ 451 __rxd->wrx_special = 0; \ 452 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 453 \ 454 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 455 } while (/*CONSTCOND*/0) 456 457 static void wm_start(struct ifnet *); 458 static void wm_watchdog(struct ifnet *); 459 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 460 static int wm_init(struct ifnet *); 461 static void wm_stop(struct ifnet *, int); 462 463 static void wm_shutdown(void *); 464 465 static void wm_reset(struct wm_softc *); 466 static void wm_rxdrain(struct wm_softc *); 467 static int wm_add_rxbuf(struct wm_softc *, int); 468 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 469 static void wm_tick(void *); 470 471 static void wm_set_filter(struct wm_softc *); 472 473 static int wm_intr(void *); 474 static void wm_txintr(struct wm_softc *); 475 static void wm_rxintr(struct wm_softc *); 476 static void wm_linkintr(struct wm_softc *, uint32_t); 477 478 static void wm_tbi_mediainit(struct wm_softc *); 479 static int wm_tbi_mediachange(struct ifnet *); 480 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 481 482 static void wm_tbi_set_linkled(struct wm_softc *); 483 static void wm_tbi_check_link(struct wm_softc *); 484 485 static void wm_gmii_reset(struct wm_softc *); 486 487 static int wm_gmii_i82543_readreg(struct device *, int, int); 488 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 489 490 static int wm_gmii_i82544_readreg(struct device *, int, int); 491 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 492 493 static void wm_gmii_statchg(struct device *); 494 495 static void wm_gmii_mediainit(struct wm_softc *); 496 static int wm_gmii_mediachange(struct ifnet *); 497 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 498 499 static int wm_match(struct device *, struct cfdata *, void *); 500 static void wm_attach(struct device *, struct device *, void *); 501 502 CFATTACH_DECL(wm, sizeof(struct wm_softc), 503 wm_match, wm_attach, NULL, NULL); 504 505 static void wm_82547_txfifo_stall(void *); 506 507 /* 508 * Devices supported by this driver. 509 */ 510 static const struct wm_product { 511 pci_vendor_id_t wmp_vendor; 512 pci_product_id_t wmp_product; 513 const char *wmp_name; 514 wm_chip_type wmp_type; 515 int wmp_flags; 516 #define WMP_F_1000X 0x01 517 #define WMP_F_1000T 0x02 518 } wm_products[] = { 519 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 520 "Intel i82542 1000BASE-X Ethernet", 521 WM_T_82542_2_1, WMP_F_1000X }, 522 523 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 524 "Intel i82543GC 1000BASE-X Ethernet", 525 WM_T_82543, WMP_F_1000X }, 526 527 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 528 "Intel i82543GC 1000BASE-T Ethernet", 529 WM_T_82543, WMP_F_1000T }, 530 531 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 532 "Intel i82544EI 1000BASE-T Ethernet", 533 WM_T_82544, WMP_F_1000T }, 534 535 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 536 "Intel i82544EI 1000BASE-X Ethernet", 537 WM_T_82544, WMP_F_1000X }, 538 539 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 540 "Intel i82544GC 1000BASE-T Ethernet", 541 WM_T_82544, WMP_F_1000T }, 542 543 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 544 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 545 WM_T_82544, WMP_F_1000T }, 546 547 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 548 "Intel i82540EM 1000BASE-T Ethernet", 549 WM_T_82540, WMP_F_1000T }, 550 551 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 552 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 553 WM_T_82540, WMP_F_1000T }, 554 555 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 556 "Intel i82540EP 1000BASE-T Ethernet", 557 WM_T_82540, WMP_F_1000T }, 558 559 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 560 "Intel i82540EP 1000BASE-T Ethernet", 561 WM_T_82540, WMP_F_1000T }, 562 563 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 564 "Intel i82540EP 1000BASE-T Ethernet", 565 WM_T_82540, WMP_F_1000T }, 566 567 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 568 "Intel i82545EM 1000BASE-T Ethernet", 569 WM_T_82545, WMP_F_1000T }, 570 571 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 572 "Intel i82545GM 1000BASE-T Ethernet", 573 WM_T_82545_3, WMP_F_1000T }, 574 575 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 576 "Intel i82545GM 1000BASE-X Ethernet", 577 WM_T_82545_3, WMP_F_1000X }, 578 #if 0 579 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 580 "Intel i82545GM Gigabit Ethernet (SERDES)", 581 WM_T_82545_3, WMP_F_SERDES }, 582 #endif 583 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 584 "Intel i82546EB 1000BASE-T Ethernet", 585 WM_T_82546, WMP_F_1000T }, 586 587 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 588 "Intel i82546EB 1000BASE-T Ethernet", 589 WM_T_82546, WMP_F_1000T }, 590 591 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 592 "Intel i82545EM 1000BASE-X Ethernet", 593 WM_T_82545, WMP_F_1000X }, 594 595 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 596 "Intel i82546EB 1000BASE-X Ethernet", 597 WM_T_82546, WMP_F_1000X }, 598 599 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 600 "Intel i82546GB 1000BASE-T Ethernet", 601 WM_T_82546_3, WMP_F_1000T }, 602 603 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 604 "Intel i82546GB 1000BASE-X Ethernet", 605 WM_T_82546_3, WMP_F_1000X }, 606 #if 0 607 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 608 "Intel i82546GB Gigabit Ethernet (SERDES)", 609 WM_T_82546_3, WMP_F_SERDES }, 610 #endif 611 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 612 "Intel i82541EI 1000BASE-T Ethernet", 613 WM_T_82541, WMP_F_1000T }, 614 615 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 616 "Intel i82541EI Mobile 1000BASE-T Ethernet", 617 WM_T_82541, WMP_F_1000T }, 618 619 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 620 "Intel i82541ER 1000BASE-T Ethernet", 621 WM_T_82541_2, WMP_F_1000T }, 622 623 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 624 "Intel i82541GI 1000BASE-T Ethernet", 625 WM_T_82541_2, WMP_F_1000T }, 626 627 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 628 "Intel i82541GI Mobile 1000BASE-T Ethernet", 629 WM_T_82541_2, WMP_F_1000T }, 630 631 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 632 "Intel i82547EI 1000BASE-T Ethernet", 633 WM_T_82547, WMP_F_1000T }, 634 635 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 636 "Intel i82547GI 1000BASE-T Ethernet", 637 WM_T_82547_2, WMP_F_1000T }, 638 { 0, 0, 639 NULL, 640 0, 0 }, 641 }; 642 643 #ifdef WM_EVENT_COUNTERS 644 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 645 #endif /* WM_EVENT_COUNTERS */ 646 647 #if 0 /* Not currently used */ 648 static __inline uint32_t 649 wm_io_read(struct wm_softc *sc, int reg) 650 { 651 652 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 653 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 654 } 655 #endif 656 657 static __inline void 658 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 659 { 660 661 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 662 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 663 } 664 665 static __inline void 666 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 667 { 668 wa->wa_low = htole32(v & 0xffffffffU); 669 if (sizeof(bus_addr_t) == 8) 670 wa->wa_high = htole32((uint64_t) v >> 32); 671 else 672 wa->wa_high = 0; 673 } 674 675 static const struct wm_product * 676 wm_lookup(const struct pci_attach_args *pa) 677 { 678 const struct wm_product *wmp; 679 680 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 681 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 682 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 683 return (wmp); 684 } 685 return (NULL); 686 } 687 688 static int 689 wm_match(struct device *parent, struct cfdata *cf, void *aux) 690 { 691 struct pci_attach_args *pa = aux; 692 693 if (wm_lookup(pa) != NULL) 694 return (1); 695 696 return (0); 697 } 698 699 static void 700 wm_attach(struct device *parent, struct device *self, void *aux) 701 { 702 struct wm_softc *sc = (void *) self; 703 struct pci_attach_args *pa = aux; 704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 705 pci_chipset_tag_t pc = pa->pa_pc; 706 pci_intr_handle_t ih; 707 size_t cdata_size; 708 const char *intrstr = NULL; 709 const char *eetype; 710 bus_space_tag_t memt; 711 bus_space_handle_t memh; 712 bus_dma_segment_t seg; 713 int memh_valid; 714 int i, rseg, error; 715 const struct wm_product *wmp; 716 uint8_t enaddr[ETHER_ADDR_LEN]; 717 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 718 pcireg_t preg, memtype; 719 uint32_t reg; 720 int pmreg; 721 722 callout_init(&sc->sc_tick_ch); 723 724 wmp = wm_lookup(pa); 725 if (wmp == NULL) { 726 printf("\n"); 727 panic("wm_attach: impossible"); 728 } 729 730 if (pci_dma64_available(pa)) 731 sc->sc_dmat = pa->pa_dmat64; 732 else 733 sc->sc_dmat = pa->pa_dmat; 734 735 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 736 aprint_naive(": Ethernet controller\n"); 737 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 738 739 sc->sc_type = wmp->wmp_type; 740 if (sc->sc_type < WM_T_82543) { 741 if (preg < 2) { 742 aprint_error("%s: i82542 must be at least rev. 2\n", 743 sc->sc_dev.dv_xname); 744 return; 745 } 746 if (preg < 3) 747 sc->sc_type = WM_T_82542_2_0; 748 } 749 750 /* 751 * Map the device. All devices support memory-mapped acccess, 752 * and it is really required for normal operation. 753 */ 754 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 755 switch (memtype) { 756 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 757 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 758 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 759 memtype, 0, &memt, &memh, NULL, NULL) == 0); 760 break; 761 default: 762 memh_valid = 0; 763 } 764 765 if (memh_valid) { 766 sc->sc_st = memt; 767 sc->sc_sh = memh; 768 } else { 769 aprint_error("%s: unable to map device registers\n", 770 sc->sc_dev.dv_xname); 771 return; 772 } 773 774 /* 775 * In addition, i82544 and later support I/O mapped indirect 776 * register access. It is not desirable (nor supported in 777 * this driver) to use it for normal operation, though it is 778 * required to work around bugs in some chip versions. 779 */ 780 if (sc->sc_type >= WM_T_82544) { 781 /* First we have to find the I/O BAR. */ 782 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 783 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 784 PCI_MAPREG_TYPE_IO) 785 break; 786 } 787 if (i == PCI_MAPREG_END) 788 aprint_error("%s: WARNING: unable to find I/O BAR\n", 789 sc->sc_dev.dv_xname); 790 else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 791 0, &sc->sc_iot, &sc->sc_ioh, 792 NULL, NULL) == 0) 793 sc->sc_flags |= WM_F_IOH_VALID; 794 else 795 aprint_error("%s: WARNING: unable to map I/O space\n", 796 sc->sc_dev.dv_xname); 797 } 798 799 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 800 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 801 preg |= PCI_COMMAND_MASTER_ENABLE; 802 if (sc->sc_type < WM_T_82542_2_1) 803 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 804 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 805 806 /* Get it out of power save mode, if needed. */ 807 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 808 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 809 PCI_PMCSR_STATE_MASK; 810 if (preg == PCI_PMCSR_STATE_D3) { 811 /* 812 * The card has lost all configuration data in 813 * this state, so punt. 814 */ 815 aprint_error("%s: unable to wake from power state D3\n", 816 sc->sc_dev.dv_xname); 817 return; 818 } 819 if (preg != PCI_PMCSR_STATE_D0) { 820 aprint_normal("%s: waking up from power state D%d\n", 821 sc->sc_dev.dv_xname, preg); 822 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 823 PCI_PMCSR_STATE_D0); 824 } 825 } 826 827 /* 828 * Map and establish our interrupt. 829 */ 830 if (pci_intr_map(pa, &ih)) { 831 aprint_error("%s: unable to map interrupt\n", 832 sc->sc_dev.dv_xname); 833 return; 834 } 835 intrstr = pci_intr_string(pc, ih); 836 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 837 if (sc->sc_ih == NULL) { 838 aprint_error("%s: unable to establish interrupt", 839 sc->sc_dev.dv_xname); 840 if (intrstr != NULL) 841 aprint_normal(" at %s", intrstr); 842 aprint_normal("\n"); 843 return; 844 } 845 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 846 847 /* 848 * Determine a few things about the bus we're connected to. 849 */ 850 if (sc->sc_type < WM_T_82543) { 851 /* We don't really know the bus characteristics here. */ 852 sc->sc_bus_speed = 33; 853 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 854 /* 855 * CSA (Communication Streaming Architecture) is about as fast 856 * a 32-bit 66MHz PCI Bus. 857 */ 858 sc->sc_flags |= WM_F_CSA; 859 sc->sc_bus_speed = 66; 860 aprint_verbose("%s: Communication Streaming Architecture\n", 861 sc->sc_dev.dv_xname); 862 if (sc->sc_type == WM_T_82547) { 863 callout_init(&sc->sc_txfifo_ch); 864 callout_setfunc(&sc->sc_txfifo_ch, 865 wm_82547_txfifo_stall, sc); 866 aprint_verbose("%s: using 82547 Tx FIFO stall " 867 "work-around\n", sc->sc_dev.dv_xname); 868 } 869 } else { 870 reg = CSR_READ(sc, WMREG_STATUS); 871 if (reg & STATUS_BUS64) 872 sc->sc_flags |= WM_F_BUS64; 873 if (sc->sc_type >= WM_T_82544 && 874 (reg & STATUS_PCIX_MODE) != 0) { 875 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 876 877 sc->sc_flags |= WM_F_PCIX; 878 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 879 PCI_CAP_PCIX, 880 &sc->sc_pcix_offset, NULL) == 0) 881 aprint_error("%s: unable to find PCIX " 882 "capability\n", sc->sc_dev.dv_xname); 883 else if (sc->sc_type != WM_T_82545_3 && 884 sc->sc_type != WM_T_82546_3) { 885 /* 886 * Work around a problem caused by the BIOS 887 * setting the max memory read byte count 888 * incorrectly. 889 */ 890 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 891 sc->sc_pcix_offset + PCI_PCIX_CMD); 892 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 893 sc->sc_pcix_offset + PCI_PCIX_STATUS); 894 895 bytecnt = 896 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 897 PCI_PCIX_CMD_BYTECNT_SHIFT; 898 maxb = 899 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 900 PCI_PCIX_STATUS_MAXB_SHIFT; 901 if (bytecnt > maxb) { 902 aprint_verbose("%s: resetting PCI-X " 903 "MMRBC: %d -> %d\n", 904 sc->sc_dev.dv_xname, 905 512 << bytecnt, 512 << maxb); 906 pcix_cmd = (pcix_cmd & 907 ~PCI_PCIX_CMD_BYTECNT_MASK) | 908 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 909 pci_conf_write(pa->pa_pc, pa->pa_tag, 910 sc->sc_pcix_offset + PCI_PCIX_CMD, 911 pcix_cmd); 912 } 913 } 914 } 915 /* 916 * The quad port adapter is special; it has a PCIX-PCIX 917 * bridge on the board, and can run the secondary bus at 918 * a higher speed. 919 */ 920 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 921 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 922 : 66; 923 } else if (sc->sc_flags & WM_F_PCIX) { 924 switch (reg & STATUS_PCIXSPD_MASK) { 925 case STATUS_PCIXSPD_50_66: 926 sc->sc_bus_speed = 66; 927 break; 928 case STATUS_PCIXSPD_66_100: 929 sc->sc_bus_speed = 100; 930 break; 931 case STATUS_PCIXSPD_100_133: 932 sc->sc_bus_speed = 133; 933 break; 934 default: 935 aprint_error( 936 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 937 sc->sc_dev.dv_xname, 938 reg & STATUS_PCIXSPD_MASK); 939 sc->sc_bus_speed = 66; 940 } 941 } else 942 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 943 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 944 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 945 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 946 } 947 948 /* 949 * Allocate the control data structures, and create and load the 950 * DMA map for it. 951 * 952 * NOTE: All Tx descriptors must be in the same 4G segment of 953 * memory. So must Rx descriptors. We simplify by allocating 954 * both sets within the same 4G segment. 955 */ 956 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 957 WM_NTXDESC_82542 : WM_NTXDESC_82544; 958 cdata_size = sc->sc_type < WM_T_82544 ? 959 sizeof(struct wm_control_data_82542) : 960 sizeof(struct wm_control_data_82544); 961 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 962 (bus_size_t) 0x100000000ULL, 963 &seg, 1, &rseg, 0)) != 0) { 964 aprint_error( 965 "%s: unable to allocate control data, error = %d\n", 966 sc->sc_dev.dv_xname, error); 967 goto fail_0; 968 } 969 970 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 971 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 972 aprint_error("%s: unable to map control data, error = %d\n", 973 sc->sc_dev.dv_xname, error); 974 goto fail_1; 975 } 976 977 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 978 0, 0, &sc->sc_cddmamap)) != 0) { 979 aprint_error("%s: unable to create control data DMA map, " 980 "error = %d\n", sc->sc_dev.dv_xname, error); 981 goto fail_2; 982 } 983 984 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 985 sc->sc_control_data, cdata_size, NULL, 986 0)) != 0) { 987 aprint_error( 988 "%s: unable to load control data DMA map, error = %d\n", 989 sc->sc_dev.dv_xname, error); 990 goto fail_3; 991 } 992 993 994 /* 995 * Create the transmit buffer DMA maps. 996 */ 997 WM_TXQUEUELEN(sc) = 998 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 999 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1000 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1001 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1002 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1003 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1004 aprint_error("%s: unable to create Tx DMA map %d, " 1005 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1006 goto fail_4; 1007 } 1008 } 1009 1010 /* 1011 * Create the receive buffer DMA maps. 1012 */ 1013 for (i = 0; i < WM_NRXDESC; i++) { 1014 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1015 MCLBYTES, 0, 0, 1016 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1017 aprint_error("%s: unable to create Rx DMA map %d, " 1018 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1019 goto fail_5; 1020 } 1021 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1022 } 1023 1024 /* 1025 * Reset the chip to a known state. 1026 */ 1027 wm_reset(sc); 1028 1029 /* 1030 * Get some information about the EEPROM. 1031 */ 1032 if (sc->sc_type >= WM_T_82540) 1033 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1034 if (sc->sc_type <= WM_T_82544) 1035 sc->sc_ee_addrbits = 6; 1036 else if (sc->sc_type <= WM_T_82546_3) { 1037 reg = CSR_READ(sc, WMREG_EECD); 1038 if (reg & EECD_EE_SIZE) 1039 sc->sc_ee_addrbits = 8; 1040 else 1041 sc->sc_ee_addrbits = 6; 1042 } else if (sc->sc_type <= WM_T_82547_2) { 1043 reg = CSR_READ(sc, WMREG_EECD); 1044 if (reg & EECD_EE_TYPE) { 1045 sc->sc_flags |= WM_F_EEPROM_SPI; 1046 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1047 } else 1048 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1049 } else { 1050 /* Assume everything else is SPI. */ 1051 reg = CSR_READ(sc, WMREG_EECD); 1052 sc->sc_flags |= WM_F_EEPROM_SPI; 1053 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1054 } 1055 if (sc->sc_flags & WM_F_EEPROM_SPI) 1056 eetype = "SPI"; 1057 else 1058 eetype = "MicroWire"; 1059 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1060 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1061 sc->sc_ee_addrbits, eetype); 1062 1063 /* 1064 * Read the Ethernet address from the EEPROM. 1065 */ 1066 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1067 sizeof(myea) / sizeof(myea[0]), myea)) { 1068 aprint_error("%s: unable to read Ethernet address\n", 1069 sc->sc_dev.dv_xname); 1070 return; 1071 } 1072 enaddr[0] = myea[0] & 0xff; 1073 enaddr[1] = myea[0] >> 8; 1074 enaddr[2] = myea[1] & 0xff; 1075 enaddr[3] = myea[1] >> 8; 1076 enaddr[4] = myea[2] & 0xff; 1077 enaddr[5] = myea[2] >> 8; 1078 1079 /* 1080 * Toggle the LSB of the MAC address on the second port 1081 * of the i82546. 1082 */ 1083 if (sc->sc_type == WM_T_82546) { 1084 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1085 enaddr[5] ^= 1; 1086 } 1087 1088 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1089 ether_sprintf(enaddr)); 1090 1091 /* 1092 * Read the config info from the EEPROM, and set up various 1093 * bits in the control registers based on their contents. 1094 */ 1095 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1096 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1097 sc->sc_dev.dv_xname); 1098 return; 1099 } 1100 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1101 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1102 sc->sc_dev.dv_xname); 1103 return; 1104 } 1105 if (sc->sc_type >= WM_T_82544) { 1106 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1107 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1108 sc->sc_dev.dv_xname); 1109 return; 1110 } 1111 } 1112 1113 if (cfg1 & EEPROM_CFG1_ILOS) 1114 sc->sc_ctrl |= CTRL_ILOS; 1115 if (sc->sc_type >= WM_T_82544) { 1116 sc->sc_ctrl |= 1117 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1118 CTRL_SWDPIO_SHIFT; 1119 sc->sc_ctrl |= 1120 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1121 CTRL_SWDPINS_SHIFT; 1122 } else { 1123 sc->sc_ctrl |= 1124 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1125 CTRL_SWDPIO_SHIFT; 1126 } 1127 1128 #if 0 1129 if (sc->sc_type >= WM_T_82544) { 1130 if (cfg1 & EEPROM_CFG1_IPS0) 1131 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1132 if (cfg1 & EEPROM_CFG1_IPS1) 1133 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1134 sc->sc_ctrl_ext |= 1135 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1136 CTRL_EXT_SWDPIO_SHIFT; 1137 sc->sc_ctrl_ext |= 1138 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1139 CTRL_EXT_SWDPINS_SHIFT; 1140 } else { 1141 sc->sc_ctrl_ext |= 1142 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1143 CTRL_EXT_SWDPIO_SHIFT; 1144 } 1145 #endif 1146 1147 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1148 #if 0 1149 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1150 #endif 1151 1152 /* 1153 * Set up some register offsets that are different between 1154 * the i82542 and the i82543 and later chips. 1155 */ 1156 if (sc->sc_type < WM_T_82543) { 1157 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1158 sc->sc_tdt_reg = WMREG_OLD_TDT; 1159 } else { 1160 sc->sc_rdt_reg = WMREG_RDT; 1161 sc->sc_tdt_reg = WMREG_TDT; 1162 } 1163 1164 /* 1165 * Determine if we're TBI or GMII mode, and initialize the 1166 * media structures accordingly. 1167 */ 1168 if (sc->sc_type < WM_T_82543 || 1169 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1170 if (wmp->wmp_flags & WMP_F_1000T) 1171 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1172 "product!\n", sc->sc_dev.dv_xname); 1173 wm_tbi_mediainit(sc); 1174 } else { 1175 if (wmp->wmp_flags & WMP_F_1000X) 1176 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1177 "product!\n", sc->sc_dev.dv_xname); 1178 wm_gmii_mediainit(sc); 1179 } 1180 1181 ifp = &sc->sc_ethercom.ec_if; 1182 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1183 ifp->if_softc = sc; 1184 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1185 ifp->if_ioctl = wm_ioctl; 1186 ifp->if_start = wm_start; 1187 ifp->if_watchdog = wm_watchdog; 1188 ifp->if_init = wm_init; 1189 ifp->if_stop = wm_stop; 1190 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1191 IFQ_SET_READY(&ifp->if_snd); 1192 1193 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1194 1195 /* 1196 * If we're a i82543 or greater, we can support VLANs. 1197 */ 1198 if (sc->sc_type >= WM_T_82543) 1199 sc->sc_ethercom.ec_capabilities |= 1200 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1201 1202 /* 1203 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1204 * on i82543 and later. 1205 */ 1206 if (sc->sc_type >= WM_T_82543) 1207 ifp->if_capabilities |= 1208 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1209 1210 /* 1211 * Attach the interface. 1212 */ 1213 if_attach(ifp); 1214 ether_ifattach(ifp, enaddr); 1215 #if NRND > 0 1216 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1217 RND_TYPE_NET, 0); 1218 #endif 1219 1220 #ifdef WM_EVENT_COUNTERS 1221 /* Attach event counters. */ 1222 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1223 NULL, sc->sc_dev.dv_xname, "txsstall"); 1224 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1225 NULL, sc->sc_dev.dv_xname, "txdstall"); 1226 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1227 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1228 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1229 NULL, sc->sc_dev.dv_xname, "txdw"); 1230 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1231 NULL, sc->sc_dev.dv_xname, "txqe"); 1232 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1233 NULL, sc->sc_dev.dv_xname, "rxintr"); 1234 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1235 NULL, sc->sc_dev.dv_xname, "linkintr"); 1236 1237 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1238 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1239 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1240 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1241 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1242 NULL, sc->sc_dev.dv_xname, "txipsum"); 1243 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1244 NULL, sc->sc_dev.dv_xname, "txtusum"); 1245 1246 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 1247 NULL, sc->sc_dev.dv_xname, "txctx init"); 1248 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 1249 NULL, sc->sc_dev.dv_xname, "txctx hit"); 1250 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 1251 NULL, sc->sc_dev.dv_xname, "txctx miss"); 1252 1253 for (i = 0; i < WM_NTXSEGS; i++) { 1254 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1255 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1256 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1257 } 1258 1259 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1260 NULL, sc->sc_dev.dv_xname, "txdrop"); 1261 1262 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1263 NULL, sc->sc_dev.dv_xname, "tu"); 1264 1265 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1266 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1267 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1268 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1269 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1270 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1271 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1272 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1273 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1274 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1275 #endif /* WM_EVENT_COUNTERS */ 1276 1277 /* 1278 * Make sure the interface is shutdown during reboot. 1279 */ 1280 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1281 if (sc->sc_sdhook == NULL) 1282 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1283 sc->sc_dev.dv_xname); 1284 return; 1285 1286 /* 1287 * Free any resources we've allocated during the failed attach 1288 * attempt. Do this in reverse order and fall through. 1289 */ 1290 fail_5: 1291 for (i = 0; i < WM_NRXDESC; i++) { 1292 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1293 bus_dmamap_destroy(sc->sc_dmat, 1294 sc->sc_rxsoft[i].rxs_dmamap); 1295 } 1296 fail_4: 1297 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1298 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1299 bus_dmamap_destroy(sc->sc_dmat, 1300 sc->sc_txsoft[i].txs_dmamap); 1301 } 1302 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1303 fail_3: 1304 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1305 fail_2: 1306 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1307 cdata_size); 1308 fail_1: 1309 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1310 fail_0: 1311 return; 1312 } 1313 1314 /* 1315 * wm_shutdown: 1316 * 1317 * Make sure the interface is stopped at reboot time. 1318 */ 1319 static void 1320 wm_shutdown(void *arg) 1321 { 1322 struct wm_softc *sc = arg; 1323 1324 wm_stop(&sc->sc_ethercom.ec_if, 1); 1325 } 1326 1327 /* 1328 * wm_tx_cksum: 1329 * 1330 * Set up TCP/IP checksumming parameters for the 1331 * specified packet. 1332 */ 1333 static int 1334 wm_tx_cksum(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1335 uint8_t *fieldsp) 1336 { 1337 struct mbuf *m0 = txs->txs_mbuf; 1338 struct livengood_tcpip_ctxdesc *t; 1339 uint32_t ipcs, tucs; 1340 struct ip *ip; 1341 struct ether_header *eh; 1342 int offset, iphl; 1343 uint8_t fields = 0; 1344 1345 /* 1346 * XXX It would be nice if the mbuf pkthdr had offset 1347 * fields for the protocol headers. 1348 */ 1349 1350 eh = mtod(m0, struct ether_header *); 1351 switch (htons(eh->ether_type)) { 1352 case ETHERTYPE_IP: 1353 iphl = sizeof(struct ip); 1354 offset = ETHER_HDR_LEN; 1355 break; 1356 1357 case ETHERTYPE_VLAN: 1358 iphl = sizeof(struct ip); 1359 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1360 break; 1361 1362 default: 1363 /* 1364 * Don't support this protocol or encapsulation. 1365 */ 1366 *fieldsp = 0; 1367 *cmdp = 0; 1368 return (0); 1369 } 1370 1371 if (m0->m_len < (offset + iphl)) { 1372 if ((txs->txs_mbuf = m_pullup(m0, offset + iphl)) == NULL) { 1373 log(LOG_ERR, "%s: wm_tx_cksum: mbuf allocation failed, " 1374 "packet dropped\n", sc->sc_dev.dv_xname); 1375 return (ENOMEM); 1376 } 1377 m0 = txs->txs_mbuf; 1378 } 1379 1380 ip = (struct ip *) (mtod(m0, caddr_t) + offset); 1381 iphl = ip->ip_hl << 2; 1382 1383 /* 1384 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1385 * offload feature, if we load the context descriptor, we 1386 * MUST provide valid values for IPCSS and TUCSS fields. 1387 */ 1388 1389 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1390 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1391 fields |= WTX_IXSM; 1392 ipcs = WTX_TCPIP_IPCSS(offset) | 1393 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1394 WTX_TCPIP_IPCSE(offset + iphl - 1); 1395 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1396 /* Use the cached value. */ 1397 ipcs = sc->sc_txctx_ipcs; 1398 } else { 1399 /* Just initialize it to the likely value anyway. */ 1400 ipcs = WTX_TCPIP_IPCSS(offset) | 1401 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1402 WTX_TCPIP_IPCSE(offset + iphl - 1); 1403 } 1404 1405 offset += iphl; 1406 1407 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1408 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1409 fields |= WTX_TXSM; 1410 tucs = WTX_TCPIP_TUCSS(offset) | 1411 WTX_TCPIP_TUCSO(offset + m0->m_pkthdr.csum_data) | 1412 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1413 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1414 /* Use the cached value. */ 1415 tucs = sc->sc_txctx_tucs; 1416 } else { 1417 /* Just initialize it to a valid TCP context. */ 1418 tucs = WTX_TCPIP_TUCSS(offset) | 1419 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1420 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1421 } 1422 1423 if (sc->sc_txctx_ipcs == ipcs && 1424 sc->sc_txctx_tucs == tucs) { 1425 /* Cached context is fine. */ 1426 WM_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1427 } else { 1428 /* Fill in the context descriptor. */ 1429 #ifdef WM_EVENT_COUNTERS 1430 if (sc->sc_txctx_ipcs == 0xffffffff && 1431 sc->sc_txctx_tucs == 0xffffffff) 1432 WM_EVCNT_INCR(&sc->sc_ev_txctx_init); 1433 else 1434 WM_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1435 #endif 1436 t = (struct livengood_tcpip_ctxdesc *) 1437 &sc->sc_txdescs[sc->sc_txnext]; 1438 t->tcpip_ipcs = htole32(ipcs); 1439 t->tcpip_tucs = htole32(tucs); 1440 t->tcpip_cmdlen = htole32(WTX_CMD_DEXT | WTX_DTYP_C); 1441 t->tcpip_seg = 0; 1442 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1443 1444 sc->sc_txctx_ipcs = ipcs; 1445 sc->sc_txctx_tucs = tucs; 1446 1447 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1448 txs->txs_ndesc++; 1449 } 1450 1451 *cmdp = WTX_CMD_DEXT | WTX_DTYP_D; 1452 *fieldsp = fields; 1453 1454 return (0); 1455 } 1456 1457 static void 1458 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1459 { 1460 struct mbuf *m; 1461 int i; 1462 1463 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1464 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1465 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1466 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1467 m->m_data, m->m_len, m->m_flags); 1468 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1469 i, i == 1 ? "" : "s"); 1470 } 1471 1472 /* 1473 * wm_82547_txfifo_stall: 1474 * 1475 * Callout used to wait for the 82547 Tx FIFO to drain, 1476 * reset the FIFO pointers, and restart packet transmission. 1477 */ 1478 static void 1479 wm_82547_txfifo_stall(void *arg) 1480 { 1481 struct wm_softc *sc = arg; 1482 int s; 1483 1484 s = splnet(); 1485 1486 if (sc->sc_txfifo_stall) { 1487 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1488 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1489 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1490 /* 1491 * Packets have drained. Stop transmitter, reset 1492 * FIFO pointers, restart transmitter, and kick 1493 * the packet queue. 1494 */ 1495 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1496 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1497 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1498 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1499 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1500 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1501 CSR_WRITE(sc, WMREG_TCTL, tctl); 1502 CSR_WRITE_FLUSH(sc); 1503 1504 sc->sc_txfifo_head = 0; 1505 sc->sc_txfifo_stall = 0; 1506 wm_start(&sc->sc_ethercom.ec_if); 1507 } else { 1508 /* 1509 * Still waiting for packets to drain; try again in 1510 * another tick. 1511 */ 1512 callout_schedule(&sc->sc_txfifo_ch, 1); 1513 } 1514 } 1515 1516 splx(s); 1517 } 1518 1519 /* 1520 * wm_82547_txfifo_bugchk: 1521 * 1522 * Check for bug condition in the 82547 Tx FIFO. We need to 1523 * prevent enqueueing a packet that would wrap around the end 1524 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1525 * 1526 * We do this by checking the amount of space before the end 1527 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1528 * the Tx FIFO, wait for all remaining packets to drain, reset 1529 * the internal FIFO pointers to the beginning, and restart 1530 * transmission on the interface. 1531 */ 1532 #define WM_FIFO_HDR 0x10 1533 #define WM_82547_PAD_LEN 0x3e0 1534 static int 1535 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1536 { 1537 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1538 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1539 1540 /* Just return if already stalled. */ 1541 if (sc->sc_txfifo_stall) 1542 return (1); 1543 1544 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1545 /* Stall only occurs in half-duplex mode. */ 1546 goto send_packet; 1547 } 1548 1549 if (len >= WM_82547_PAD_LEN + space) { 1550 sc->sc_txfifo_stall = 1; 1551 callout_schedule(&sc->sc_txfifo_ch, 1); 1552 return (1); 1553 } 1554 1555 send_packet: 1556 sc->sc_txfifo_head += len; 1557 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1558 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1559 1560 return (0); 1561 } 1562 1563 /* 1564 * wm_start: [ifnet interface function] 1565 * 1566 * Start packet transmission on the interface. 1567 */ 1568 static void 1569 wm_start(struct ifnet *ifp) 1570 { 1571 struct wm_softc *sc = ifp->if_softc; 1572 struct mbuf *m0; 1573 #if 0 /* XXXJRT */ 1574 struct m_tag *mtag; 1575 #endif 1576 struct wm_txsoft *txs; 1577 bus_dmamap_t dmamap; 1578 int error, nexttx, lasttx = -1, ofree, seg, segs_needed; 1579 bus_addr_t curaddr; 1580 bus_size_t seglen, curlen; 1581 uint32_t cksumcmd; 1582 uint8_t cksumfields; 1583 1584 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1585 return; 1586 1587 /* 1588 * Remember the previous number of free descriptors. 1589 */ 1590 ofree = sc->sc_txfree; 1591 1592 /* 1593 * Loop through the send queue, setting up transmit descriptors 1594 * until we drain the queue, or use up all available transmit 1595 * descriptors. 1596 */ 1597 for (;;) { 1598 /* Grab a packet off the queue. */ 1599 IFQ_POLL(&ifp->if_snd, m0); 1600 if (m0 == NULL) 1601 break; 1602 1603 DPRINTF(WM_DEBUG_TX, 1604 ("%s: TX: have packet to transmit: %p\n", 1605 sc->sc_dev.dv_xname, m0)); 1606 1607 /* Get a work queue entry. */ 1608 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1609 wm_txintr(sc); 1610 if (sc->sc_txsfree == 0) { 1611 DPRINTF(WM_DEBUG_TX, 1612 ("%s: TX: no free job descriptors\n", 1613 sc->sc_dev.dv_xname)); 1614 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1615 break; 1616 } 1617 } 1618 1619 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1620 dmamap = txs->txs_dmamap; 1621 1622 /* 1623 * Load the DMA map. If this fails, the packet either 1624 * didn't fit in the allotted number of segments, or we 1625 * were short on resources. For the too-many-segments 1626 * case, we simply report an error and drop the packet, 1627 * since we can't sanely copy a jumbo packet to a single 1628 * buffer. 1629 */ 1630 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1631 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1632 if (error) { 1633 if (error == EFBIG) { 1634 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1635 log(LOG_ERR, "%s: Tx packet consumes too many " 1636 "DMA segments, dropping...\n", 1637 sc->sc_dev.dv_xname); 1638 IFQ_DEQUEUE(&ifp->if_snd, m0); 1639 wm_dump_mbuf_chain(sc, m0); 1640 m_freem(m0); 1641 continue; 1642 } 1643 /* 1644 * Short on resources, just stop for now. 1645 */ 1646 DPRINTF(WM_DEBUG_TX, 1647 ("%s: TX: dmamap load failed: %d\n", 1648 sc->sc_dev.dv_xname, error)); 1649 break; 1650 } 1651 1652 segs_needed = dmamap->dm_nsegs; 1653 1654 /* 1655 * Ensure we have enough descriptors free to describe 1656 * the packet. Note, we always reserve one descriptor 1657 * at the end of the ring due to the semantics of the 1658 * TDT register, plus one more in the event we need 1659 * to re-load checksum offload context. 1660 */ 1661 if (segs_needed > sc->sc_txfree - 2) { 1662 /* 1663 * Not enough free descriptors to transmit this 1664 * packet. We haven't committed anything yet, 1665 * so just unload the DMA map, put the packet 1666 * pack on the queue, and punt. Notify the upper 1667 * layer that there are no more slots left. 1668 */ 1669 DPRINTF(WM_DEBUG_TX, 1670 ("%s: TX: need %d (%) descriptors, have %d\n", 1671 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1672 sc->sc_txfree - 1)); 1673 ifp->if_flags |= IFF_OACTIVE; 1674 bus_dmamap_unload(sc->sc_dmat, dmamap); 1675 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1676 break; 1677 } 1678 1679 /* 1680 * Check for 82547 Tx FIFO bug. We need to do this 1681 * once we know we can transmit the packet, since we 1682 * do some internal FIFO space accounting here. 1683 */ 1684 if (sc->sc_type == WM_T_82547 && 1685 wm_82547_txfifo_bugchk(sc, m0)) { 1686 DPRINTF(WM_DEBUG_TX, 1687 ("%s: TX: 82547 Tx FIFO bug detected\n", 1688 sc->sc_dev.dv_xname)); 1689 ifp->if_flags |= IFF_OACTIVE; 1690 bus_dmamap_unload(sc->sc_dmat, dmamap); 1691 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1692 break; 1693 } 1694 1695 IFQ_DEQUEUE(&ifp->if_snd, m0); 1696 1697 /* 1698 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1699 */ 1700 1701 DPRINTF(WM_DEBUG_TX, 1702 ("%s: TX: packet has %d (%d) DMA segments\n", 1703 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1704 1705 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1706 1707 /* 1708 * Store a pointer to the packet so that we can free it 1709 * later. 1710 * 1711 * Initially, we consider the number of descriptors the 1712 * packet uses the number of DMA segments. This may be 1713 * incremented by 1 if we do checksum offload (a descriptor 1714 * is used to set the checksum context). 1715 */ 1716 txs->txs_mbuf = m0; 1717 txs->txs_firstdesc = sc->sc_txnext; 1718 txs->txs_ndesc = segs_needed; 1719 1720 /* 1721 * Set up checksum offload parameters for 1722 * this packet. 1723 */ 1724 if (m0->m_pkthdr.csum_flags & 1725 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1726 if (wm_tx_cksum(sc, txs, &cksumcmd, 1727 &cksumfields) != 0) { 1728 /* Error message already displayed. */ 1729 bus_dmamap_unload(sc->sc_dmat, dmamap); 1730 continue; 1731 } 1732 } else { 1733 cksumcmd = 0; 1734 cksumfields = 0; 1735 } 1736 1737 cksumcmd |= WTX_CMD_IDE; 1738 1739 /* Sync the DMA map. */ 1740 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1741 BUS_DMASYNC_PREWRITE); 1742 1743 /* 1744 * Initialize the transmit descriptor. 1745 */ 1746 for (nexttx = sc->sc_txnext, seg = 0; 1747 seg < dmamap->dm_nsegs; seg++) { 1748 for (seglen = dmamap->dm_segs[seg].ds_len, 1749 curaddr = dmamap->dm_segs[seg].ds_addr; 1750 seglen != 0; 1751 curaddr += curlen, seglen -= curlen, 1752 nexttx = WM_NEXTTX(sc, nexttx)) { 1753 curlen = seglen; 1754 1755 wm_set_dma_addr( 1756 &sc->sc_txdescs[nexttx].wtx_addr, 1757 curaddr); 1758 sc->sc_txdescs[nexttx].wtx_cmdlen = 1759 htole32(cksumcmd | curlen); 1760 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1761 0; 1762 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1763 cksumfields; 1764 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1765 lasttx = nexttx; 1766 1767 DPRINTF(WM_DEBUG_TX, 1768 ("%s: TX: desc %d: low 0x%08x, " 1769 "len 0x%04x\n", 1770 sc->sc_dev.dv_xname, nexttx, 1771 curaddr & 0xffffffffU, curlen, curlen)); 1772 } 1773 } 1774 1775 KASSERT(lasttx != -1); 1776 1777 /* 1778 * Set up the command byte on the last descriptor of 1779 * the packet. If we're in the interrupt delay window, 1780 * delay the interrupt. 1781 */ 1782 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1783 htole32(WTX_CMD_EOP | WTX_CMD_IFCS | WTX_CMD_RS); 1784 1785 #if 0 /* XXXJRT */ 1786 /* 1787 * If VLANs are enabled and the packet has a VLAN tag, set 1788 * up the descriptor to encapsulate the packet for us. 1789 * 1790 * This is only valid on the last descriptor of the packet. 1791 */ 1792 if (sc->sc_ethercom.ec_nvlans != 0 && 1793 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1794 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1795 htole32(WTX_CMD_VLE); 1796 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1797 = htole16(*(u_int *)(mtag + 1) & 0xffff); 1798 } 1799 #endif /* XXXJRT */ 1800 1801 txs->txs_lastdesc = lasttx; 1802 1803 DPRINTF(WM_DEBUG_TX, 1804 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1805 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1806 1807 /* Sync the descriptors we're using. */ 1808 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1809 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1810 1811 /* Give the packet to the chip. */ 1812 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1813 1814 DPRINTF(WM_DEBUG_TX, 1815 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1816 1817 DPRINTF(WM_DEBUG_TX, 1818 ("%s: TX: finished transmitting packet, job %d\n", 1819 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1820 1821 /* Advance the tx pointer. */ 1822 sc->sc_txfree -= txs->txs_ndesc; 1823 sc->sc_txnext = nexttx; 1824 1825 sc->sc_txsfree--; 1826 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1827 1828 #if NBPFILTER > 0 1829 /* Pass the packet to any BPF listeners. */ 1830 if (ifp->if_bpf) 1831 bpf_mtap(ifp->if_bpf, m0); 1832 #endif /* NBPFILTER > 0 */ 1833 } 1834 1835 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1836 /* No more slots; notify upper layer. */ 1837 ifp->if_flags |= IFF_OACTIVE; 1838 } 1839 1840 if (sc->sc_txfree != ofree) { 1841 /* Set a watchdog timer in case the chip flakes out. */ 1842 ifp->if_timer = 5; 1843 } 1844 } 1845 1846 /* 1847 * wm_watchdog: [ifnet interface function] 1848 * 1849 * Watchdog timer handler. 1850 */ 1851 static void 1852 wm_watchdog(struct ifnet *ifp) 1853 { 1854 struct wm_softc *sc = ifp->if_softc; 1855 1856 /* 1857 * Since we're using delayed interrupts, sweep up 1858 * before we report an error. 1859 */ 1860 wm_txintr(sc); 1861 1862 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1863 log(LOG_ERR, 1864 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1865 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1866 sc->sc_txnext); 1867 ifp->if_oerrors++; 1868 1869 /* Reset the interface. */ 1870 (void) wm_init(ifp); 1871 } 1872 1873 /* Try to get more packets going. */ 1874 wm_start(ifp); 1875 } 1876 1877 /* 1878 * wm_ioctl: [ifnet interface function] 1879 * 1880 * Handle control requests from the operator. 1881 */ 1882 static int 1883 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1884 { 1885 struct wm_softc *sc = ifp->if_softc; 1886 struct ifreq *ifr = (struct ifreq *) data; 1887 int s, error; 1888 1889 s = splnet(); 1890 1891 switch (cmd) { 1892 case SIOCSIFMEDIA: 1893 case SIOCGIFMEDIA: 1894 /* Flow control requires full-duplex mode. */ 1895 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1896 (ifr->ifr_media & IFM_FDX) == 0) 1897 ifr->ifr_media &= ~IFM_ETH_FMASK; 1898 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1899 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1900 /* We can do both TXPAUSE and RXPAUSE. */ 1901 ifr->ifr_media |= 1902 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1903 } 1904 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1905 } 1906 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1907 break; 1908 default: 1909 error = ether_ioctl(ifp, cmd, data); 1910 if (error == ENETRESET) { 1911 /* 1912 * Multicast list has changed; set the hardware filter 1913 * accordingly. 1914 */ 1915 if (ifp->if_flags & IFF_RUNNING) 1916 wm_set_filter(sc); 1917 error = 0; 1918 } 1919 break; 1920 } 1921 1922 /* Try to get more packets going. */ 1923 wm_start(ifp); 1924 1925 splx(s); 1926 return (error); 1927 } 1928 1929 /* 1930 * wm_intr: 1931 * 1932 * Interrupt service routine. 1933 */ 1934 static int 1935 wm_intr(void *arg) 1936 { 1937 struct wm_softc *sc = arg; 1938 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1939 uint32_t icr; 1940 int wantinit, handled = 0; 1941 1942 for (wantinit = 0; wantinit == 0;) { 1943 icr = CSR_READ(sc, WMREG_ICR); 1944 if ((icr & sc->sc_icr) == 0) 1945 break; 1946 1947 #if 0 /*NRND > 0*/ 1948 if (RND_ENABLED(&sc->rnd_source)) 1949 rnd_add_uint32(&sc->rnd_source, icr); 1950 #endif 1951 1952 handled = 1; 1953 1954 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1955 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1956 DPRINTF(WM_DEBUG_RX, 1957 ("%s: RX: got Rx intr 0x%08x\n", 1958 sc->sc_dev.dv_xname, 1959 icr & (ICR_RXDMT0|ICR_RXT0))); 1960 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 1961 } 1962 #endif 1963 wm_rxintr(sc); 1964 1965 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1966 if (icr & ICR_TXDW) { 1967 DPRINTF(WM_DEBUG_TX, 1968 ("%s: TX: got TXDW interrupt\n", 1969 sc->sc_dev.dv_xname)); 1970 WM_EVCNT_INCR(&sc->sc_ev_txdw); 1971 } 1972 #endif 1973 wm_txintr(sc); 1974 1975 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 1976 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 1977 wm_linkintr(sc, icr); 1978 } 1979 1980 if (icr & ICR_RXO) { 1981 log(LOG_WARNING, "%s: Receive overrun\n", 1982 sc->sc_dev.dv_xname); 1983 wantinit = 1; 1984 } 1985 } 1986 1987 if (handled) { 1988 if (wantinit) 1989 wm_init(ifp); 1990 1991 /* Try to get more packets going. */ 1992 wm_start(ifp); 1993 } 1994 1995 return (handled); 1996 } 1997 1998 /* 1999 * wm_txintr: 2000 * 2001 * Helper; handle transmit interrupts. 2002 */ 2003 static void 2004 wm_txintr(struct wm_softc *sc) 2005 { 2006 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2007 struct wm_txsoft *txs; 2008 uint8_t status; 2009 int i; 2010 2011 ifp->if_flags &= ~IFF_OACTIVE; 2012 2013 /* 2014 * Go through the Tx list and free mbufs for those 2015 * frames which have been transmitted. 2016 */ 2017 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2018 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2019 txs = &sc->sc_txsoft[i]; 2020 2021 DPRINTF(WM_DEBUG_TX, 2022 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2023 2024 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2025 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2026 2027 status = 2028 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2029 if ((status & WTX_ST_DD) == 0) { 2030 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2031 BUS_DMASYNC_PREREAD); 2032 break; 2033 } 2034 2035 DPRINTF(WM_DEBUG_TX, 2036 ("%s: TX: job %d done: descs %d..%d\n", 2037 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2038 txs->txs_lastdesc)); 2039 2040 /* 2041 * XXX We should probably be using the statistics 2042 * XXX registers, but I don't know if they exist 2043 * XXX on chips before the i82544. 2044 */ 2045 2046 #ifdef WM_EVENT_COUNTERS 2047 if (status & WTX_ST_TU) 2048 WM_EVCNT_INCR(&sc->sc_ev_tu); 2049 #endif /* WM_EVENT_COUNTERS */ 2050 2051 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2052 ifp->if_oerrors++; 2053 if (status & WTX_ST_LC) 2054 log(LOG_WARNING, "%s: late collision\n", 2055 sc->sc_dev.dv_xname); 2056 else if (status & WTX_ST_EC) { 2057 ifp->if_collisions += 16; 2058 log(LOG_WARNING, "%s: excessive collisions\n", 2059 sc->sc_dev.dv_xname); 2060 } 2061 } else 2062 ifp->if_opackets++; 2063 2064 sc->sc_txfree += txs->txs_ndesc; 2065 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2066 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2067 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2068 m_freem(txs->txs_mbuf); 2069 txs->txs_mbuf = NULL; 2070 } 2071 2072 /* Update the dirty transmit buffer pointer. */ 2073 sc->sc_txsdirty = i; 2074 DPRINTF(WM_DEBUG_TX, 2075 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2076 2077 /* 2078 * If there are no more pending transmissions, cancel the watchdog 2079 * timer. 2080 */ 2081 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2082 ifp->if_timer = 0; 2083 } 2084 2085 /* 2086 * wm_rxintr: 2087 * 2088 * Helper; handle receive interrupts. 2089 */ 2090 static void 2091 wm_rxintr(struct wm_softc *sc) 2092 { 2093 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2094 struct wm_rxsoft *rxs; 2095 struct mbuf *m; 2096 int i, len; 2097 uint8_t status, errors; 2098 2099 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2100 rxs = &sc->sc_rxsoft[i]; 2101 2102 DPRINTF(WM_DEBUG_RX, 2103 ("%s: RX: checking descriptor %d\n", 2104 sc->sc_dev.dv_xname, i)); 2105 2106 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2107 2108 status = sc->sc_rxdescs[i].wrx_status; 2109 errors = sc->sc_rxdescs[i].wrx_errors; 2110 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2111 2112 if ((status & WRX_ST_DD) == 0) { 2113 /* 2114 * We have processed all of the receive descriptors. 2115 */ 2116 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2117 break; 2118 } 2119 2120 if (__predict_false(sc->sc_rxdiscard)) { 2121 DPRINTF(WM_DEBUG_RX, 2122 ("%s: RX: discarding contents of descriptor %d\n", 2123 sc->sc_dev.dv_xname, i)); 2124 WM_INIT_RXDESC(sc, i); 2125 if (status & WRX_ST_EOP) { 2126 /* Reset our state. */ 2127 DPRINTF(WM_DEBUG_RX, 2128 ("%s: RX: resetting rxdiscard -> 0\n", 2129 sc->sc_dev.dv_xname)); 2130 sc->sc_rxdiscard = 0; 2131 } 2132 continue; 2133 } 2134 2135 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2136 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2137 2138 m = rxs->rxs_mbuf; 2139 2140 /* 2141 * Add a new receive buffer to the ring. 2142 */ 2143 if (wm_add_rxbuf(sc, i) != 0) { 2144 /* 2145 * Failed, throw away what we've done so 2146 * far, and discard the rest of the packet. 2147 */ 2148 ifp->if_ierrors++; 2149 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2150 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2151 WM_INIT_RXDESC(sc, i); 2152 if ((status & WRX_ST_EOP) == 0) 2153 sc->sc_rxdiscard = 1; 2154 if (sc->sc_rxhead != NULL) 2155 m_freem(sc->sc_rxhead); 2156 WM_RXCHAIN_RESET(sc); 2157 DPRINTF(WM_DEBUG_RX, 2158 ("%s: RX: Rx buffer allocation failed, " 2159 "dropping packet%s\n", sc->sc_dev.dv_xname, 2160 sc->sc_rxdiscard ? " (discard)" : "")); 2161 continue; 2162 } 2163 2164 WM_RXCHAIN_LINK(sc, m); 2165 2166 m->m_len = len; 2167 2168 DPRINTF(WM_DEBUG_RX, 2169 ("%s: RX: buffer at %p len %d\n", 2170 sc->sc_dev.dv_xname, m->m_data, len)); 2171 2172 /* 2173 * If this is not the end of the packet, keep 2174 * looking. 2175 */ 2176 if ((status & WRX_ST_EOP) == 0) { 2177 sc->sc_rxlen += len; 2178 DPRINTF(WM_DEBUG_RX, 2179 ("%s: RX: not yet EOP, rxlen -> %d\n", 2180 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2181 continue; 2182 } 2183 2184 /* 2185 * Okay, we have the entire packet now... 2186 */ 2187 *sc->sc_rxtailp = NULL; 2188 m = sc->sc_rxhead; 2189 len += sc->sc_rxlen; 2190 2191 WM_RXCHAIN_RESET(sc); 2192 2193 DPRINTF(WM_DEBUG_RX, 2194 ("%s: RX: have entire packet, len -> %d\n", 2195 sc->sc_dev.dv_xname, len)); 2196 2197 /* 2198 * If an error occurred, update stats and drop the packet. 2199 */ 2200 if (errors & 2201 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2202 ifp->if_ierrors++; 2203 if (errors & WRX_ER_SE) 2204 log(LOG_WARNING, "%s: symbol error\n", 2205 sc->sc_dev.dv_xname); 2206 else if (errors & WRX_ER_SEQ) 2207 log(LOG_WARNING, "%s: receive sequence error\n", 2208 sc->sc_dev.dv_xname); 2209 else if (errors & WRX_ER_CE) 2210 log(LOG_WARNING, "%s: CRC error\n", 2211 sc->sc_dev.dv_xname); 2212 m_freem(m); 2213 continue; 2214 } 2215 2216 /* 2217 * No errors. Receive the packet. 2218 * 2219 * Note, we have configured the chip to include the 2220 * CRC with every packet. 2221 */ 2222 m->m_flags |= M_HASFCS; 2223 m->m_pkthdr.rcvif = ifp; 2224 m->m_pkthdr.len = len; 2225 2226 #if 0 /* XXXJRT */ 2227 /* 2228 * If VLANs are enabled, VLAN packets have been unwrapped 2229 * for us. Associate the tag with the packet. 2230 */ 2231 if (sc->sc_ethercom.ec_nvlans != 0 && 2232 (status & WRX_ST_VP) != 0) { 2233 struct m_tag *vtag; 2234 2235 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2236 M_NOWAIT); 2237 if (vtag == NULL) { 2238 ifp->if_ierrors++; 2239 log(LOG_ERR, 2240 "%s: unable to allocate VLAN tag\n", 2241 sc->sc_dev.dv_xname); 2242 m_freem(m); 2243 continue; 2244 } 2245 2246 *(u_int *)(vtag + 1) = 2247 le16toh(sc->sc_rxdescs[i].wrx_special); 2248 } 2249 #endif /* XXXJRT */ 2250 2251 /* 2252 * Set up checksum info for this packet. 2253 */ 2254 if (status & WRX_ST_IPCS) { 2255 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2256 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2257 if (errors & WRX_ER_IPE) 2258 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2259 } 2260 if (status & WRX_ST_TCPCS) { 2261 /* 2262 * Note: we don't know if this was TCP or UDP, 2263 * so we just set both bits, and expect the 2264 * upper layers to deal. 2265 */ 2266 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2267 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2268 if (errors & WRX_ER_TCPE) 2269 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2270 } 2271 2272 ifp->if_ipackets++; 2273 2274 #if NBPFILTER > 0 2275 /* Pass this up to any BPF listeners. */ 2276 if (ifp->if_bpf) 2277 bpf_mtap(ifp->if_bpf, m); 2278 #endif /* NBPFILTER > 0 */ 2279 2280 /* Pass it on. */ 2281 (*ifp->if_input)(ifp, m); 2282 } 2283 2284 /* Update the receive pointer. */ 2285 sc->sc_rxptr = i; 2286 2287 DPRINTF(WM_DEBUG_RX, 2288 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2289 } 2290 2291 /* 2292 * wm_linkintr: 2293 * 2294 * Helper; handle link interrupts. 2295 */ 2296 static void 2297 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2298 { 2299 uint32_t status; 2300 2301 /* 2302 * If we get a link status interrupt on a 1000BASE-T 2303 * device, just fall into the normal MII tick path. 2304 */ 2305 if (sc->sc_flags & WM_F_HAS_MII) { 2306 if (icr & ICR_LSC) { 2307 DPRINTF(WM_DEBUG_LINK, 2308 ("%s: LINK: LSC -> mii_tick\n", 2309 sc->sc_dev.dv_xname)); 2310 mii_tick(&sc->sc_mii); 2311 } else if (icr & ICR_RXSEQ) { 2312 DPRINTF(WM_DEBUG_LINK, 2313 ("%s: LINK Receive sequence error\n", 2314 sc->sc_dev.dv_xname)); 2315 } 2316 return; 2317 } 2318 2319 /* 2320 * If we are now receiving /C/, check for link again in 2321 * a couple of link clock ticks. 2322 */ 2323 if (icr & ICR_RXCFG) { 2324 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2325 sc->sc_dev.dv_xname)); 2326 sc->sc_tbi_anstate = 2; 2327 } 2328 2329 if (icr & ICR_LSC) { 2330 status = CSR_READ(sc, WMREG_STATUS); 2331 if (status & STATUS_LU) { 2332 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2333 sc->sc_dev.dv_xname, 2334 (status & STATUS_FD) ? "FDX" : "HDX")); 2335 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2336 sc->sc_fcrtl &= ~FCRTL_XONE; 2337 if (status & STATUS_FD) 2338 sc->sc_tctl |= 2339 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2340 else 2341 sc->sc_tctl |= 2342 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2343 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2344 sc->sc_fcrtl |= FCRTL_XONE; 2345 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2346 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2347 WMREG_OLD_FCRTL : WMREG_FCRTL, 2348 sc->sc_fcrtl); 2349 sc->sc_tbi_linkup = 1; 2350 } else { 2351 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2352 sc->sc_dev.dv_xname)); 2353 sc->sc_tbi_linkup = 0; 2354 } 2355 sc->sc_tbi_anstate = 2; 2356 wm_tbi_set_linkled(sc); 2357 } else if (icr & ICR_RXSEQ) { 2358 DPRINTF(WM_DEBUG_LINK, 2359 ("%s: LINK: Receive sequence error\n", 2360 sc->sc_dev.dv_xname)); 2361 } 2362 } 2363 2364 /* 2365 * wm_tick: 2366 * 2367 * One second timer, used to check link status, sweep up 2368 * completed transmit jobs, etc. 2369 */ 2370 static void 2371 wm_tick(void *arg) 2372 { 2373 struct wm_softc *sc = arg; 2374 int s; 2375 2376 s = splnet(); 2377 2378 if (sc->sc_type >= WM_T_82542_2_1) { 2379 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2380 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2381 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2382 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2383 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2384 } 2385 2386 if (sc->sc_flags & WM_F_HAS_MII) 2387 mii_tick(&sc->sc_mii); 2388 else 2389 wm_tbi_check_link(sc); 2390 2391 splx(s); 2392 2393 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2394 } 2395 2396 /* 2397 * wm_reset: 2398 * 2399 * Reset the i82542 chip. 2400 */ 2401 static void 2402 wm_reset(struct wm_softc *sc) 2403 { 2404 int i; 2405 2406 /* 2407 * Allocate on-chip memory according to the MTU size. 2408 * The Packet Buffer Allocation register must be written 2409 * before the chip is reset. 2410 */ 2411 if (sc->sc_type < WM_T_82547) { 2412 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2413 PBA_40K : PBA_48K; 2414 } else { 2415 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2416 PBA_22K : PBA_30K; 2417 sc->sc_txfifo_head = 0; 2418 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2419 sc->sc_txfifo_size = 2420 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2421 sc->sc_txfifo_stall = 0; 2422 } 2423 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2424 2425 switch (sc->sc_type) { 2426 case WM_T_82544: 2427 case WM_T_82540: 2428 case WM_T_82545: 2429 case WM_T_82546: 2430 case WM_T_82541: 2431 case WM_T_82541_2: 2432 /* 2433 * These chips have a problem with the memory-mapped 2434 * write cycle when issuing the reset, so use I/O-mapped 2435 * access, if possible. 2436 */ 2437 if (sc->sc_flags & WM_F_IOH_VALID) 2438 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2439 else 2440 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2441 break; 2442 2443 case WM_T_82545_3: 2444 case WM_T_82546_3: 2445 /* Use the shadow control register on these chips. */ 2446 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2447 break; 2448 2449 default: 2450 /* Everything else can safely use the documented method. */ 2451 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2452 break; 2453 } 2454 delay(10000); 2455 2456 for (i = 0; i < 1000; i++) { 2457 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2458 return; 2459 delay(20); 2460 } 2461 2462 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2463 log(LOG_ERR, "%s: reset failed to complete\n", 2464 sc->sc_dev.dv_xname); 2465 } 2466 2467 /* 2468 * wm_init: [ifnet interface function] 2469 * 2470 * Initialize the interface. Must be called at splnet(). 2471 */ 2472 static int 2473 wm_init(struct ifnet *ifp) 2474 { 2475 struct wm_softc *sc = ifp->if_softc; 2476 struct wm_rxsoft *rxs; 2477 int i, error = 0; 2478 uint32_t reg; 2479 2480 /* 2481 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2482 * There is a small but measurable benefit to avoiding the adjusment 2483 * of the descriptor so that the headers are aligned, for normal mtu, 2484 * on such platforms. One possibility is that the DMA itself is 2485 * slightly more efficient if the front of the entire packet (instead 2486 * of the front of the headers) is aligned. 2487 * 2488 * Note we must always set align_tweak to 0 if we are using 2489 * jumbo frames. 2490 */ 2491 #ifdef __NO_STRICT_ALIGNMENT 2492 sc->sc_align_tweak = 0; 2493 #else 2494 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2495 sc->sc_align_tweak = 0; 2496 else 2497 sc->sc_align_tweak = 2; 2498 #endif /* __NO_STRICT_ALIGNMENT */ 2499 2500 /* Cancel any pending I/O. */ 2501 wm_stop(ifp, 0); 2502 2503 /* Reset the chip to a known state. */ 2504 wm_reset(sc); 2505 2506 /* Initialize the transmit descriptor ring. */ 2507 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2508 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2509 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2510 sc->sc_txfree = WM_NTXDESC(sc); 2511 sc->sc_txnext = 0; 2512 2513 sc->sc_txctx_ipcs = 0xffffffff; 2514 sc->sc_txctx_tucs = 0xffffffff; 2515 2516 if (sc->sc_type < WM_T_82543) { 2517 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2518 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2519 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2520 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2521 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2522 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2523 } else { 2524 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2525 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2526 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2527 CSR_WRITE(sc, WMREG_TDH, 0); 2528 CSR_WRITE(sc, WMREG_TDT, 0); 2529 CSR_WRITE(sc, WMREG_TIDV, 128); 2530 2531 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2532 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2533 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2534 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2535 } 2536 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2537 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2538 2539 /* Initialize the transmit job descriptors. */ 2540 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2541 sc->sc_txsoft[i].txs_mbuf = NULL; 2542 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2543 sc->sc_txsnext = 0; 2544 sc->sc_txsdirty = 0; 2545 2546 /* 2547 * Initialize the receive descriptor and receive job 2548 * descriptor rings. 2549 */ 2550 if (sc->sc_type < WM_T_82543) { 2551 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2552 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2553 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2554 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2555 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2556 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2557 2558 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2559 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2560 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2561 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2562 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2563 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2564 } else { 2565 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2566 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2567 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2568 CSR_WRITE(sc, WMREG_RDH, 0); 2569 CSR_WRITE(sc, WMREG_RDT, 0); 2570 CSR_WRITE(sc, WMREG_RDTR, 28 | RDTR_FPD); 2571 } 2572 for (i = 0; i < WM_NRXDESC; i++) { 2573 rxs = &sc->sc_rxsoft[i]; 2574 if (rxs->rxs_mbuf == NULL) { 2575 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2576 log(LOG_ERR, "%s: unable to allocate or map rx " 2577 "buffer %d, error = %d\n", 2578 sc->sc_dev.dv_xname, i, error); 2579 /* 2580 * XXX Should attempt to run with fewer receive 2581 * XXX buffers instead of just failing. 2582 */ 2583 wm_rxdrain(sc); 2584 goto out; 2585 } 2586 } else 2587 WM_INIT_RXDESC(sc, i); 2588 } 2589 sc->sc_rxptr = 0; 2590 sc->sc_rxdiscard = 0; 2591 WM_RXCHAIN_RESET(sc); 2592 2593 /* 2594 * Clear out the VLAN table -- we don't use it (yet). 2595 */ 2596 CSR_WRITE(sc, WMREG_VET, 0); 2597 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2598 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2599 2600 /* 2601 * Set up flow-control parameters. 2602 * 2603 * XXX Values could probably stand some tuning. 2604 */ 2605 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2606 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2607 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2608 2609 sc->sc_fcrtl = FCRTL_DFLT; 2610 if (sc->sc_type < WM_T_82543) { 2611 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2612 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2613 } else { 2614 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2615 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2616 } 2617 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2618 2619 #if 0 /* XXXJRT */ 2620 /* Deal with VLAN enables. */ 2621 if (sc->sc_ethercom.ec_nvlans != 0) 2622 sc->sc_ctrl |= CTRL_VME; 2623 else 2624 #endif /* XXXJRT */ 2625 sc->sc_ctrl &= ~CTRL_VME; 2626 2627 /* Write the control registers. */ 2628 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2629 #if 0 2630 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2631 #endif 2632 2633 /* 2634 * Set up checksum offload parameters. 2635 */ 2636 reg = CSR_READ(sc, WMREG_RXCSUM); 2637 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2638 reg |= RXCSUM_IPOFL; 2639 else 2640 reg &= ~RXCSUM_IPOFL; 2641 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2642 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2643 else { 2644 reg &= ~RXCSUM_TUOFL; 2645 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2646 reg &= ~RXCSUM_IPOFL; 2647 } 2648 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2649 2650 /* 2651 * Set up the interrupt registers. 2652 */ 2653 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2654 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2655 ICR_RXO | ICR_RXT0; 2656 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2657 sc->sc_icr |= ICR_RXCFG; 2658 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2659 2660 /* Set up the inter-packet gap. */ 2661 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2662 2663 #if 0 /* XXXJRT */ 2664 /* Set the VLAN ethernetype. */ 2665 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2666 #endif 2667 2668 /* 2669 * Set up the transmit control register; we start out with 2670 * a collision distance suitable for FDX, but update it whe 2671 * we resolve the media type. 2672 */ 2673 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2674 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2675 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2676 2677 /* Set the media. */ 2678 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2679 2680 /* 2681 * Set up the receive control register; we actually program 2682 * the register when we set the receive filter. Use multicast 2683 * address offset type 0. 2684 * 2685 * Only the i82544 has the ability to strip the incoming 2686 * CRC, so we don't enable that feature. 2687 */ 2688 sc->sc_mchash_type = 0; 2689 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2690 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2691 2692 if(MCLBYTES == 2048) { 2693 sc->sc_rctl |= RCTL_2k; 2694 } else { 2695 if(sc->sc_type >= WM_T_82543) { 2696 switch(MCLBYTES) { 2697 case 4096: 2698 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2699 break; 2700 case 8192: 2701 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2702 break; 2703 case 16384: 2704 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2705 break; 2706 default: 2707 panic("wm_init: MCLBYTES %d unsupported", 2708 MCLBYTES); 2709 break; 2710 } 2711 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2712 } 2713 2714 /* Set the receive filter. */ 2715 wm_set_filter(sc); 2716 2717 /* Start the one second link check clock. */ 2718 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2719 2720 /* ...all done! */ 2721 ifp->if_flags |= IFF_RUNNING; 2722 ifp->if_flags &= ~IFF_OACTIVE; 2723 2724 out: 2725 if (error) 2726 log(LOG_ERR, "%s: interface not running\n", 2727 sc->sc_dev.dv_xname); 2728 return (error); 2729 } 2730 2731 /* 2732 * wm_rxdrain: 2733 * 2734 * Drain the receive queue. 2735 */ 2736 static void 2737 wm_rxdrain(struct wm_softc *sc) 2738 { 2739 struct wm_rxsoft *rxs; 2740 int i; 2741 2742 for (i = 0; i < WM_NRXDESC; i++) { 2743 rxs = &sc->sc_rxsoft[i]; 2744 if (rxs->rxs_mbuf != NULL) { 2745 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2746 m_freem(rxs->rxs_mbuf); 2747 rxs->rxs_mbuf = NULL; 2748 } 2749 } 2750 } 2751 2752 /* 2753 * wm_stop: [ifnet interface function] 2754 * 2755 * Stop transmission on the interface. 2756 */ 2757 static void 2758 wm_stop(struct ifnet *ifp, int disable) 2759 { 2760 struct wm_softc *sc = ifp->if_softc; 2761 struct wm_txsoft *txs; 2762 int i; 2763 2764 /* Stop the one second clock. */ 2765 callout_stop(&sc->sc_tick_ch); 2766 2767 /* Stop the 82547 Tx FIFO stall check timer. */ 2768 if (sc->sc_type == WM_T_82547) 2769 callout_stop(&sc->sc_txfifo_ch); 2770 2771 if (sc->sc_flags & WM_F_HAS_MII) { 2772 /* Down the MII. */ 2773 mii_down(&sc->sc_mii); 2774 } 2775 2776 /* Stop the transmit and receive processes. */ 2777 CSR_WRITE(sc, WMREG_TCTL, 0); 2778 CSR_WRITE(sc, WMREG_RCTL, 0); 2779 2780 /* Release any queued transmit buffers. */ 2781 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2782 txs = &sc->sc_txsoft[i]; 2783 if (txs->txs_mbuf != NULL) { 2784 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2785 m_freem(txs->txs_mbuf); 2786 txs->txs_mbuf = NULL; 2787 } 2788 } 2789 2790 if (disable) 2791 wm_rxdrain(sc); 2792 2793 /* Mark the interface as down and cancel the watchdog timer. */ 2794 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2795 ifp->if_timer = 0; 2796 } 2797 2798 /* 2799 * wm_acquire_eeprom: 2800 * 2801 * Perform the EEPROM handshake required on some chips. 2802 */ 2803 static int 2804 wm_acquire_eeprom(struct wm_softc *sc) 2805 { 2806 uint32_t reg; 2807 int x; 2808 2809 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2810 reg = CSR_READ(sc, WMREG_EECD); 2811 2812 /* Request EEPROM access. */ 2813 reg |= EECD_EE_REQ; 2814 CSR_WRITE(sc, WMREG_EECD, reg); 2815 2816 /* ..and wait for it to be granted. */ 2817 for (x = 0; x < 100; x++) { 2818 reg = CSR_READ(sc, WMREG_EECD); 2819 if (reg & EECD_EE_GNT) 2820 break; 2821 delay(5); 2822 } 2823 if ((reg & EECD_EE_GNT) == 0) { 2824 aprint_error("%s: could not acquire EEPROM GNT\n", 2825 sc->sc_dev.dv_xname); 2826 reg &= ~EECD_EE_REQ; 2827 CSR_WRITE(sc, WMREG_EECD, reg); 2828 return (1); 2829 } 2830 } 2831 2832 return (0); 2833 } 2834 2835 /* 2836 * wm_release_eeprom: 2837 * 2838 * Release the EEPROM mutex. 2839 */ 2840 static void 2841 wm_release_eeprom(struct wm_softc *sc) 2842 { 2843 uint32_t reg; 2844 2845 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2846 reg = CSR_READ(sc, WMREG_EECD); 2847 reg &= ~EECD_EE_REQ; 2848 CSR_WRITE(sc, WMREG_EECD, reg); 2849 } 2850 } 2851 2852 /* 2853 * wm_eeprom_sendbits: 2854 * 2855 * Send a series of bits to the EEPROM. 2856 */ 2857 static void 2858 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2859 { 2860 uint32_t reg; 2861 int x; 2862 2863 reg = CSR_READ(sc, WMREG_EECD); 2864 2865 for (x = nbits; x > 0; x--) { 2866 if (bits & (1U << (x - 1))) 2867 reg |= EECD_DI; 2868 else 2869 reg &= ~EECD_DI; 2870 CSR_WRITE(sc, WMREG_EECD, reg); 2871 delay(2); 2872 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2873 delay(2); 2874 CSR_WRITE(sc, WMREG_EECD, reg); 2875 delay(2); 2876 } 2877 } 2878 2879 /* 2880 * wm_eeprom_recvbits: 2881 * 2882 * Receive a series of bits from the EEPROM. 2883 */ 2884 static void 2885 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2886 { 2887 uint32_t reg, val; 2888 int x; 2889 2890 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2891 2892 val = 0; 2893 for (x = nbits; x > 0; x--) { 2894 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2895 delay(2); 2896 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2897 val |= (1U << (x - 1)); 2898 CSR_WRITE(sc, WMREG_EECD, reg); 2899 delay(2); 2900 } 2901 *valp = val; 2902 } 2903 2904 /* 2905 * wm_read_eeprom_uwire: 2906 * 2907 * Read a word from the EEPROM using the MicroWire protocol. 2908 */ 2909 static int 2910 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2911 { 2912 uint32_t reg, val; 2913 int i; 2914 2915 for (i = 0; i < wordcnt; i++) { 2916 /* Clear SK and DI. */ 2917 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2918 CSR_WRITE(sc, WMREG_EECD, reg); 2919 2920 /* Set CHIP SELECT. */ 2921 reg |= EECD_CS; 2922 CSR_WRITE(sc, WMREG_EECD, reg); 2923 delay(2); 2924 2925 /* Shift in the READ command. */ 2926 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2927 2928 /* Shift in address. */ 2929 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2930 2931 /* Shift out the data. */ 2932 wm_eeprom_recvbits(sc, &val, 16); 2933 data[i] = val & 0xffff; 2934 2935 /* Clear CHIP SELECT. */ 2936 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 2937 CSR_WRITE(sc, WMREG_EECD, reg); 2938 delay(2); 2939 } 2940 2941 return (0); 2942 } 2943 2944 /* 2945 * wm_spi_eeprom_ready: 2946 * 2947 * Wait for a SPI EEPROM to be ready for commands. 2948 */ 2949 static int 2950 wm_spi_eeprom_ready(struct wm_softc *sc) 2951 { 2952 uint32_t val; 2953 int usec; 2954 2955 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 2956 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 2957 wm_eeprom_recvbits(sc, &val, 8); 2958 if ((val & SPI_SR_RDY) == 0) 2959 break; 2960 } 2961 if (usec >= SPI_MAX_RETRIES) { 2962 aprint_error("%s: EEPROM failed to become ready\n", 2963 sc->sc_dev.dv_xname); 2964 return (1); 2965 } 2966 return (0); 2967 } 2968 2969 /* 2970 * wm_read_eeprom_spi: 2971 * 2972 * Read a work from the EEPROM using the SPI protocol. 2973 */ 2974 static int 2975 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2976 { 2977 uint32_t reg, val; 2978 int i; 2979 uint8_t opc; 2980 2981 /* Clear SK and CS. */ 2982 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 2983 CSR_WRITE(sc, WMREG_EECD, reg); 2984 delay(2); 2985 2986 if (wm_spi_eeprom_ready(sc)) 2987 return (1); 2988 2989 /* Toggle CS to flush commands. */ 2990 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 2991 delay(2); 2992 CSR_WRITE(sc, WMREG_EECD, reg); 2993 delay(2); 2994 2995 opc = SPI_OPC_READ; 2996 if (sc->sc_ee_addrbits == 8 && word >= 128) 2997 opc |= SPI_OPC_A8; 2998 2999 wm_eeprom_sendbits(sc, opc, 8); 3000 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3001 3002 for (i = 0; i < wordcnt; i++) { 3003 wm_eeprom_recvbits(sc, &val, 16); 3004 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3005 } 3006 3007 /* Raise CS and clear SK. */ 3008 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3009 CSR_WRITE(sc, WMREG_EECD, reg); 3010 delay(2); 3011 3012 return (0); 3013 } 3014 3015 /* 3016 * wm_read_eeprom: 3017 * 3018 * Read data from the serial EEPROM. 3019 */ 3020 static int 3021 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3022 { 3023 int rv; 3024 3025 if (wm_acquire_eeprom(sc)) 3026 return (1); 3027 3028 if (sc->sc_flags & WM_F_EEPROM_SPI) 3029 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3030 else 3031 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3032 3033 wm_release_eeprom(sc); 3034 return (rv); 3035 } 3036 3037 /* 3038 * wm_add_rxbuf: 3039 * 3040 * Add a receive buffer to the indiciated descriptor. 3041 */ 3042 static int 3043 wm_add_rxbuf(struct wm_softc *sc, int idx) 3044 { 3045 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3046 struct mbuf *m; 3047 int error; 3048 3049 MGETHDR(m, M_DONTWAIT, MT_DATA); 3050 if (m == NULL) 3051 return (ENOBUFS); 3052 3053 MCLGET(m, M_DONTWAIT); 3054 if ((m->m_flags & M_EXT) == 0) { 3055 m_freem(m); 3056 return (ENOBUFS); 3057 } 3058 3059 if (rxs->rxs_mbuf != NULL) 3060 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3061 3062 rxs->rxs_mbuf = m; 3063 3064 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3065 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3066 BUS_DMA_READ|BUS_DMA_NOWAIT); 3067 if (error) { 3068 /* XXX XXX XXX */ 3069 printf("%s: unable to load rx DMA map %d, error = %d\n", 3070 sc->sc_dev.dv_xname, idx, error); 3071 panic("wm_add_rxbuf"); 3072 } 3073 3074 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3075 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3076 3077 WM_INIT_RXDESC(sc, idx); 3078 3079 return (0); 3080 } 3081 3082 /* 3083 * wm_set_ral: 3084 * 3085 * Set an entery in the receive address list. 3086 */ 3087 static void 3088 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3089 { 3090 uint32_t ral_lo, ral_hi; 3091 3092 if (enaddr != NULL) { 3093 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3094 (enaddr[3] << 24); 3095 ral_hi = enaddr[4] | (enaddr[5] << 8); 3096 ral_hi |= RAL_AV; 3097 } else { 3098 ral_lo = 0; 3099 ral_hi = 0; 3100 } 3101 3102 if (sc->sc_type >= WM_T_82544) { 3103 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3104 ral_lo); 3105 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3106 ral_hi); 3107 } else { 3108 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3109 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3110 } 3111 } 3112 3113 /* 3114 * wm_mchash: 3115 * 3116 * Compute the hash of the multicast address for the 4096-bit 3117 * multicast filter. 3118 */ 3119 static uint32_t 3120 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3121 { 3122 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3123 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3124 uint32_t hash; 3125 3126 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3127 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3128 3129 return (hash & 0xfff); 3130 } 3131 3132 /* 3133 * wm_set_filter: 3134 * 3135 * Set up the receive filter. 3136 */ 3137 static void 3138 wm_set_filter(struct wm_softc *sc) 3139 { 3140 struct ethercom *ec = &sc->sc_ethercom; 3141 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3142 struct ether_multi *enm; 3143 struct ether_multistep step; 3144 bus_addr_t mta_reg; 3145 uint32_t hash, reg, bit; 3146 int i; 3147 3148 if (sc->sc_type >= WM_T_82544) 3149 mta_reg = WMREG_CORDOVA_MTA; 3150 else 3151 mta_reg = WMREG_MTA; 3152 3153 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3154 3155 if (ifp->if_flags & IFF_BROADCAST) 3156 sc->sc_rctl |= RCTL_BAM; 3157 if (ifp->if_flags & IFF_PROMISC) { 3158 sc->sc_rctl |= RCTL_UPE; 3159 goto allmulti; 3160 } 3161 3162 /* 3163 * Set the station address in the first RAL slot, and 3164 * clear the remaining slots. 3165 */ 3166 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3167 for (i = 1; i < WM_RAL_TABSIZE; i++) 3168 wm_set_ral(sc, NULL, i); 3169 3170 /* Clear out the multicast table. */ 3171 for (i = 0; i < WM_MC_TABSIZE; i++) 3172 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3173 3174 ETHER_FIRST_MULTI(step, ec, enm); 3175 while (enm != NULL) { 3176 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3177 /* 3178 * We must listen to a range of multicast addresses. 3179 * For now, just accept all multicasts, rather than 3180 * trying to set only those filter bits needed to match 3181 * the range. (At this time, the only use of address 3182 * ranges is for IP multicast routing, for which the 3183 * range is big enough to require all bits set.) 3184 */ 3185 goto allmulti; 3186 } 3187 3188 hash = wm_mchash(sc, enm->enm_addrlo); 3189 3190 reg = (hash >> 5) & 0x7f; 3191 bit = hash & 0x1f; 3192 3193 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3194 hash |= 1U << bit; 3195 3196 /* XXX Hardware bug?? */ 3197 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3198 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3199 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3200 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3201 } else 3202 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3203 3204 ETHER_NEXT_MULTI(step, enm); 3205 } 3206 3207 ifp->if_flags &= ~IFF_ALLMULTI; 3208 goto setit; 3209 3210 allmulti: 3211 ifp->if_flags |= IFF_ALLMULTI; 3212 sc->sc_rctl |= RCTL_MPE; 3213 3214 setit: 3215 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3216 } 3217 3218 /* 3219 * wm_tbi_mediainit: 3220 * 3221 * Initialize media for use on 1000BASE-X devices. 3222 */ 3223 static void 3224 wm_tbi_mediainit(struct wm_softc *sc) 3225 { 3226 const char *sep = ""; 3227 3228 if (sc->sc_type < WM_T_82543) 3229 sc->sc_tipg = TIPG_WM_DFLT; 3230 else 3231 sc->sc_tipg = TIPG_LG_DFLT; 3232 3233 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3234 wm_tbi_mediastatus); 3235 3236 /* 3237 * SWD Pins: 3238 * 3239 * 0 = Link LED (output) 3240 * 1 = Loss Of Signal (input) 3241 */ 3242 sc->sc_ctrl |= CTRL_SWDPIO(0); 3243 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3244 3245 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3246 3247 #define ADD(ss, mm, dd) \ 3248 do { \ 3249 aprint_normal("%s%s", sep, ss); \ 3250 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3251 sep = ", "; \ 3252 } while (/*CONSTCOND*/0) 3253 3254 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3255 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3256 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3257 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3258 aprint_normal("\n"); 3259 3260 #undef ADD 3261 3262 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3263 } 3264 3265 /* 3266 * wm_tbi_mediastatus: [ifmedia interface function] 3267 * 3268 * Get the current interface media status on a 1000BASE-X device. 3269 */ 3270 static void 3271 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3272 { 3273 struct wm_softc *sc = ifp->if_softc; 3274 uint32_t ctrl; 3275 3276 ifmr->ifm_status = IFM_AVALID; 3277 ifmr->ifm_active = IFM_ETHER; 3278 3279 if (sc->sc_tbi_linkup == 0) { 3280 ifmr->ifm_active |= IFM_NONE; 3281 return; 3282 } 3283 3284 ifmr->ifm_status |= IFM_ACTIVE; 3285 ifmr->ifm_active |= IFM_1000_SX; 3286 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3287 ifmr->ifm_active |= IFM_FDX; 3288 ctrl = CSR_READ(sc, WMREG_CTRL); 3289 if (ctrl & CTRL_RFCE) 3290 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3291 if (ctrl & CTRL_TFCE) 3292 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3293 } 3294 3295 /* 3296 * wm_tbi_mediachange: [ifmedia interface function] 3297 * 3298 * Set hardware to newly-selected media on a 1000BASE-X device. 3299 */ 3300 static int 3301 wm_tbi_mediachange(struct ifnet *ifp) 3302 { 3303 struct wm_softc *sc = ifp->if_softc; 3304 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3305 uint32_t status; 3306 int i; 3307 3308 sc->sc_txcw = ife->ifm_data; 3309 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3310 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3311 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3312 sc->sc_txcw |= TXCW_ANE; 3313 3314 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3315 delay(10000); 3316 3317 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3318 3319 sc->sc_tbi_anstate = 0; 3320 3321 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3322 /* Have signal; wait for the link to come up. */ 3323 for (i = 0; i < 50; i++) { 3324 delay(10000); 3325 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3326 break; 3327 } 3328 3329 status = CSR_READ(sc, WMREG_STATUS); 3330 if (status & STATUS_LU) { 3331 /* Link is up. */ 3332 DPRINTF(WM_DEBUG_LINK, 3333 ("%s: LINK: set media -> link up %s\n", 3334 sc->sc_dev.dv_xname, 3335 (status & STATUS_FD) ? "FDX" : "HDX")); 3336 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3337 sc->sc_fcrtl &= ~FCRTL_XONE; 3338 if (status & STATUS_FD) 3339 sc->sc_tctl |= 3340 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3341 else 3342 sc->sc_tctl |= 3343 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3344 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3345 sc->sc_fcrtl |= FCRTL_XONE; 3346 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3347 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3348 WMREG_OLD_FCRTL : WMREG_FCRTL, 3349 sc->sc_fcrtl); 3350 sc->sc_tbi_linkup = 1; 3351 } else { 3352 /* Link is down. */ 3353 DPRINTF(WM_DEBUG_LINK, 3354 ("%s: LINK: set media -> link down\n", 3355 sc->sc_dev.dv_xname)); 3356 sc->sc_tbi_linkup = 0; 3357 } 3358 } else { 3359 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3360 sc->sc_dev.dv_xname)); 3361 sc->sc_tbi_linkup = 0; 3362 } 3363 3364 wm_tbi_set_linkled(sc); 3365 3366 return (0); 3367 } 3368 3369 /* 3370 * wm_tbi_set_linkled: 3371 * 3372 * Update the link LED on 1000BASE-X devices. 3373 */ 3374 static void 3375 wm_tbi_set_linkled(struct wm_softc *sc) 3376 { 3377 3378 if (sc->sc_tbi_linkup) 3379 sc->sc_ctrl |= CTRL_SWDPIN(0); 3380 else 3381 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3382 3383 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3384 } 3385 3386 /* 3387 * wm_tbi_check_link: 3388 * 3389 * Check the link on 1000BASE-X devices. 3390 */ 3391 static void 3392 wm_tbi_check_link(struct wm_softc *sc) 3393 { 3394 uint32_t rxcw, ctrl, status; 3395 3396 if (sc->sc_tbi_anstate == 0) 3397 return; 3398 else if (sc->sc_tbi_anstate > 1) { 3399 DPRINTF(WM_DEBUG_LINK, 3400 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3401 sc->sc_tbi_anstate)); 3402 sc->sc_tbi_anstate--; 3403 return; 3404 } 3405 3406 sc->sc_tbi_anstate = 0; 3407 3408 rxcw = CSR_READ(sc, WMREG_RXCW); 3409 ctrl = CSR_READ(sc, WMREG_CTRL); 3410 status = CSR_READ(sc, WMREG_STATUS); 3411 3412 if ((status & STATUS_LU) == 0) { 3413 DPRINTF(WM_DEBUG_LINK, 3414 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3415 sc->sc_tbi_linkup = 0; 3416 } else { 3417 DPRINTF(WM_DEBUG_LINK, 3418 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3419 (status & STATUS_FD) ? "FDX" : "HDX")); 3420 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3421 sc->sc_fcrtl &= ~FCRTL_XONE; 3422 if (status & STATUS_FD) 3423 sc->sc_tctl |= 3424 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3425 else 3426 sc->sc_tctl |= 3427 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3428 if (ctrl & CTRL_TFCE) 3429 sc->sc_fcrtl |= FCRTL_XONE; 3430 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3431 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3432 WMREG_OLD_FCRTL : WMREG_FCRTL, 3433 sc->sc_fcrtl); 3434 sc->sc_tbi_linkup = 1; 3435 } 3436 3437 wm_tbi_set_linkled(sc); 3438 } 3439 3440 /* 3441 * wm_gmii_reset: 3442 * 3443 * Reset the PHY. 3444 */ 3445 static void 3446 wm_gmii_reset(struct wm_softc *sc) 3447 { 3448 uint32_t reg; 3449 3450 if (sc->sc_type >= WM_T_82544) { 3451 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3452 delay(20000); 3453 3454 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3455 delay(20000); 3456 } else { 3457 /* The PHY reset pin is active-low. */ 3458 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3459 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3460 CTRL_EXT_SWDPIN(4)); 3461 reg |= CTRL_EXT_SWDPIO(4); 3462 3463 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3464 delay(10); 3465 3466 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3467 delay(10); 3468 3469 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3470 delay(10); 3471 #if 0 3472 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3473 #endif 3474 } 3475 } 3476 3477 /* 3478 * wm_gmii_mediainit: 3479 * 3480 * Initialize media for use on 1000BASE-T devices. 3481 */ 3482 static void 3483 wm_gmii_mediainit(struct wm_softc *sc) 3484 { 3485 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3486 3487 /* We have MII. */ 3488 sc->sc_flags |= WM_F_HAS_MII; 3489 3490 sc->sc_tipg = TIPG_1000T_DFLT; 3491 3492 /* 3493 * Let the chip set speed/duplex on its own based on 3494 * signals from the PHY. 3495 */ 3496 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3497 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3498 3499 /* Initialize our media structures and probe the GMII. */ 3500 sc->sc_mii.mii_ifp = ifp; 3501 3502 if (sc->sc_type >= WM_T_82544) { 3503 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3504 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3505 } else { 3506 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3507 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3508 } 3509 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3510 3511 wm_gmii_reset(sc); 3512 3513 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3514 wm_gmii_mediastatus); 3515 3516 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3517 MII_OFFSET_ANY, MIIF_DOPAUSE); 3518 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3519 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3520 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3521 } else 3522 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3523 } 3524 3525 /* 3526 * wm_gmii_mediastatus: [ifmedia interface function] 3527 * 3528 * Get the current interface media status on a 1000BASE-T device. 3529 */ 3530 static void 3531 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3532 { 3533 struct wm_softc *sc = ifp->if_softc; 3534 3535 mii_pollstat(&sc->sc_mii); 3536 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3537 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3538 sc->sc_flowflags; 3539 } 3540 3541 /* 3542 * wm_gmii_mediachange: [ifmedia interface function] 3543 * 3544 * Set hardware to newly-selected media on a 1000BASE-T device. 3545 */ 3546 static int 3547 wm_gmii_mediachange(struct ifnet *ifp) 3548 { 3549 struct wm_softc *sc = ifp->if_softc; 3550 3551 if (ifp->if_flags & IFF_UP) 3552 mii_mediachg(&sc->sc_mii); 3553 return (0); 3554 } 3555 3556 #define MDI_IO CTRL_SWDPIN(2) 3557 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3558 #define MDI_CLK CTRL_SWDPIN(3) 3559 3560 static void 3561 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3562 { 3563 uint32_t i, v; 3564 3565 v = CSR_READ(sc, WMREG_CTRL); 3566 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3567 v |= MDI_DIR | CTRL_SWDPIO(3); 3568 3569 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3570 if (data & i) 3571 v |= MDI_IO; 3572 else 3573 v &= ~MDI_IO; 3574 CSR_WRITE(sc, WMREG_CTRL, v); 3575 delay(10); 3576 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3577 delay(10); 3578 CSR_WRITE(sc, WMREG_CTRL, v); 3579 delay(10); 3580 } 3581 } 3582 3583 static uint32_t 3584 i82543_mii_recvbits(struct wm_softc *sc) 3585 { 3586 uint32_t v, i, data = 0; 3587 3588 v = CSR_READ(sc, WMREG_CTRL); 3589 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3590 v |= CTRL_SWDPIO(3); 3591 3592 CSR_WRITE(sc, WMREG_CTRL, v); 3593 delay(10); 3594 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3595 delay(10); 3596 CSR_WRITE(sc, WMREG_CTRL, v); 3597 delay(10); 3598 3599 for (i = 0; i < 16; i++) { 3600 data <<= 1; 3601 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3602 delay(10); 3603 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3604 data |= 1; 3605 CSR_WRITE(sc, WMREG_CTRL, v); 3606 delay(10); 3607 } 3608 3609 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3610 delay(10); 3611 CSR_WRITE(sc, WMREG_CTRL, v); 3612 delay(10); 3613 3614 return (data); 3615 } 3616 3617 #undef MDI_IO 3618 #undef MDI_DIR 3619 #undef MDI_CLK 3620 3621 /* 3622 * wm_gmii_i82543_readreg: [mii interface function] 3623 * 3624 * Read a PHY register on the GMII (i82543 version). 3625 */ 3626 static int 3627 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3628 { 3629 struct wm_softc *sc = (void *) self; 3630 int rv; 3631 3632 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3633 i82543_mii_sendbits(sc, reg | (phy << 5) | 3634 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3635 rv = i82543_mii_recvbits(sc) & 0xffff; 3636 3637 DPRINTF(WM_DEBUG_GMII, 3638 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3639 sc->sc_dev.dv_xname, phy, reg, rv)); 3640 3641 return (rv); 3642 } 3643 3644 /* 3645 * wm_gmii_i82543_writereg: [mii interface function] 3646 * 3647 * Write a PHY register on the GMII (i82543 version). 3648 */ 3649 static void 3650 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3651 { 3652 struct wm_softc *sc = (void *) self; 3653 3654 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3655 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3656 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3657 (MII_COMMAND_START << 30), 32); 3658 } 3659 3660 /* 3661 * wm_gmii_i82544_readreg: [mii interface function] 3662 * 3663 * Read a PHY register on the GMII. 3664 */ 3665 static int 3666 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3667 { 3668 struct wm_softc *sc = (void *) self; 3669 uint32_t mdic = 0; 3670 int i, rv; 3671 3672 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3673 MDIC_REGADD(reg)); 3674 3675 for (i = 0; i < 100; i++) { 3676 mdic = CSR_READ(sc, WMREG_MDIC); 3677 if (mdic & MDIC_READY) 3678 break; 3679 delay(10); 3680 } 3681 3682 if ((mdic & MDIC_READY) == 0) { 3683 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3684 sc->sc_dev.dv_xname, phy, reg); 3685 rv = 0; 3686 } else if (mdic & MDIC_E) { 3687 #if 0 /* This is normal if no PHY is present. */ 3688 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3689 sc->sc_dev.dv_xname, phy, reg); 3690 #endif 3691 rv = 0; 3692 } else { 3693 rv = MDIC_DATA(mdic); 3694 if (rv == 0xffff) 3695 rv = 0; 3696 } 3697 3698 return (rv); 3699 } 3700 3701 /* 3702 * wm_gmii_i82544_writereg: [mii interface function] 3703 * 3704 * Write a PHY register on the GMII. 3705 */ 3706 static void 3707 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3708 { 3709 struct wm_softc *sc = (void *) self; 3710 uint32_t mdic = 0; 3711 int i; 3712 3713 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3714 MDIC_REGADD(reg) | MDIC_DATA(val)); 3715 3716 for (i = 0; i < 100; i++) { 3717 mdic = CSR_READ(sc, WMREG_MDIC); 3718 if (mdic & MDIC_READY) 3719 break; 3720 delay(10); 3721 } 3722 3723 if ((mdic & MDIC_READY) == 0) 3724 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3725 sc->sc_dev.dv_xname, phy, reg); 3726 else if (mdic & MDIC_E) 3727 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3728 sc->sc_dev.dv_xname, phy, reg); 3729 } 3730 3731 /* 3732 * wm_gmii_statchg: [mii interface function] 3733 * 3734 * Callback from MII layer when media changes. 3735 */ 3736 static void 3737 wm_gmii_statchg(struct device *self) 3738 { 3739 struct wm_softc *sc = (void *) self; 3740 struct mii_data *mii = &sc->sc_mii; 3741 3742 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3743 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3744 sc->sc_fcrtl &= ~FCRTL_XONE; 3745 3746 /* 3747 * Get flow control negotiation result. 3748 */ 3749 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3750 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3751 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3752 mii->mii_media_active &= ~IFM_ETH_FMASK; 3753 } 3754 3755 if (sc->sc_flowflags & IFM_FLOW) { 3756 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3757 sc->sc_ctrl |= CTRL_TFCE; 3758 sc->sc_fcrtl |= FCRTL_XONE; 3759 } 3760 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3761 sc->sc_ctrl |= CTRL_RFCE; 3762 } 3763 3764 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3765 DPRINTF(WM_DEBUG_LINK, 3766 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3767 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3768 } else { 3769 DPRINTF(WM_DEBUG_LINK, 3770 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3771 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3772 } 3773 3774 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3775 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3776 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3777 : WMREG_FCRTL, sc->sc_fcrtl); 3778 } 3779
Indexes created Tue Sep 23 13:09:54 GMT 2025