if_wm.c revision 1.87
1 /* $NetBSD: if_wm.c,v 1.87 2004/11/24 00:02:50 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.87 2004/11/24 00:02:50 thorpej Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA ETHER_MAX_LEN_JUMBO 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make serveral things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 280 /* m_pullup() needed for Tx offload */ 281 struct evcnt sc_ev_txpullup_needed; 282 /* ...failed due to no memory */ 283 struct evcnt sc_ev_txpullup_nomem; 284 /* ...failed due to lack of space in first mbuf */ 285 struct evcnt sc_ev_txpullup_fail; 286 287 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 288 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 289 290 struct evcnt sc_ev_tu; /* Tx underrun */ 291 292 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 293 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 294 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 295 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 296 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 297 #endif /* WM_EVENT_COUNTERS */ 298 299 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 300 301 int sc_txfree; /* number of free Tx descriptors */ 302 int sc_txnext; /* next ready Tx descriptor */ 303 304 int sc_txsfree; /* number of free Tx jobs */ 305 int sc_txsnext; /* next free Tx job */ 306 int sc_txsdirty; /* dirty Tx jobs */ 307 308 /* These 5 variables are used only on the 82547. */ 309 int sc_txfifo_size; /* Tx FIFO size */ 310 int sc_txfifo_head; /* current head of FIFO */ 311 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 312 int sc_txfifo_stall; /* Tx FIFO is stalled */ 313 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 314 315 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 316 317 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 318 int sc_rxdiscard; 319 int sc_rxlen; 320 struct mbuf *sc_rxhead; 321 struct mbuf *sc_rxtail; 322 struct mbuf **sc_rxtailp; 323 324 uint32_t sc_ctrl; /* prototype CTRL register */ 325 #if 0 326 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 327 #endif 328 uint32_t sc_icr; /* prototype interrupt bits */ 329 uint32_t sc_tctl; /* prototype TCTL register */ 330 uint32_t sc_rctl; /* prototype RCTL register */ 331 uint32_t sc_txcw; /* prototype TXCW register */ 332 uint32_t sc_tipg; /* prototype TIPG register */ 333 uint32_t sc_fcrtl; /* prototype FCRTL register */ 334 uint32_t sc_pba; /* prototype PBA register */ 335 336 int sc_tbi_linkup; /* TBI link status */ 337 int sc_tbi_anstate; /* autonegotiation state */ 338 339 int sc_mchash_type; /* multicast filter offset */ 340 341 #if NRND > 0 342 rndsource_element_t rnd_source; /* random source */ 343 #endif 344 }; 345 346 #define WM_RXCHAIN_RESET(sc) \ 347 do { \ 348 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 349 *(sc)->sc_rxtailp = NULL; \ 350 (sc)->sc_rxlen = 0; \ 351 } while (/*CONSTCOND*/0) 352 353 #define WM_RXCHAIN_LINK(sc, m) \ 354 do { \ 355 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 356 (sc)->sc_rxtailp = &(m)->m_next; \ 357 } while (/*CONSTCOND*/0) 358 359 /* sc_flags */ 360 #define WM_F_HAS_MII 0x01 /* has MII */ 361 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 362 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 363 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 364 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 365 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 366 #define WM_F_CSA 0x80 /* bus is CSA */ 367 368 #ifdef WM_EVENT_COUNTERS 369 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 370 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 371 #else 372 #define WM_EVCNT_INCR(ev) /* nothing */ 373 #define WM_EVCNT_ADD(ev, val) /* nothing */ 374 #endif 375 376 #define CSR_READ(sc, reg) \ 377 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 378 #define CSR_WRITE(sc, reg, val) \ 379 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 380 #define CSR_WRITE_FLUSH(sc) \ 381 (void) CSR_READ((sc), WMREG_STATUS) 382 383 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 384 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 385 386 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 387 #define WM_CDTXADDR_HI(sc, x) \ 388 (sizeof(bus_addr_t) == 8 ? \ 389 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 390 391 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 392 #define WM_CDRXADDR_HI(sc, x) \ 393 (sizeof(bus_addr_t) == 8 ? \ 394 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 395 396 #define WM_CDTXSYNC(sc, x, n, ops) \ 397 do { \ 398 int __x, __n; \ 399 \ 400 __x = (x); \ 401 __n = (n); \ 402 \ 403 /* If it will wrap around, sync to the end of the ring. */ \ 404 if ((__x + __n) > WM_NTXDESC(sc)) { \ 405 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 406 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 407 (WM_NTXDESC(sc) - __x), (ops)); \ 408 __n -= (WM_NTXDESC(sc) - __x); \ 409 __x = 0; \ 410 } \ 411 \ 412 /* Now sync whatever is left. */ \ 413 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 414 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 415 } while (/*CONSTCOND*/0) 416 417 #define WM_CDRXSYNC(sc, x, ops) \ 418 do { \ 419 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 420 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 421 } while (/*CONSTCOND*/0) 422 423 #define WM_INIT_RXDESC(sc, x) \ 424 do { \ 425 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 426 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 427 struct mbuf *__m = __rxs->rxs_mbuf; \ 428 \ 429 /* \ 430 * Note: We scoot the packet forward 2 bytes in the buffer \ 431 * so that the payload after the Ethernet header is aligned \ 432 * to a 4-byte boundary. \ 433 * \ 434 * XXX BRAINDAMAGE ALERT! \ 435 * The stupid chip uses the same size for every buffer, which \ 436 * is set in the Receive Control register. We are using the 2K \ 437 * size option, but what we REALLY want is (2K - 2)! For this \ 438 * reason, we can't "scoot" packets longer than the standard \ 439 * Ethernet MTU. On strict-alignment platforms, if the total \ 440 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 441 * the upper layer copy the headers. \ 442 */ \ 443 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 444 \ 445 wm_set_dma_addr(&__rxd->wrx_addr, \ 446 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 447 __rxd->wrx_len = 0; \ 448 __rxd->wrx_cksum = 0; \ 449 __rxd->wrx_status = 0; \ 450 __rxd->wrx_errors = 0; \ 451 __rxd->wrx_special = 0; \ 452 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 453 \ 454 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 455 } while (/*CONSTCOND*/0) 456 457 static void wm_start(struct ifnet *); 458 static void wm_watchdog(struct ifnet *); 459 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 460 static int wm_init(struct ifnet *); 461 static void wm_stop(struct ifnet *, int); 462 463 static void wm_shutdown(void *); 464 465 static void wm_reset(struct wm_softc *); 466 static void wm_rxdrain(struct wm_softc *); 467 static int wm_add_rxbuf(struct wm_softc *, int); 468 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 469 static void wm_tick(void *); 470 471 static void wm_set_filter(struct wm_softc *); 472 473 static int wm_intr(void *); 474 static void wm_txintr(struct wm_softc *); 475 static void wm_rxintr(struct wm_softc *); 476 static void wm_linkintr(struct wm_softc *, uint32_t); 477 478 static void wm_tbi_mediainit(struct wm_softc *); 479 static int wm_tbi_mediachange(struct ifnet *); 480 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 481 482 static void wm_tbi_set_linkled(struct wm_softc *); 483 static void wm_tbi_check_link(struct wm_softc *); 484 485 static void wm_gmii_reset(struct wm_softc *); 486 487 static int wm_gmii_i82543_readreg(struct device *, int, int); 488 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 489 490 static int wm_gmii_i82544_readreg(struct device *, int, int); 491 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 492 493 static void wm_gmii_statchg(struct device *); 494 495 static void wm_gmii_mediainit(struct wm_softc *); 496 static int wm_gmii_mediachange(struct ifnet *); 497 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 498 499 static int wm_match(struct device *, struct cfdata *, void *); 500 static void wm_attach(struct device *, struct device *, void *); 501 502 CFATTACH_DECL(wm, sizeof(struct wm_softc), 503 wm_match, wm_attach, NULL, NULL); 504 505 static void wm_82547_txfifo_stall(void *); 506 507 /* 508 * Devices supported by this driver. 509 */ 510 static const struct wm_product { 511 pci_vendor_id_t wmp_vendor; 512 pci_product_id_t wmp_product; 513 const char *wmp_name; 514 wm_chip_type wmp_type; 515 int wmp_flags; 516 #define WMP_F_1000X 0x01 517 #define WMP_F_1000T 0x02 518 } wm_products[] = { 519 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 520 "Intel i82542 1000BASE-X Ethernet", 521 WM_T_82542_2_1, WMP_F_1000X }, 522 523 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 524 "Intel i82543GC 1000BASE-X Ethernet", 525 WM_T_82543, WMP_F_1000X }, 526 527 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 528 "Intel i82543GC 1000BASE-T Ethernet", 529 WM_T_82543, WMP_F_1000T }, 530 531 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 532 "Intel i82544EI 1000BASE-T Ethernet", 533 WM_T_82544, WMP_F_1000T }, 534 535 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 536 "Intel i82544EI 1000BASE-X Ethernet", 537 WM_T_82544, WMP_F_1000X }, 538 539 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 540 "Intel i82544GC 1000BASE-T Ethernet", 541 WM_T_82544, WMP_F_1000T }, 542 543 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 544 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 545 WM_T_82544, WMP_F_1000T }, 546 547 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 548 "Intel i82540EM 1000BASE-T Ethernet", 549 WM_T_82540, WMP_F_1000T }, 550 551 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 552 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 553 WM_T_82540, WMP_F_1000T }, 554 555 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 556 "Intel i82540EP 1000BASE-T Ethernet", 557 WM_T_82540, WMP_F_1000T }, 558 559 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 560 "Intel i82540EP 1000BASE-T Ethernet", 561 WM_T_82540, WMP_F_1000T }, 562 563 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 564 "Intel i82540EP 1000BASE-T Ethernet", 565 WM_T_82540, WMP_F_1000T }, 566 567 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 568 "Intel i82545EM 1000BASE-T Ethernet", 569 WM_T_82545, WMP_F_1000T }, 570 571 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 572 "Intel i82545GM 1000BASE-T Ethernet", 573 WM_T_82545_3, WMP_F_1000T }, 574 575 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 576 "Intel i82545GM 1000BASE-X Ethernet", 577 WM_T_82545_3, WMP_F_1000X }, 578 #if 0 579 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 580 "Intel i82545GM Gigabit Ethernet (SERDES)", 581 WM_T_82545_3, WMP_F_SERDES }, 582 #endif 583 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 584 "Intel i82546EB 1000BASE-T Ethernet", 585 WM_T_82546, WMP_F_1000T }, 586 587 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 588 "Intel i82546EB 1000BASE-T Ethernet", 589 WM_T_82546, WMP_F_1000T }, 590 591 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 592 "Intel i82545EM 1000BASE-X Ethernet", 593 WM_T_82545, WMP_F_1000X }, 594 595 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 596 "Intel i82546EB 1000BASE-X Ethernet", 597 WM_T_82546, WMP_F_1000X }, 598 599 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 600 "Intel i82546GB 1000BASE-T Ethernet", 601 WM_T_82546_3, WMP_F_1000T }, 602 603 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 604 "Intel i82546GB 1000BASE-X Ethernet", 605 WM_T_82546_3, WMP_F_1000X }, 606 #if 0 607 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 608 "Intel i82546GB Gigabit Ethernet (SERDES)", 609 WM_T_82546_3, WMP_F_SERDES }, 610 #endif 611 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 612 "Intel i82541EI 1000BASE-T Ethernet", 613 WM_T_82541, WMP_F_1000T }, 614 615 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 616 "Intel i82541EI Mobile 1000BASE-T Ethernet", 617 WM_T_82541, WMP_F_1000T }, 618 619 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 620 "Intel i82541ER 1000BASE-T Ethernet", 621 WM_T_82541_2, WMP_F_1000T }, 622 623 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 624 "Intel i82541GI 1000BASE-T Ethernet", 625 WM_T_82541_2, WMP_F_1000T }, 626 627 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 628 "Intel i82541GI Mobile 1000BASE-T Ethernet", 629 WM_T_82541_2, WMP_F_1000T }, 630 631 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 632 "Intel i82547EI 1000BASE-T Ethernet", 633 WM_T_82547, WMP_F_1000T }, 634 635 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 636 "Intel i82547GI 1000BASE-T Ethernet", 637 WM_T_82547_2, WMP_F_1000T }, 638 { 0, 0, 639 NULL, 640 0, 0 }, 641 }; 642 643 #ifdef WM_EVENT_COUNTERS 644 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 645 #endif /* WM_EVENT_COUNTERS */ 646 647 #if 0 /* Not currently used */ 648 static __inline uint32_t 649 wm_io_read(struct wm_softc *sc, int reg) 650 { 651 652 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 653 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 654 } 655 #endif 656 657 static __inline void 658 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 659 { 660 661 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 662 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 663 } 664 665 static __inline void 666 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 667 { 668 wa->wa_low = htole32(v & 0xffffffffU); 669 if (sizeof(bus_addr_t) == 8) 670 wa->wa_high = htole32((uint64_t) v >> 32); 671 else 672 wa->wa_high = 0; 673 } 674 675 static const struct wm_product * 676 wm_lookup(const struct pci_attach_args *pa) 677 { 678 const struct wm_product *wmp; 679 680 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 681 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 682 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 683 return (wmp); 684 } 685 return (NULL); 686 } 687 688 static int 689 wm_match(struct device *parent, struct cfdata *cf, void *aux) 690 { 691 struct pci_attach_args *pa = aux; 692 693 if (wm_lookup(pa) != NULL) 694 return (1); 695 696 return (0); 697 } 698 699 static void 700 wm_attach(struct device *parent, struct device *self, void *aux) 701 { 702 struct wm_softc *sc = (void *) self; 703 struct pci_attach_args *pa = aux; 704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 705 pci_chipset_tag_t pc = pa->pa_pc; 706 pci_intr_handle_t ih; 707 size_t cdata_size; 708 const char *intrstr = NULL; 709 const char *eetype; 710 bus_space_tag_t memt; 711 bus_space_handle_t memh; 712 bus_dma_segment_t seg; 713 int memh_valid; 714 int i, rseg, error; 715 const struct wm_product *wmp; 716 uint8_t enaddr[ETHER_ADDR_LEN]; 717 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 718 pcireg_t preg, memtype; 719 uint32_t reg; 720 int pmreg; 721 722 callout_init(&sc->sc_tick_ch); 723 724 wmp = wm_lookup(pa); 725 if (wmp == NULL) { 726 printf("\n"); 727 panic("wm_attach: impossible"); 728 } 729 730 if (pci_dma64_available(pa)) 731 sc->sc_dmat = pa->pa_dmat64; 732 else 733 sc->sc_dmat = pa->pa_dmat; 734 735 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 736 aprint_naive(": Ethernet controller\n"); 737 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 738 739 sc->sc_type = wmp->wmp_type; 740 if (sc->sc_type < WM_T_82543) { 741 if (preg < 2) { 742 aprint_error("%s: i82542 must be at least rev. 2\n", 743 sc->sc_dev.dv_xname); 744 return; 745 } 746 if (preg < 3) 747 sc->sc_type = WM_T_82542_2_0; 748 } 749 750 /* 751 * Map the device. All devices support memory-mapped acccess, 752 * and it is really required for normal operation. 753 */ 754 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 755 switch (memtype) { 756 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 757 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 758 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 759 memtype, 0, &memt, &memh, NULL, NULL) == 0); 760 break; 761 default: 762 memh_valid = 0; 763 } 764 765 if (memh_valid) { 766 sc->sc_st = memt; 767 sc->sc_sh = memh; 768 } else { 769 aprint_error("%s: unable to map device registers\n", 770 sc->sc_dev.dv_xname); 771 return; 772 } 773 774 /* 775 * In addition, i82544 and later support I/O mapped indirect 776 * register access. It is not desirable (nor supported in 777 * this driver) to use it for normal operation, though it is 778 * required to work around bugs in some chip versions. 779 */ 780 if (sc->sc_type >= WM_T_82544) { 781 /* First we have to find the I/O BAR. */ 782 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 783 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 784 PCI_MAPREG_TYPE_IO) 785 break; 786 } 787 if (i == PCI_MAPREG_END) 788 aprint_error("%s: WARNING: unable to find I/O BAR\n", 789 sc->sc_dev.dv_xname); 790 else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 791 0, &sc->sc_iot, &sc->sc_ioh, 792 NULL, NULL) == 0) 793 sc->sc_flags |= WM_F_IOH_VALID; 794 else 795 aprint_error("%s: WARNING: unable to map I/O space\n", 796 sc->sc_dev.dv_xname); 797 } 798 799 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 800 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 801 preg |= PCI_COMMAND_MASTER_ENABLE; 802 if (sc->sc_type < WM_T_82542_2_1) 803 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 804 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 805 806 /* Get it out of power save mode, if needed. */ 807 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 808 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 809 PCI_PMCSR_STATE_MASK; 810 if (preg == PCI_PMCSR_STATE_D3) { 811 /* 812 * The card has lost all configuration data in 813 * this state, so punt. 814 */ 815 aprint_error("%s: unable to wake from power state D3\n", 816 sc->sc_dev.dv_xname); 817 return; 818 } 819 if (preg != PCI_PMCSR_STATE_D0) { 820 aprint_normal("%s: waking up from power state D%d\n", 821 sc->sc_dev.dv_xname, preg); 822 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 823 PCI_PMCSR_STATE_D0); 824 } 825 } 826 827 /* 828 * Map and establish our interrupt. 829 */ 830 if (pci_intr_map(pa, &ih)) { 831 aprint_error("%s: unable to map interrupt\n", 832 sc->sc_dev.dv_xname); 833 return; 834 } 835 intrstr = pci_intr_string(pc, ih); 836 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 837 if (sc->sc_ih == NULL) { 838 aprint_error("%s: unable to establish interrupt", 839 sc->sc_dev.dv_xname); 840 if (intrstr != NULL) 841 aprint_normal(" at %s", intrstr); 842 aprint_normal("\n"); 843 return; 844 } 845 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 846 847 /* 848 * Determine a few things about the bus we're connected to. 849 */ 850 if (sc->sc_type < WM_T_82543) { 851 /* We don't really know the bus characteristics here. */ 852 sc->sc_bus_speed = 33; 853 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 854 /* 855 * CSA (Communication Streaming Architecture) is about as fast 856 * a 32-bit 66MHz PCI Bus. 857 */ 858 sc->sc_flags |= WM_F_CSA; 859 sc->sc_bus_speed = 66; 860 aprint_verbose("%s: Communication Streaming Architecture\n", 861 sc->sc_dev.dv_xname); 862 if (sc->sc_type == WM_T_82547) { 863 callout_init(&sc->sc_txfifo_ch); 864 callout_setfunc(&sc->sc_txfifo_ch, 865 wm_82547_txfifo_stall, sc); 866 aprint_verbose("%s: using 82547 Tx FIFO stall " 867 "work-around\n", sc->sc_dev.dv_xname); 868 } 869 } else { 870 reg = CSR_READ(sc, WMREG_STATUS); 871 if (reg & STATUS_BUS64) 872 sc->sc_flags |= WM_F_BUS64; 873 if (sc->sc_type >= WM_T_82544 && 874 (reg & STATUS_PCIX_MODE) != 0) { 875 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 876 877 sc->sc_flags |= WM_F_PCIX; 878 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 879 PCI_CAP_PCIX, 880 &sc->sc_pcix_offset, NULL) == 0) 881 aprint_error("%s: unable to find PCIX " 882 "capability\n", sc->sc_dev.dv_xname); 883 else if (sc->sc_type != WM_T_82545_3 && 884 sc->sc_type != WM_T_82546_3) { 885 /* 886 * Work around a problem caused by the BIOS 887 * setting the max memory read byte count 888 * incorrectly. 889 */ 890 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 891 sc->sc_pcix_offset + PCI_PCIX_CMD); 892 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 893 sc->sc_pcix_offset + PCI_PCIX_STATUS); 894 895 bytecnt = 896 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 897 PCI_PCIX_CMD_BYTECNT_SHIFT; 898 maxb = 899 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 900 PCI_PCIX_STATUS_MAXB_SHIFT; 901 if (bytecnt > maxb) { 902 aprint_verbose("%s: resetting PCI-X " 903 "MMRBC: %d -> %d\n", 904 sc->sc_dev.dv_xname, 905 512 << bytecnt, 512 << maxb); 906 pcix_cmd = (pcix_cmd & 907 ~PCI_PCIX_CMD_BYTECNT_MASK) | 908 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 909 pci_conf_write(pa->pa_pc, pa->pa_tag, 910 sc->sc_pcix_offset + PCI_PCIX_CMD, 911 pcix_cmd); 912 } 913 } 914 } 915 /* 916 * The quad port adapter is special; it has a PCIX-PCIX 917 * bridge on the board, and can run the secondary bus at 918 * a higher speed. 919 */ 920 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 921 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 922 : 66; 923 } else if (sc->sc_flags & WM_F_PCIX) { 924 switch (reg & STATUS_PCIXSPD_MASK) { 925 case STATUS_PCIXSPD_50_66: 926 sc->sc_bus_speed = 66; 927 break; 928 case STATUS_PCIXSPD_66_100: 929 sc->sc_bus_speed = 100; 930 break; 931 case STATUS_PCIXSPD_100_133: 932 sc->sc_bus_speed = 133; 933 break; 934 default: 935 aprint_error( 936 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 937 sc->sc_dev.dv_xname, 938 reg & STATUS_PCIXSPD_MASK); 939 sc->sc_bus_speed = 66; 940 } 941 } else 942 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 943 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 944 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 945 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 946 } 947 948 /* 949 * Allocate the control data structures, and create and load the 950 * DMA map for it. 951 * 952 * NOTE: All Tx descriptors must be in the same 4G segment of 953 * memory. So must Rx descriptors. We simplify by allocating 954 * both sets within the same 4G segment. 955 */ 956 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 957 WM_NTXDESC_82542 : WM_NTXDESC_82544; 958 cdata_size = sc->sc_type < WM_T_82544 ? 959 sizeof(struct wm_control_data_82542) : 960 sizeof(struct wm_control_data_82544); 961 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 962 (bus_size_t) 0x100000000ULL, 963 &seg, 1, &rseg, 0)) != 0) { 964 aprint_error( 965 "%s: unable to allocate control data, error = %d\n", 966 sc->sc_dev.dv_xname, error); 967 goto fail_0; 968 } 969 970 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 971 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 972 aprint_error("%s: unable to map control data, error = %d\n", 973 sc->sc_dev.dv_xname, error); 974 goto fail_1; 975 } 976 977 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 978 0, 0, &sc->sc_cddmamap)) != 0) { 979 aprint_error("%s: unable to create control data DMA map, " 980 "error = %d\n", sc->sc_dev.dv_xname, error); 981 goto fail_2; 982 } 983 984 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 985 sc->sc_control_data, cdata_size, NULL, 986 0)) != 0) { 987 aprint_error( 988 "%s: unable to load control data DMA map, error = %d\n", 989 sc->sc_dev.dv_xname, error); 990 goto fail_3; 991 } 992 993 994 /* 995 * Create the transmit buffer DMA maps. 996 */ 997 WM_TXQUEUELEN(sc) = 998 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 999 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1000 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1001 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1002 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1003 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1004 aprint_error("%s: unable to create Tx DMA map %d, " 1005 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1006 goto fail_4; 1007 } 1008 } 1009 1010 /* 1011 * Create the receive buffer DMA maps. 1012 */ 1013 for (i = 0; i < WM_NRXDESC; i++) { 1014 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1015 MCLBYTES, 0, 0, 1016 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1017 aprint_error("%s: unable to create Rx DMA map %d, " 1018 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1019 goto fail_5; 1020 } 1021 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1022 } 1023 1024 /* 1025 * Reset the chip to a known state. 1026 */ 1027 wm_reset(sc); 1028 1029 /* 1030 * Get some information about the EEPROM. 1031 */ 1032 if (sc->sc_type >= WM_T_82540) 1033 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1034 if (sc->sc_type <= WM_T_82544) 1035 sc->sc_ee_addrbits = 6; 1036 else if (sc->sc_type <= WM_T_82546_3) { 1037 reg = CSR_READ(sc, WMREG_EECD); 1038 if (reg & EECD_EE_SIZE) 1039 sc->sc_ee_addrbits = 8; 1040 else 1041 sc->sc_ee_addrbits = 6; 1042 } else if (sc->sc_type <= WM_T_82547_2) { 1043 reg = CSR_READ(sc, WMREG_EECD); 1044 if (reg & EECD_EE_TYPE) { 1045 sc->sc_flags |= WM_F_EEPROM_SPI; 1046 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1047 } else 1048 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1049 } else { 1050 /* Assume everything else is SPI. */ 1051 reg = CSR_READ(sc, WMREG_EECD); 1052 sc->sc_flags |= WM_F_EEPROM_SPI; 1053 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1054 } 1055 if (sc->sc_flags & WM_F_EEPROM_SPI) 1056 eetype = "SPI"; 1057 else 1058 eetype = "MicroWire"; 1059 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1060 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1061 sc->sc_ee_addrbits, eetype); 1062 1063 /* 1064 * Read the Ethernet address from the EEPROM. 1065 */ 1066 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1067 sizeof(myea) / sizeof(myea[0]), myea)) { 1068 aprint_error("%s: unable to read Ethernet address\n", 1069 sc->sc_dev.dv_xname); 1070 return; 1071 } 1072 enaddr[0] = myea[0] & 0xff; 1073 enaddr[1] = myea[0] >> 8; 1074 enaddr[2] = myea[1] & 0xff; 1075 enaddr[3] = myea[1] >> 8; 1076 enaddr[4] = myea[2] & 0xff; 1077 enaddr[5] = myea[2] >> 8; 1078 1079 /* 1080 * Toggle the LSB of the MAC address on the second port 1081 * of the i82546. 1082 */ 1083 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1084 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1085 enaddr[5] ^= 1; 1086 } 1087 1088 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1089 ether_sprintf(enaddr)); 1090 1091 /* 1092 * Read the config info from the EEPROM, and set up various 1093 * bits in the control registers based on their contents. 1094 */ 1095 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1096 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1097 sc->sc_dev.dv_xname); 1098 return; 1099 } 1100 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1101 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1102 sc->sc_dev.dv_xname); 1103 return; 1104 } 1105 if (sc->sc_type >= WM_T_82544) { 1106 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1107 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1108 sc->sc_dev.dv_xname); 1109 return; 1110 } 1111 } 1112 1113 if (cfg1 & EEPROM_CFG1_ILOS) 1114 sc->sc_ctrl |= CTRL_ILOS; 1115 if (sc->sc_type >= WM_T_82544) { 1116 sc->sc_ctrl |= 1117 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1118 CTRL_SWDPIO_SHIFT; 1119 sc->sc_ctrl |= 1120 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1121 CTRL_SWDPINS_SHIFT; 1122 } else { 1123 sc->sc_ctrl |= 1124 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1125 CTRL_SWDPIO_SHIFT; 1126 } 1127 1128 #if 0 1129 if (sc->sc_type >= WM_T_82544) { 1130 if (cfg1 & EEPROM_CFG1_IPS0) 1131 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1132 if (cfg1 & EEPROM_CFG1_IPS1) 1133 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1134 sc->sc_ctrl_ext |= 1135 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1136 CTRL_EXT_SWDPIO_SHIFT; 1137 sc->sc_ctrl_ext |= 1138 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1139 CTRL_EXT_SWDPINS_SHIFT; 1140 } else { 1141 sc->sc_ctrl_ext |= 1142 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1143 CTRL_EXT_SWDPIO_SHIFT; 1144 } 1145 #endif 1146 1147 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1148 #if 0 1149 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1150 #endif 1151 1152 /* 1153 * Set up some register offsets that are different between 1154 * the i82542 and the i82543 and later chips. 1155 */ 1156 if (sc->sc_type < WM_T_82543) { 1157 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1158 sc->sc_tdt_reg = WMREG_OLD_TDT; 1159 } else { 1160 sc->sc_rdt_reg = WMREG_RDT; 1161 sc->sc_tdt_reg = WMREG_TDT; 1162 } 1163 1164 /* 1165 * Determine if we're TBI or GMII mode, and initialize the 1166 * media structures accordingly. 1167 */ 1168 if (sc->sc_type < WM_T_82543 || 1169 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1170 if (wmp->wmp_flags & WMP_F_1000T) 1171 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1172 "product!\n", sc->sc_dev.dv_xname); 1173 wm_tbi_mediainit(sc); 1174 } else { 1175 if (wmp->wmp_flags & WMP_F_1000X) 1176 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1177 "product!\n", sc->sc_dev.dv_xname); 1178 wm_gmii_mediainit(sc); 1179 } 1180 1181 ifp = &sc->sc_ethercom.ec_if; 1182 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1183 ifp->if_softc = sc; 1184 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1185 ifp->if_ioctl = wm_ioctl; 1186 ifp->if_start = wm_start; 1187 ifp->if_watchdog = wm_watchdog; 1188 ifp->if_init = wm_init; 1189 ifp->if_stop = wm_stop; 1190 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1191 IFQ_SET_READY(&ifp->if_snd); 1192 1193 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1194 1195 /* 1196 * If we're a i82543 or greater, we can support VLANs. 1197 */ 1198 if (sc->sc_type >= WM_T_82543) 1199 sc->sc_ethercom.ec_capabilities |= 1200 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1201 1202 /* 1203 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1204 * on i82543 and later. 1205 */ 1206 if (sc->sc_type >= WM_T_82543) 1207 ifp->if_capabilities |= 1208 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1209 1210 /* 1211 * Attach the interface. 1212 */ 1213 if_attach(ifp); 1214 ether_ifattach(ifp, enaddr); 1215 #if NRND > 0 1216 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1217 RND_TYPE_NET, 0); 1218 #endif 1219 1220 #ifdef WM_EVENT_COUNTERS 1221 /* Attach event counters. */ 1222 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1223 NULL, sc->sc_dev.dv_xname, "txsstall"); 1224 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1225 NULL, sc->sc_dev.dv_xname, "txdstall"); 1226 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1227 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1228 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1229 NULL, sc->sc_dev.dv_xname, "txdw"); 1230 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1231 NULL, sc->sc_dev.dv_xname, "txqe"); 1232 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1233 NULL, sc->sc_dev.dv_xname, "rxintr"); 1234 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1235 NULL, sc->sc_dev.dv_xname, "linkintr"); 1236 1237 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1238 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1239 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1240 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1241 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1242 NULL, sc->sc_dev.dv_xname, "txipsum"); 1243 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1244 NULL, sc->sc_dev.dv_xname, "txtusum"); 1245 1246 evcnt_attach_dynamic(&sc->sc_ev_txpullup_needed, EVCNT_TYPE_MISC, 1247 NULL, sc->sc_dev.dv_xname, "txpullup needed"); 1248 evcnt_attach_dynamic(&sc->sc_ev_txpullup_nomem, EVCNT_TYPE_MISC, 1249 NULL, sc->sc_dev.dv_xname, "txpullup nomem"); 1250 evcnt_attach_dynamic(&sc->sc_ev_txpullup_fail, EVCNT_TYPE_MISC, 1251 NULL, sc->sc_dev.dv_xname, "txpullup fail"); 1252 1253 for (i = 0; i < WM_NTXSEGS; i++) { 1254 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1255 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1256 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1257 } 1258 1259 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1260 NULL, sc->sc_dev.dv_xname, "txdrop"); 1261 1262 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1263 NULL, sc->sc_dev.dv_xname, "tu"); 1264 1265 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1266 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1267 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1268 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1269 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1270 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1271 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1272 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1273 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1274 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1275 #endif /* WM_EVENT_COUNTERS */ 1276 1277 /* 1278 * Make sure the interface is shutdown during reboot. 1279 */ 1280 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1281 if (sc->sc_sdhook == NULL) 1282 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1283 sc->sc_dev.dv_xname); 1284 return; 1285 1286 /* 1287 * Free any resources we've allocated during the failed attach 1288 * attempt. Do this in reverse order and fall through. 1289 */ 1290 fail_5: 1291 for (i = 0; i < WM_NRXDESC; i++) { 1292 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1293 bus_dmamap_destroy(sc->sc_dmat, 1294 sc->sc_rxsoft[i].rxs_dmamap); 1295 } 1296 fail_4: 1297 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1298 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1299 bus_dmamap_destroy(sc->sc_dmat, 1300 sc->sc_txsoft[i].txs_dmamap); 1301 } 1302 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1303 fail_3: 1304 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1305 fail_2: 1306 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1307 cdata_size); 1308 fail_1: 1309 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1310 fail_0: 1311 return; 1312 } 1313 1314 /* 1315 * wm_shutdown: 1316 * 1317 * Make sure the interface is stopped at reboot time. 1318 */ 1319 static void 1320 wm_shutdown(void *arg) 1321 { 1322 struct wm_softc *sc = arg; 1323 1324 wm_stop(&sc->sc_ethercom.ec_if, 1); 1325 } 1326 1327 /* 1328 * wm_tx_offload: 1329 * 1330 * Set up TCP/IP checksumming parameters for the 1331 * specified packet. 1332 */ 1333 static int 1334 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1335 uint8_t *fieldsp) 1336 { 1337 struct mbuf *m0 = txs->txs_mbuf; 1338 struct livengood_tcpip_ctxdesc *t; 1339 uint32_t ipcs, tucs; 1340 struct ip *ip; 1341 struct ether_header *eh; 1342 int offset, iphl; 1343 uint8_t fields = 0; 1344 1345 /* 1346 * XXX It would be nice if the mbuf pkthdr had offset 1347 * fields for the protocol headers. 1348 */ 1349 1350 eh = mtod(m0, struct ether_header *); 1351 switch (htons(eh->ether_type)) { 1352 case ETHERTYPE_IP: 1353 iphl = sizeof(struct ip); 1354 offset = ETHER_HDR_LEN; 1355 break; 1356 1357 case ETHERTYPE_VLAN: 1358 iphl = sizeof(struct ip); 1359 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1360 break; 1361 1362 default: 1363 /* 1364 * Don't support this protocol or encapsulation. 1365 */ 1366 *fieldsp = 0; 1367 *cmdp = 0; 1368 return (0); 1369 } 1370 1371 if (m0->m_len < (offset + iphl)) { 1372 /* 1373 * Packet headers aren't in the first mbuf. Let's hope 1374 * there is space at the end if it for them. 1375 */ 1376 WM_EVCNT_INCR(&sc->sc_ev_txpullup_needed); 1377 if ((txs->txs_mbuf = m_pullup(m0, offset + iphl)) == NULL) { 1378 WM_EVCNT_INCR(&sc->sc_ev_txpullup_nomem); 1379 log(LOG_ERR, 1380 "%s: wm_tx_offload: mbuf allocation failed, " 1381 "packet dropped\n", sc->sc_dev.dv_xname); 1382 return (ENOMEM); 1383 } else if (m0 != txs->txs_mbuf) { 1384 /* 1385 * The DMA map has already been loaded, so we 1386 * would have to unload and reload it. But then 1387 * if that were to fail, we are already committed 1388 * to transmitting the packet (can't put it back 1389 * on the queue), so we have to drop the packet. 1390 */ 1391 WM_EVCNT_INCR(&sc->sc_ev_txpullup_fail); 1392 log(LOG_ERR, "%s: wm_tx_offload: packet headers did " 1393 "not fit in first mbuf, packet dropped\n", 1394 sc->sc_dev.dv_xname); 1395 m_freem(txs->txs_mbuf); 1396 txs->txs_mbuf = NULL; 1397 return (EINVAL); 1398 } 1399 } 1400 1401 ip = (struct ip *) (mtod(m0, caddr_t) + offset); 1402 iphl = ip->ip_hl << 2; 1403 1404 /* 1405 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1406 * offload feature, if we load the context descriptor, we 1407 * MUST provide valid values for IPCSS and TUCSS fields. 1408 */ 1409 1410 ipcs = WTX_TCPIP_IPCSS(offset) | 1411 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1412 WTX_TCPIP_IPCSE(offset + iphl - 1); 1413 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1414 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1415 fields |= WTX_IXSM; 1416 } 1417 1418 offset += iphl; 1419 1420 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1421 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1422 fields |= WTX_TXSM; 1423 tucs = WTX_TCPIP_TUCSS(offset) | 1424 WTX_TCPIP_TUCSO(offset + m0->m_pkthdr.csum_data) | 1425 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1426 } else { 1427 /* Just initialize it to a valid TCP context. */ 1428 tucs = WTX_TCPIP_TUCSS(offset) | 1429 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1430 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1431 } 1432 1433 /* Fill in the context descriptor. */ 1434 t = (struct livengood_tcpip_ctxdesc *) 1435 &sc->sc_txdescs[sc->sc_txnext]; 1436 t->tcpip_ipcs = htole32(ipcs); 1437 t->tcpip_tucs = htole32(tucs); 1438 t->tcpip_cmdlen = htole32(WTX_CMD_DEXT | WTX_DTYP_C); 1439 t->tcpip_seg = 0; 1440 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1441 1442 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1443 txs->txs_ndesc++; 1444 1445 *cmdp = WTX_CMD_DEXT | WTX_DTYP_D; 1446 *fieldsp = fields; 1447 1448 return (0); 1449 } 1450 1451 static void 1452 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1453 { 1454 struct mbuf *m; 1455 int i; 1456 1457 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1458 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1459 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1460 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1461 m->m_data, m->m_len, m->m_flags); 1462 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1463 i, i == 1 ? "" : "s"); 1464 } 1465 1466 /* 1467 * wm_82547_txfifo_stall: 1468 * 1469 * Callout used to wait for the 82547 Tx FIFO to drain, 1470 * reset the FIFO pointers, and restart packet transmission. 1471 */ 1472 static void 1473 wm_82547_txfifo_stall(void *arg) 1474 { 1475 struct wm_softc *sc = arg; 1476 int s; 1477 1478 s = splnet(); 1479 1480 if (sc->sc_txfifo_stall) { 1481 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1482 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1483 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1484 /* 1485 * Packets have drained. Stop transmitter, reset 1486 * FIFO pointers, restart transmitter, and kick 1487 * the packet queue. 1488 */ 1489 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1490 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1491 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1492 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1493 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1494 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1495 CSR_WRITE(sc, WMREG_TCTL, tctl); 1496 CSR_WRITE_FLUSH(sc); 1497 1498 sc->sc_txfifo_head = 0; 1499 sc->sc_txfifo_stall = 0; 1500 wm_start(&sc->sc_ethercom.ec_if); 1501 } else { 1502 /* 1503 * Still waiting for packets to drain; try again in 1504 * another tick. 1505 */ 1506 callout_schedule(&sc->sc_txfifo_ch, 1); 1507 } 1508 } 1509 1510 splx(s); 1511 } 1512 1513 /* 1514 * wm_82547_txfifo_bugchk: 1515 * 1516 * Check for bug condition in the 82547 Tx FIFO. We need to 1517 * prevent enqueueing a packet that would wrap around the end 1518 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1519 * 1520 * We do this by checking the amount of space before the end 1521 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1522 * the Tx FIFO, wait for all remaining packets to drain, reset 1523 * the internal FIFO pointers to the beginning, and restart 1524 * transmission on the interface. 1525 */ 1526 #define WM_FIFO_HDR 0x10 1527 #define WM_82547_PAD_LEN 0x3e0 1528 static int 1529 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1530 { 1531 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1532 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1533 1534 /* Just return if already stalled. */ 1535 if (sc->sc_txfifo_stall) 1536 return (1); 1537 1538 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1539 /* Stall only occurs in half-duplex mode. */ 1540 goto send_packet; 1541 } 1542 1543 if (len >= WM_82547_PAD_LEN + space) { 1544 sc->sc_txfifo_stall = 1; 1545 callout_schedule(&sc->sc_txfifo_ch, 1); 1546 return (1); 1547 } 1548 1549 send_packet: 1550 sc->sc_txfifo_head += len; 1551 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1552 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1553 1554 return (0); 1555 } 1556 1557 /* 1558 * wm_start: [ifnet interface function] 1559 * 1560 * Start packet transmission on the interface. 1561 */ 1562 static void 1563 wm_start(struct ifnet *ifp) 1564 { 1565 struct wm_softc *sc = ifp->if_softc; 1566 struct mbuf *m0; 1567 #if 0 /* XXXJRT */ 1568 struct m_tag *mtag; 1569 #endif 1570 struct wm_txsoft *txs; 1571 bus_dmamap_t dmamap; 1572 int error, nexttx, lasttx = -1, ofree, seg, segs_needed; 1573 bus_addr_t curaddr; 1574 bus_size_t seglen, curlen; 1575 uint32_t cksumcmd; 1576 uint8_t cksumfields; 1577 1578 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1579 return; 1580 1581 /* 1582 * Remember the previous number of free descriptors. 1583 */ 1584 ofree = sc->sc_txfree; 1585 1586 /* 1587 * Loop through the send queue, setting up transmit descriptors 1588 * until we drain the queue, or use up all available transmit 1589 * descriptors. 1590 */ 1591 for (;;) { 1592 /* Grab a packet off the queue. */ 1593 IFQ_POLL(&ifp->if_snd, m0); 1594 if (m0 == NULL) 1595 break; 1596 1597 DPRINTF(WM_DEBUG_TX, 1598 ("%s: TX: have packet to transmit: %p\n", 1599 sc->sc_dev.dv_xname, m0)); 1600 1601 /* Get a work queue entry. */ 1602 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1603 wm_txintr(sc); 1604 if (sc->sc_txsfree == 0) { 1605 DPRINTF(WM_DEBUG_TX, 1606 ("%s: TX: no free job descriptors\n", 1607 sc->sc_dev.dv_xname)); 1608 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1609 break; 1610 } 1611 } 1612 1613 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1614 dmamap = txs->txs_dmamap; 1615 1616 /* 1617 * Load the DMA map. If this fails, the packet either 1618 * didn't fit in the allotted number of segments, or we 1619 * were short on resources. For the too-many-segments 1620 * case, we simply report an error and drop the packet, 1621 * since we can't sanely copy a jumbo packet to a single 1622 * buffer. 1623 */ 1624 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1625 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1626 if (error) { 1627 if (error == EFBIG) { 1628 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1629 log(LOG_ERR, "%s: Tx packet consumes too many " 1630 "DMA segments, dropping...\n", 1631 sc->sc_dev.dv_xname); 1632 IFQ_DEQUEUE(&ifp->if_snd, m0); 1633 wm_dump_mbuf_chain(sc, m0); 1634 m_freem(m0); 1635 continue; 1636 } 1637 /* 1638 * Short on resources, just stop for now. 1639 */ 1640 DPRINTF(WM_DEBUG_TX, 1641 ("%s: TX: dmamap load failed: %d\n", 1642 sc->sc_dev.dv_xname, error)); 1643 break; 1644 } 1645 1646 segs_needed = dmamap->dm_nsegs; 1647 1648 /* 1649 * Ensure we have enough descriptors free to describe 1650 * the packet. Note, we always reserve one descriptor 1651 * at the end of the ring due to the semantics of the 1652 * TDT register, plus one more in the event we need 1653 * to load offload context. 1654 */ 1655 if (segs_needed > sc->sc_txfree - 2) { 1656 /* 1657 * Not enough free descriptors to transmit this 1658 * packet. We haven't committed anything yet, 1659 * so just unload the DMA map, put the packet 1660 * pack on the queue, and punt. Notify the upper 1661 * layer that there are no more slots left. 1662 */ 1663 DPRINTF(WM_DEBUG_TX, 1664 ("%s: TX: need %d (%) descriptors, have %d\n", 1665 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1666 sc->sc_txfree - 1)); 1667 ifp->if_flags |= IFF_OACTIVE; 1668 bus_dmamap_unload(sc->sc_dmat, dmamap); 1669 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1670 break; 1671 } 1672 1673 /* 1674 * Check for 82547 Tx FIFO bug. We need to do this 1675 * once we know we can transmit the packet, since we 1676 * do some internal FIFO space accounting here. 1677 */ 1678 if (sc->sc_type == WM_T_82547 && 1679 wm_82547_txfifo_bugchk(sc, m0)) { 1680 DPRINTF(WM_DEBUG_TX, 1681 ("%s: TX: 82547 Tx FIFO bug detected\n", 1682 sc->sc_dev.dv_xname)); 1683 ifp->if_flags |= IFF_OACTIVE; 1684 bus_dmamap_unload(sc->sc_dmat, dmamap); 1685 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1686 break; 1687 } 1688 1689 IFQ_DEQUEUE(&ifp->if_snd, m0); 1690 1691 /* 1692 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1693 */ 1694 1695 DPRINTF(WM_DEBUG_TX, 1696 ("%s: TX: packet has %d (%d) DMA segments\n", 1697 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1698 1699 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1700 1701 /* 1702 * Store a pointer to the packet so that we can free it 1703 * later. 1704 * 1705 * Initially, we consider the number of descriptors the 1706 * packet uses the number of DMA segments. This may be 1707 * incremented by 1 if we do checksum offload (a descriptor 1708 * is used to set the checksum context). 1709 */ 1710 txs->txs_mbuf = m0; 1711 txs->txs_firstdesc = sc->sc_txnext; 1712 txs->txs_ndesc = segs_needed; 1713 1714 /* Set up offload parameters for this packet. */ 1715 if (m0->m_pkthdr.csum_flags & 1716 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1717 if (wm_tx_offload(sc, txs, &cksumcmd, 1718 &cksumfields) != 0) { 1719 /* Error message already displayed. */ 1720 bus_dmamap_unload(sc->sc_dmat, dmamap); 1721 continue; 1722 } 1723 } else { 1724 cksumcmd = 0; 1725 cksumfields = 0; 1726 } 1727 1728 cksumcmd |= WTX_CMD_IDE; 1729 1730 /* Sync the DMA map. */ 1731 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1732 BUS_DMASYNC_PREWRITE); 1733 1734 /* 1735 * Initialize the transmit descriptor. 1736 */ 1737 for (nexttx = sc->sc_txnext, seg = 0; 1738 seg < dmamap->dm_nsegs; seg++) { 1739 for (seglen = dmamap->dm_segs[seg].ds_len, 1740 curaddr = dmamap->dm_segs[seg].ds_addr; 1741 seglen != 0; 1742 curaddr += curlen, seglen -= curlen, 1743 nexttx = WM_NEXTTX(sc, nexttx)) { 1744 curlen = seglen; 1745 1746 wm_set_dma_addr( 1747 &sc->sc_txdescs[nexttx].wtx_addr, 1748 curaddr); 1749 sc->sc_txdescs[nexttx].wtx_cmdlen = 1750 htole32(cksumcmd | curlen); 1751 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1752 0; 1753 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1754 cksumfields; 1755 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1756 lasttx = nexttx; 1757 1758 DPRINTF(WM_DEBUG_TX, 1759 ("%s: TX: desc %d: low 0x%08x, " 1760 "len 0x%04x\n", 1761 sc->sc_dev.dv_xname, nexttx, 1762 curaddr & 0xffffffffU, curlen, curlen)); 1763 } 1764 } 1765 1766 KASSERT(lasttx != -1); 1767 1768 /* 1769 * Set up the command byte on the last descriptor of 1770 * the packet. If we're in the interrupt delay window, 1771 * delay the interrupt. 1772 */ 1773 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1774 htole32(WTX_CMD_EOP | WTX_CMD_IFCS | WTX_CMD_RS); 1775 1776 #if 0 /* XXXJRT */ 1777 /* 1778 * If VLANs are enabled and the packet has a VLAN tag, set 1779 * up the descriptor to encapsulate the packet for us. 1780 * 1781 * This is only valid on the last descriptor of the packet. 1782 */ 1783 if (sc->sc_ethercom.ec_nvlans != 0 && 1784 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1785 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1786 htole32(WTX_CMD_VLE); 1787 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1788 = htole16(*(u_int *)(mtag + 1) & 0xffff); 1789 } 1790 #endif /* XXXJRT */ 1791 1792 txs->txs_lastdesc = lasttx; 1793 1794 DPRINTF(WM_DEBUG_TX, 1795 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1796 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1797 1798 /* Sync the descriptors we're using. */ 1799 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1800 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1801 1802 /* Give the packet to the chip. */ 1803 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1804 1805 DPRINTF(WM_DEBUG_TX, 1806 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1807 1808 DPRINTF(WM_DEBUG_TX, 1809 ("%s: TX: finished transmitting packet, job %d\n", 1810 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1811 1812 /* Advance the tx pointer. */ 1813 sc->sc_txfree -= txs->txs_ndesc; 1814 sc->sc_txnext = nexttx; 1815 1816 sc->sc_txsfree--; 1817 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1818 1819 #if NBPFILTER > 0 1820 /* Pass the packet to any BPF listeners. */ 1821 if (ifp->if_bpf) 1822 bpf_mtap(ifp->if_bpf, m0); 1823 #endif /* NBPFILTER > 0 */ 1824 } 1825 1826 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1827 /* No more slots; notify upper layer. */ 1828 ifp->if_flags |= IFF_OACTIVE; 1829 } 1830 1831 if (sc->sc_txfree != ofree) { 1832 /* Set a watchdog timer in case the chip flakes out. */ 1833 ifp->if_timer = 5; 1834 } 1835 } 1836 1837 /* 1838 * wm_watchdog: [ifnet interface function] 1839 * 1840 * Watchdog timer handler. 1841 */ 1842 static void 1843 wm_watchdog(struct ifnet *ifp) 1844 { 1845 struct wm_softc *sc = ifp->if_softc; 1846 1847 /* 1848 * Since we're using delayed interrupts, sweep up 1849 * before we report an error. 1850 */ 1851 wm_txintr(sc); 1852 1853 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1854 log(LOG_ERR, 1855 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1856 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1857 sc->sc_txnext); 1858 ifp->if_oerrors++; 1859 1860 /* Reset the interface. */ 1861 (void) wm_init(ifp); 1862 } 1863 1864 /* Try to get more packets going. */ 1865 wm_start(ifp); 1866 } 1867 1868 /* 1869 * wm_ioctl: [ifnet interface function] 1870 * 1871 * Handle control requests from the operator. 1872 */ 1873 static int 1874 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1875 { 1876 struct wm_softc *sc = ifp->if_softc; 1877 struct ifreq *ifr = (struct ifreq *) data; 1878 int s, error; 1879 1880 s = splnet(); 1881 1882 switch (cmd) { 1883 case SIOCSIFMEDIA: 1884 case SIOCGIFMEDIA: 1885 /* Flow control requires full-duplex mode. */ 1886 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1887 (ifr->ifr_media & IFM_FDX) == 0) 1888 ifr->ifr_media &= ~IFM_ETH_FMASK; 1889 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1890 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1891 /* We can do both TXPAUSE and RXPAUSE. */ 1892 ifr->ifr_media |= 1893 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1894 } 1895 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1896 } 1897 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1898 break; 1899 default: 1900 error = ether_ioctl(ifp, cmd, data); 1901 if (error == ENETRESET) { 1902 /* 1903 * Multicast list has changed; set the hardware filter 1904 * accordingly. 1905 */ 1906 if (ifp->if_flags & IFF_RUNNING) 1907 wm_set_filter(sc); 1908 error = 0; 1909 } 1910 break; 1911 } 1912 1913 /* Try to get more packets going. */ 1914 wm_start(ifp); 1915 1916 splx(s); 1917 return (error); 1918 } 1919 1920 /* 1921 * wm_intr: 1922 * 1923 * Interrupt service routine. 1924 */ 1925 static int 1926 wm_intr(void *arg) 1927 { 1928 struct wm_softc *sc = arg; 1929 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1930 uint32_t icr; 1931 int wantinit, handled = 0; 1932 1933 for (wantinit = 0; wantinit == 0;) { 1934 icr = CSR_READ(sc, WMREG_ICR); 1935 if ((icr & sc->sc_icr) == 0) 1936 break; 1937 1938 #if 0 /*NRND > 0*/ 1939 if (RND_ENABLED(&sc->rnd_source)) 1940 rnd_add_uint32(&sc->rnd_source, icr); 1941 #endif 1942 1943 handled = 1; 1944 1945 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1946 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1947 DPRINTF(WM_DEBUG_RX, 1948 ("%s: RX: got Rx intr 0x%08x\n", 1949 sc->sc_dev.dv_xname, 1950 icr & (ICR_RXDMT0|ICR_RXT0))); 1951 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 1952 } 1953 #endif 1954 wm_rxintr(sc); 1955 1956 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1957 if (icr & ICR_TXDW) { 1958 DPRINTF(WM_DEBUG_TX, 1959 ("%s: TX: got TXDW interrupt\n", 1960 sc->sc_dev.dv_xname)); 1961 WM_EVCNT_INCR(&sc->sc_ev_txdw); 1962 } 1963 #endif 1964 wm_txintr(sc); 1965 1966 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 1967 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 1968 wm_linkintr(sc, icr); 1969 } 1970 1971 if (icr & ICR_RXO) { 1972 log(LOG_WARNING, "%s: Receive overrun\n", 1973 sc->sc_dev.dv_xname); 1974 wantinit = 1; 1975 } 1976 } 1977 1978 if (handled) { 1979 if (wantinit) 1980 wm_init(ifp); 1981 1982 /* Try to get more packets going. */ 1983 wm_start(ifp); 1984 } 1985 1986 return (handled); 1987 } 1988 1989 /* 1990 * wm_txintr: 1991 * 1992 * Helper; handle transmit interrupts. 1993 */ 1994 static void 1995 wm_txintr(struct wm_softc *sc) 1996 { 1997 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1998 struct wm_txsoft *txs; 1999 uint8_t status; 2000 int i; 2001 2002 ifp->if_flags &= ~IFF_OACTIVE; 2003 2004 /* 2005 * Go through the Tx list and free mbufs for those 2006 * frames which have been transmitted. 2007 */ 2008 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2009 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2010 txs = &sc->sc_txsoft[i]; 2011 2012 DPRINTF(WM_DEBUG_TX, 2013 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2014 2015 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2016 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2017 2018 status = 2019 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2020 if ((status & WTX_ST_DD) == 0) { 2021 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2022 BUS_DMASYNC_PREREAD); 2023 break; 2024 } 2025 2026 DPRINTF(WM_DEBUG_TX, 2027 ("%s: TX: job %d done: descs %d..%d\n", 2028 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2029 txs->txs_lastdesc)); 2030 2031 /* 2032 * XXX We should probably be using the statistics 2033 * XXX registers, but I don't know if they exist 2034 * XXX on chips before the i82544. 2035 */ 2036 2037 #ifdef WM_EVENT_COUNTERS 2038 if (status & WTX_ST_TU) 2039 WM_EVCNT_INCR(&sc->sc_ev_tu); 2040 #endif /* WM_EVENT_COUNTERS */ 2041 2042 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2043 ifp->if_oerrors++; 2044 if (status & WTX_ST_LC) 2045 log(LOG_WARNING, "%s: late collision\n", 2046 sc->sc_dev.dv_xname); 2047 else if (status & WTX_ST_EC) { 2048 ifp->if_collisions += 16; 2049 log(LOG_WARNING, "%s: excessive collisions\n", 2050 sc->sc_dev.dv_xname); 2051 } 2052 } else 2053 ifp->if_opackets++; 2054 2055 sc->sc_txfree += txs->txs_ndesc; 2056 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2057 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2058 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2059 m_freem(txs->txs_mbuf); 2060 txs->txs_mbuf = NULL; 2061 } 2062 2063 /* Update the dirty transmit buffer pointer. */ 2064 sc->sc_txsdirty = i; 2065 DPRINTF(WM_DEBUG_TX, 2066 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2067 2068 /* 2069 * If there are no more pending transmissions, cancel the watchdog 2070 * timer. 2071 */ 2072 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2073 ifp->if_timer = 0; 2074 } 2075 2076 /* 2077 * wm_rxintr: 2078 * 2079 * Helper; handle receive interrupts. 2080 */ 2081 static void 2082 wm_rxintr(struct wm_softc *sc) 2083 { 2084 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2085 struct wm_rxsoft *rxs; 2086 struct mbuf *m; 2087 int i, len; 2088 uint8_t status, errors; 2089 2090 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2091 rxs = &sc->sc_rxsoft[i]; 2092 2093 DPRINTF(WM_DEBUG_RX, 2094 ("%s: RX: checking descriptor %d\n", 2095 sc->sc_dev.dv_xname, i)); 2096 2097 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2098 2099 status = sc->sc_rxdescs[i].wrx_status; 2100 errors = sc->sc_rxdescs[i].wrx_errors; 2101 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2102 2103 if ((status & WRX_ST_DD) == 0) { 2104 /* 2105 * We have processed all of the receive descriptors. 2106 */ 2107 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2108 break; 2109 } 2110 2111 if (__predict_false(sc->sc_rxdiscard)) { 2112 DPRINTF(WM_DEBUG_RX, 2113 ("%s: RX: discarding contents of descriptor %d\n", 2114 sc->sc_dev.dv_xname, i)); 2115 WM_INIT_RXDESC(sc, i); 2116 if (status & WRX_ST_EOP) { 2117 /* Reset our state. */ 2118 DPRINTF(WM_DEBUG_RX, 2119 ("%s: RX: resetting rxdiscard -> 0\n", 2120 sc->sc_dev.dv_xname)); 2121 sc->sc_rxdiscard = 0; 2122 } 2123 continue; 2124 } 2125 2126 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2127 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2128 2129 m = rxs->rxs_mbuf; 2130 2131 /* 2132 * Add a new receive buffer to the ring. 2133 */ 2134 if (wm_add_rxbuf(sc, i) != 0) { 2135 /* 2136 * Failed, throw away what we've done so 2137 * far, and discard the rest of the packet. 2138 */ 2139 ifp->if_ierrors++; 2140 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2141 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2142 WM_INIT_RXDESC(sc, i); 2143 if ((status & WRX_ST_EOP) == 0) 2144 sc->sc_rxdiscard = 1; 2145 if (sc->sc_rxhead != NULL) 2146 m_freem(sc->sc_rxhead); 2147 WM_RXCHAIN_RESET(sc); 2148 DPRINTF(WM_DEBUG_RX, 2149 ("%s: RX: Rx buffer allocation failed, " 2150 "dropping packet%s\n", sc->sc_dev.dv_xname, 2151 sc->sc_rxdiscard ? " (discard)" : "")); 2152 continue; 2153 } 2154 2155 WM_RXCHAIN_LINK(sc, m); 2156 2157 m->m_len = len; 2158 2159 DPRINTF(WM_DEBUG_RX, 2160 ("%s: RX: buffer at %p len %d\n", 2161 sc->sc_dev.dv_xname, m->m_data, len)); 2162 2163 /* 2164 * If this is not the end of the packet, keep 2165 * looking. 2166 */ 2167 if ((status & WRX_ST_EOP) == 0) { 2168 sc->sc_rxlen += len; 2169 DPRINTF(WM_DEBUG_RX, 2170 ("%s: RX: not yet EOP, rxlen -> %d\n", 2171 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2172 continue; 2173 } 2174 2175 /* 2176 * Okay, we have the entire packet now... 2177 */ 2178 *sc->sc_rxtailp = NULL; 2179 m = sc->sc_rxhead; 2180 len += sc->sc_rxlen; 2181 2182 WM_RXCHAIN_RESET(sc); 2183 2184 DPRINTF(WM_DEBUG_RX, 2185 ("%s: RX: have entire packet, len -> %d\n", 2186 sc->sc_dev.dv_xname, len)); 2187 2188 /* 2189 * If an error occurred, update stats and drop the packet. 2190 */ 2191 if (errors & 2192 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2193 ifp->if_ierrors++; 2194 if (errors & WRX_ER_SE) 2195 log(LOG_WARNING, "%s: symbol error\n", 2196 sc->sc_dev.dv_xname); 2197 else if (errors & WRX_ER_SEQ) 2198 log(LOG_WARNING, "%s: receive sequence error\n", 2199 sc->sc_dev.dv_xname); 2200 else if (errors & WRX_ER_CE) 2201 log(LOG_WARNING, "%s: CRC error\n", 2202 sc->sc_dev.dv_xname); 2203 m_freem(m); 2204 continue; 2205 } 2206 2207 /* 2208 * No errors. Receive the packet. 2209 * 2210 * Note, we have configured the chip to include the 2211 * CRC with every packet. 2212 */ 2213 m->m_flags |= M_HASFCS; 2214 m->m_pkthdr.rcvif = ifp; 2215 m->m_pkthdr.len = len; 2216 2217 #if 0 /* XXXJRT */ 2218 /* 2219 * If VLANs are enabled, VLAN packets have been unwrapped 2220 * for us. Associate the tag with the packet. 2221 */ 2222 if (sc->sc_ethercom.ec_nvlans != 0 && 2223 (status & WRX_ST_VP) != 0) { 2224 struct m_tag *vtag; 2225 2226 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2227 M_NOWAIT); 2228 if (vtag == NULL) { 2229 ifp->if_ierrors++; 2230 log(LOG_ERR, 2231 "%s: unable to allocate VLAN tag\n", 2232 sc->sc_dev.dv_xname); 2233 m_freem(m); 2234 continue; 2235 } 2236 2237 *(u_int *)(vtag + 1) = 2238 le16toh(sc->sc_rxdescs[i].wrx_special); 2239 } 2240 #endif /* XXXJRT */ 2241 2242 /* 2243 * Set up checksum info for this packet. 2244 */ 2245 if (status & WRX_ST_IPCS) { 2246 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2247 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2248 if (errors & WRX_ER_IPE) 2249 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2250 } 2251 if (status & WRX_ST_TCPCS) { 2252 /* 2253 * Note: we don't know if this was TCP or UDP, 2254 * so we just set both bits, and expect the 2255 * upper layers to deal. 2256 */ 2257 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2258 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2259 if (errors & WRX_ER_TCPE) 2260 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2261 } 2262 2263 ifp->if_ipackets++; 2264 2265 #if NBPFILTER > 0 2266 /* Pass this up to any BPF listeners. */ 2267 if (ifp->if_bpf) 2268 bpf_mtap(ifp->if_bpf, m); 2269 #endif /* NBPFILTER > 0 */ 2270 2271 /* Pass it on. */ 2272 (*ifp->if_input)(ifp, m); 2273 } 2274 2275 /* Update the receive pointer. */ 2276 sc->sc_rxptr = i; 2277 2278 DPRINTF(WM_DEBUG_RX, 2279 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2280 } 2281 2282 /* 2283 * wm_linkintr: 2284 * 2285 * Helper; handle link interrupts. 2286 */ 2287 static void 2288 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2289 { 2290 uint32_t status; 2291 2292 /* 2293 * If we get a link status interrupt on a 1000BASE-T 2294 * device, just fall into the normal MII tick path. 2295 */ 2296 if (sc->sc_flags & WM_F_HAS_MII) { 2297 if (icr & ICR_LSC) { 2298 DPRINTF(WM_DEBUG_LINK, 2299 ("%s: LINK: LSC -> mii_tick\n", 2300 sc->sc_dev.dv_xname)); 2301 mii_tick(&sc->sc_mii); 2302 } else if (icr & ICR_RXSEQ) { 2303 DPRINTF(WM_DEBUG_LINK, 2304 ("%s: LINK Receive sequence error\n", 2305 sc->sc_dev.dv_xname)); 2306 } 2307 return; 2308 } 2309 2310 /* 2311 * If we are now receiving /C/, check for link again in 2312 * a couple of link clock ticks. 2313 */ 2314 if (icr & ICR_RXCFG) { 2315 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2316 sc->sc_dev.dv_xname)); 2317 sc->sc_tbi_anstate = 2; 2318 } 2319 2320 if (icr & ICR_LSC) { 2321 status = CSR_READ(sc, WMREG_STATUS); 2322 if (status & STATUS_LU) { 2323 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2324 sc->sc_dev.dv_xname, 2325 (status & STATUS_FD) ? "FDX" : "HDX")); 2326 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2327 sc->sc_fcrtl &= ~FCRTL_XONE; 2328 if (status & STATUS_FD) 2329 sc->sc_tctl |= 2330 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2331 else 2332 sc->sc_tctl |= 2333 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2334 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2335 sc->sc_fcrtl |= FCRTL_XONE; 2336 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2337 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2338 WMREG_OLD_FCRTL : WMREG_FCRTL, 2339 sc->sc_fcrtl); 2340 sc->sc_tbi_linkup = 1; 2341 } else { 2342 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2343 sc->sc_dev.dv_xname)); 2344 sc->sc_tbi_linkup = 0; 2345 } 2346 sc->sc_tbi_anstate = 2; 2347 wm_tbi_set_linkled(sc); 2348 } else if (icr & ICR_RXSEQ) { 2349 DPRINTF(WM_DEBUG_LINK, 2350 ("%s: LINK: Receive sequence error\n", 2351 sc->sc_dev.dv_xname)); 2352 } 2353 } 2354 2355 /* 2356 * wm_tick: 2357 * 2358 * One second timer, used to check link status, sweep up 2359 * completed transmit jobs, etc. 2360 */ 2361 static void 2362 wm_tick(void *arg) 2363 { 2364 struct wm_softc *sc = arg; 2365 int s; 2366 2367 s = splnet(); 2368 2369 if (sc->sc_type >= WM_T_82542_2_1) { 2370 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2371 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2372 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2373 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2374 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2375 } 2376 2377 if (sc->sc_flags & WM_F_HAS_MII) 2378 mii_tick(&sc->sc_mii); 2379 else 2380 wm_tbi_check_link(sc); 2381 2382 splx(s); 2383 2384 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2385 } 2386 2387 /* 2388 * wm_reset: 2389 * 2390 * Reset the i82542 chip. 2391 */ 2392 static void 2393 wm_reset(struct wm_softc *sc) 2394 { 2395 int i; 2396 2397 /* 2398 * Allocate on-chip memory according to the MTU size. 2399 * The Packet Buffer Allocation register must be written 2400 * before the chip is reset. 2401 */ 2402 if (sc->sc_type < WM_T_82547) { 2403 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2404 PBA_40K : PBA_48K; 2405 } else { 2406 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2407 PBA_22K : PBA_30K; 2408 sc->sc_txfifo_head = 0; 2409 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2410 sc->sc_txfifo_size = 2411 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2412 sc->sc_txfifo_stall = 0; 2413 } 2414 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2415 2416 switch (sc->sc_type) { 2417 case WM_T_82544: 2418 case WM_T_82540: 2419 case WM_T_82545: 2420 case WM_T_82546: 2421 case WM_T_82541: 2422 case WM_T_82541_2: 2423 /* 2424 * These chips have a problem with the memory-mapped 2425 * write cycle when issuing the reset, so use I/O-mapped 2426 * access, if possible. 2427 */ 2428 if (sc->sc_flags & WM_F_IOH_VALID) 2429 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2430 else 2431 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2432 break; 2433 2434 case WM_T_82545_3: 2435 case WM_T_82546_3: 2436 /* Use the shadow control register on these chips. */ 2437 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2438 break; 2439 2440 default: 2441 /* Everything else can safely use the documented method. */ 2442 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2443 break; 2444 } 2445 delay(10000); 2446 2447 for (i = 0; i < 1000; i++) { 2448 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2449 return; 2450 delay(20); 2451 } 2452 2453 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2454 log(LOG_ERR, "%s: reset failed to complete\n", 2455 sc->sc_dev.dv_xname); 2456 } 2457 2458 /* 2459 * wm_init: [ifnet interface function] 2460 * 2461 * Initialize the interface. Must be called at splnet(). 2462 */ 2463 static int 2464 wm_init(struct ifnet *ifp) 2465 { 2466 struct wm_softc *sc = ifp->if_softc; 2467 struct wm_rxsoft *rxs; 2468 int i, error = 0; 2469 uint32_t reg; 2470 2471 /* 2472 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2473 * There is a small but measurable benefit to avoiding the adjusment 2474 * of the descriptor so that the headers are aligned, for normal mtu, 2475 * on such platforms. One possibility is that the DMA itself is 2476 * slightly more efficient if the front of the entire packet (instead 2477 * of the front of the headers) is aligned. 2478 * 2479 * Note we must always set align_tweak to 0 if we are using 2480 * jumbo frames. 2481 */ 2482 #ifdef __NO_STRICT_ALIGNMENT 2483 sc->sc_align_tweak = 0; 2484 #else 2485 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2486 sc->sc_align_tweak = 0; 2487 else 2488 sc->sc_align_tweak = 2; 2489 #endif /* __NO_STRICT_ALIGNMENT */ 2490 2491 /* Cancel any pending I/O. */ 2492 wm_stop(ifp, 0); 2493 2494 /* Reset the chip to a known state. */ 2495 wm_reset(sc); 2496 2497 /* Initialize the transmit descriptor ring. */ 2498 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2499 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2500 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2501 sc->sc_txfree = WM_NTXDESC(sc); 2502 sc->sc_txnext = 0; 2503 2504 if (sc->sc_type < WM_T_82543) { 2505 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2506 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2507 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2508 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2509 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2510 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2511 } else { 2512 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2513 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2514 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2515 CSR_WRITE(sc, WMREG_TDH, 0); 2516 CSR_WRITE(sc, WMREG_TDT, 0); 2517 CSR_WRITE(sc, WMREG_TIDV, 128); 2518 2519 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2520 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2521 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2522 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2523 } 2524 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2525 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2526 2527 /* Initialize the transmit job descriptors. */ 2528 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2529 sc->sc_txsoft[i].txs_mbuf = NULL; 2530 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2531 sc->sc_txsnext = 0; 2532 sc->sc_txsdirty = 0; 2533 2534 /* 2535 * Initialize the receive descriptor and receive job 2536 * descriptor rings. 2537 */ 2538 if (sc->sc_type < WM_T_82543) { 2539 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2540 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2541 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2542 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2543 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2544 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2545 2546 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2547 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2548 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2549 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2550 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2551 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2552 } else { 2553 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2554 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2555 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2556 CSR_WRITE(sc, WMREG_RDH, 0); 2557 CSR_WRITE(sc, WMREG_RDT, 0); 2558 CSR_WRITE(sc, WMREG_RDTR, 28 | RDTR_FPD); 2559 } 2560 for (i = 0; i < WM_NRXDESC; i++) { 2561 rxs = &sc->sc_rxsoft[i]; 2562 if (rxs->rxs_mbuf == NULL) { 2563 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2564 log(LOG_ERR, "%s: unable to allocate or map rx " 2565 "buffer %d, error = %d\n", 2566 sc->sc_dev.dv_xname, i, error); 2567 /* 2568 * XXX Should attempt to run with fewer receive 2569 * XXX buffers instead of just failing. 2570 */ 2571 wm_rxdrain(sc); 2572 goto out; 2573 } 2574 } else 2575 WM_INIT_RXDESC(sc, i); 2576 } 2577 sc->sc_rxptr = 0; 2578 sc->sc_rxdiscard = 0; 2579 WM_RXCHAIN_RESET(sc); 2580 2581 /* 2582 * Clear out the VLAN table -- we don't use it (yet). 2583 */ 2584 CSR_WRITE(sc, WMREG_VET, 0); 2585 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2586 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2587 2588 /* 2589 * Set up flow-control parameters. 2590 * 2591 * XXX Values could probably stand some tuning. 2592 */ 2593 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2594 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2595 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2596 2597 sc->sc_fcrtl = FCRTL_DFLT; 2598 if (sc->sc_type < WM_T_82543) { 2599 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2600 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2601 } else { 2602 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2603 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2604 } 2605 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2606 2607 #if 0 /* XXXJRT */ 2608 /* Deal with VLAN enables. */ 2609 if (sc->sc_ethercom.ec_nvlans != 0) 2610 sc->sc_ctrl |= CTRL_VME; 2611 else 2612 #endif /* XXXJRT */ 2613 sc->sc_ctrl &= ~CTRL_VME; 2614 2615 /* Write the control registers. */ 2616 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2617 #if 0 2618 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2619 #endif 2620 2621 /* 2622 * Set up checksum offload parameters. 2623 */ 2624 reg = CSR_READ(sc, WMREG_RXCSUM); 2625 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2626 reg |= RXCSUM_IPOFL; 2627 else 2628 reg &= ~RXCSUM_IPOFL; 2629 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2630 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2631 else { 2632 reg &= ~RXCSUM_TUOFL; 2633 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2634 reg &= ~RXCSUM_IPOFL; 2635 } 2636 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2637 2638 /* 2639 * Set up the interrupt registers. 2640 */ 2641 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2642 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2643 ICR_RXO | ICR_RXT0; 2644 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2645 sc->sc_icr |= ICR_RXCFG; 2646 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2647 2648 /* Set up the inter-packet gap. */ 2649 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2650 2651 #if 0 /* XXXJRT */ 2652 /* Set the VLAN ethernetype. */ 2653 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2654 #endif 2655 2656 /* 2657 * Set up the transmit control register; we start out with 2658 * a collision distance suitable for FDX, but update it whe 2659 * we resolve the media type. 2660 */ 2661 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2662 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2663 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2664 2665 /* Set the media. */ 2666 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2667 2668 /* 2669 * Set up the receive control register; we actually program 2670 * the register when we set the receive filter. Use multicast 2671 * address offset type 0. 2672 * 2673 * Only the i82544 has the ability to strip the incoming 2674 * CRC, so we don't enable that feature. 2675 */ 2676 sc->sc_mchash_type = 0; 2677 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2678 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2679 2680 if(MCLBYTES == 2048) { 2681 sc->sc_rctl |= RCTL_2k; 2682 } else { 2683 if(sc->sc_type >= WM_T_82543) { 2684 switch(MCLBYTES) { 2685 case 4096: 2686 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2687 break; 2688 case 8192: 2689 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2690 break; 2691 case 16384: 2692 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2693 break; 2694 default: 2695 panic("wm_init: MCLBYTES %d unsupported", 2696 MCLBYTES); 2697 break; 2698 } 2699 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2700 } 2701 2702 /* Set the receive filter. */ 2703 wm_set_filter(sc); 2704 2705 /* Start the one second link check clock. */ 2706 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2707 2708 /* ...all done! */ 2709 ifp->if_flags |= IFF_RUNNING; 2710 ifp->if_flags &= ~IFF_OACTIVE; 2711 2712 out: 2713 if (error) 2714 log(LOG_ERR, "%s: interface not running\n", 2715 sc->sc_dev.dv_xname); 2716 return (error); 2717 } 2718 2719 /* 2720 * wm_rxdrain: 2721 * 2722 * Drain the receive queue. 2723 */ 2724 static void 2725 wm_rxdrain(struct wm_softc *sc) 2726 { 2727 struct wm_rxsoft *rxs; 2728 int i; 2729 2730 for (i = 0; i < WM_NRXDESC; i++) { 2731 rxs = &sc->sc_rxsoft[i]; 2732 if (rxs->rxs_mbuf != NULL) { 2733 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2734 m_freem(rxs->rxs_mbuf); 2735 rxs->rxs_mbuf = NULL; 2736 } 2737 } 2738 } 2739 2740 /* 2741 * wm_stop: [ifnet interface function] 2742 * 2743 * Stop transmission on the interface. 2744 */ 2745 static void 2746 wm_stop(struct ifnet *ifp, int disable) 2747 { 2748 struct wm_softc *sc = ifp->if_softc; 2749 struct wm_txsoft *txs; 2750 int i; 2751 2752 /* Stop the one second clock. */ 2753 callout_stop(&sc->sc_tick_ch); 2754 2755 /* Stop the 82547 Tx FIFO stall check timer. */ 2756 if (sc->sc_type == WM_T_82547) 2757 callout_stop(&sc->sc_txfifo_ch); 2758 2759 if (sc->sc_flags & WM_F_HAS_MII) { 2760 /* Down the MII. */ 2761 mii_down(&sc->sc_mii); 2762 } 2763 2764 /* Stop the transmit and receive processes. */ 2765 CSR_WRITE(sc, WMREG_TCTL, 0); 2766 CSR_WRITE(sc, WMREG_RCTL, 0); 2767 2768 /* Release any queued transmit buffers. */ 2769 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2770 txs = &sc->sc_txsoft[i]; 2771 if (txs->txs_mbuf != NULL) { 2772 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2773 m_freem(txs->txs_mbuf); 2774 txs->txs_mbuf = NULL; 2775 } 2776 } 2777 2778 if (disable) 2779 wm_rxdrain(sc); 2780 2781 /* Mark the interface as down and cancel the watchdog timer. */ 2782 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2783 ifp->if_timer = 0; 2784 } 2785 2786 /* 2787 * wm_acquire_eeprom: 2788 * 2789 * Perform the EEPROM handshake required on some chips. 2790 */ 2791 static int 2792 wm_acquire_eeprom(struct wm_softc *sc) 2793 { 2794 uint32_t reg; 2795 int x; 2796 2797 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2798 reg = CSR_READ(sc, WMREG_EECD); 2799 2800 /* Request EEPROM access. */ 2801 reg |= EECD_EE_REQ; 2802 CSR_WRITE(sc, WMREG_EECD, reg); 2803 2804 /* ..and wait for it to be granted. */ 2805 for (x = 0; x < 100; x++) { 2806 reg = CSR_READ(sc, WMREG_EECD); 2807 if (reg & EECD_EE_GNT) 2808 break; 2809 delay(5); 2810 } 2811 if ((reg & EECD_EE_GNT) == 0) { 2812 aprint_error("%s: could not acquire EEPROM GNT\n", 2813 sc->sc_dev.dv_xname); 2814 reg &= ~EECD_EE_REQ; 2815 CSR_WRITE(sc, WMREG_EECD, reg); 2816 return (1); 2817 } 2818 } 2819 2820 return (0); 2821 } 2822 2823 /* 2824 * wm_release_eeprom: 2825 * 2826 * Release the EEPROM mutex. 2827 */ 2828 static void 2829 wm_release_eeprom(struct wm_softc *sc) 2830 { 2831 uint32_t reg; 2832 2833 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2834 reg = CSR_READ(sc, WMREG_EECD); 2835 reg &= ~EECD_EE_REQ; 2836 CSR_WRITE(sc, WMREG_EECD, reg); 2837 } 2838 } 2839 2840 /* 2841 * wm_eeprom_sendbits: 2842 * 2843 * Send a series of bits to the EEPROM. 2844 */ 2845 static void 2846 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2847 { 2848 uint32_t reg; 2849 int x; 2850 2851 reg = CSR_READ(sc, WMREG_EECD); 2852 2853 for (x = nbits; x > 0; x--) { 2854 if (bits & (1U << (x - 1))) 2855 reg |= EECD_DI; 2856 else 2857 reg &= ~EECD_DI; 2858 CSR_WRITE(sc, WMREG_EECD, reg); 2859 delay(2); 2860 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2861 delay(2); 2862 CSR_WRITE(sc, WMREG_EECD, reg); 2863 delay(2); 2864 } 2865 } 2866 2867 /* 2868 * wm_eeprom_recvbits: 2869 * 2870 * Receive a series of bits from the EEPROM. 2871 */ 2872 static void 2873 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2874 { 2875 uint32_t reg, val; 2876 int x; 2877 2878 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2879 2880 val = 0; 2881 for (x = nbits; x > 0; x--) { 2882 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2883 delay(2); 2884 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2885 val |= (1U << (x - 1)); 2886 CSR_WRITE(sc, WMREG_EECD, reg); 2887 delay(2); 2888 } 2889 *valp = val; 2890 } 2891 2892 /* 2893 * wm_read_eeprom_uwire: 2894 * 2895 * Read a word from the EEPROM using the MicroWire protocol. 2896 */ 2897 static int 2898 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2899 { 2900 uint32_t reg, val; 2901 int i; 2902 2903 for (i = 0; i < wordcnt; i++) { 2904 /* Clear SK and DI. */ 2905 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2906 CSR_WRITE(sc, WMREG_EECD, reg); 2907 2908 /* Set CHIP SELECT. */ 2909 reg |= EECD_CS; 2910 CSR_WRITE(sc, WMREG_EECD, reg); 2911 delay(2); 2912 2913 /* Shift in the READ command. */ 2914 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2915 2916 /* Shift in address. */ 2917 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2918 2919 /* Shift out the data. */ 2920 wm_eeprom_recvbits(sc, &val, 16); 2921 data[i] = val & 0xffff; 2922 2923 /* Clear CHIP SELECT. */ 2924 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 2925 CSR_WRITE(sc, WMREG_EECD, reg); 2926 delay(2); 2927 } 2928 2929 return (0); 2930 } 2931 2932 /* 2933 * wm_spi_eeprom_ready: 2934 * 2935 * Wait for a SPI EEPROM to be ready for commands. 2936 */ 2937 static int 2938 wm_spi_eeprom_ready(struct wm_softc *sc) 2939 { 2940 uint32_t val; 2941 int usec; 2942 2943 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 2944 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 2945 wm_eeprom_recvbits(sc, &val, 8); 2946 if ((val & SPI_SR_RDY) == 0) 2947 break; 2948 } 2949 if (usec >= SPI_MAX_RETRIES) { 2950 aprint_error("%s: EEPROM failed to become ready\n", 2951 sc->sc_dev.dv_xname); 2952 return (1); 2953 } 2954 return (0); 2955 } 2956 2957 /* 2958 * wm_read_eeprom_spi: 2959 * 2960 * Read a work from the EEPROM using the SPI protocol. 2961 */ 2962 static int 2963 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2964 { 2965 uint32_t reg, val; 2966 int i; 2967 uint8_t opc; 2968 2969 /* Clear SK and CS. */ 2970 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 2971 CSR_WRITE(sc, WMREG_EECD, reg); 2972 delay(2); 2973 2974 if (wm_spi_eeprom_ready(sc)) 2975 return (1); 2976 2977 /* Toggle CS to flush commands. */ 2978 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 2979 delay(2); 2980 CSR_WRITE(sc, WMREG_EECD, reg); 2981 delay(2); 2982 2983 opc = SPI_OPC_READ; 2984 if (sc->sc_ee_addrbits == 8 && word >= 128) 2985 opc |= SPI_OPC_A8; 2986 2987 wm_eeprom_sendbits(sc, opc, 8); 2988 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 2989 2990 for (i = 0; i < wordcnt; i++) { 2991 wm_eeprom_recvbits(sc, &val, 16); 2992 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 2993 } 2994 2995 /* Raise CS and clear SK. */ 2996 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 2997 CSR_WRITE(sc, WMREG_EECD, reg); 2998 delay(2); 2999 3000 return (0); 3001 } 3002 3003 /* 3004 * wm_read_eeprom: 3005 * 3006 * Read data from the serial EEPROM. 3007 */ 3008 static int 3009 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3010 { 3011 int rv; 3012 3013 if (wm_acquire_eeprom(sc)) 3014 return (1); 3015 3016 if (sc->sc_flags & WM_F_EEPROM_SPI) 3017 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3018 else 3019 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3020 3021 wm_release_eeprom(sc); 3022 return (rv); 3023 } 3024 3025 /* 3026 * wm_add_rxbuf: 3027 * 3028 * Add a receive buffer to the indiciated descriptor. 3029 */ 3030 static int 3031 wm_add_rxbuf(struct wm_softc *sc, int idx) 3032 { 3033 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3034 struct mbuf *m; 3035 int error; 3036 3037 MGETHDR(m, M_DONTWAIT, MT_DATA); 3038 if (m == NULL) 3039 return (ENOBUFS); 3040 3041 MCLGET(m, M_DONTWAIT); 3042 if ((m->m_flags & M_EXT) == 0) { 3043 m_freem(m); 3044 return (ENOBUFS); 3045 } 3046 3047 if (rxs->rxs_mbuf != NULL) 3048 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3049 3050 rxs->rxs_mbuf = m; 3051 3052 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3053 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3054 BUS_DMA_READ|BUS_DMA_NOWAIT); 3055 if (error) { 3056 /* XXX XXX XXX */ 3057 printf("%s: unable to load rx DMA map %d, error = %d\n", 3058 sc->sc_dev.dv_xname, idx, error); 3059 panic("wm_add_rxbuf"); 3060 } 3061 3062 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3063 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3064 3065 WM_INIT_RXDESC(sc, idx); 3066 3067 return (0); 3068 } 3069 3070 /* 3071 * wm_set_ral: 3072 * 3073 * Set an entery in the receive address list. 3074 */ 3075 static void 3076 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3077 { 3078 uint32_t ral_lo, ral_hi; 3079 3080 if (enaddr != NULL) { 3081 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3082 (enaddr[3] << 24); 3083 ral_hi = enaddr[4] | (enaddr[5] << 8); 3084 ral_hi |= RAL_AV; 3085 } else { 3086 ral_lo = 0; 3087 ral_hi = 0; 3088 } 3089 3090 if (sc->sc_type >= WM_T_82544) { 3091 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3092 ral_lo); 3093 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3094 ral_hi); 3095 } else { 3096 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3097 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3098 } 3099 } 3100 3101 /* 3102 * wm_mchash: 3103 * 3104 * Compute the hash of the multicast address for the 4096-bit 3105 * multicast filter. 3106 */ 3107 static uint32_t 3108 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3109 { 3110 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3111 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3112 uint32_t hash; 3113 3114 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3115 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3116 3117 return (hash & 0xfff); 3118 } 3119 3120 /* 3121 * wm_set_filter: 3122 * 3123 * Set up the receive filter. 3124 */ 3125 static void 3126 wm_set_filter(struct wm_softc *sc) 3127 { 3128 struct ethercom *ec = &sc->sc_ethercom; 3129 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3130 struct ether_multi *enm; 3131 struct ether_multistep step; 3132 bus_addr_t mta_reg; 3133 uint32_t hash, reg, bit; 3134 int i; 3135 3136 if (sc->sc_type >= WM_T_82544) 3137 mta_reg = WMREG_CORDOVA_MTA; 3138 else 3139 mta_reg = WMREG_MTA; 3140 3141 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3142 3143 if (ifp->if_flags & IFF_BROADCAST) 3144 sc->sc_rctl |= RCTL_BAM; 3145 if (ifp->if_flags & IFF_PROMISC) { 3146 sc->sc_rctl |= RCTL_UPE; 3147 goto allmulti; 3148 } 3149 3150 /* 3151 * Set the station address in the first RAL slot, and 3152 * clear the remaining slots. 3153 */ 3154 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3155 for (i = 1; i < WM_RAL_TABSIZE; i++) 3156 wm_set_ral(sc, NULL, i); 3157 3158 /* Clear out the multicast table. */ 3159 for (i = 0; i < WM_MC_TABSIZE; i++) 3160 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3161 3162 ETHER_FIRST_MULTI(step, ec, enm); 3163 while (enm != NULL) { 3164 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3165 /* 3166 * We must listen to a range of multicast addresses. 3167 * For now, just accept all multicasts, rather than 3168 * trying to set only those filter bits needed to match 3169 * the range. (At this time, the only use of address 3170 * ranges is for IP multicast routing, for which the 3171 * range is big enough to require all bits set.) 3172 */ 3173 goto allmulti; 3174 } 3175 3176 hash = wm_mchash(sc, enm->enm_addrlo); 3177 3178 reg = (hash >> 5) & 0x7f; 3179 bit = hash & 0x1f; 3180 3181 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3182 hash |= 1U << bit; 3183 3184 /* XXX Hardware bug?? */ 3185 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3186 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3187 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3188 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3189 } else 3190 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3191 3192 ETHER_NEXT_MULTI(step, enm); 3193 } 3194 3195 ifp->if_flags &= ~IFF_ALLMULTI; 3196 goto setit; 3197 3198 allmulti: 3199 ifp->if_flags |= IFF_ALLMULTI; 3200 sc->sc_rctl |= RCTL_MPE; 3201 3202 setit: 3203 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3204 } 3205 3206 /* 3207 * wm_tbi_mediainit: 3208 * 3209 * Initialize media for use on 1000BASE-X devices. 3210 */ 3211 static void 3212 wm_tbi_mediainit(struct wm_softc *sc) 3213 { 3214 const char *sep = ""; 3215 3216 if (sc->sc_type < WM_T_82543) 3217 sc->sc_tipg = TIPG_WM_DFLT; 3218 else 3219 sc->sc_tipg = TIPG_LG_DFLT; 3220 3221 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3222 wm_tbi_mediastatus); 3223 3224 /* 3225 * SWD Pins: 3226 * 3227 * 0 = Link LED (output) 3228 * 1 = Loss Of Signal (input) 3229 */ 3230 sc->sc_ctrl |= CTRL_SWDPIO(0); 3231 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3232 3233 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3234 3235 #define ADD(ss, mm, dd) \ 3236 do { \ 3237 aprint_normal("%s%s", sep, ss); \ 3238 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3239 sep = ", "; \ 3240 } while (/*CONSTCOND*/0) 3241 3242 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3243 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3244 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3245 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3246 aprint_normal("\n"); 3247 3248 #undef ADD 3249 3250 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3251 } 3252 3253 /* 3254 * wm_tbi_mediastatus: [ifmedia interface function] 3255 * 3256 * Get the current interface media status on a 1000BASE-X device. 3257 */ 3258 static void 3259 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3260 { 3261 struct wm_softc *sc = ifp->if_softc; 3262 uint32_t ctrl; 3263 3264 ifmr->ifm_status = IFM_AVALID; 3265 ifmr->ifm_active = IFM_ETHER; 3266 3267 if (sc->sc_tbi_linkup == 0) { 3268 ifmr->ifm_active |= IFM_NONE; 3269 return; 3270 } 3271 3272 ifmr->ifm_status |= IFM_ACTIVE; 3273 ifmr->ifm_active |= IFM_1000_SX; 3274 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3275 ifmr->ifm_active |= IFM_FDX; 3276 ctrl = CSR_READ(sc, WMREG_CTRL); 3277 if (ctrl & CTRL_RFCE) 3278 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3279 if (ctrl & CTRL_TFCE) 3280 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3281 } 3282 3283 /* 3284 * wm_tbi_mediachange: [ifmedia interface function] 3285 * 3286 * Set hardware to newly-selected media on a 1000BASE-X device. 3287 */ 3288 static int 3289 wm_tbi_mediachange(struct ifnet *ifp) 3290 { 3291 struct wm_softc *sc = ifp->if_softc; 3292 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3293 uint32_t status; 3294 int i; 3295 3296 sc->sc_txcw = ife->ifm_data; 3297 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3298 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3299 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3300 sc->sc_txcw |= TXCW_ANE; 3301 3302 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3303 delay(10000); 3304 3305 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3306 3307 sc->sc_tbi_anstate = 0; 3308 3309 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3310 /* Have signal; wait for the link to come up. */ 3311 for (i = 0; i < 50; i++) { 3312 delay(10000); 3313 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3314 break; 3315 } 3316 3317 status = CSR_READ(sc, WMREG_STATUS); 3318 if (status & STATUS_LU) { 3319 /* Link is up. */ 3320 DPRINTF(WM_DEBUG_LINK, 3321 ("%s: LINK: set media -> link up %s\n", 3322 sc->sc_dev.dv_xname, 3323 (status & STATUS_FD) ? "FDX" : "HDX")); 3324 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3325 sc->sc_fcrtl &= ~FCRTL_XONE; 3326 if (status & STATUS_FD) 3327 sc->sc_tctl |= 3328 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3329 else 3330 sc->sc_tctl |= 3331 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3332 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3333 sc->sc_fcrtl |= FCRTL_XONE; 3334 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3335 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3336 WMREG_OLD_FCRTL : WMREG_FCRTL, 3337 sc->sc_fcrtl); 3338 sc->sc_tbi_linkup = 1; 3339 } else { 3340 /* Link is down. */ 3341 DPRINTF(WM_DEBUG_LINK, 3342 ("%s: LINK: set media -> link down\n", 3343 sc->sc_dev.dv_xname)); 3344 sc->sc_tbi_linkup = 0; 3345 } 3346 } else { 3347 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3348 sc->sc_dev.dv_xname)); 3349 sc->sc_tbi_linkup = 0; 3350 } 3351 3352 wm_tbi_set_linkled(sc); 3353 3354 return (0); 3355 } 3356 3357 /* 3358 * wm_tbi_set_linkled: 3359 * 3360 * Update the link LED on 1000BASE-X devices. 3361 */ 3362 static void 3363 wm_tbi_set_linkled(struct wm_softc *sc) 3364 { 3365 3366 if (sc->sc_tbi_linkup) 3367 sc->sc_ctrl |= CTRL_SWDPIN(0); 3368 else 3369 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3370 3371 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3372 } 3373 3374 /* 3375 * wm_tbi_check_link: 3376 * 3377 * Check the link on 1000BASE-X devices. 3378 */ 3379 static void 3380 wm_tbi_check_link(struct wm_softc *sc) 3381 { 3382 uint32_t rxcw, ctrl, status; 3383 3384 if (sc->sc_tbi_anstate == 0) 3385 return; 3386 else if (sc->sc_tbi_anstate > 1) { 3387 DPRINTF(WM_DEBUG_LINK, 3388 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3389 sc->sc_tbi_anstate)); 3390 sc->sc_tbi_anstate--; 3391 return; 3392 } 3393 3394 sc->sc_tbi_anstate = 0; 3395 3396 rxcw = CSR_READ(sc, WMREG_RXCW); 3397 ctrl = CSR_READ(sc, WMREG_CTRL); 3398 status = CSR_READ(sc, WMREG_STATUS); 3399 3400 if ((status & STATUS_LU) == 0) { 3401 DPRINTF(WM_DEBUG_LINK, 3402 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3403 sc->sc_tbi_linkup = 0; 3404 } else { 3405 DPRINTF(WM_DEBUG_LINK, 3406 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3407 (status & STATUS_FD) ? "FDX" : "HDX")); 3408 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3409 sc->sc_fcrtl &= ~FCRTL_XONE; 3410 if (status & STATUS_FD) 3411 sc->sc_tctl |= 3412 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3413 else 3414 sc->sc_tctl |= 3415 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3416 if (ctrl & CTRL_TFCE) 3417 sc->sc_fcrtl |= FCRTL_XONE; 3418 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3419 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3420 WMREG_OLD_FCRTL : WMREG_FCRTL, 3421 sc->sc_fcrtl); 3422 sc->sc_tbi_linkup = 1; 3423 } 3424 3425 wm_tbi_set_linkled(sc); 3426 } 3427 3428 /* 3429 * wm_gmii_reset: 3430 * 3431 * Reset the PHY. 3432 */ 3433 static void 3434 wm_gmii_reset(struct wm_softc *sc) 3435 { 3436 uint32_t reg; 3437 3438 if (sc->sc_type >= WM_T_82544) { 3439 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3440 delay(20000); 3441 3442 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3443 delay(20000); 3444 } else { 3445 /* The PHY reset pin is active-low. */ 3446 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3447 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3448 CTRL_EXT_SWDPIN(4)); 3449 reg |= CTRL_EXT_SWDPIO(4); 3450 3451 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3452 delay(10); 3453 3454 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3455 delay(10); 3456 3457 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3458 delay(10); 3459 #if 0 3460 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3461 #endif 3462 } 3463 } 3464 3465 /* 3466 * wm_gmii_mediainit: 3467 * 3468 * Initialize media for use on 1000BASE-T devices. 3469 */ 3470 static void 3471 wm_gmii_mediainit(struct wm_softc *sc) 3472 { 3473 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3474 3475 /* We have MII. */ 3476 sc->sc_flags |= WM_F_HAS_MII; 3477 3478 sc->sc_tipg = TIPG_1000T_DFLT; 3479 3480 /* 3481 * Let the chip set speed/duplex on its own based on 3482 * signals from the PHY. 3483 */ 3484 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3485 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3486 3487 /* Initialize our media structures and probe the GMII. */ 3488 sc->sc_mii.mii_ifp = ifp; 3489 3490 if (sc->sc_type >= WM_T_82544) { 3491 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3492 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3493 } else { 3494 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3495 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3496 } 3497 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3498 3499 wm_gmii_reset(sc); 3500 3501 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3502 wm_gmii_mediastatus); 3503 3504 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3505 MII_OFFSET_ANY, MIIF_DOPAUSE); 3506 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3507 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3508 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3509 } else 3510 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3511 } 3512 3513 /* 3514 * wm_gmii_mediastatus: [ifmedia interface function] 3515 * 3516 * Get the current interface media status on a 1000BASE-T device. 3517 */ 3518 static void 3519 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3520 { 3521 struct wm_softc *sc = ifp->if_softc; 3522 3523 mii_pollstat(&sc->sc_mii); 3524 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3525 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3526 sc->sc_flowflags; 3527 } 3528 3529 /* 3530 * wm_gmii_mediachange: [ifmedia interface function] 3531 * 3532 * Set hardware to newly-selected media on a 1000BASE-T device. 3533 */ 3534 static int 3535 wm_gmii_mediachange(struct ifnet *ifp) 3536 { 3537 struct wm_softc *sc = ifp->if_softc; 3538 3539 if (ifp->if_flags & IFF_UP) 3540 mii_mediachg(&sc->sc_mii); 3541 return (0); 3542 } 3543 3544 #define MDI_IO CTRL_SWDPIN(2) 3545 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3546 #define MDI_CLK CTRL_SWDPIN(3) 3547 3548 static void 3549 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3550 { 3551 uint32_t i, v; 3552 3553 v = CSR_READ(sc, WMREG_CTRL); 3554 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3555 v |= MDI_DIR | CTRL_SWDPIO(3); 3556 3557 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3558 if (data & i) 3559 v |= MDI_IO; 3560 else 3561 v &= ~MDI_IO; 3562 CSR_WRITE(sc, WMREG_CTRL, v); 3563 delay(10); 3564 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3565 delay(10); 3566 CSR_WRITE(sc, WMREG_CTRL, v); 3567 delay(10); 3568 } 3569 } 3570 3571 static uint32_t 3572 i82543_mii_recvbits(struct wm_softc *sc) 3573 { 3574 uint32_t v, i, data = 0; 3575 3576 v = CSR_READ(sc, WMREG_CTRL); 3577 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3578 v |= CTRL_SWDPIO(3); 3579 3580 CSR_WRITE(sc, WMREG_CTRL, v); 3581 delay(10); 3582 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3583 delay(10); 3584 CSR_WRITE(sc, WMREG_CTRL, v); 3585 delay(10); 3586 3587 for (i = 0; i < 16; i++) { 3588 data <<= 1; 3589 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3590 delay(10); 3591 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3592 data |= 1; 3593 CSR_WRITE(sc, WMREG_CTRL, v); 3594 delay(10); 3595 } 3596 3597 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3598 delay(10); 3599 CSR_WRITE(sc, WMREG_CTRL, v); 3600 delay(10); 3601 3602 return (data); 3603 } 3604 3605 #undef MDI_IO 3606 #undef MDI_DIR 3607 #undef MDI_CLK 3608 3609 /* 3610 * wm_gmii_i82543_readreg: [mii interface function] 3611 * 3612 * Read a PHY register on the GMII (i82543 version). 3613 */ 3614 static int 3615 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3616 { 3617 struct wm_softc *sc = (void *) self; 3618 int rv; 3619 3620 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3621 i82543_mii_sendbits(sc, reg | (phy << 5) | 3622 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3623 rv = i82543_mii_recvbits(sc) & 0xffff; 3624 3625 DPRINTF(WM_DEBUG_GMII, 3626 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3627 sc->sc_dev.dv_xname, phy, reg, rv)); 3628 3629 return (rv); 3630 } 3631 3632 /* 3633 * wm_gmii_i82543_writereg: [mii interface function] 3634 * 3635 * Write a PHY register on the GMII (i82543 version). 3636 */ 3637 static void 3638 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3639 { 3640 struct wm_softc *sc = (void *) self; 3641 3642 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3643 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3644 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3645 (MII_COMMAND_START << 30), 32); 3646 } 3647 3648 /* 3649 * wm_gmii_i82544_readreg: [mii interface function] 3650 * 3651 * Read a PHY register on the GMII. 3652 */ 3653 static int 3654 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3655 { 3656 struct wm_softc *sc = (void *) self; 3657 uint32_t mdic = 0; 3658 int i, rv; 3659 3660 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3661 MDIC_REGADD(reg)); 3662 3663 for (i = 0; i < 100; i++) { 3664 mdic = CSR_READ(sc, WMREG_MDIC); 3665 if (mdic & MDIC_READY) 3666 break; 3667 delay(10); 3668 } 3669 3670 if ((mdic & MDIC_READY) == 0) { 3671 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3672 sc->sc_dev.dv_xname, phy, reg); 3673 rv = 0; 3674 } else if (mdic & MDIC_E) { 3675 #if 0 /* This is normal if no PHY is present. */ 3676 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3677 sc->sc_dev.dv_xname, phy, reg); 3678 #endif 3679 rv = 0; 3680 } else { 3681 rv = MDIC_DATA(mdic); 3682 if (rv == 0xffff) 3683 rv = 0; 3684 } 3685 3686 return (rv); 3687 } 3688 3689 /* 3690 * wm_gmii_i82544_writereg: [mii interface function] 3691 * 3692 * Write a PHY register on the GMII. 3693 */ 3694 static void 3695 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3696 { 3697 struct wm_softc *sc = (void *) self; 3698 uint32_t mdic = 0; 3699 int i; 3700 3701 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3702 MDIC_REGADD(reg) | MDIC_DATA(val)); 3703 3704 for (i = 0; i < 100; i++) { 3705 mdic = CSR_READ(sc, WMREG_MDIC); 3706 if (mdic & MDIC_READY) 3707 break; 3708 delay(10); 3709 } 3710 3711 if ((mdic & MDIC_READY) == 0) 3712 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3713 sc->sc_dev.dv_xname, phy, reg); 3714 else if (mdic & MDIC_E) 3715 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3716 sc->sc_dev.dv_xname, phy, reg); 3717 } 3718 3719 /* 3720 * wm_gmii_statchg: [mii interface function] 3721 * 3722 * Callback from MII layer when media changes. 3723 */ 3724 static void 3725 wm_gmii_statchg(struct device *self) 3726 { 3727 struct wm_softc *sc = (void *) self; 3728 struct mii_data *mii = &sc->sc_mii; 3729 3730 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3731 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3732 sc->sc_fcrtl &= ~FCRTL_XONE; 3733 3734 /* 3735 * Get flow control negotiation result. 3736 */ 3737 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3738 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3739 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3740 mii->mii_media_active &= ~IFM_ETH_FMASK; 3741 } 3742 3743 if (sc->sc_flowflags & IFM_FLOW) { 3744 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3745 sc->sc_ctrl |= CTRL_TFCE; 3746 sc->sc_fcrtl |= FCRTL_XONE; 3747 } 3748 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3749 sc->sc_ctrl |= CTRL_RFCE; 3750 } 3751 3752 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3753 DPRINTF(WM_DEBUG_LINK, 3754 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3755 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3756 } else { 3757 DPRINTF(WM_DEBUG_LINK, 3758 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3759 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3760 } 3761 3762 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3763 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3764 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3765 : WMREG_FCRTL, sc->sc_fcrtl); 3766 } 3767
Indexes created Tue Sep 23 07:09:52 GMT 2025