if_wm.c revision 1.88
1 /* $NetBSD: if_wm.c,v 1.88 2004/11/24 15:14:13 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.88 2004/11/24 15:14:13 briggs Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA ETHER_MAX_LEN_JUMBO 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make serveral things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 280 /* m_pullup() needed for Tx offload */ 281 struct evcnt sc_ev_txpullup_needed; 282 /* ...failed due to no memory */ 283 struct evcnt sc_ev_txpullup_nomem; 284 /* ...failed due to lack of space in first mbuf */ 285 struct evcnt sc_ev_txpullup_fail; 286 287 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 288 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 289 290 struct evcnt sc_ev_tu; /* Tx underrun */ 291 292 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 293 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 294 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 295 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 296 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 297 #endif /* WM_EVENT_COUNTERS */ 298 299 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 300 301 int sc_txfree; /* number of free Tx descriptors */ 302 int sc_txnext; /* next ready Tx descriptor */ 303 304 int sc_txsfree; /* number of free Tx jobs */ 305 int sc_txsnext; /* next free Tx job */ 306 int sc_txsdirty; /* dirty Tx jobs */ 307 308 /* These 5 variables are used only on the 82547. */ 309 int sc_txfifo_size; /* Tx FIFO size */ 310 int sc_txfifo_head; /* current head of FIFO */ 311 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 312 int sc_txfifo_stall; /* Tx FIFO is stalled */ 313 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 314 315 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 316 317 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 318 int sc_rxdiscard; 319 int sc_rxlen; 320 struct mbuf *sc_rxhead; 321 struct mbuf *sc_rxtail; 322 struct mbuf **sc_rxtailp; 323 324 uint32_t sc_ctrl; /* prototype CTRL register */ 325 #if 0 326 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 327 #endif 328 uint32_t sc_icr; /* prototype interrupt bits */ 329 uint32_t sc_tctl; /* prototype TCTL register */ 330 uint32_t sc_rctl; /* prototype RCTL register */ 331 uint32_t sc_txcw; /* prototype TXCW register */ 332 uint32_t sc_tipg; /* prototype TIPG register */ 333 uint32_t sc_fcrtl; /* prototype FCRTL register */ 334 uint32_t sc_pba; /* prototype PBA register */ 335 336 int sc_tbi_linkup; /* TBI link status */ 337 int sc_tbi_anstate; /* autonegotiation state */ 338 339 int sc_mchash_type; /* multicast filter offset */ 340 341 #if NRND > 0 342 rndsource_element_t rnd_source; /* random source */ 343 #endif 344 }; 345 346 #define WM_RXCHAIN_RESET(sc) \ 347 do { \ 348 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 349 *(sc)->sc_rxtailp = NULL; \ 350 (sc)->sc_rxlen = 0; \ 351 } while (/*CONSTCOND*/0) 352 353 #define WM_RXCHAIN_LINK(sc, m) \ 354 do { \ 355 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 356 (sc)->sc_rxtailp = &(m)->m_next; \ 357 } while (/*CONSTCOND*/0) 358 359 /* sc_flags */ 360 #define WM_F_HAS_MII 0x01 /* has MII */ 361 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 362 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 363 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 364 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 365 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 366 #define WM_F_CSA 0x80 /* bus is CSA */ 367 368 #ifdef WM_EVENT_COUNTERS 369 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 370 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 371 #else 372 #define WM_EVCNT_INCR(ev) /* nothing */ 373 #define WM_EVCNT_ADD(ev, val) /* nothing */ 374 #endif 375 376 #define CSR_READ(sc, reg) \ 377 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 378 #define CSR_WRITE(sc, reg, val) \ 379 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 380 #define CSR_WRITE_FLUSH(sc) \ 381 (void) CSR_READ((sc), WMREG_STATUS) 382 383 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 384 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 385 386 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 387 #define WM_CDTXADDR_HI(sc, x) \ 388 (sizeof(bus_addr_t) == 8 ? \ 389 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 390 391 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 392 #define WM_CDRXADDR_HI(sc, x) \ 393 (sizeof(bus_addr_t) == 8 ? \ 394 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 395 396 #define WM_CDTXSYNC(sc, x, n, ops) \ 397 do { \ 398 int __x, __n; \ 399 \ 400 __x = (x); \ 401 __n = (n); \ 402 \ 403 /* If it will wrap around, sync to the end of the ring. */ \ 404 if ((__x + __n) > WM_NTXDESC(sc)) { \ 405 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 406 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 407 (WM_NTXDESC(sc) - __x), (ops)); \ 408 __n -= (WM_NTXDESC(sc) - __x); \ 409 __x = 0; \ 410 } \ 411 \ 412 /* Now sync whatever is left. */ \ 413 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 414 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 415 } while (/*CONSTCOND*/0) 416 417 #define WM_CDRXSYNC(sc, x, ops) \ 418 do { \ 419 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 420 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 421 } while (/*CONSTCOND*/0) 422 423 #define WM_INIT_RXDESC(sc, x) \ 424 do { \ 425 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 426 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 427 struct mbuf *__m = __rxs->rxs_mbuf; \ 428 \ 429 /* \ 430 * Note: We scoot the packet forward 2 bytes in the buffer \ 431 * so that the payload after the Ethernet header is aligned \ 432 * to a 4-byte boundary. \ 433 * \ 434 * XXX BRAINDAMAGE ALERT! \ 435 * The stupid chip uses the same size for every buffer, which \ 436 * is set in the Receive Control register. We are using the 2K \ 437 * size option, but what we REALLY want is (2K - 2)! For this \ 438 * reason, we can't "scoot" packets longer than the standard \ 439 * Ethernet MTU. On strict-alignment platforms, if the total \ 440 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 441 * the upper layer copy the headers. \ 442 */ \ 443 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 444 \ 445 wm_set_dma_addr(&__rxd->wrx_addr, \ 446 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 447 __rxd->wrx_len = 0; \ 448 __rxd->wrx_cksum = 0; \ 449 __rxd->wrx_status = 0; \ 450 __rxd->wrx_errors = 0; \ 451 __rxd->wrx_special = 0; \ 452 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 453 \ 454 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 455 } while (/*CONSTCOND*/0) 456 457 static void wm_start(struct ifnet *); 458 static void wm_watchdog(struct ifnet *); 459 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 460 static int wm_init(struct ifnet *); 461 static void wm_stop(struct ifnet *, int); 462 463 static void wm_shutdown(void *); 464 465 static void wm_reset(struct wm_softc *); 466 static void wm_rxdrain(struct wm_softc *); 467 static int wm_add_rxbuf(struct wm_softc *, int); 468 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 469 static void wm_tick(void *); 470 471 static void wm_set_filter(struct wm_softc *); 472 473 static int wm_intr(void *); 474 static void wm_txintr(struct wm_softc *); 475 static void wm_rxintr(struct wm_softc *); 476 static void wm_linkintr(struct wm_softc *, uint32_t); 477 478 static void wm_tbi_mediainit(struct wm_softc *); 479 static int wm_tbi_mediachange(struct ifnet *); 480 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 481 482 static void wm_tbi_set_linkled(struct wm_softc *); 483 static void wm_tbi_check_link(struct wm_softc *); 484 485 static void wm_gmii_reset(struct wm_softc *); 486 487 static int wm_gmii_i82543_readreg(struct device *, int, int); 488 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 489 490 static int wm_gmii_i82544_readreg(struct device *, int, int); 491 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 492 493 static void wm_gmii_statchg(struct device *); 494 495 static void wm_gmii_mediainit(struct wm_softc *); 496 static int wm_gmii_mediachange(struct ifnet *); 497 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 498 499 static int wm_match(struct device *, struct cfdata *, void *); 500 static void wm_attach(struct device *, struct device *, void *); 501 502 CFATTACH_DECL(wm, sizeof(struct wm_softc), 503 wm_match, wm_attach, NULL, NULL); 504 505 static void wm_82547_txfifo_stall(void *); 506 507 /* 508 * Devices supported by this driver. 509 */ 510 static const struct wm_product { 511 pci_vendor_id_t wmp_vendor; 512 pci_product_id_t wmp_product; 513 const char *wmp_name; 514 wm_chip_type wmp_type; 515 int wmp_flags; 516 #define WMP_F_1000X 0x01 517 #define WMP_F_1000T 0x02 518 } wm_products[] = { 519 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 520 "Intel i82542 1000BASE-X Ethernet", 521 WM_T_82542_2_1, WMP_F_1000X }, 522 523 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 524 "Intel i82543GC 1000BASE-X Ethernet", 525 WM_T_82543, WMP_F_1000X }, 526 527 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 528 "Intel i82543GC 1000BASE-T Ethernet", 529 WM_T_82543, WMP_F_1000T }, 530 531 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 532 "Intel i82544EI 1000BASE-T Ethernet", 533 WM_T_82544, WMP_F_1000T }, 534 535 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 536 "Intel i82544EI 1000BASE-X Ethernet", 537 WM_T_82544, WMP_F_1000X }, 538 539 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 540 "Intel i82544GC 1000BASE-T Ethernet", 541 WM_T_82544, WMP_F_1000T }, 542 543 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 544 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 545 WM_T_82544, WMP_F_1000T }, 546 547 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 548 "Intel i82540EM 1000BASE-T Ethernet", 549 WM_T_82540, WMP_F_1000T }, 550 551 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 552 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 553 WM_T_82540, WMP_F_1000T }, 554 555 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 556 "Intel i82540EP 1000BASE-T Ethernet", 557 WM_T_82540, WMP_F_1000T }, 558 559 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 560 "Intel i82540EP 1000BASE-T Ethernet", 561 WM_T_82540, WMP_F_1000T }, 562 563 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 564 "Intel i82540EP 1000BASE-T Ethernet", 565 WM_T_82540, WMP_F_1000T }, 566 567 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 568 "Intel i82545EM 1000BASE-T Ethernet", 569 WM_T_82545, WMP_F_1000T }, 570 571 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 572 "Intel i82545GM 1000BASE-T Ethernet", 573 WM_T_82545_3, WMP_F_1000T }, 574 575 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 576 "Intel i82545GM 1000BASE-X Ethernet", 577 WM_T_82545_3, WMP_F_1000X }, 578 #if 0 579 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 580 "Intel i82545GM Gigabit Ethernet (SERDES)", 581 WM_T_82545_3, WMP_F_SERDES }, 582 #endif 583 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 584 "Intel i82546EB 1000BASE-T Ethernet", 585 WM_T_82546, WMP_F_1000T }, 586 587 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 588 "Intel i82546EB 1000BASE-T Ethernet", 589 WM_T_82546, WMP_F_1000T }, 590 591 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 592 "Intel i82545EM 1000BASE-X Ethernet", 593 WM_T_82545, WMP_F_1000X }, 594 595 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 596 "Intel i82546EB 1000BASE-X Ethernet", 597 WM_T_82546, WMP_F_1000X }, 598 599 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 600 "Intel i82546GB 1000BASE-T Ethernet", 601 WM_T_82546_3, WMP_F_1000T }, 602 603 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 604 "Intel i82546GB 1000BASE-X Ethernet", 605 WM_T_82546_3, WMP_F_1000X }, 606 #if 0 607 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 608 "Intel i82546GB Gigabit Ethernet (SERDES)", 609 WM_T_82546_3, WMP_F_SERDES }, 610 #endif 611 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 612 "Intel i82541EI 1000BASE-T Ethernet", 613 WM_T_82541, WMP_F_1000T }, 614 615 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 616 "Intel i82541EI Mobile 1000BASE-T Ethernet", 617 WM_T_82541, WMP_F_1000T }, 618 619 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 620 "Intel i82541ER 1000BASE-T Ethernet", 621 WM_T_82541_2, WMP_F_1000T }, 622 623 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 624 "Intel i82541GI 1000BASE-T Ethernet", 625 WM_T_82541_2, WMP_F_1000T }, 626 627 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 628 "Intel i82541GI Mobile 1000BASE-T Ethernet", 629 WM_T_82541_2, WMP_F_1000T }, 630 631 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 632 "Intel i82547EI 1000BASE-T Ethernet", 633 WM_T_82547, WMP_F_1000T }, 634 635 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 636 "Intel i82547GI 1000BASE-T Ethernet", 637 WM_T_82547_2, WMP_F_1000T }, 638 { 0, 0, 639 NULL, 640 0, 0 }, 641 }; 642 643 #ifdef WM_EVENT_COUNTERS 644 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 645 #endif /* WM_EVENT_COUNTERS */ 646 647 #if 0 /* Not currently used */ 648 static __inline uint32_t 649 wm_io_read(struct wm_softc *sc, int reg) 650 { 651 652 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 653 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 654 } 655 #endif 656 657 static __inline void 658 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 659 { 660 661 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 662 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 663 } 664 665 static __inline void 666 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 667 { 668 wa->wa_low = htole32(v & 0xffffffffU); 669 if (sizeof(bus_addr_t) == 8) 670 wa->wa_high = htole32((uint64_t) v >> 32); 671 else 672 wa->wa_high = 0; 673 } 674 675 static const struct wm_product * 676 wm_lookup(const struct pci_attach_args *pa) 677 { 678 const struct wm_product *wmp; 679 680 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 681 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 682 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 683 return (wmp); 684 } 685 return (NULL); 686 } 687 688 static int 689 wm_match(struct device *parent, struct cfdata *cf, void *aux) 690 { 691 struct pci_attach_args *pa = aux; 692 693 if (wm_lookup(pa) != NULL) 694 return (1); 695 696 return (0); 697 } 698 699 static void 700 wm_attach(struct device *parent, struct device *self, void *aux) 701 { 702 struct wm_softc *sc = (void *) self; 703 struct pci_attach_args *pa = aux; 704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 705 pci_chipset_tag_t pc = pa->pa_pc; 706 pci_intr_handle_t ih; 707 size_t cdata_size; 708 const char *intrstr = NULL; 709 const char *eetype; 710 bus_space_tag_t memt; 711 bus_space_handle_t memh; 712 bus_dma_segment_t seg; 713 int memh_valid; 714 int i, rseg, error; 715 const struct wm_product *wmp; 716 uint8_t enaddr[ETHER_ADDR_LEN]; 717 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 718 pcireg_t preg, memtype; 719 uint32_t reg; 720 int pmreg; 721 722 callout_init(&sc->sc_tick_ch); 723 724 wmp = wm_lookup(pa); 725 if (wmp == NULL) { 726 printf("\n"); 727 panic("wm_attach: impossible"); 728 } 729 730 if (pci_dma64_available(pa)) 731 sc->sc_dmat = pa->pa_dmat64; 732 else 733 sc->sc_dmat = pa->pa_dmat; 734 735 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 736 aprint_naive(": Ethernet controller\n"); 737 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 738 739 sc->sc_type = wmp->wmp_type; 740 if (sc->sc_type < WM_T_82543) { 741 if (preg < 2) { 742 aprint_error("%s: i82542 must be at least rev. 2\n", 743 sc->sc_dev.dv_xname); 744 return; 745 } 746 if (preg < 3) 747 sc->sc_type = WM_T_82542_2_0; 748 } 749 750 /* 751 * Map the device. All devices support memory-mapped acccess, 752 * and it is really required for normal operation. 753 */ 754 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 755 switch (memtype) { 756 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 757 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 758 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 759 memtype, 0, &memt, &memh, NULL, NULL) == 0); 760 break; 761 default: 762 memh_valid = 0; 763 } 764 765 if (memh_valid) { 766 sc->sc_st = memt; 767 sc->sc_sh = memh; 768 } else { 769 aprint_error("%s: unable to map device registers\n", 770 sc->sc_dev.dv_xname); 771 return; 772 } 773 774 /* 775 * In addition, i82544 and later support I/O mapped indirect 776 * register access. It is not desirable (nor supported in 777 * this driver) to use it for normal operation, though it is 778 * required to work around bugs in some chip versions. 779 */ 780 if (sc->sc_type >= WM_T_82544) { 781 /* First we have to find the I/O BAR. */ 782 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 783 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 784 PCI_MAPREG_TYPE_IO) 785 break; 786 } 787 if (i == PCI_MAPREG_END) 788 aprint_error("%s: WARNING: unable to find I/O BAR\n", 789 sc->sc_dev.dv_xname); 790 else { 791 /* 792 * The i8254x doesn't apparently respond when the 793 * I/O BAR is 0, which looks somewhat like it's not 794 * been configured. 795 */ 796 preg = pci_conf_read(pc, pa->pa_tag, i); 797 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 798 aprint_error("%s: WARNING: I/O BAR at zero.", 799 sc->sc_dev.dv_xname); 800 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 801 0, &sc->sc_iot, &sc->sc_ioh, 802 NULL, NULL) == 0) { 803 sc->sc_flags |= WM_F_IOH_VALID; 804 } else { 805 aprint_error("%s: WARNING: unable to map " 806 "I/O space\n", sc->sc_dev.dv_xname); 807 } 808 } 809 810 } 811 812 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 813 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 814 preg |= PCI_COMMAND_MASTER_ENABLE; 815 if (sc->sc_type < WM_T_82542_2_1) 816 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 817 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 818 819 /* Get it out of power save mode, if needed. */ 820 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 821 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 822 PCI_PMCSR_STATE_MASK; 823 if (preg == PCI_PMCSR_STATE_D3) { 824 /* 825 * The card has lost all configuration data in 826 * this state, so punt. 827 */ 828 aprint_error("%s: unable to wake from power state D3\n", 829 sc->sc_dev.dv_xname); 830 return; 831 } 832 if (preg != PCI_PMCSR_STATE_D0) { 833 aprint_normal("%s: waking up from power state D%d\n", 834 sc->sc_dev.dv_xname, preg); 835 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 836 PCI_PMCSR_STATE_D0); 837 } 838 } 839 840 /* 841 * Map and establish our interrupt. 842 */ 843 if (pci_intr_map(pa, &ih)) { 844 aprint_error("%s: unable to map interrupt\n", 845 sc->sc_dev.dv_xname); 846 return; 847 } 848 intrstr = pci_intr_string(pc, ih); 849 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 850 if (sc->sc_ih == NULL) { 851 aprint_error("%s: unable to establish interrupt", 852 sc->sc_dev.dv_xname); 853 if (intrstr != NULL) 854 aprint_normal(" at %s", intrstr); 855 aprint_normal("\n"); 856 return; 857 } 858 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 859 860 /* 861 * Determine a few things about the bus we're connected to. 862 */ 863 if (sc->sc_type < WM_T_82543) { 864 /* We don't really know the bus characteristics here. */ 865 sc->sc_bus_speed = 33; 866 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 867 /* 868 * CSA (Communication Streaming Architecture) is about as fast 869 * a 32-bit 66MHz PCI Bus. 870 */ 871 sc->sc_flags |= WM_F_CSA; 872 sc->sc_bus_speed = 66; 873 aprint_verbose("%s: Communication Streaming Architecture\n", 874 sc->sc_dev.dv_xname); 875 if (sc->sc_type == WM_T_82547) { 876 callout_init(&sc->sc_txfifo_ch); 877 callout_setfunc(&sc->sc_txfifo_ch, 878 wm_82547_txfifo_stall, sc); 879 aprint_verbose("%s: using 82547 Tx FIFO stall " 880 "work-around\n", sc->sc_dev.dv_xname); 881 } 882 } else { 883 reg = CSR_READ(sc, WMREG_STATUS); 884 if (reg & STATUS_BUS64) 885 sc->sc_flags |= WM_F_BUS64; 886 if (sc->sc_type >= WM_T_82544 && 887 (reg & STATUS_PCIX_MODE) != 0) { 888 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 889 890 sc->sc_flags |= WM_F_PCIX; 891 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 892 PCI_CAP_PCIX, 893 &sc->sc_pcix_offset, NULL) == 0) 894 aprint_error("%s: unable to find PCIX " 895 "capability\n", sc->sc_dev.dv_xname); 896 else if (sc->sc_type != WM_T_82545_3 && 897 sc->sc_type != WM_T_82546_3) { 898 /* 899 * Work around a problem caused by the BIOS 900 * setting the max memory read byte count 901 * incorrectly. 902 */ 903 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 904 sc->sc_pcix_offset + PCI_PCIX_CMD); 905 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 906 sc->sc_pcix_offset + PCI_PCIX_STATUS); 907 908 bytecnt = 909 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 910 PCI_PCIX_CMD_BYTECNT_SHIFT; 911 maxb = 912 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 913 PCI_PCIX_STATUS_MAXB_SHIFT; 914 if (bytecnt > maxb) { 915 aprint_verbose("%s: resetting PCI-X " 916 "MMRBC: %d -> %d\n", 917 sc->sc_dev.dv_xname, 918 512 << bytecnt, 512 << maxb); 919 pcix_cmd = (pcix_cmd & 920 ~PCI_PCIX_CMD_BYTECNT_MASK) | 921 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 922 pci_conf_write(pa->pa_pc, pa->pa_tag, 923 sc->sc_pcix_offset + PCI_PCIX_CMD, 924 pcix_cmd); 925 } 926 } 927 } 928 /* 929 * The quad port adapter is special; it has a PCIX-PCIX 930 * bridge on the board, and can run the secondary bus at 931 * a higher speed. 932 */ 933 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 934 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 935 : 66; 936 } else if (sc->sc_flags & WM_F_PCIX) { 937 switch (reg & STATUS_PCIXSPD_MASK) { 938 case STATUS_PCIXSPD_50_66: 939 sc->sc_bus_speed = 66; 940 break; 941 case STATUS_PCIXSPD_66_100: 942 sc->sc_bus_speed = 100; 943 break; 944 case STATUS_PCIXSPD_100_133: 945 sc->sc_bus_speed = 133; 946 break; 947 default: 948 aprint_error( 949 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 950 sc->sc_dev.dv_xname, 951 reg & STATUS_PCIXSPD_MASK); 952 sc->sc_bus_speed = 66; 953 } 954 } else 955 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 956 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 957 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 958 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 959 } 960 961 /* 962 * Allocate the control data structures, and create and load the 963 * DMA map for it. 964 * 965 * NOTE: All Tx descriptors must be in the same 4G segment of 966 * memory. So must Rx descriptors. We simplify by allocating 967 * both sets within the same 4G segment. 968 */ 969 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 970 WM_NTXDESC_82542 : WM_NTXDESC_82544; 971 cdata_size = sc->sc_type < WM_T_82544 ? 972 sizeof(struct wm_control_data_82542) : 973 sizeof(struct wm_control_data_82544); 974 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 975 (bus_size_t) 0x100000000ULL, 976 &seg, 1, &rseg, 0)) != 0) { 977 aprint_error( 978 "%s: unable to allocate control data, error = %d\n", 979 sc->sc_dev.dv_xname, error); 980 goto fail_0; 981 } 982 983 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 984 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 985 aprint_error("%s: unable to map control data, error = %d\n", 986 sc->sc_dev.dv_xname, error); 987 goto fail_1; 988 } 989 990 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 991 0, 0, &sc->sc_cddmamap)) != 0) { 992 aprint_error("%s: unable to create control data DMA map, " 993 "error = %d\n", sc->sc_dev.dv_xname, error); 994 goto fail_2; 995 } 996 997 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 998 sc->sc_control_data, cdata_size, NULL, 999 0)) != 0) { 1000 aprint_error( 1001 "%s: unable to load control data DMA map, error = %d\n", 1002 sc->sc_dev.dv_xname, error); 1003 goto fail_3; 1004 } 1005 1006 1007 /* 1008 * Create the transmit buffer DMA maps. 1009 */ 1010 WM_TXQUEUELEN(sc) = 1011 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1012 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1013 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1014 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1015 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1016 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1017 aprint_error("%s: unable to create Tx DMA map %d, " 1018 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1019 goto fail_4; 1020 } 1021 } 1022 1023 /* 1024 * Create the receive buffer DMA maps. 1025 */ 1026 for (i = 0; i < WM_NRXDESC; i++) { 1027 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1028 MCLBYTES, 0, 0, 1029 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1030 aprint_error("%s: unable to create Rx DMA map %d, " 1031 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1032 goto fail_5; 1033 } 1034 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1035 } 1036 1037 /* 1038 * Reset the chip to a known state. 1039 */ 1040 wm_reset(sc); 1041 1042 /* 1043 * Get some information about the EEPROM. 1044 */ 1045 if (sc->sc_type >= WM_T_82540) 1046 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1047 if (sc->sc_type <= WM_T_82544) 1048 sc->sc_ee_addrbits = 6; 1049 else if (sc->sc_type <= WM_T_82546_3) { 1050 reg = CSR_READ(sc, WMREG_EECD); 1051 if (reg & EECD_EE_SIZE) 1052 sc->sc_ee_addrbits = 8; 1053 else 1054 sc->sc_ee_addrbits = 6; 1055 } else if (sc->sc_type <= WM_T_82547_2) { 1056 reg = CSR_READ(sc, WMREG_EECD); 1057 if (reg & EECD_EE_TYPE) { 1058 sc->sc_flags |= WM_F_EEPROM_SPI; 1059 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1060 } else 1061 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1062 } else { 1063 /* Assume everything else is SPI. */ 1064 reg = CSR_READ(sc, WMREG_EECD); 1065 sc->sc_flags |= WM_F_EEPROM_SPI; 1066 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1067 } 1068 if (sc->sc_flags & WM_F_EEPROM_SPI) 1069 eetype = "SPI"; 1070 else 1071 eetype = "MicroWire"; 1072 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1073 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1074 sc->sc_ee_addrbits, eetype); 1075 1076 /* 1077 * Read the Ethernet address from the EEPROM. 1078 */ 1079 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1080 sizeof(myea) / sizeof(myea[0]), myea)) { 1081 aprint_error("%s: unable to read Ethernet address\n", 1082 sc->sc_dev.dv_xname); 1083 return; 1084 } 1085 enaddr[0] = myea[0] & 0xff; 1086 enaddr[1] = myea[0] >> 8; 1087 enaddr[2] = myea[1] & 0xff; 1088 enaddr[3] = myea[1] >> 8; 1089 enaddr[4] = myea[2] & 0xff; 1090 enaddr[5] = myea[2] >> 8; 1091 1092 /* 1093 * Toggle the LSB of the MAC address on the second port 1094 * of the i82546. 1095 */ 1096 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1097 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1098 enaddr[5] ^= 1; 1099 } 1100 1101 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1102 ether_sprintf(enaddr)); 1103 1104 /* 1105 * Read the config info from the EEPROM, and set up various 1106 * bits in the control registers based on their contents. 1107 */ 1108 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1109 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1110 sc->sc_dev.dv_xname); 1111 return; 1112 } 1113 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1114 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1115 sc->sc_dev.dv_xname); 1116 return; 1117 } 1118 if (sc->sc_type >= WM_T_82544) { 1119 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1120 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1121 sc->sc_dev.dv_xname); 1122 return; 1123 } 1124 } 1125 1126 if (cfg1 & EEPROM_CFG1_ILOS) 1127 sc->sc_ctrl |= CTRL_ILOS; 1128 if (sc->sc_type >= WM_T_82544) { 1129 sc->sc_ctrl |= 1130 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1131 CTRL_SWDPIO_SHIFT; 1132 sc->sc_ctrl |= 1133 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1134 CTRL_SWDPINS_SHIFT; 1135 } else { 1136 sc->sc_ctrl |= 1137 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1138 CTRL_SWDPIO_SHIFT; 1139 } 1140 1141 #if 0 1142 if (sc->sc_type >= WM_T_82544) { 1143 if (cfg1 & EEPROM_CFG1_IPS0) 1144 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1145 if (cfg1 & EEPROM_CFG1_IPS1) 1146 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1147 sc->sc_ctrl_ext |= 1148 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1149 CTRL_EXT_SWDPIO_SHIFT; 1150 sc->sc_ctrl_ext |= 1151 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1152 CTRL_EXT_SWDPINS_SHIFT; 1153 } else { 1154 sc->sc_ctrl_ext |= 1155 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1156 CTRL_EXT_SWDPIO_SHIFT; 1157 } 1158 #endif 1159 1160 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1161 #if 0 1162 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1163 #endif 1164 1165 /* 1166 * Set up some register offsets that are different between 1167 * the i82542 and the i82543 and later chips. 1168 */ 1169 if (sc->sc_type < WM_T_82543) { 1170 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1171 sc->sc_tdt_reg = WMREG_OLD_TDT; 1172 } else { 1173 sc->sc_rdt_reg = WMREG_RDT; 1174 sc->sc_tdt_reg = WMREG_TDT; 1175 } 1176 1177 /* 1178 * Determine if we're TBI or GMII mode, and initialize the 1179 * media structures accordingly. 1180 */ 1181 if (sc->sc_type < WM_T_82543 || 1182 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1183 if (wmp->wmp_flags & WMP_F_1000T) 1184 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1185 "product!\n", sc->sc_dev.dv_xname); 1186 wm_tbi_mediainit(sc); 1187 } else { 1188 if (wmp->wmp_flags & WMP_F_1000X) 1189 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1190 "product!\n", sc->sc_dev.dv_xname); 1191 wm_gmii_mediainit(sc); 1192 } 1193 1194 ifp = &sc->sc_ethercom.ec_if; 1195 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1196 ifp->if_softc = sc; 1197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1198 ifp->if_ioctl = wm_ioctl; 1199 ifp->if_start = wm_start; 1200 ifp->if_watchdog = wm_watchdog; 1201 ifp->if_init = wm_init; 1202 ifp->if_stop = wm_stop; 1203 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1204 IFQ_SET_READY(&ifp->if_snd); 1205 1206 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1207 1208 /* 1209 * If we're a i82543 or greater, we can support VLANs. 1210 */ 1211 if (sc->sc_type >= WM_T_82543) 1212 sc->sc_ethercom.ec_capabilities |= 1213 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1214 1215 /* 1216 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1217 * on i82543 and later. 1218 */ 1219 if (sc->sc_type >= WM_T_82543) 1220 ifp->if_capabilities |= 1221 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1222 1223 /* 1224 * Attach the interface. 1225 */ 1226 if_attach(ifp); 1227 ether_ifattach(ifp, enaddr); 1228 #if NRND > 0 1229 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1230 RND_TYPE_NET, 0); 1231 #endif 1232 1233 #ifdef WM_EVENT_COUNTERS 1234 /* Attach event counters. */ 1235 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1236 NULL, sc->sc_dev.dv_xname, "txsstall"); 1237 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1238 NULL, sc->sc_dev.dv_xname, "txdstall"); 1239 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1240 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1241 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1242 NULL, sc->sc_dev.dv_xname, "txdw"); 1243 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1244 NULL, sc->sc_dev.dv_xname, "txqe"); 1245 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1246 NULL, sc->sc_dev.dv_xname, "rxintr"); 1247 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1248 NULL, sc->sc_dev.dv_xname, "linkintr"); 1249 1250 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1251 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1252 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1253 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1254 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1255 NULL, sc->sc_dev.dv_xname, "txipsum"); 1256 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1257 NULL, sc->sc_dev.dv_xname, "txtusum"); 1258 1259 evcnt_attach_dynamic(&sc->sc_ev_txpullup_needed, EVCNT_TYPE_MISC, 1260 NULL, sc->sc_dev.dv_xname, "txpullup needed"); 1261 evcnt_attach_dynamic(&sc->sc_ev_txpullup_nomem, EVCNT_TYPE_MISC, 1262 NULL, sc->sc_dev.dv_xname, "txpullup nomem"); 1263 evcnt_attach_dynamic(&sc->sc_ev_txpullup_fail, EVCNT_TYPE_MISC, 1264 NULL, sc->sc_dev.dv_xname, "txpullup fail"); 1265 1266 for (i = 0; i < WM_NTXSEGS; i++) { 1267 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1268 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1269 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1270 } 1271 1272 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1273 NULL, sc->sc_dev.dv_xname, "txdrop"); 1274 1275 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1276 NULL, sc->sc_dev.dv_xname, "tu"); 1277 1278 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1279 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1280 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1281 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1282 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1283 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1284 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1285 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1286 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1287 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1288 #endif /* WM_EVENT_COUNTERS */ 1289 1290 /* 1291 * Make sure the interface is shutdown during reboot. 1292 */ 1293 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1294 if (sc->sc_sdhook == NULL) 1295 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1296 sc->sc_dev.dv_xname); 1297 return; 1298 1299 /* 1300 * Free any resources we've allocated during the failed attach 1301 * attempt. Do this in reverse order and fall through. 1302 */ 1303 fail_5: 1304 for (i = 0; i < WM_NRXDESC; i++) { 1305 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1306 bus_dmamap_destroy(sc->sc_dmat, 1307 sc->sc_rxsoft[i].rxs_dmamap); 1308 } 1309 fail_4: 1310 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1311 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1312 bus_dmamap_destroy(sc->sc_dmat, 1313 sc->sc_txsoft[i].txs_dmamap); 1314 } 1315 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1316 fail_3: 1317 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1318 fail_2: 1319 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1320 cdata_size); 1321 fail_1: 1322 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1323 fail_0: 1324 return; 1325 } 1326 1327 /* 1328 * wm_shutdown: 1329 * 1330 * Make sure the interface is stopped at reboot time. 1331 */ 1332 static void 1333 wm_shutdown(void *arg) 1334 { 1335 struct wm_softc *sc = arg; 1336 1337 wm_stop(&sc->sc_ethercom.ec_if, 1); 1338 } 1339 1340 /* 1341 * wm_tx_offload: 1342 * 1343 * Set up TCP/IP checksumming parameters for the 1344 * specified packet. 1345 */ 1346 static int 1347 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1348 uint8_t *fieldsp) 1349 { 1350 struct mbuf *m0 = txs->txs_mbuf; 1351 struct livengood_tcpip_ctxdesc *t; 1352 uint32_t ipcs, tucs; 1353 struct ip *ip; 1354 struct ether_header *eh; 1355 int offset, iphl; 1356 uint8_t fields = 0; 1357 1358 /* 1359 * XXX It would be nice if the mbuf pkthdr had offset 1360 * fields for the protocol headers. 1361 */ 1362 1363 eh = mtod(m0, struct ether_header *); 1364 switch (htons(eh->ether_type)) { 1365 case ETHERTYPE_IP: 1366 iphl = sizeof(struct ip); 1367 offset = ETHER_HDR_LEN; 1368 break; 1369 1370 case ETHERTYPE_VLAN: 1371 iphl = sizeof(struct ip); 1372 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1373 break; 1374 1375 default: 1376 /* 1377 * Don't support this protocol or encapsulation. 1378 */ 1379 *fieldsp = 0; 1380 *cmdp = 0; 1381 return (0); 1382 } 1383 1384 if (m0->m_len < (offset + iphl)) { 1385 /* 1386 * Packet headers aren't in the first mbuf. Let's hope 1387 * there is space at the end if it for them. 1388 */ 1389 WM_EVCNT_INCR(&sc->sc_ev_txpullup_needed); 1390 if ((txs->txs_mbuf = m_pullup(m0, offset + iphl)) == NULL) { 1391 WM_EVCNT_INCR(&sc->sc_ev_txpullup_nomem); 1392 log(LOG_ERR, 1393 "%s: wm_tx_offload: mbuf allocation failed, " 1394 "packet dropped\n", sc->sc_dev.dv_xname); 1395 return (ENOMEM); 1396 } else if (m0 != txs->txs_mbuf) { 1397 /* 1398 * The DMA map has already been loaded, so we 1399 * would have to unload and reload it. But then 1400 * if that were to fail, we are already committed 1401 * to transmitting the packet (can't put it back 1402 * on the queue), so we have to drop the packet. 1403 */ 1404 WM_EVCNT_INCR(&sc->sc_ev_txpullup_fail); 1405 log(LOG_ERR, "%s: wm_tx_offload: packet headers did " 1406 "not fit in first mbuf, packet dropped\n", 1407 sc->sc_dev.dv_xname); 1408 m_freem(txs->txs_mbuf); 1409 txs->txs_mbuf = NULL; 1410 return (EINVAL); 1411 } 1412 } 1413 1414 ip = (struct ip *) (mtod(m0, caddr_t) + offset); 1415 iphl = ip->ip_hl << 2; 1416 1417 /* 1418 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1419 * offload feature, if we load the context descriptor, we 1420 * MUST provide valid values for IPCSS and TUCSS fields. 1421 */ 1422 1423 ipcs = WTX_TCPIP_IPCSS(offset) | 1424 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1425 WTX_TCPIP_IPCSE(offset + iphl - 1); 1426 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1427 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1428 fields |= WTX_IXSM; 1429 } 1430 1431 offset += iphl; 1432 1433 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1434 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1435 fields |= WTX_TXSM; 1436 tucs = WTX_TCPIP_TUCSS(offset) | 1437 WTX_TCPIP_TUCSO(offset + m0->m_pkthdr.csum_data) | 1438 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1439 } else { 1440 /* Just initialize it to a valid TCP context. */ 1441 tucs = WTX_TCPIP_TUCSS(offset) | 1442 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1443 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1444 } 1445 1446 /* Fill in the context descriptor. */ 1447 t = (struct livengood_tcpip_ctxdesc *) 1448 &sc->sc_txdescs[sc->sc_txnext]; 1449 t->tcpip_ipcs = htole32(ipcs); 1450 t->tcpip_tucs = htole32(tucs); 1451 t->tcpip_cmdlen = htole32(WTX_CMD_DEXT | WTX_DTYP_C); 1452 t->tcpip_seg = 0; 1453 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1454 1455 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1456 txs->txs_ndesc++; 1457 1458 *cmdp = WTX_CMD_DEXT | WTX_DTYP_D; 1459 *fieldsp = fields; 1460 1461 return (0); 1462 } 1463 1464 static void 1465 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1466 { 1467 struct mbuf *m; 1468 int i; 1469 1470 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1471 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1472 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1473 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1474 m->m_data, m->m_len, m->m_flags); 1475 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1476 i, i == 1 ? "" : "s"); 1477 } 1478 1479 /* 1480 * wm_82547_txfifo_stall: 1481 * 1482 * Callout used to wait for the 82547 Tx FIFO to drain, 1483 * reset the FIFO pointers, and restart packet transmission. 1484 */ 1485 static void 1486 wm_82547_txfifo_stall(void *arg) 1487 { 1488 struct wm_softc *sc = arg; 1489 int s; 1490 1491 s = splnet(); 1492 1493 if (sc->sc_txfifo_stall) { 1494 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1495 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1496 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1497 /* 1498 * Packets have drained. Stop transmitter, reset 1499 * FIFO pointers, restart transmitter, and kick 1500 * the packet queue. 1501 */ 1502 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1503 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1504 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1505 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1506 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1507 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1508 CSR_WRITE(sc, WMREG_TCTL, tctl); 1509 CSR_WRITE_FLUSH(sc); 1510 1511 sc->sc_txfifo_head = 0; 1512 sc->sc_txfifo_stall = 0; 1513 wm_start(&sc->sc_ethercom.ec_if); 1514 } else { 1515 /* 1516 * Still waiting for packets to drain; try again in 1517 * another tick. 1518 */ 1519 callout_schedule(&sc->sc_txfifo_ch, 1); 1520 } 1521 } 1522 1523 splx(s); 1524 } 1525 1526 /* 1527 * wm_82547_txfifo_bugchk: 1528 * 1529 * Check for bug condition in the 82547 Tx FIFO. We need to 1530 * prevent enqueueing a packet that would wrap around the end 1531 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1532 * 1533 * We do this by checking the amount of space before the end 1534 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1535 * the Tx FIFO, wait for all remaining packets to drain, reset 1536 * the internal FIFO pointers to the beginning, and restart 1537 * transmission on the interface. 1538 */ 1539 #define WM_FIFO_HDR 0x10 1540 #define WM_82547_PAD_LEN 0x3e0 1541 static int 1542 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1543 { 1544 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1545 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1546 1547 /* Just return if already stalled. */ 1548 if (sc->sc_txfifo_stall) 1549 return (1); 1550 1551 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1552 /* Stall only occurs in half-duplex mode. */ 1553 goto send_packet; 1554 } 1555 1556 if (len >= WM_82547_PAD_LEN + space) { 1557 sc->sc_txfifo_stall = 1; 1558 callout_schedule(&sc->sc_txfifo_ch, 1); 1559 return (1); 1560 } 1561 1562 send_packet: 1563 sc->sc_txfifo_head += len; 1564 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1565 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1566 1567 return (0); 1568 } 1569 1570 /* 1571 * wm_start: [ifnet interface function] 1572 * 1573 * Start packet transmission on the interface. 1574 */ 1575 static void 1576 wm_start(struct ifnet *ifp) 1577 { 1578 struct wm_softc *sc = ifp->if_softc; 1579 struct mbuf *m0; 1580 #if 0 /* XXXJRT */ 1581 struct m_tag *mtag; 1582 #endif 1583 struct wm_txsoft *txs; 1584 bus_dmamap_t dmamap; 1585 int error, nexttx, lasttx = -1, ofree, seg, segs_needed; 1586 bus_addr_t curaddr; 1587 bus_size_t seglen, curlen; 1588 uint32_t cksumcmd; 1589 uint8_t cksumfields; 1590 1591 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1592 return; 1593 1594 /* 1595 * Remember the previous number of free descriptors. 1596 */ 1597 ofree = sc->sc_txfree; 1598 1599 /* 1600 * Loop through the send queue, setting up transmit descriptors 1601 * until we drain the queue, or use up all available transmit 1602 * descriptors. 1603 */ 1604 for (;;) { 1605 /* Grab a packet off the queue. */ 1606 IFQ_POLL(&ifp->if_snd, m0); 1607 if (m0 == NULL) 1608 break; 1609 1610 DPRINTF(WM_DEBUG_TX, 1611 ("%s: TX: have packet to transmit: %p\n", 1612 sc->sc_dev.dv_xname, m0)); 1613 1614 /* Get a work queue entry. */ 1615 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1616 wm_txintr(sc); 1617 if (sc->sc_txsfree == 0) { 1618 DPRINTF(WM_DEBUG_TX, 1619 ("%s: TX: no free job descriptors\n", 1620 sc->sc_dev.dv_xname)); 1621 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1622 break; 1623 } 1624 } 1625 1626 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1627 dmamap = txs->txs_dmamap; 1628 1629 /* 1630 * Load the DMA map. If this fails, the packet either 1631 * didn't fit in the allotted number of segments, or we 1632 * were short on resources. For the too-many-segments 1633 * case, we simply report an error and drop the packet, 1634 * since we can't sanely copy a jumbo packet to a single 1635 * buffer. 1636 */ 1637 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1638 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1639 if (error) { 1640 if (error == EFBIG) { 1641 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1642 log(LOG_ERR, "%s: Tx packet consumes too many " 1643 "DMA segments, dropping...\n", 1644 sc->sc_dev.dv_xname); 1645 IFQ_DEQUEUE(&ifp->if_snd, m0); 1646 wm_dump_mbuf_chain(sc, m0); 1647 m_freem(m0); 1648 continue; 1649 } 1650 /* 1651 * Short on resources, just stop for now. 1652 */ 1653 DPRINTF(WM_DEBUG_TX, 1654 ("%s: TX: dmamap load failed: %d\n", 1655 sc->sc_dev.dv_xname, error)); 1656 break; 1657 } 1658 1659 segs_needed = dmamap->dm_nsegs; 1660 1661 /* 1662 * Ensure we have enough descriptors free to describe 1663 * the packet. Note, we always reserve one descriptor 1664 * at the end of the ring due to the semantics of the 1665 * TDT register, plus one more in the event we need 1666 * to load offload context. 1667 */ 1668 if (segs_needed > sc->sc_txfree - 2) { 1669 /* 1670 * Not enough free descriptors to transmit this 1671 * packet. We haven't committed anything yet, 1672 * so just unload the DMA map, put the packet 1673 * pack on the queue, and punt. Notify the upper 1674 * layer that there are no more slots left. 1675 */ 1676 DPRINTF(WM_DEBUG_TX, 1677 ("%s: TX: need %d (%) descriptors, have %d\n", 1678 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1679 sc->sc_txfree - 1)); 1680 ifp->if_flags |= IFF_OACTIVE; 1681 bus_dmamap_unload(sc->sc_dmat, dmamap); 1682 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1683 break; 1684 } 1685 1686 /* 1687 * Check for 82547 Tx FIFO bug. We need to do this 1688 * once we know we can transmit the packet, since we 1689 * do some internal FIFO space accounting here. 1690 */ 1691 if (sc->sc_type == WM_T_82547 && 1692 wm_82547_txfifo_bugchk(sc, m0)) { 1693 DPRINTF(WM_DEBUG_TX, 1694 ("%s: TX: 82547 Tx FIFO bug detected\n", 1695 sc->sc_dev.dv_xname)); 1696 ifp->if_flags |= IFF_OACTIVE; 1697 bus_dmamap_unload(sc->sc_dmat, dmamap); 1698 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1699 break; 1700 } 1701 1702 IFQ_DEQUEUE(&ifp->if_snd, m0); 1703 1704 /* 1705 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1706 */ 1707 1708 DPRINTF(WM_DEBUG_TX, 1709 ("%s: TX: packet has %d (%d) DMA segments\n", 1710 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1711 1712 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1713 1714 /* 1715 * Store a pointer to the packet so that we can free it 1716 * later. 1717 * 1718 * Initially, we consider the number of descriptors the 1719 * packet uses the number of DMA segments. This may be 1720 * incremented by 1 if we do checksum offload (a descriptor 1721 * is used to set the checksum context). 1722 */ 1723 txs->txs_mbuf = m0; 1724 txs->txs_firstdesc = sc->sc_txnext; 1725 txs->txs_ndesc = segs_needed; 1726 1727 /* Set up offload parameters for this packet. */ 1728 if (m0->m_pkthdr.csum_flags & 1729 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1730 if (wm_tx_offload(sc, txs, &cksumcmd, 1731 &cksumfields) != 0) { 1732 /* Error message already displayed. */ 1733 bus_dmamap_unload(sc->sc_dmat, dmamap); 1734 continue; 1735 } 1736 } else { 1737 cksumcmd = 0; 1738 cksumfields = 0; 1739 } 1740 1741 cksumcmd |= WTX_CMD_IDE; 1742 1743 /* Sync the DMA map. */ 1744 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1745 BUS_DMASYNC_PREWRITE); 1746 1747 /* 1748 * Initialize the transmit descriptor. 1749 */ 1750 for (nexttx = sc->sc_txnext, seg = 0; 1751 seg < dmamap->dm_nsegs; seg++) { 1752 for (seglen = dmamap->dm_segs[seg].ds_len, 1753 curaddr = dmamap->dm_segs[seg].ds_addr; 1754 seglen != 0; 1755 curaddr += curlen, seglen -= curlen, 1756 nexttx = WM_NEXTTX(sc, nexttx)) { 1757 curlen = seglen; 1758 1759 wm_set_dma_addr( 1760 &sc->sc_txdescs[nexttx].wtx_addr, 1761 curaddr); 1762 sc->sc_txdescs[nexttx].wtx_cmdlen = 1763 htole32(cksumcmd | curlen); 1764 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1765 0; 1766 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1767 cksumfields; 1768 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1769 lasttx = nexttx; 1770 1771 DPRINTF(WM_DEBUG_TX, 1772 ("%s: TX: desc %d: low 0x%08x, " 1773 "len 0x%04x\n", 1774 sc->sc_dev.dv_xname, nexttx, 1775 curaddr & 0xffffffffU, curlen, curlen)); 1776 } 1777 } 1778 1779 KASSERT(lasttx != -1); 1780 1781 /* 1782 * Set up the command byte on the last descriptor of 1783 * the packet. If we're in the interrupt delay window, 1784 * delay the interrupt. 1785 */ 1786 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1787 htole32(WTX_CMD_EOP | WTX_CMD_IFCS | WTX_CMD_RS); 1788 1789 #if 0 /* XXXJRT */ 1790 /* 1791 * If VLANs are enabled and the packet has a VLAN tag, set 1792 * up the descriptor to encapsulate the packet for us. 1793 * 1794 * This is only valid on the last descriptor of the packet. 1795 */ 1796 if (sc->sc_ethercom.ec_nvlans != 0 && 1797 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1798 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1799 htole32(WTX_CMD_VLE); 1800 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1801 = htole16(*(u_int *)(mtag + 1) & 0xffff); 1802 } 1803 #endif /* XXXJRT */ 1804 1805 txs->txs_lastdesc = lasttx; 1806 1807 DPRINTF(WM_DEBUG_TX, 1808 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1809 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1810 1811 /* Sync the descriptors we're using. */ 1812 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1813 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1814 1815 /* Give the packet to the chip. */ 1816 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1817 1818 DPRINTF(WM_DEBUG_TX, 1819 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1820 1821 DPRINTF(WM_DEBUG_TX, 1822 ("%s: TX: finished transmitting packet, job %d\n", 1823 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1824 1825 /* Advance the tx pointer. */ 1826 sc->sc_txfree -= txs->txs_ndesc; 1827 sc->sc_txnext = nexttx; 1828 1829 sc->sc_txsfree--; 1830 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1831 1832 #if NBPFILTER > 0 1833 /* Pass the packet to any BPF listeners. */ 1834 if (ifp->if_bpf) 1835 bpf_mtap(ifp->if_bpf, m0); 1836 #endif /* NBPFILTER > 0 */ 1837 } 1838 1839 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1840 /* No more slots; notify upper layer. */ 1841 ifp->if_flags |= IFF_OACTIVE; 1842 } 1843 1844 if (sc->sc_txfree != ofree) { 1845 /* Set a watchdog timer in case the chip flakes out. */ 1846 ifp->if_timer = 5; 1847 } 1848 } 1849 1850 /* 1851 * wm_watchdog: [ifnet interface function] 1852 * 1853 * Watchdog timer handler. 1854 */ 1855 static void 1856 wm_watchdog(struct ifnet *ifp) 1857 { 1858 struct wm_softc *sc = ifp->if_softc; 1859 1860 /* 1861 * Since we're using delayed interrupts, sweep up 1862 * before we report an error. 1863 */ 1864 wm_txintr(sc); 1865 1866 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1867 log(LOG_ERR, 1868 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1869 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1870 sc->sc_txnext); 1871 ifp->if_oerrors++; 1872 1873 /* Reset the interface. */ 1874 (void) wm_init(ifp); 1875 } 1876 1877 /* Try to get more packets going. */ 1878 wm_start(ifp); 1879 } 1880 1881 /* 1882 * wm_ioctl: [ifnet interface function] 1883 * 1884 * Handle control requests from the operator. 1885 */ 1886 static int 1887 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1888 { 1889 struct wm_softc *sc = ifp->if_softc; 1890 struct ifreq *ifr = (struct ifreq *) data; 1891 int s, error; 1892 1893 s = splnet(); 1894 1895 switch (cmd) { 1896 case SIOCSIFMEDIA: 1897 case SIOCGIFMEDIA: 1898 /* Flow control requires full-duplex mode. */ 1899 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1900 (ifr->ifr_media & IFM_FDX) == 0) 1901 ifr->ifr_media &= ~IFM_ETH_FMASK; 1902 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1903 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1904 /* We can do both TXPAUSE and RXPAUSE. */ 1905 ifr->ifr_media |= 1906 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1907 } 1908 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1909 } 1910 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1911 break; 1912 default: 1913 error = ether_ioctl(ifp, cmd, data); 1914 if (error == ENETRESET) { 1915 /* 1916 * Multicast list has changed; set the hardware filter 1917 * accordingly. 1918 */ 1919 if (ifp->if_flags & IFF_RUNNING) 1920 wm_set_filter(sc); 1921 error = 0; 1922 } 1923 break; 1924 } 1925 1926 /* Try to get more packets going. */ 1927 wm_start(ifp); 1928 1929 splx(s); 1930 return (error); 1931 } 1932 1933 /* 1934 * wm_intr: 1935 * 1936 * Interrupt service routine. 1937 */ 1938 static int 1939 wm_intr(void *arg) 1940 { 1941 struct wm_softc *sc = arg; 1942 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1943 uint32_t icr; 1944 int wantinit, handled = 0; 1945 1946 for (wantinit = 0; wantinit == 0;) { 1947 icr = CSR_READ(sc, WMREG_ICR); 1948 if ((icr & sc->sc_icr) == 0) 1949 break; 1950 1951 #if 0 /*NRND > 0*/ 1952 if (RND_ENABLED(&sc->rnd_source)) 1953 rnd_add_uint32(&sc->rnd_source, icr); 1954 #endif 1955 1956 handled = 1; 1957 1958 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1959 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1960 DPRINTF(WM_DEBUG_RX, 1961 ("%s: RX: got Rx intr 0x%08x\n", 1962 sc->sc_dev.dv_xname, 1963 icr & (ICR_RXDMT0|ICR_RXT0))); 1964 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 1965 } 1966 #endif 1967 wm_rxintr(sc); 1968 1969 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1970 if (icr & ICR_TXDW) { 1971 DPRINTF(WM_DEBUG_TX, 1972 ("%s: TX: got TXDW interrupt\n", 1973 sc->sc_dev.dv_xname)); 1974 WM_EVCNT_INCR(&sc->sc_ev_txdw); 1975 } 1976 #endif 1977 wm_txintr(sc); 1978 1979 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 1980 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 1981 wm_linkintr(sc, icr); 1982 } 1983 1984 if (icr & ICR_RXO) { 1985 log(LOG_WARNING, "%s: Receive overrun\n", 1986 sc->sc_dev.dv_xname); 1987 wantinit = 1; 1988 } 1989 } 1990 1991 if (handled) { 1992 if (wantinit) 1993 wm_init(ifp); 1994 1995 /* Try to get more packets going. */ 1996 wm_start(ifp); 1997 } 1998 1999 return (handled); 2000 } 2001 2002 /* 2003 * wm_txintr: 2004 * 2005 * Helper; handle transmit interrupts. 2006 */ 2007 static void 2008 wm_txintr(struct wm_softc *sc) 2009 { 2010 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2011 struct wm_txsoft *txs; 2012 uint8_t status; 2013 int i; 2014 2015 ifp->if_flags &= ~IFF_OACTIVE; 2016 2017 /* 2018 * Go through the Tx list and free mbufs for those 2019 * frames which have been transmitted. 2020 */ 2021 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2022 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2023 txs = &sc->sc_txsoft[i]; 2024 2025 DPRINTF(WM_DEBUG_TX, 2026 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2027 2028 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2029 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2030 2031 status = 2032 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2033 if ((status & WTX_ST_DD) == 0) { 2034 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2035 BUS_DMASYNC_PREREAD); 2036 break; 2037 } 2038 2039 DPRINTF(WM_DEBUG_TX, 2040 ("%s: TX: job %d done: descs %d..%d\n", 2041 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2042 txs->txs_lastdesc)); 2043 2044 /* 2045 * XXX We should probably be using the statistics 2046 * XXX registers, but I don't know if they exist 2047 * XXX on chips before the i82544. 2048 */ 2049 2050 #ifdef WM_EVENT_COUNTERS 2051 if (status & WTX_ST_TU) 2052 WM_EVCNT_INCR(&sc->sc_ev_tu); 2053 #endif /* WM_EVENT_COUNTERS */ 2054 2055 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2056 ifp->if_oerrors++; 2057 if (status & WTX_ST_LC) 2058 log(LOG_WARNING, "%s: late collision\n", 2059 sc->sc_dev.dv_xname); 2060 else if (status & WTX_ST_EC) { 2061 ifp->if_collisions += 16; 2062 log(LOG_WARNING, "%s: excessive collisions\n", 2063 sc->sc_dev.dv_xname); 2064 } 2065 } else 2066 ifp->if_opackets++; 2067 2068 sc->sc_txfree += txs->txs_ndesc; 2069 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2070 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2071 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2072 m_freem(txs->txs_mbuf); 2073 txs->txs_mbuf = NULL; 2074 } 2075 2076 /* Update the dirty transmit buffer pointer. */ 2077 sc->sc_txsdirty = i; 2078 DPRINTF(WM_DEBUG_TX, 2079 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2080 2081 /* 2082 * If there are no more pending transmissions, cancel the watchdog 2083 * timer. 2084 */ 2085 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2086 ifp->if_timer = 0; 2087 } 2088 2089 /* 2090 * wm_rxintr: 2091 * 2092 * Helper; handle receive interrupts. 2093 */ 2094 static void 2095 wm_rxintr(struct wm_softc *sc) 2096 { 2097 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2098 struct wm_rxsoft *rxs; 2099 struct mbuf *m; 2100 int i, len; 2101 uint8_t status, errors; 2102 2103 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2104 rxs = &sc->sc_rxsoft[i]; 2105 2106 DPRINTF(WM_DEBUG_RX, 2107 ("%s: RX: checking descriptor %d\n", 2108 sc->sc_dev.dv_xname, i)); 2109 2110 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2111 2112 status = sc->sc_rxdescs[i].wrx_status; 2113 errors = sc->sc_rxdescs[i].wrx_errors; 2114 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2115 2116 if ((status & WRX_ST_DD) == 0) { 2117 /* 2118 * We have processed all of the receive descriptors. 2119 */ 2120 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2121 break; 2122 } 2123 2124 if (__predict_false(sc->sc_rxdiscard)) { 2125 DPRINTF(WM_DEBUG_RX, 2126 ("%s: RX: discarding contents of descriptor %d\n", 2127 sc->sc_dev.dv_xname, i)); 2128 WM_INIT_RXDESC(sc, i); 2129 if (status & WRX_ST_EOP) { 2130 /* Reset our state. */ 2131 DPRINTF(WM_DEBUG_RX, 2132 ("%s: RX: resetting rxdiscard -> 0\n", 2133 sc->sc_dev.dv_xname)); 2134 sc->sc_rxdiscard = 0; 2135 } 2136 continue; 2137 } 2138 2139 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2140 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2141 2142 m = rxs->rxs_mbuf; 2143 2144 /* 2145 * Add a new receive buffer to the ring. 2146 */ 2147 if (wm_add_rxbuf(sc, i) != 0) { 2148 /* 2149 * Failed, throw away what we've done so 2150 * far, and discard the rest of the packet. 2151 */ 2152 ifp->if_ierrors++; 2153 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2154 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2155 WM_INIT_RXDESC(sc, i); 2156 if ((status & WRX_ST_EOP) == 0) 2157 sc->sc_rxdiscard = 1; 2158 if (sc->sc_rxhead != NULL) 2159 m_freem(sc->sc_rxhead); 2160 WM_RXCHAIN_RESET(sc); 2161 DPRINTF(WM_DEBUG_RX, 2162 ("%s: RX: Rx buffer allocation failed, " 2163 "dropping packet%s\n", sc->sc_dev.dv_xname, 2164 sc->sc_rxdiscard ? " (discard)" : "")); 2165 continue; 2166 } 2167 2168 WM_RXCHAIN_LINK(sc, m); 2169 2170 m->m_len = len; 2171 2172 DPRINTF(WM_DEBUG_RX, 2173 ("%s: RX: buffer at %p len %d\n", 2174 sc->sc_dev.dv_xname, m->m_data, len)); 2175 2176 /* 2177 * If this is not the end of the packet, keep 2178 * looking. 2179 */ 2180 if ((status & WRX_ST_EOP) == 0) { 2181 sc->sc_rxlen += len; 2182 DPRINTF(WM_DEBUG_RX, 2183 ("%s: RX: not yet EOP, rxlen -> %d\n", 2184 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2185 continue; 2186 } 2187 2188 /* 2189 * Okay, we have the entire packet now... 2190 */ 2191 *sc->sc_rxtailp = NULL; 2192 m = sc->sc_rxhead; 2193 len += sc->sc_rxlen; 2194 2195 WM_RXCHAIN_RESET(sc); 2196 2197 DPRINTF(WM_DEBUG_RX, 2198 ("%s: RX: have entire packet, len -> %d\n", 2199 sc->sc_dev.dv_xname, len)); 2200 2201 /* 2202 * If an error occurred, update stats and drop the packet. 2203 */ 2204 if (errors & 2205 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2206 ifp->if_ierrors++; 2207 if (errors & WRX_ER_SE) 2208 log(LOG_WARNING, "%s: symbol error\n", 2209 sc->sc_dev.dv_xname); 2210 else if (errors & WRX_ER_SEQ) 2211 log(LOG_WARNING, "%s: receive sequence error\n", 2212 sc->sc_dev.dv_xname); 2213 else if (errors & WRX_ER_CE) 2214 log(LOG_WARNING, "%s: CRC error\n", 2215 sc->sc_dev.dv_xname); 2216 m_freem(m); 2217 continue; 2218 } 2219 2220 /* 2221 * No errors. Receive the packet. 2222 * 2223 * Note, we have configured the chip to include the 2224 * CRC with every packet. 2225 */ 2226 m->m_flags |= M_HASFCS; 2227 m->m_pkthdr.rcvif = ifp; 2228 m->m_pkthdr.len = len; 2229 2230 #if 0 /* XXXJRT */ 2231 /* 2232 * If VLANs are enabled, VLAN packets have been unwrapped 2233 * for us. Associate the tag with the packet. 2234 */ 2235 if (sc->sc_ethercom.ec_nvlans != 0 && 2236 (status & WRX_ST_VP) != 0) { 2237 struct m_tag *vtag; 2238 2239 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2240 M_NOWAIT); 2241 if (vtag == NULL) { 2242 ifp->if_ierrors++; 2243 log(LOG_ERR, 2244 "%s: unable to allocate VLAN tag\n", 2245 sc->sc_dev.dv_xname); 2246 m_freem(m); 2247 continue; 2248 } 2249 2250 *(u_int *)(vtag + 1) = 2251 le16toh(sc->sc_rxdescs[i].wrx_special); 2252 } 2253 #endif /* XXXJRT */ 2254 2255 /* 2256 * Set up checksum info for this packet. 2257 */ 2258 if (status & WRX_ST_IPCS) { 2259 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2260 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2261 if (errors & WRX_ER_IPE) 2262 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2263 } 2264 if (status & WRX_ST_TCPCS) { 2265 /* 2266 * Note: we don't know if this was TCP or UDP, 2267 * so we just set both bits, and expect the 2268 * upper layers to deal. 2269 */ 2270 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2271 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2272 if (errors & WRX_ER_TCPE) 2273 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2274 } 2275 2276 ifp->if_ipackets++; 2277 2278 #if NBPFILTER > 0 2279 /* Pass this up to any BPF listeners. */ 2280 if (ifp->if_bpf) 2281 bpf_mtap(ifp->if_bpf, m); 2282 #endif /* NBPFILTER > 0 */ 2283 2284 /* Pass it on. */ 2285 (*ifp->if_input)(ifp, m); 2286 } 2287 2288 /* Update the receive pointer. */ 2289 sc->sc_rxptr = i; 2290 2291 DPRINTF(WM_DEBUG_RX, 2292 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2293 } 2294 2295 /* 2296 * wm_linkintr: 2297 * 2298 * Helper; handle link interrupts. 2299 */ 2300 static void 2301 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2302 { 2303 uint32_t status; 2304 2305 /* 2306 * If we get a link status interrupt on a 1000BASE-T 2307 * device, just fall into the normal MII tick path. 2308 */ 2309 if (sc->sc_flags & WM_F_HAS_MII) { 2310 if (icr & ICR_LSC) { 2311 DPRINTF(WM_DEBUG_LINK, 2312 ("%s: LINK: LSC -> mii_tick\n", 2313 sc->sc_dev.dv_xname)); 2314 mii_tick(&sc->sc_mii); 2315 } else if (icr & ICR_RXSEQ) { 2316 DPRINTF(WM_DEBUG_LINK, 2317 ("%s: LINK Receive sequence error\n", 2318 sc->sc_dev.dv_xname)); 2319 } 2320 return; 2321 } 2322 2323 /* 2324 * If we are now receiving /C/, check for link again in 2325 * a couple of link clock ticks. 2326 */ 2327 if (icr & ICR_RXCFG) { 2328 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2329 sc->sc_dev.dv_xname)); 2330 sc->sc_tbi_anstate = 2; 2331 } 2332 2333 if (icr & ICR_LSC) { 2334 status = CSR_READ(sc, WMREG_STATUS); 2335 if (status & STATUS_LU) { 2336 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2337 sc->sc_dev.dv_xname, 2338 (status & STATUS_FD) ? "FDX" : "HDX")); 2339 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2340 sc->sc_fcrtl &= ~FCRTL_XONE; 2341 if (status & STATUS_FD) 2342 sc->sc_tctl |= 2343 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2344 else 2345 sc->sc_tctl |= 2346 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2347 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2348 sc->sc_fcrtl |= FCRTL_XONE; 2349 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2350 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2351 WMREG_OLD_FCRTL : WMREG_FCRTL, 2352 sc->sc_fcrtl); 2353 sc->sc_tbi_linkup = 1; 2354 } else { 2355 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2356 sc->sc_dev.dv_xname)); 2357 sc->sc_tbi_linkup = 0; 2358 } 2359 sc->sc_tbi_anstate = 2; 2360 wm_tbi_set_linkled(sc); 2361 } else if (icr & ICR_RXSEQ) { 2362 DPRINTF(WM_DEBUG_LINK, 2363 ("%s: LINK: Receive sequence error\n", 2364 sc->sc_dev.dv_xname)); 2365 } 2366 } 2367 2368 /* 2369 * wm_tick: 2370 * 2371 * One second timer, used to check link status, sweep up 2372 * completed transmit jobs, etc. 2373 */ 2374 static void 2375 wm_tick(void *arg) 2376 { 2377 struct wm_softc *sc = arg; 2378 int s; 2379 2380 s = splnet(); 2381 2382 if (sc->sc_type >= WM_T_82542_2_1) { 2383 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2384 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2385 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2386 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2387 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2388 } 2389 2390 if (sc->sc_flags & WM_F_HAS_MII) 2391 mii_tick(&sc->sc_mii); 2392 else 2393 wm_tbi_check_link(sc); 2394 2395 splx(s); 2396 2397 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2398 } 2399 2400 /* 2401 * wm_reset: 2402 * 2403 * Reset the i82542 chip. 2404 */ 2405 static void 2406 wm_reset(struct wm_softc *sc) 2407 { 2408 int i; 2409 2410 /* 2411 * Allocate on-chip memory according to the MTU size. 2412 * The Packet Buffer Allocation register must be written 2413 * before the chip is reset. 2414 */ 2415 if (sc->sc_type < WM_T_82547) { 2416 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2417 PBA_40K : PBA_48K; 2418 } else { 2419 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2420 PBA_22K : PBA_30K; 2421 sc->sc_txfifo_head = 0; 2422 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2423 sc->sc_txfifo_size = 2424 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2425 sc->sc_txfifo_stall = 0; 2426 } 2427 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2428 2429 switch (sc->sc_type) { 2430 case WM_T_82544: 2431 case WM_T_82540: 2432 case WM_T_82545: 2433 case WM_T_82546: 2434 case WM_T_82541: 2435 case WM_T_82541_2: 2436 /* 2437 * On some chipsets, a reset through a memory-mapped write 2438 * cycle can cause the chip to reset before completing the 2439 * write cycle. This causes major headache that can be 2440 * avoided by issuing the reset via indirect register writes 2441 * through I/O space. 2442 * 2443 * So, if we successfully mapped the I/O BAR at attach time, 2444 * use that. Otherwise, try our luck with a memory-mapped 2445 * reset. 2446 */ 2447 if (sc->sc_flags & WM_F_IOH_VALID) 2448 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2449 else 2450 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2451 break; 2452 2453 case WM_T_82545_3: 2454 case WM_T_82546_3: 2455 /* Use the shadow control register on these chips. */ 2456 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2457 break; 2458 2459 default: 2460 /* Everything else can safely use the documented method. */ 2461 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2462 break; 2463 } 2464 delay(10000); 2465 2466 for (i = 0; i < 1000; i++) { 2467 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2468 return; 2469 delay(20); 2470 } 2471 2472 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2473 log(LOG_ERR, "%s: reset failed to complete\n", 2474 sc->sc_dev.dv_xname); 2475 } 2476 2477 /* 2478 * wm_init: [ifnet interface function] 2479 * 2480 * Initialize the interface. Must be called at splnet(). 2481 */ 2482 static int 2483 wm_init(struct ifnet *ifp) 2484 { 2485 struct wm_softc *sc = ifp->if_softc; 2486 struct wm_rxsoft *rxs; 2487 int i, error = 0; 2488 uint32_t reg; 2489 2490 /* 2491 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2492 * There is a small but measurable benefit to avoiding the adjusment 2493 * of the descriptor so that the headers are aligned, for normal mtu, 2494 * on such platforms. One possibility is that the DMA itself is 2495 * slightly more efficient if the front of the entire packet (instead 2496 * of the front of the headers) is aligned. 2497 * 2498 * Note we must always set align_tweak to 0 if we are using 2499 * jumbo frames. 2500 */ 2501 #ifdef __NO_STRICT_ALIGNMENT 2502 sc->sc_align_tweak = 0; 2503 #else 2504 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2505 sc->sc_align_tweak = 0; 2506 else 2507 sc->sc_align_tweak = 2; 2508 #endif /* __NO_STRICT_ALIGNMENT */ 2509 2510 /* Cancel any pending I/O. */ 2511 wm_stop(ifp, 0); 2512 2513 /* Reset the chip to a known state. */ 2514 wm_reset(sc); 2515 2516 /* Initialize the transmit descriptor ring. */ 2517 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2518 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2519 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2520 sc->sc_txfree = WM_NTXDESC(sc); 2521 sc->sc_txnext = 0; 2522 2523 if (sc->sc_type < WM_T_82543) { 2524 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2525 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2526 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2527 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2528 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2529 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2530 } else { 2531 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2532 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2533 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2534 CSR_WRITE(sc, WMREG_TDH, 0); 2535 CSR_WRITE(sc, WMREG_TDT, 0); 2536 CSR_WRITE(sc, WMREG_TIDV, 128); 2537 2538 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2539 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2540 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2541 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2542 } 2543 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2544 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2545 2546 /* Initialize the transmit job descriptors. */ 2547 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2548 sc->sc_txsoft[i].txs_mbuf = NULL; 2549 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2550 sc->sc_txsnext = 0; 2551 sc->sc_txsdirty = 0; 2552 2553 /* 2554 * Initialize the receive descriptor and receive job 2555 * descriptor rings. 2556 */ 2557 if (sc->sc_type < WM_T_82543) { 2558 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2559 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2560 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2561 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2562 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2563 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2564 2565 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2566 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2567 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2568 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2569 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2570 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2571 } else { 2572 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2573 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2574 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2575 CSR_WRITE(sc, WMREG_RDH, 0); 2576 CSR_WRITE(sc, WMREG_RDT, 0); 2577 CSR_WRITE(sc, WMREG_RDTR, 28 | RDTR_FPD); 2578 } 2579 for (i = 0; i < WM_NRXDESC; i++) { 2580 rxs = &sc->sc_rxsoft[i]; 2581 if (rxs->rxs_mbuf == NULL) { 2582 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2583 log(LOG_ERR, "%s: unable to allocate or map rx " 2584 "buffer %d, error = %d\n", 2585 sc->sc_dev.dv_xname, i, error); 2586 /* 2587 * XXX Should attempt to run with fewer receive 2588 * XXX buffers instead of just failing. 2589 */ 2590 wm_rxdrain(sc); 2591 goto out; 2592 } 2593 } else 2594 WM_INIT_RXDESC(sc, i); 2595 } 2596 sc->sc_rxptr = 0; 2597 sc->sc_rxdiscard = 0; 2598 WM_RXCHAIN_RESET(sc); 2599 2600 /* 2601 * Clear out the VLAN table -- we don't use it (yet). 2602 */ 2603 CSR_WRITE(sc, WMREG_VET, 0); 2604 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2605 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2606 2607 /* 2608 * Set up flow-control parameters. 2609 * 2610 * XXX Values could probably stand some tuning. 2611 */ 2612 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2613 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2614 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2615 2616 sc->sc_fcrtl = FCRTL_DFLT; 2617 if (sc->sc_type < WM_T_82543) { 2618 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2619 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2620 } else { 2621 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2622 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2623 } 2624 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2625 2626 #if 0 /* XXXJRT */ 2627 /* Deal with VLAN enables. */ 2628 if (sc->sc_ethercom.ec_nvlans != 0) 2629 sc->sc_ctrl |= CTRL_VME; 2630 else 2631 #endif /* XXXJRT */ 2632 sc->sc_ctrl &= ~CTRL_VME; 2633 2634 /* Write the control registers. */ 2635 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2636 #if 0 2637 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2638 #endif 2639 2640 /* 2641 * Set up checksum offload parameters. 2642 */ 2643 reg = CSR_READ(sc, WMREG_RXCSUM); 2644 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2645 reg |= RXCSUM_IPOFL; 2646 else 2647 reg &= ~RXCSUM_IPOFL; 2648 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2649 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2650 else { 2651 reg &= ~RXCSUM_TUOFL; 2652 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2653 reg &= ~RXCSUM_IPOFL; 2654 } 2655 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2656 2657 /* 2658 * Set up the interrupt registers. 2659 */ 2660 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2661 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2662 ICR_RXO | ICR_RXT0; 2663 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2664 sc->sc_icr |= ICR_RXCFG; 2665 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2666 2667 /* Set up the inter-packet gap. */ 2668 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2669 2670 #if 0 /* XXXJRT */ 2671 /* Set the VLAN ethernetype. */ 2672 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2673 #endif 2674 2675 /* 2676 * Set up the transmit control register; we start out with 2677 * a collision distance suitable for FDX, but update it whe 2678 * we resolve the media type. 2679 */ 2680 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2681 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2682 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2683 2684 /* Set the media. */ 2685 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2686 2687 /* 2688 * Set up the receive control register; we actually program 2689 * the register when we set the receive filter. Use multicast 2690 * address offset type 0. 2691 * 2692 * Only the i82544 has the ability to strip the incoming 2693 * CRC, so we don't enable that feature. 2694 */ 2695 sc->sc_mchash_type = 0; 2696 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2697 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2698 2699 if(MCLBYTES == 2048) { 2700 sc->sc_rctl |= RCTL_2k; 2701 } else { 2702 if(sc->sc_type >= WM_T_82543) { 2703 switch(MCLBYTES) { 2704 case 4096: 2705 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2706 break; 2707 case 8192: 2708 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2709 break; 2710 case 16384: 2711 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2712 break; 2713 default: 2714 panic("wm_init: MCLBYTES %d unsupported", 2715 MCLBYTES); 2716 break; 2717 } 2718 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2719 } 2720 2721 /* Set the receive filter. */ 2722 wm_set_filter(sc); 2723 2724 /* Start the one second link check clock. */ 2725 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2726 2727 /* ...all done! */ 2728 ifp->if_flags |= IFF_RUNNING; 2729 ifp->if_flags &= ~IFF_OACTIVE; 2730 2731 out: 2732 if (error) 2733 log(LOG_ERR, "%s: interface not running\n", 2734 sc->sc_dev.dv_xname); 2735 return (error); 2736 } 2737 2738 /* 2739 * wm_rxdrain: 2740 * 2741 * Drain the receive queue. 2742 */ 2743 static void 2744 wm_rxdrain(struct wm_softc *sc) 2745 { 2746 struct wm_rxsoft *rxs; 2747 int i; 2748 2749 for (i = 0; i < WM_NRXDESC; i++) { 2750 rxs = &sc->sc_rxsoft[i]; 2751 if (rxs->rxs_mbuf != NULL) { 2752 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2753 m_freem(rxs->rxs_mbuf); 2754 rxs->rxs_mbuf = NULL; 2755 } 2756 } 2757 } 2758 2759 /* 2760 * wm_stop: [ifnet interface function] 2761 * 2762 * Stop transmission on the interface. 2763 */ 2764 static void 2765 wm_stop(struct ifnet *ifp, int disable) 2766 { 2767 struct wm_softc *sc = ifp->if_softc; 2768 struct wm_txsoft *txs; 2769 int i; 2770 2771 /* Stop the one second clock. */ 2772 callout_stop(&sc->sc_tick_ch); 2773 2774 /* Stop the 82547 Tx FIFO stall check timer. */ 2775 if (sc->sc_type == WM_T_82547) 2776 callout_stop(&sc->sc_txfifo_ch); 2777 2778 if (sc->sc_flags & WM_F_HAS_MII) { 2779 /* Down the MII. */ 2780 mii_down(&sc->sc_mii); 2781 } 2782 2783 /* Stop the transmit and receive processes. */ 2784 CSR_WRITE(sc, WMREG_TCTL, 0); 2785 CSR_WRITE(sc, WMREG_RCTL, 0); 2786 2787 /* Release any queued transmit buffers. */ 2788 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2789 txs = &sc->sc_txsoft[i]; 2790 if (txs->txs_mbuf != NULL) { 2791 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2792 m_freem(txs->txs_mbuf); 2793 txs->txs_mbuf = NULL; 2794 } 2795 } 2796 2797 if (disable) 2798 wm_rxdrain(sc); 2799 2800 /* Mark the interface as down and cancel the watchdog timer. */ 2801 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2802 ifp->if_timer = 0; 2803 } 2804 2805 /* 2806 * wm_acquire_eeprom: 2807 * 2808 * Perform the EEPROM handshake required on some chips. 2809 */ 2810 static int 2811 wm_acquire_eeprom(struct wm_softc *sc) 2812 { 2813 uint32_t reg; 2814 int x; 2815 2816 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2817 reg = CSR_READ(sc, WMREG_EECD); 2818 2819 /* Request EEPROM access. */ 2820 reg |= EECD_EE_REQ; 2821 CSR_WRITE(sc, WMREG_EECD, reg); 2822 2823 /* ..and wait for it to be granted. */ 2824 for (x = 0; x < 100; x++) { 2825 reg = CSR_READ(sc, WMREG_EECD); 2826 if (reg & EECD_EE_GNT) 2827 break; 2828 delay(5); 2829 } 2830 if ((reg & EECD_EE_GNT) == 0) { 2831 aprint_error("%s: could not acquire EEPROM GNT\n", 2832 sc->sc_dev.dv_xname); 2833 reg &= ~EECD_EE_REQ; 2834 CSR_WRITE(sc, WMREG_EECD, reg); 2835 return (1); 2836 } 2837 } 2838 2839 return (0); 2840 } 2841 2842 /* 2843 * wm_release_eeprom: 2844 * 2845 * Release the EEPROM mutex. 2846 */ 2847 static void 2848 wm_release_eeprom(struct wm_softc *sc) 2849 { 2850 uint32_t reg; 2851 2852 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2853 reg = CSR_READ(sc, WMREG_EECD); 2854 reg &= ~EECD_EE_REQ; 2855 CSR_WRITE(sc, WMREG_EECD, reg); 2856 } 2857 } 2858 2859 /* 2860 * wm_eeprom_sendbits: 2861 * 2862 * Send a series of bits to the EEPROM. 2863 */ 2864 static void 2865 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2866 { 2867 uint32_t reg; 2868 int x; 2869 2870 reg = CSR_READ(sc, WMREG_EECD); 2871 2872 for (x = nbits; x > 0; x--) { 2873 if (bits & (1U << (x - 1))) 2874 reg |= EECD_DI; 2875 else 2876 reg &= ~EECD_DI; 2877 CSR_WRITE(sc, WMREG_EECD, reg); 2878 delay(2); 2879 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2880 delay(2); 2881 CSR_WRITE(sc, WMREG_EECD, reg); 2882 delay(2); 2883 } 2884 } 2885 2886 /* 2887 * wm_eeprom_recvbits: 2888 * 2889 * Receive a series of bits from the EEPROM. 2890 */ 2891 static void 2892 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2893 { 2894 uint32_t reg, val; 2895 int x; 2896 2897 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2898 2899 val = 0; 2900 for (x = nbits; x > 0; x--) { 2901 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2902 delay(2); 2903 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2904 val |= (1U << (x - 1)); 2905 CSR_WRITE(sc, WMREG_EECD, reg); 2906 delay(2); 2907 } 2908 *valp = val; 2909 } 2910 2911 /* 2912 * wm_read_eeprom_uwire: 2913 * 2914 * Read a word from the EEPROM using the MicroWire protocol. 2915 */ 2916 static int 2917 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2918 { 2919 uint32_t reg, val; 2920 int i; 2921 2922 for (i = 0; i < wordcnt; i++) { 2923 /* Clear SK and DI. */ 2924 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2925 CSR_WRITE(sc, WMREG_EECD, reg); 2926 2927 /* Set CHIP SELECT. */ 2928 reg |= EECD_CS; 2929 CSR_WRITE(sc, WMREG_EECD, reg); 2930 delay(2); 2931 2932 /* Shift in the READ command. */ 2933 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2934 2935 /* Shift in address. */ 2936 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2937 2938 /* Shift out the data. */ 2939 wm_eeprom_recvbits(sc, &val, 16); 2940 data[i] = val & 0xffff; 2941 2942 /* Clear CHIP SELECT. */ 2943 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 2944 CSR_WRITE(sc, WMREG_EECD, reg); 2945 delay(2); 2946 } 2947 2948 return (0); 2949 } 2950 2951 /* 2952 * wm_spi_eeprom_ready: 2953 * 2954 * Wait for a SPI EEPROM to be ready for commands. 2955 */ 2956 static int 2957 wm_spi_eeprom_ready(struct wm_softc *sc) 2958 { 2959 uint32_t val; 2960 int usec; 2961 2962 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 2963 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 2964 wm_eeprom_recvbits(sc, &val, 8); 2965 if ((val & SPI_SR_RDY) == 0) 2966 break; 2967 } 2968 if (usec >= SPI_MAX_RETRIES) { 2969 aprint_error("%s: EEPROM failed to become ready\n", 2970 sc->sc_dev.dv_xname); 2971 return (1); 2972 } 2973 return (0); 2974 } 2975 2976 /* 2977 * wm_read_eeprom_spi: 2978 * 2979 * Read a work from the EEPROM using the SPI protocol. 2980 */ 2981 static int 2982 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2983 { 2984 uint32_t reg, val; 2985 int i; 2986 uint8_t opc; 2987 2988 /* Clear SK and CS. */ 2989 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 2990 CSR_WRITE(sc, WMREG_EECD, reg); 2991 delay(2); 2992 2993 if (wm_spi_eeprom_ready(sc)) 2994 return (1); 2995 2996 /* Toggle CS to flush commands. */ 2997 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 2998 delay(2); 2999 CSR_WRITE(sc, WMREG_EECD, reg); 3000 delay(2); 3001 3002 opc = SPI_OPC_READ; 3003 if (sc->sc_ee_addrbits == 8 && word >= 128) 3004 opc |= SPI_OPC_A8; 3005 3006 wm_eeprom_sendbits(sc, opc, 8); 3007 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3008 3009 for (i = 0; i < wordcnt; i++) { 3010 wm_eeprom_recvbits(sc, &val, 16); 3011 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3012 } 3013 3014 /* Raise CS and clear SK. */ 3015 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3016 CSR_WRITE(sc, WMREG_EECD, reg); 3017 delay(2); 3018 3019 return (0); 3020 } 3021 3022 /* 3023 * wm_read_eeprom: 3024 * 3025 * Read data from the serial EEPROM. 3026 */ 3027 static int 3028 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3029 { 3030 int rv; 3031 3032 if (wm_acquire_eeprom(sc)) 3033 return (1); 3034 3035 if (sc->sc_flags & WM_F_EEPROM_SPI) 3036 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3037 else 3038 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3039 3040 wm_release_eeprom(sc); 3041 return (rv); 3042 } 3043 3044 /* 3045 * wm_add_rxbuf: 3046 * 3047 * Add a receive buffer to the indiciated descriptor. 3048 */ 3049 static int 3050 wm_add_rxbuf(struct wm_softc *sc, int idx) 3051 { 3052 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3053 struct mbuf *m; 3054 int error; 3055 3056 MGETHDR(m, M_DONTWAIT, MT_DATA); 3057 if (m == NULL) 3058 return (ENOBUFS); 3059 3060 MCLGET(m, M_DONTWAIT); 3061 if ((m->m_flags & M_EXT) == 0) { 3062 m_freem(m); 3063 return (ENOBUFS); 3064 } 3065 3066 if (rxs->rxs_mbuf != NULL) 3067 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3068 3069 rxs->rxs_mbuf = m; 3070 3071 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3072 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3073 BUS_DMA_READ|BUS_DMA_NOWAIT); 3074 if (error) { 3075 /* XXX XXX XXX */ 3076 printf("%s: unable to load rx DMA map %d, error = %d\n", 3077 sc->sc_dev.dv_xname, idx, error); 3078 panic("wm_add_rxbuf"); 3079 } 3080 3081 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3082 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3083 3084 WM_INIT_RXDESC(sc, idx); 3085 3086 return (0); 3087 } 3088 3089 /* 3090 * wm_set_ral: 3091 * 3092 * Set an entery in the receive address list. 3093 */ 3094 static void 3095 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3096 { 3097 uint32_t ral_lo, ral_hi; 3098 3099 if (enaddr != NULL) { 3100 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3101 (enaddr[3] << 24); 3102 ral_hi = enaddr[4] | (enaddr[5] << 8); 3103 ral_hi |= RAL_AV; 3104 } else { 3105 ral_lo = 0; 3106 ral_hi = 0; 3107 } 3108 3109 if (sc->sc_type >= WM_T_82544) { 3110 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3111 ral_lo); 3112 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3113 ral_hi); 3114 } else { 3115 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3116 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3117 } 3118 } 3119 3120 /* 3121 * wm_mchash: 3122 * 3123 * Compute the hash of the multicast address for the 4096-bit 3124 * multicast filter. 3125 */ 3126 static uint32_t 3127 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3128 { 3129 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3130 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3131 uint32_t hash; 3132 3133 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3134 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3135 3136 return (hash & 0xfff); 3137 } 3138 3139 /* 3140 * wm_set_filter: 3141 * 3142 * Set up the receive filter. 3143 */ 3144 static void 3145 wm_set_filter(struct wm_softc *sc) 3146 { 3147 struct ethercom *ec = &sc->sc_ethercom; 3148 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3149 struct ether_multi *enm; 3150 struct ether_multistep step; 3151 bus_addr_t mta_reg; 3152 uint32_t hash, reg, bit; 3153 int i; 3154 3155 if (sc->sc_type >= WM_T_82544) 3156 mta_reg = WMREG_CORDOVA_MTA; 3157 else 3158 mta_reg = WMREG_MTA; 3159 3160 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3161 3162 if (ifp->if_flags & IFF_BROADCAST) 3163 sc->sc_rctl |= RCTL_BAM; 3164 if (ifp->if_flags & IFF_PROMISC) { 3165 sc->sc_rctl |= RCTL_UPE; 3166 goto allmulti; 3167 } 3168 3169 /* 3170 * Set the station address in the first RAL slot, and 3171 * clear the remaining slots. 3172 */ 3173 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3174 for (i = 1; i < WM_RAL_TABSIZE; i++) 3175 wm_set_ral(sc, NULL, i); 3176 3177 /* Clear out the multicast table. */ 3178 for (i = 0; i < WM_MC_TABSIZE; i++) 3179 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3180 3181 ETHER_FIRST_MULTI(step, ec, enm); 3182 while (enm != NULL) { 3183 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3184 /* 3185 * We must listen to a range of multicast addresses. 3186 * For now, just accept all multicasts, rather than 3187 * trying to set only those filter bits needed to match 3188 * the range. (At this time, the only use of address 3189 * ranges is for IP multicast routing, for which the 3190 * range is big enough to require all bits set.) 3191 */ 3192 goto allmulti; 3193 } 3194 3195 hash = wm_mchash(sc, enm->enm_addrlo); 3196 3197 reg = (hash >> 5) & 0x7f; 3198 bit = hash & 0x1f; 3199 3200 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3201 hash |= 1U << bit; 3202 3203 /* XXX Hardware bug?? */ 3204 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3205 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3206 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3207 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3208 } else 3209 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3210 3211 ETHER_NEXT_MULTI(step, enm); 3212 } 3213 3214 ifp->if_flags &= ~IFF_ALLMULTI; 3215 goto setit; 3216 3217 allmulti: 3218 ifp->if_flags |= IFF_ALLMULTI; 3219 sc->sc_rctl |= RCTL_MPE; 3220 3221 setit: 3222 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3223 } 3224 3225 /* 3226 * wm_tbi_mediainit: 3227 * 3228 * Initialize media for use on 1000BASE-X devices. 3229 */ 3230 static void 3231 wm_tbi_mediainit(struct wm_softc *sc) 3232 { 3233 const char *sep = ""; 3234 3235 if (sc->sc_type < WM_T_82543) 3236 sc->sc_tipg = TIPG_WM_DFLT; 3237 else 3238 sc->sc_tipg = TIPG_LG_DFLT; 3239 3240 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3241 wm_tbi_mediastatus); 3242 3243 /* 3244 * SWD Pins: 3245 * 3246 * 0 = Link LED (output) 3247 * 1 = Loss Of Signal (input) 3248 */ 3249 sc->sc_ctrl |= CTRL_SWDPIO(0); 3250 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3251 3252 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3253 3254 #define ADD(ss, mm, dd) \ 3255 do { \ 3256 aprint_normal("%s%s", sep, ss); \ 3257 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3258 sep = ", "; \ 3259 } while (/*CONSTCOND*/0) 3260 3261 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3262 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3263 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3264 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3265 aprint_normal("\n"); 3266 3267 #undef ADD 3268 3269 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3270 } 3271 3272 /* 3273 * wm_tbi_mediastatus: [ifmedia interface function] 3274 * 3275 * Get the current interface media status on a 1000BASE-X device. 3276 */ 3277 static void 3278 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3279 { 3280 struct wm_softc *sc = ifp->if_softc; 3281 uint32_t ctrl; 3282 3283 ifmr->ifm_status = IFM_AVALID; 3284 ifmr->ifm_active = IFM_ETHER; 3285 3286 if (sc->sc_tbi_linkup == 0) { 3287 ifmr->ifm_active |= IFM_NONE; 3288 return; 3289 } 3290 3291 ifmr->ifm_status |= IFM_ACTIVE; 3292 ifmr->ifm_active |= IFM_1000_SX; 3293 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3294 ifmr->ifm_active |= IFM_FDX; 3295 ctrl = CSR_READ(sc, WMREG_CTRL); 3296 if (ctrl & CTRL_RFCE) 3297 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3298 if (ctrl & CTRL_TFCE) 3299 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3300 } 3301 3302 /* 3303 * wm_tbi_mediachange: [ifmedia interface function] 3304 * 3305 * Set hardware to newly-selected media on a 1000BASE-X device. 3306 */ 3307 static int 3308 wm_tbi_mediachange(struct ifnet *ifp) 3309 { 3310 struct wm_softc *sc = ifp->if_softc; 3311 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3312 uint32_t status; 3313 int i; 3314 3315 sc->sc_txcw = ife->ifm_data; 3316 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3317 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3318 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3319 sc->sc_txcw |= TXCW_ANE; 3320 3321 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3322 delay(10000); 3323 3324 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3325 3326 sc->sc_tbi_anstate = 0; 3327 3328 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3329 /* Have signal; wait for the link to come up. */ 3330 for (i = 0; i < 50; i++) { 3331 delay(10000); 3332 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3333 break; 3334 } 3335 3336 status = CSR_READ(sc, WMREG_STATUS); 3337 if (status & STATUS_LU) { 3338 /* Link is up. */ 3339 DPRINTF(WM_DEBUG_LINK, 3340 ("%s: LINK: set media -> link up %s\n", 3341 sc->sc_dev.dv_xname, 3342 (status & STATUS_FD) ? "FDX" : "HDX")); 3343 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3344 sc->sc_fcrtl &= ~FCRTL_XONE; 3345 if (status & STATUS_FD) 3346 sc->sc_tctl |= 3347 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3348 else 3349 sc->sc_tctl |= 3350 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3351 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3352 sc->sc_fcrtl |= FCRTL_XONE; 3353 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3354 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3355 WMREG_OLD_FCRTL : WMREG_FCRTL, 3356 sc->sc_fcrtl); 3357 sc->sc_tbi_linkup = 1; 3358 } else { 3359 /* Link is down. */ 3360 DPRINTF(WM_DEBUG_LINK, 3361 ("%s: LINK: set media -> link down\n", 3362 sc->sc_dev.dv_xname)); 3363 sc->sc_tbi_linkup = 0; 3364 } 3365 } else { 3366 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3367 sc->sc_dev.dv_xname)); 3368 sc->sc_tbi_linkup = 0; 3369 } 3370 3371 wm_tbi_set_linkled(sc); 3372 3373 return (0); 3374 } 3375 3376 /* 3377 * wm_tbi_set_linkled: 3378 * 3379 * Update the link LED on 1000BASE-X devices. 3380 */ 3381 static void 3382 wm_tbi_set_linkled(struct wm_softc *sc) 3383 { 3384 3385 if (sc->sc_tbi_linkup) 3386 sc->sc_ctrl |= CTRL_SWDPIN(0); 3387 else 3388 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3389 3390 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3391 } 3392 3393 /* 3394 * wm_tbi_check_link: 3395 * 3396 * Check the link on 1000BASE-X devices. 3397 */ 3398 static void 3399 wm_tbi_check_link(struct wm_softc *sc) 3400 { 3401 uint32_t rxcw, ctrl, status; 3402 3403 if (sc->sc_tbi_anstate == 0) 3404 return; 3405 else if (sc->sc_tbi_anstate > 1) { 3406 DPRINTF(WM_DEBUG_LINK, 3407 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3408 sc->sc_tbi_anstate)); 3409 sc->sc_tbi_anstate--; 3410 return; 3411 } 3412 3413 sc->sc_tbi_anstate = 0; 3414 3415 rxcw = CSR_READ(sc, WMREG_RXCW); 3416 ctrl = CSR_READ(sc, WMREG_CTRL); 3417 status = CSR_READ(sc, WMREG_STATUS); 3418 3419 if ((status & STATUS_LU) == 0) { 3420 DPRINTF(WM_DEBUG_LINK, 3421 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3422 sc->sc_tbi_linkup = 0; 3423 } else { 3424 DPRINTF(WM_DEBUG_LINK, 3425 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3426 (status & STATUS_FD) ? "FDX" : "HDX")); 3427 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3428 sc->sc_fcrtl &= ~FCRTL_XONE; 3429 if (status & STATUS_FD) 3430 sc->sc_tctl |= 3431 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3432 else 3433 sc->sc_tctl |= 3434 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3435 if (ctrl & CTRL_TFCE) 3436 sc->sc_fcrtl |= FCRTL_XONE; 3437 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3438 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3439 WMREG_OLD_FCRTL : WMREG_FCRTL, 3440 sc->sc_fcrtl); 3441 sc->sc_tbi_linkup = 1; 3442 } 3443 3444 wm_tbi_set_linkled(sc); 3445 } 3446 3447 /* 3448 * wm_gmii_reset: 3449 * 3450 * Reset the PHY. 3451 */ 3452 static void 3453 wm_gmii_reset(struct wm_softc *sc) 3454 { 3455 uint32_t reg; 3456 3457 if (sc->sc_type >= WM_T_82544) { 3458 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3459 delay(20000); 3460 3461 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3462 delay(20000); 3463 } else { 3464 /* The PHY reset pin is active-low. */ 3465 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3466 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3467 CTRL_EXT_SWDPIN(4)); 3468 reg |= CTRL_EXT_SWDPIO(4); 3469 3470 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3471 delay(10); 3472 3473 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3474 delay(10); 3475 3476 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3477 delay(10); 3478 #if 0 3479 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3480 #endif 3481 } 3482 } 3483 3484 /* 3485 * wm_gmii_mediainit: 3486 * 3487 * Initialize media for use on 1000BASE-T devices. 3488 */ 3489 static void 3490 wm_gmii_mediainit(struct wm_softc *sc) 3491 { 3492 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3493 3494 /* We have MII. */ 3495 sc->sc_flags |= WM_F_HAS_MII; 3496 3497 sc->sc_tipg = TIPG_1000T_DFLT; 3498 3499 /* 3500 * Let the chip set speed/duplex on its own based on 3501 * signals from the PHY. 3502 */ 3503 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3504 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3505 3506 /* Initialize our media structures and probe the GMII. */ 3507 sc->sc_mii.mii_ifp = ifp; 3508 3509 if (sc->sc_type >= WM_T_82544) { 3510 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3511 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3512 } else { 3513 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3514 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3515 } 3516 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3517 3518 wm_gmii_reset(sc); 3519 3520 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3521 wm_gmii_mediastatus); 3522 3523 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3524 MII_OFFSET_ANY, MIIF_DOPAUSE); 3525 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3526 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3527 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3528 } else 3529 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3530 } 3531 3532 /* 3533 * wm_gmii_mediastatus: [ifmedia interface function] 3534 * 3535 * Get the current interface media status on a 1000BASE-T device. 3536 */ 3537 static void 3538 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3539 { 3540 struct wm_softc *sc = ifp->if_softc; 3541 3542 mii_pollstat(&sc->sc_mii); 3543 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3544 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3545 sc->sc_flowflags; 3546 } 3547 3548 /* 3549 * wm_gmii_mediachange: [ifmedia interface function] 3550 * 3551 * Set hardware to newly-selected media on a 1000BASE-T device. 3552 */ 3553 static int 3554 wm_gmii_mediachange(struct ifnet *ifp) 3555 { 3556 struct wm_softc *sc = ifp->if_softc; 3557 3558 if (ifp->if_flags & IFF_UP) 3559 mii_mediachg(&sc->sc_mii); 3560 return (0); 3561 } 3562 3563 #define MDI_IO CTRL_SWDPIN(2) 3564 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3565 #define MDI_CLK CTRL_SWDPIN(3) 3566 3567 static void 3568 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3569 { 3570 uint32_t i, v; 3571 3572 v = CSR_READ(sc, WMREG_CTRL); 3573 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3574 v |= MDI_DIR | CTRL_SWDPIO(3); 3575 3576 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3577 if (data & i) 3578 v |= MDI_IO; 3579 else 3580 v &= ~MDI_IO; 3581 CSR_WRITE(sc, WMREG_CTRL, v); 3582 delay(10); 3583 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3584 delay(10); 3585 CSR_WRITE(sc, WMREG_CTRL, v); 3586 delay(10); 3587 } 3588 } 3589 3590 static uint32_t 3591 i82543_mii_recvbits(struct wm_softc *sc) 3592 { 3593 uint32_t v, i, data = 0; 3594 3595 v = CSR_READ(sc, WMREG_CTRL); 3596 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3597 v |= CTRL_SWDPIO(3); 3598 3599 CSR_WRITE(sc, WMREG_CTRL, v); 3600 delay(10); 3601 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3602 delay(10); 3603 CSR_WRITE(sc, WMREG_CTRL, v); 3604 delay(10); 3605 3606 for (i = 0; i < 16; i++) { 3607 data <<= 1; 3608 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3609 delay(10); 3610 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3611 data |= 1; 3612 CSR_WRITE(sc, WMREG_CTRL, v); 3613 delay(10); 3614 } 3615 3616 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3617 delay(10); 3618 CSR_WRITE(sc, WMREG_CTRL, v); 3619 delay(10); 3620 3621 return (data); 3622 } 3623 3624 #undef MDI_IO 3625 #undef MDI_DIR 3626 #undef MDI_CLK 3627 3628 /* 3629 * wm_gmii_i82543_readreg: [mii interface function] 3630 * 3631 * Read a PHY register on the GMII (i82543 version). 3632 */ 3633 static int 3634 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3635 { 3636 struct wm_softc *sc = (void *) self; 3637 int rv; 3638 3639 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3640 i82543_mii_sendbits(sc, reg | (phy << 5) | 3641 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3642 rv = i82543_mii_recvbits(sc) & 0xffff; 3643 3644 DPRINTF(WM_DEBUG_GMII, 3645 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3646 sc->sc_dev.dv_xname, phy, reg, rv)); 3647 3648 return (rv); 3649 } 3650 3651 /* 3652 * wm_gmii_i82543_writereg: [mii interface function] 3653 * 3654 * Write a PHY register on the GMII (i82543 version). 3655 */ 3656 static void 3657 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3658 { 3659 struct wm_softc *sc = (void *) self; 3660 3661 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3662 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3663 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3664 (MII_COMMAND_START << 30), 32); 3665 } 3666 3667 /* 3668 * wm_gmii_i82544_readreg: [mii interface function] 3669 * 3670 * Read a PHY register on the GMII. 3671 */ 3672 static int 3673 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3674 { 3675 struct wm_softc *sc = (void *) self; 3676 uint32_t mdic = 0; 3677 int i, rv; 3678 3679 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3680 MDIC_REGADD(reg)); 3681 3682 for (i = 0; i < 100; i++) { 3683 mdic = CSR_READ(sc, WMREG_MDIC); 3684 if (mdic & MDIC_READY) 3685 break; 3686 delay(10); 3687 } 3688 3689 if ((mdic & MDIC_READY) == 0) { 3690 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3691 sc->sc_dev.dv_xname, phy, reg); 3692 rv = 0; 3693 } else if (mdic & MDIC_E) { 3694 #if 0 /* This is normal if no PHY is present. */ 3695 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3696 sc->sc_dev.dv_xname, phy, reg); 3697 #endif 3698 rv = 0; 3699 } else { 3700 rv = MDIC_DATA(mdic); 3701 if (rv == 0xffff) 3702 rv = 0; 3703 } 3704 3705 return (rv); 3706 } 3707 3708 /* 3709 * wm_gmii_i82544_writereg: [mii interface function] 3710 * 3711 * Write a PHY register on the GMII. 3712 */ 3713 static void 3714 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3715 { 3716 struct wm_softc *sc = (void *) self; 3717 uint32_t mdic = 0; 3718 int i; 3719 3720 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3721 MDIC_REGADD(reg) | MDIC_DATA(val)); 3722 3723 for (i = 0; i < 100; i++) { 3724 mdic = CSR_READ(sc, WMREG_MDIC); 3725 if (mdic & MDIC_READY) 3726 break; 3727 delay(10); 3728 } 3729 3730 if ((mdic & MDIC_READY) == 0) 3731 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3732 sc->sc_dev.dv_xname, phy, reg); 3733 else if (mdic & MDIC_E) 3734 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3735 sc->sc_dev.dv_xname, phy, reg); 3736 } 3737 3738 /* 3739 * wm_gmii_statchg: [mii interface function] 3740 * 3741 * Callback from MII layer when media changes. 3742 */ 3743 static void 3744 wm_gmii_statchg(struct device *self) 3745 { 3746 struct wm_softc *sc = (void *) self; 3747 struct mii_data *mii = &sc->sc_mii; 3748 3749 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3750 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3751 sc->sc_fcrtl &= ~FCRTL_XONE; 3752 3753 /* 3754 * Get flow control negotiation result. 3755 */ 3756 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3757 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3758 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3759 mii->mii_media_active &= ~IFM_ETH_FMASK; 3760 } 3761 3762 if (sc->sc_flowflags & IFM_FLOW) { 3763 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3764 sc->sc_ctrl |= CTRL_TFCE; 3765 sc->sc_fcrtl |= FCRTL_XONE; 3766 } 3767 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3768 sc->sc_ctrl |= CTRL_RFCE; 3769 } 3770 3771 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3772 DPRINTF(WM_DEBUG_LINK, 3773 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3774 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3775 } else { 3776 DPRINTF(WM_DEBUG_LINK, 3777 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3778 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3779 } 3780 3781 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3782 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3783 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3784 : WMREG_FCRTL, sc->sc_fcrtl); 3785 } 3786
Indexes created Tue Sep 23 07:09:52 GMT 2025