if_wm.c revision 1.92
1 /* $NetBSD: if_wm.c,v 1.92 2005/02/18 04:32:35 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.92 2005/02/18 04:32:35 briggs Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA ETHER_MAX_LEN_JUMBO 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make serveral things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 280 /* m_pullup() needed for Tx offload */ 281 struct evcnt sc_ev_txpullup_needed; 282 /* ...failed due to no memory */ 283 struct evcnt sc_ev_txpullup_nomem; 284 /* ...failed due to lack of space in first mbuf */ 285 struct evcnt sc_ev_txpullup_fail; 286 287 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 288 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 289 290 struct evcnt sc_ev_tu; /* Tx underrun */ 291 292 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 293 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 294 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 295 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 296 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 297 #endif /* WM_EVENT_COUNTERS */ 298 299 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 300 301 int sc_txfree; /* number of free Tx descriptors */ 302 int sc_txnext; /* next ready Tx descriptor */ 303 304 int sc_txsfree; /* number of free Tx jobs */ 305 int sc_txsnext; /* next free Tx job */ 306 int sc_txsdirty; /* dirty Tx jobs */ 307 308 /* These 5 variables are used only on the 82547. */ 309 int sc_txfifo_size; /* Tx FIFO size */ 310 int sc_txfifo_head; /* current head of FIFO */ 311 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 312 int sc_txfifo_stall; /* Tx FIFO is stalled */ 313 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 314 315 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 316 317 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 318 int sc_rxdiscard; 319 int sc_rxlen; 320 struct mbuf *sc_rxhead; 321 struct mbuf *sc_rxtail; 322 struct mbuf **sc_rxtailp; 323 324 uint32_t sc_ctrl; /* prototype CTRL register */ 325 #if 0 326 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 327 #endif 328 uint32_t sc_icr; /* prototype interrupt bits */ 329 uint32_t sc_itr; /* prototype intr throttling reg */ 330 uint32_t sc_tctl; /* prototype TCTL register */ 331 uint32_t sc_rctl; /* prototype RCTL register */ 332 uint32_t sc_txcw; /* prototype TXCW register */ 333 uint32_t sc_tipg; /* prototype TIPG register */ 334 uint32_t sc_fcrtl; /* prototype FCRTL register */ 335 uint32_t sc_pba; /* prototype PBA register */ 336 337 int sc_tbi_linkup; /* TBI link status */ 338 int sc_tbi_anstate; /* autonegotiation state */ 339 340 int sc_mchash_type; /* multicast filter offset */ 341 342 #if NRND > 0 343 rndsource_element_t rnd_source; /* random source */ 344 #endif 345 }; 346 347 #define WM_RXCHAIN_RESET(sc) \ 348 do { \ 349 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 350 *(sc)->sc_rxtailp = NULL; \ 351 (sc)->sc_rxlen = 0; \ 352 } while (/*CONSTCOND*/0) 353 354 #define WM_RXCHAIN_LINK(sc, m) \ 355 do { \ 356 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 357 (sc)->sc_rxtailp = &(m)->m_next; \ 358 } while (/*CONSTCOND*/0) 359 360 /* sc_flags */ 361 #define WM_F_HAS_MII 0x01 /* has MII */ 362 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 363 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 364 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 365 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 366 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 367 #define WM_F_CSA 0x80 /* bus is CSA */ 368 369 #ifdef WM_EVENT_COUNTERS 370 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 371 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 372 #else 373 #define WM_EVCNT_INCR(ev) /* nothing */ 374 #define WM_EVCNT_ADD(ev, val) /* nothing */ 375 #endif 376 377 #define CSR_READ(sc, reg) \ 378 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 379 #define CSR_WRITE(sc, reg, val) \ 380 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 381 #define CSR_WRITE_FLUSH(sc) \ 382 (void) CSR_READ((sc), WMREG_STATUS) 383 384 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 385 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 386 387 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 388 #define WM_CDTXADDR_HI(sc, x) \ 389 (sizeof(bus_addr_t) == 8 ? \ 390 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 391 392 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 393 #define WM_CDRXADDR_HI(sc, x) \ 394 (sizeof(bus_addr_t) == 8 ? \ 395 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 396 397 #define WM_CDTXSYNC(sc, x, n, ops) \ 398 do { \ 399 int __x, __n; \ 400 \ 401 __x = (x); \ 402 __n = (n); \ 403 \ 404 /* If it will wrap around, sync to the end of the ring. */ \ 405 if ((__x + __n) > WM_NTXDESC(sc)) { \ 406 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 407 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 408 (WM_NTXDESC(sc) - __x), (ops)); \ 409 __n -= (WM_NTXDESC(sc) - __x); \ 410 __x = 0; \ 411 } \ 412 \ 413 /* Now sync whatever is left. */ \ 414 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 415 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 416 } while (/*CONSTCOND*/0) 417 418 #define WM_CDRXSYNC(sc, x, ops) \ 419 do { \ 420 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 421 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 422 } while (/*CONSTCOND*/0) 423 424 #define WM_INIT_RXDESC(sc, x) \ 425 do { \ 426 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 427 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 428 struct mbuf *__m = __rxs->rxs_mbuf; \ 429 \ 430 /* \ 431 * Note: We scoot the packet forward 2 bytes in the buffer \ 432 * so that the payload after the Ethernet header is aligned \ 433 * to a 4-byte boundary. \ 434 * \ 435 * XXX BRAINDAMAGE ALERT! \ 436 * The stupid chip uses the same size for every buffer, which \ 437 * is set in the Receive Control register. We are using the 2K \ 438 * size option, but what we REALLY want is (2K - 2)! For this \ 439 * reason, we can't "scoot" packets longer than the standard \ 440 * Ethernet MTU. On strict-alignment platforms, if the total \ 441 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 442 * the upper layer copy the headers. \ 443 */ \ 444 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 445 \ 446 wm_set_dma_addr(&__rxd->wrx_addr, \ 447 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 448 __rxd->wrx_len = 0; \ 449 __rxd->wrx_cksum = 0; \ 450 __rxd->wrx_status = 0; \ 451 __rxd->wrx_errors = 0; \ 452 __rxd->wrx_special = 0; \ 453 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 454 \ 455 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 456 } while (/*CONSTCOND*/0) 457 458 static void wm_start(struct ifnet *); 459 static void wm_watchdog(struct ifnet *); 460 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 461 static int wm_init(struct ifnet *); 462 static void wm_stop(struct ifnet *, int); 463 464 static void wm_shutdown(void *); 465 466 static void wm_reset(struct wm_softc *); 467 static void wm_rxdrain(struct wm_softc *); 468 static int wm_add_rxbuf(struct wm_softc *, int); 469 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 470 static void wm_tick(void *); 471 472 static void wm_set_filter(struct wm_softc *); 473 474 static int wm_intr(void *); 475 static void wm_txintr(struct wm_softc *); 476 static void wm_rxintr(struct wm_softc *); 477 static void wm_linkintr(struct wm_softc *, uint32_t); 478 479 static void wm_tbi_mediainit(struct wm_softc *); 480 static int wm_tbi_mediachange(struct ifnet *); 481 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 482 483 static void wm_tbi_set_linkled(struct wm_softc *); 484 static void wm_tbi_check_link(struct wm_softc *); 485 486 static void wm_gmii_reset(struct wm_softc *); 487 488 static int wm_gmii_i82543_readreg(struct device *, int, int); 489 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 490 491 static int wm_gmii_i82544_readreg(struct device *, int, int); 492 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 493 494 static void wm_gmii_statchg(struct device *); 495 496 static void wm_gmii_mediainit(struct wm_softc *); 497 static int wm_gmii_mediachange(struct ifnet *); 498 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 499 500 static int wm_match(struct device *, struct cfdata *, void *); 501 static void wm_attach(struct device *, struct device *, void *); 502 503 CFATTACH_DECL(wm, sizeof(struct wm_softc), 504 wm_match, wm_attach, NULL, NULL); 505 506 static void wm_82547_txfifo_stall(void *); 507 508 /* 509 * Devices supported by this driver. 510 */ 511 static const struct wm_product { 512 pci_vendor_id_t wmp_vendor; 513 pci_product_id_t wmp_product; 514 const char *wmp_name; 515 wm_chip_type wmp_type; 516 int wmp_flags; 517 #define WMP_F_1000X 0x01 518 #define WMP_F_1000T 0x02 519 } wm_products[] = { 520 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 521 "Intel i82542 1000BASE-X Ethernet", 522 WM_T_82542_2_1, WMP_F_1000X }, 523 524 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 525 "Intel i82543GC 1000BASE-X Ethernet", 526 WM_T_82543, WMP_F_1000X }, 527 528 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 529 "Intel i82543GC 1000BASE-T Ethernet", 530 WM_T_82543, WMP_F_1000T }, 531 532 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 533 "Intel i82544EI 1000BASE-T Ethernet", 534 WM_T_82544, WMP_F_1000T }, 535 536 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 537 "Intel i82544EI 1000BASE-X Ethernet", 538 WM_T_82544, WMP_F_1000X }, 539 540 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 541 "Intel i82544GC 1000BASE-T Ethernet", 542 WM_T_82544, WMP_F_1000T }, 543 544 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 545 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 546 WM_T_82544, WMP_F_1000T }, 547 548 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 549 "Intel i82540EM 1000BASE-T Ethernet", 550 WM_T_82540, WMP_F_1000T }, 551 552 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 553 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 554 WM_T_82540, WMP_F_1000T }, 555 556 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 557 "Intel i82540EP 1000BASE-T Ethernet", 558 WM_T_82540, WMP_F_1000T }, 559 560 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 561 "Intel i82540EP 1000BASE-T Ethernet", 562 WM_T_82540, WMP_F_1000T }, 563 564 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 565 "Intel i82540EP 1000BASE-T Ethernet", 566 WM_T_82540, WMP_F_1000T }, 567 568 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 569 "Intel i82545EM 1000BASE-T Ethernet", 570 WM_T_82545, WMP_F_1000T }, 571 572 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 573 "Intel i82545GM 1000BASE-T Ethernet", 574 WM_T_82545_3, WMP_F_1000T }, 575 576 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 577 "Intel i82545GM 1000BASE-X Ethernet", 578 WM_T_82545_3, WMP_F_1000X }, 579 #if 0 580 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 581 "Intel i82545GM Gigabit Ethernet (SERDES)", 582 WM_T_82545_3, WMP_F_SERDES }, 583 #endif 584 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 585 "Intel i82546EB 1000BASE-T Ethernet", 586 WM_T_82546, WMP_F_1000T }, 587 588 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 589 "Intel i82546EB 1000BASE-T Ethernet", 590 WM_T_82546, WMP_F_1000T }, 591 592 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 593 "Intel i82545EM 1000BASE-X Ethernet", 594 WM_T_82545, WMP_F_1000X }, 595 596 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 597 "Intel i82546EB 1000BASE-X Ethernet", 598 WM_T_82546, WMP_F_1000X }, 599 600 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 601 "Intel i82546GB 1000BASE-T Ethernet", 602 WM_T_82546_3, WMP_F_1000T }, 603 604 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 605 "Intel i82546GB 1000BASE-X Ethernet", 606 WM_T_82546_3, WMP_F_1000X }, 607 #if 0 608 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 609 "Intel i82546GB Gigabit Ethernet (SERDES)", 610 WM_T_82546_3, WMP_F_SERDES }, 611 #endif 612 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 613 "Intel i82541EI 1000BASE-T Ethernet", 614 WM_T_82541, WMP_F_1000T }, 615 616 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 617 "Intel i82541EI Mobile 1000BASE-T Ethernet", 618 WM_T_82541, WMP_F_1000T }, 619 620 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 621 "Intel i82541ER 1000BASE-T Ethernet", 622 WM_T_82541_2, WMP_F_1000T }, 623 624 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 625 "Intel i82541GI 1000BASE-T Ethernet", 626 WM_T_82541_2, WMP_F_1000T }, 627 628 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 629 "Intel i82541GI Mobile 1000BASE-T Ethernet", 630 WM_T_82541_2, WMP_F_1000T }, 631 632 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 633 "Intel i82547EI 1000BASE-T Ethernet", 634 WM_T_82547, WMP_F_1000T }, 635 636 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 637 "Intel i82547GI 1000BASE-T Ethernet", 638 WM_T_82547_2, WMP_F_1000T }, 639 { 0, 0, 640 NULL, 641 0, 0 }, 642 }; 643 644 #ifdef WM_EVENT_COUNTERS 645 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 646 #endif /* WM_EVENT_COUNTERS */ 647 648 #if 0 /* Not currently used */ 649 static __inline uint32_t 650 wm_io_read(struct wm_softc *sc, int reg) 651 { 652 653 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 654 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 655 } 656 #endif 657 658 static __inline void 659 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 660 { 661 662 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 663 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 664 } 665 666 static __inline void 667 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 668 { 669 wa->wa_low = htole32(v & 0xffffffffU); 670 if (sizeof(bus_addr_t) == 8) 671 wa->wa_high = htole32((uint64_t) v >> 32); 672 else 673 wa->wa_high = 0; 674 } 675 676 static const struct wm_product * 677 wm_lookup(const struct pci_attach_args *pa) 678 { 679 const struct wm_product *wmp; 680 681 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 682 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 683 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 684 return (wmp); 685 } 686 return (NULL); 687 } 688 689 static int 690 wm_match(struct device *parent, struct cfdata *cf, void *aux) 691 { 692 struct pci_attach_args *pa = aux; 693 694 if (wm_lookup(pa) != NULL) 695 return (1); 696 697 return (0); 698 } 699 700 static void 701 wm_attach(struct device *parent, struct device *self, void *aux) 702 { 703 struct wm_softc *sc = (void *) self; 704 struct pci_attach_args *pa = aux; 705 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 706 pci_chipset_tag_t pc = pa->pa_pc; 707 pci_intr_handle_t ih; 708 size_t cdata_size; 709 const char *intrstr = NULL; 710 const char *eetype; 711 bus_space_tag_t memt; 712 bus_space_handle_t memh; 713 bus_dma_segment_t seg; 714 int memh_valid; 715 int i, rseg, error; 716 const struct wm_product *wmp; 717 uint8_t enaddr[ETHER_ADDR_LEN]; 718 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 719 pcireg_t preg, memtype; 720 uint32_t reg; 721 int pmreg; 722 723 callout_init(&sc->sc_tick_ch); 724 725 wmp = wm_lookup(pa); 726 if (wmp == NULL) { 727 printf("\n"); 728 panic("wm_attach: impossible"); 729 } 730 731 if (pci_dma64_available(pa)) 732 sc->sc_dmat = pa->pa_dmat64; 733 else 734 sc->sc_dmat = pa->pa_dmat; 735 736 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 737 aprint_naive(": Ethernet controller\n"); 738 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 739 740 sc->sc_type = wmp->wmp_type; 741 if (sc->sc_type < WM_T_82543) { 742 if (preg < 2) { 743 aprint_error("%s: i82542 must be at least rev. 2\n", 744 sc->sc_dev.dv_xname); 745 return; 746 } 747 if (preg < 3) 748 sc->sc_type = WM_T_82542_2_0; 749 } 750 751 /* 752 * Map the device. All devices support memory-mapped acccess, 753 * and it is really required for normal operation. 754 */ 755 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 756 switch (memtype) { 757 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 758 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 759 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 760 memtype, 0, &memt, &memh, NULL, NULL) == 0); 761 break; 762 default: 763 memh_valid = 0; 764 } 765 766 if (memh_valid) { 767 sc->sc_st = memt; 768 sc->sc_sh = memh; 769 } else { 770 aprint_error("%s: unable to map device registers\n", 771 sc->sc_dev.dv_xname); 772 return; 773 } 774 775 /* 776 * In addition, i82544 and later support I/O mapped indirect 777 * register access. It is not desirable (nor supported in 778 * this driver) to use it for normal operation, though it is 779 * required to work around bugs in some chip versions. 780 */ 781 if (sc->sc_type >= WM_T_82544) { 782 /* First we have to find the I/O BAR. */ 783 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 784 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 785 PCI_MAPREG_TYPE_IO) 786 break; 787 } 788 if (i == PCI_MAPREG_END) 789 aprint_error("%s: WARNING: unable to find I/O BAR\n", 790 sc->sc_dev.dv_xname); 791 else { 792 /* 793 * The i8254x doesn't apparently respond when the 794 * I/O BAR is 0, which looks somewhat like it's not 795 * been configured. 796 */ 797 preg = pci_conf_read(pc, pa->pa_tag, i); 798 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 799 aprint_error("%s: WARNING: I/O BAR at zero.", 800 sc->sc_dev.dv_xname); 801 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 802 0, &sc->sc_iot, &sc->sc_ioh, 803 NULL, NULL) == 0) { 804 sc->sc_flags |= WM_F_IOH_VALID; 805 } else { 806 aprint_error("%s: WARNING: unable to map " 807 "I/O space\n", sc->sc_dev.dv_xname); 808 } 809 } 810 811 } 812 813 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 814 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 815 preg |= PCI_COMMAND_MASTER_ENABLE; 816 if (sc->sc_type < WM_T_82542_2_1) 817 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 818 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 819 820 /* Get it out of power save mode, if needed. */ 821 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 822 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 823 PCI_PMCSR_STATE_MASK; 824 if (preg == PCI_PMCSR_STATE_D3) { 825 /* 826 * The card has lost all configuration data in 827 * this state, so punt. 828 */ 829 aprint_error("%s: unable to wake from power state D3\n", 830 sc->sc_dev.dv_xname); 831 return; 832 } 833 if (preg != PCI_PMCSR_STATE_D0) { 834 aprint_normal("%s: waking up from power state D%d\n", 835 sc->sc_dev.dv_xname, preg); 836 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 837 PCI_PMCSR_STATE_D0); 838 } 839 } 840 841 /* 842 * Map and establish our interrupt. 843 */ 844 if (pci_intr_map(pa, &ih)) { 845 aprint_error("%s: unable to map interrupt\n", 846 sc->sc_dev.dv_xname); 847 return; 848 } 849 intrstr = pci_intr_string(pc, ih); 850 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 851 if (sc->sc_ih == NULL) { 852 aprint_error("%s: unable to establish interrupt", 853 sc->sc_dev.dv_xname); 854 if (intrstr != NULL) 855 aprint_normal(" at %s", intrstr); 856 aprint_normal("\n"); 857 return; 858 } 859 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 860 861 /* 862 * Determine a few things about the bus we're connected to. 863 */ 864 if (sc->sc_type < WM_T_82543) { 865 /* We don't really know the bus characteristics here. */ 866 sc->sc_bus_speed = 33; 867 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 868 /* 869 * CSA (Communication Streaming Architecture) is about as fast 870 * a 32-bit 66MHz PCI Bus. 871 */ 872 sc->sc_flags |= WM_F_CSA; 873 sc->sc_bus_speed = 66; 874 aprint_verbose("%s: Communication Streaming Architecture\n", 875 sc->sc_dev.dv_xname); 876 if (sc->sc_type == WM_T_82547) { 877 callout_init(&sc->sc_txfifo_ch); 878 callout_setfunc(&sc->sc_txfifo_ch, 879 wm_82547_txfifo_stall, sc); 880 aprint_verbose("%s: using 82547 Tx FIFO stall " 881 "work-around\n", sc->sc_dev.dv_xname); 882 } 883 } else { 884 reg = CSR_READ(sc, WMREG_STATUS); 885 if (reg & STATUS_BUS64) 886 sc->sc_flags |= WM_F_BUS64; 887 if (sc->sc_type >= WM_T_82544 && 888 (reg & STATUS_PCIX_MODE) != 0) { 889 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 890 891 sc->sc_flags |= WM_F_PCIX; 892 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 893 PCI_CAP_PCIX, 894 &sc->sc_pcix_offset, NULL) == 0) 895 aprint_error("%s: unable to find PCIX " 896 "capability\n", sc->sc_dev.dv_xname); 897 else if (sc->sc_type != WM_T_82545_3 && 898 sc->sc_type != WM_T_82546_3) { 899 /* 900 * Work around a problem caused by the BIOS 901 * setting the max memory read byte count 902 * incorrectly. 903 */ 904 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 905 sc->sc_pcix_offset + PCI_PCIX_CMD); 906 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 907 sc->sc_pcix_offset + PCI_PCIX_STATUS); 908 909 bytecnt = 910 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 911 PCI_PCIX_CMD_BYTECNT_SHIFT; 912 maxb = 913 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 914 PCI_PCIX_STATUS_MAXB_SHIFT; 915 if (bytecnt > maxb) { 916 aprint_verbose("%s: resetting PCI-X " 917 "MMRBC: %d -> %d\n", 918 sc->sc_dev.dv_xname, 919 512 << bytecnt, 512 << maxb); 920 pcix_cmd = (pcix_cmd & 921 ~PCI_PCIX_CMD_BYTECNT_MASK) | 922 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 923 pci_conf_write(pa->pa_pc, pa->pa_tag, 924 sc->sc_pcix_offset + PCI_PCIX_CMD, 925 pcix_cmd); 926 } 927 } 928 } 929 /* 930 * The quad port adapter is special; it has a PCIX-PCIX 931 * bridge on the board, and can run the secondary bus at 932 * a higher speed. 933 */ 934 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 935 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 936 : 66; 937 } else if (sc->sc_flags & WM_F_PCIX) { 938 switch (reg & STATUS_PCIXSPD_MASK) { 939 case STATUS_PCIXSPD_50_66: 940 sc->sc_bus_speed = 66; 941 break; 942 case STATUS_PCIXSPD_66_100: 943 sc->sc_bus_speed = 100; 944 break; 945 case STATUS_PCIXSPD_100_133: 946 sc->sc_bus_speed = 133; 947 break; 948 default: 949 aprint_error( 950 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 951 sc->sc_dev.dv_xname, 952 reg & STATUS_PCIXSPD_MASK); 953 sc->sc_bus_speed = 66; 954 } 955 } else 956 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 957 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 958 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 959 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 960 } 961 962 /* 963 * Allocate the control data structures, and create and load the 964 * DMA map for it. 965 * 966 * NOTE: All Tx descriptors must be in the same 4G segment of 967 * memory. So must Rx descriptors. We simplify by allocating 968 * both sets within the same 4G segment. 969 */ 970 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 971 WM_NTXDESC_82542 : WM_NTXDESC_82544; 972 cdata_size = sc->sc_type < WM_T_82544 ? 973 sizeof(struct wm_control_data_82542) : 974 sizeof(struct wm_control_data_82544); 975 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 976 (bus_size_t) 0x100000000ULL, 977 &seg, 1, &rseg, 0)) != 0) { 978 aprint_error( 979 "%s: unable to allocate control data, error = %d\n", 980 sc->sc_dev.dv_xname, error); 981 goto fail_0; 982 } 983 984 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 985 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 986 aprint_error("%s: unable to map control data, error = %d\n", 987 sc->sc_dev.dv_xname, error); 988 goto fail_1; 989 } 990 991 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 992 0, 0, &sc->sc_cddmamap)) != 0) { 993 aprint_error("%s: unable to create control data DMA map, " 994 "error = %d\n", sc->sc_dev.dv_xname, error); 995 goto fail_2; 996 } 997 998 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 999 sc->sc_control_data, cdata_size, NULL, 1000 0)) != 0) { 1001 aprint_error( 1002 "%s: unable to load control data DMA map, error = %d\n", 1003 sc->sc_dev.dv_xname, error); 1004 goto fail_3; 1005 } 1006 1007 1008 /* 1009 * Create the transmit buffer DMA maps. 1010 */ 1011 WM_TXQUEUELEN(sc) = 1012 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1013 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1014 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1015 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1016 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1017 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1018 aprint_error("%s: unable to create Tx DMA map %d, " 1019 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1020 goto fail_4; 1021 } 1022 } 1023 1024 /* 1025 * Create the receive buffer DMA maps. 1026 */ 1027 for (i = 0; i < WM_NRXDESC; i++) { 1028 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1029 MCLBYTES, 0, 0, 1030 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1031 aprint_error("%s: unable to create Rx DMA map %d, " 1032 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1033 goto fail_5; 1034 } 1035 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1036 } 1037 1038 /* 1039 * Reset the chip to a known state. 1040 */ 1041 wm_reset(sc); 1042 1043 /* 1044 * Get some information about the EEPROM. 1045 */ 1046 if (sc->sc_type >= WM_T_82540) 1047 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1048 if (sc->sc_type <= WM_T_82544) 1049 sc->sc_ee_addrbits = 6; 1050 else if (sc->sc_type <= WM_T_82546_3) { 1051 reg = CSR_READ(sc, WMREG_EECD); 1052 if (reg & EECD_EE_SIZE) 1053 sc->sc_ee_addrbits = 8; 1054 else 1055 sc->sc_ee_addrbits = 6; 1056 } else if (sc->sc_type <= WM_T_82547_2) { 1057 reg = CSR_READ(sc, WMREG_EECD); 1058 if (reg & EECD_EE_TYPE) { 1059 sc->sc_flags |= WM_F_EEPROM_SPI; 1060 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1061 } else 1062 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1063 } else { 1064 /* Assume everything else is SPI. */ 1065 reg = CSR_READ(sc, WMREG_EECD); 1066 sc->sc_flags |= WM_F_EEPROM_SPI; 1067 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1068 } 1069 if (sc->sc_flags & WM_F_EEPROM_SPI) 1070 eetype = "SPI"; 1071 else 1072 eetype = "MicroWire"; 1073 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1074 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1075 sc->sc_ee_addrbits, eetype); 1076 1077 /* 1078 * Read the Ethernet address from the EEPROM. 1079 */ 1080 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1081 sizeof(myea) / sizeof(myea[0]), myea)) { 1082 aprint_error("%s: unable to read Ethernet address\n", 1083 sc->sc_dev.dv_xname); 1084 return; 1085 } 1086 enaddr[0] = myea[0] & 0xff; 1087 enaddr[1] = myea[0] >> 8; 1088 enaddr[2] = myea[1] & 0xff; 1089 enaddr[3] = myea[1] >> 8; 1090 enaddr[4] = myea[2] & 0xff; 1091 enaddr[5] = myea[2] >> 8; 1092 1093 /* 1094 * Toggle the LSB of the MAC address on the second port 1095 * of the i82546. 1096 */ 1097 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1098 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1099 enaddr[5] ^= 1; 1100 } 1101 1102 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1103 ether_sprintf(enaddr)); 1104 1105 /* 1106 * Read the config info from the EEPROM, and set up various 1107 * bits in the control registers based on their contents. 1108 */ 1109 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1110 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1111 sc->sc_dev.dv_xname); 1112 return; 1113 } 1114 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1115 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1116 sc->sc_dev.dv_xname); 1117 return; 1118 } 1119 if (sc->sc_type >= WM_T_82544) { 1120 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1121 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1122 sc->sc_dev.dv_xname); 1123 return; 1124 } 1125 } 1126 1127 if (cfg1 & EEPROM_CFG1_ILOS) 1128 sc->sc_ctrl |= CTRL_ILOS; 1129 if (sc->sc_type >= WM_T_82544) { 1130 sc->sc_ctrl |= 1131 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1132 CTRL_SWDPIO_SHIFT; 1133 sc->sc_ctrl |= 1134 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1135 CTRL_SWDPINS_SHIFT; 1136 } else { 1137 sc->sc_ctrl |= 1138 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1139 CTRL_SWDPIO_SHIFT; 1140 } 1141 1142 #if 0 1143 if (sc->sc_type >= WM_T_82544) { 1144 if (cfg1 & EEPROM_CFG1_IPS0) 1145 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1146 if (cfg1 & EEPROM_CFG1_IPS1) 1147 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1148 sc->sc_ctrl_ext |= 1149 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1150 CTRL_EXT_SWDPIO_SHIFT; 1151 sc->sc_ctrl_ext |= 1152 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1153 CTRL_EXT_SWDPINS_SHIFT; 1154 } else { 1155 sc->sc_ctrl_ext |= 1156 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1157 CTRL_EXT_SWDPIO_SHIFT; 1158 } 1159 #endif 1160 1161 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1162 #if 0 1163 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1164 #endif 1165 1166 /* 1167 * Set up some register offsets that are different between 1168 * the i82542 and the i82543 and later chips. 1169 */ 1170 if (sc->sc_type < WM_T_82543) { 1171 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1172 sc->sc_tdt_reg = WMREG_OLD_TDT; 1173 } else { 1174 sc->sc_rdt_reg = WMREG_RDT; 1175 sc->sc_tdt_reg = WMREG_TDT; 1176 } 1177 1178 /* 1179 * Determine if we're TBI or GMII mode, and initialize the 1180 * media structures accordingly. 1181 */ 1182 if (sc->sc_type < WM_T_82543 || 1183 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1184 if (wmp->wmp_flags & WMP_F_1000T) 1185 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1186 "product!\n", sc->sc_dev.dv_xname); 1187 wm_tbi_mediainit(sc); 1188 } else { 1189 if (wmp->wmp_flags & WMP_F_1000X) 1190 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1191 "product!\n", sc->sc_dev.dv_xname); 1192 wm_gmii_mediainit(sc); 1193 } 1194 1195 ifp = &sc->sc_ethercom.ec_if; 1196 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1197 ifp->if_softc = sc; 1198 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1199 ifp->if_ioctl = wm_ioctl; 1200 ifp->if_start = wm_start; 1201 ifp->if_watchdog = wm_watchdog; 1202 ifp->if_init = wm_init; 1203 ifp->if_stop = wm_stop; 1204 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1205 IFQ_SET_READY(&ifp->if_snd); 1206 1207 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1208 1209 /* 1210 * If we're a i82543 or greater, we can support VLANs. 1211 */ 1212 if (sc->sc_type >= WM_T_82543) 1213 sc->sc_ethercom.ec_capabilities |= 1214 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1215 1216 /* 1217 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1218 * on i82543 and later. 1219 */ 1220 if (sc->sc_type >= WM_T_82543) 1221 ifp->if_capabilities |= 1222 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1223 1224 /* 1225 * Attach the interface. 1226 */ 1227 if_attach(ifp); 1228 ether_ifattach(ifp, enaddr); 1229 #if NRND > 0 1230 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1231 RND_TYPE_NET, 0); 1232 #endif 1233 1234 #ifdef WM_EVENT_COUNTERS 1235 /* Attach event counters. */ 1236 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1237 NULL, sc->sc_dev.dv_xname, "txsstall"); 1238 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1239 NULL, sc->sc_dev.dv_xname, "txdstall"); 1240 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1241 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1242 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1243 NULL, sc->sc_dev.dv_xname, "txdw"); 1244 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1245 NULL, sc->sc_dev.dv_xname, "txqe"); 1246 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1247 NULL, sc->sc_dev.dv_xname, "rxintr"); 1248 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1249 NULL, sc->sc_dev.dv_xname, "linkintr"); 1250 1251 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1252 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1253 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1254 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1255 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1256 NULL, sc->sc_dev.dv_xname, "txipsum"); 1257 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1258 NULL, sc->sc_dev.dv_xname, "txtusum"); 1259 1260 evcnt_attach_dynamic(&sc->sc_ev_txpullup_needed, EVCNT_TYPE_MISC, 1261 NULL, sc->sc_dev.dv_xname, "txpullup needed"); 1262 evcnt_attach_dynamic(&sc->sc_ev_txpullup_nomem, EVCNT_TYPE_MISC, 1263 NULL, sc->sc_dev.dv_xname, "txpullup nomem"); 1264 evcnt_attach_dynamic(&sc->sc_ev_txpullup_fail, EVCNT_TYPE_MISC, 1265 NULL, sc->sc_dev.dv_xname, "txpullup fail"); 1266 1267 for (i = 0; i < WM_NTXSEGS; i++) { 1268 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1269 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1270 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1271 } 1272 1273 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1274 NULL, sc->sc_dev.dv_xname, "txdrop"); 1275 1276 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1277 NULL, sc->sc_dev.dv_xname, "tu"); 1278 1279 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1280 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1281 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1282 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1283 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1284 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1285 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1286 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1287 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1288 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1289 #endif /* WM_EVENT_COUNTERS */ 1290 1291 /* 1292 * Make sure the interface is shutdown during reboot. 1293 */ 1294 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1295 if (sc->sc_sdhook == NULL) 1296 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1297 sc->sc_dev.dv_xname); 1298 return; 1299 1300 /* 1301 * Free any resources we've allocated during the failed attach 1302 * attempt. Do this in reverse order and fall through. 1303 */ 1304 fail_5: 1305 for (i = 0; i < WM_NRXDESC; i++) { 1306 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1307 bus_dmamap_destroy(sc->sc_dmat, 1308 sc->sc_rxsoft[i].rxs_dmamap); 1309 } 1310 fail_4: 1311 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1312 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1313 bus_dmamap_destroy(sc->sc_dmat, 1314 sc->sc_txsoft[i].txs_dmamap); 1315 } 1316 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1317 fail_3: 1318 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1319 fail_2: 1320 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1321 cdata_size); 1322 fail_1: 1323 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1324 fail_0: 1325 return; 1326 } 1327 1328 /* 1329 * wm_shutdown: 1330 * 1331 * Make sure the interface is stopped at reboot time. 1332 */ 1333 static void 1334 wm_shutdown(void *arg) 1335 { 1336 struct wm_softc *sc = arg; 1337 1338 wm_stop(&sc->sc_ethercom.ec_if, 1); 1339 } 1340 1341 /* 1342 * wm_tx_offload: 1343 * 1344 * Set up TCP/IP checksumming parameters for the 1345 * specified packet. 1346 */ 1347 static int 1348 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1349 uint8_t *fieldsp) 1350 { 1351 struct mbuf *m0 = txs->txs_mbuf; 1352 struct livengood_tcpip_ctxdesc *t; 1353 uint32_t ipcs, tucs; 1354 struct ip *ip; 1355 struct ether_header *eh; 1356 int offset, iphl; 1357 uint8_t fields = 0; 1358 1359 /* 1360 * XXX It would be nice if the mbuf pkthdr had offset 1361 * fields for the protocol headers. 1362 */ 1363 1364 eh = mtod(m0, struct ether_header *); 1365 switch (htons(eh->ether_type)) { 1366 case ETHERTYPE_IP: 1367 iphl = sizeof(struct ip); 1368 offset = ETHER_HDR_LEN; 1369 break; 1370 1371 case ETHERTYPE_VLAN: 1372 iphl = sizeof(struct ip); 1373 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1374 break; 1375 1376 default: 1377 /* 1378 * Don't support this protocol or encapsulation. 1379 */ 1380 *fieldsp = 0; 1381 *cmdp = 0; 1382 return (0); 1383 } 1384 1385 if (m0->m_len < (offset + iphl)) { 1386 /* 1387 * Packet headers aren't in the first mbuf. Let's hope 1388 * there is space at the end if it for them. 1389 */ 1390 WM_EVCNT_INCR(&sc->sc_ev_txpullup_needed); 1391 if ((txs->txs_mbuf = m_pullup(m0, offset + iphl)) == NULL) { 1392 WM_EVCNT_INCR(&sc->sc_ev_txpullup_nomem); 1393 log(LOG_ERR, 1394 "%s: wm_tx_offload: mbuf allocation failed, " 1395 "packet dropped\n", sc->sc_dev.dv_xname); 1396 return (ENOMEM); 1397 } else if (m0 != txs->txs_mbuf) { 1398 /* 1399 * The DMA map has already been loaded, so we 1400 * would have to unload and reload it. But then 1401 * if that were to fail, we are already committed 1402 * to transmitting the packet (can't put it back 1403 * on the queue), so we have to drop the packet. 1404 */ 1405 WM_EVCNT_INCR(&sc->sc_ev_txpullup_fail); 1406 log(LOG_ERR, "%s: wm_tx_offload: packet headers did " 1407 "not fit in first mbuf, packet dropped\n", 1408 sc->sc_dev.dv_xname); 1409 m_freem(txs->txs_mbuf); 1410 txs->txs_mbuf = NULL; 1411 return (EINVAL); 1412 } 1413 } 1414 1415 ip = (struct ip *) (mtod(m0, caddr_t) + offset); 1416 iphl = ip->ip_hl << 2; 1417 1418 /* 1419 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1420 * offload feature, if we load the context descriptor, we 1421 * MUST provide valid values for IPCSS and TUCSS fields. 1422 */ 1423 1424 ipcs = WTX_TCPIP_IPCSS(offset) | 1425 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1426 WTX_TCPIP_IPCSE(offset + iphl - 1); 1427 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1428 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1429 fields |= WTX_IXSM; 1430 } 1431 1432 offset += iphl; 1433 1434 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1435 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1436 fields |= WTX_TXSM; 1437 tucs = WTX_TCPIP_TUCSS(offset) | 1438 WTX_TCPIP_TUCSO(offset + m0->m_pkthdr.csum_data) | 1439 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1440 } else { 1441 /* Just initialize it to a valid TCP context. */ 1442 tucs = WTX_TCPIP_TUCSS(offset) | 1443 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1444 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1445 } 1446 1447 /* Fill in the context descriptor. */ 1448 t = (struct livengood_tcpip_ctxdesc *) 1449 &sc->sc_txdescs[sc->sc_txnext]; 1450 t->tcpip_ipcs = htole32(ipcs); 1451 t->tcpip_tucs = htole32(tucs); 1452 t->tcpip_cmdlen = htole32(WTX_CMD_DEXT | WTX_DTYP_C); 1453 t->tcpip_seg = 0; 1454 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1455 1456 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1457 txs->txs_ndesc++; 1458 1459 *cmdp = WTX_CMD_DEXT | WTX_DTYP_D; 1460 *fieldsp = fields; 1461 1462 return (0); 1463 } 1464 1465 static void 1466 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1467 { 1468 struct mbuf *m; 1469 int i; 1470 1471 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1472 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1473 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1474 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1475 m->m_data, m->m_len, m->m_flags); 1476 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1477 i, i == 1 ? "" : "s"); 1478 } 1479 1480 /* 1481 * wm_82547_txfifo_stall: 1482 * 1483 * Callout used to wait for the 82547 Tx FIFO to drain, 1484 * reset the FIFO pointers, and restart packet transmission. 1485 */ 1486 static void 1487 wm_82547_txfifo_stall(void *arg) 1488 { 1489 struct wm_softc *sc = arg; 1490 int s; 1491 1492 s = splnet(); 1493 1494 if (sc->sc_txfifo_stall) { 1495 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1496 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1497 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1498 /* 1499 * Packets have drained. Stop transmitter, reset 1500 * FIFO pointers, restart transmitter, and kick 1501 * the packet queue. 1502 */ 1503 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1504 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1505 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1506 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1507 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1508 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1509 CSR_WRITE(sc, WMREG_TCTL, tctl); 1510 CSR_WRITE_FLUSH(sc); 1511 1512 sc->sc_txfifo_head = 0; 1513 sc->sc_txfifo_stall = 0; 1514 wm_start(&sc->sc_ethercom.ec_if); 1515 } else { 1516 /* 1517 * Still waiting for packets to drain; try again in 1518 * another tick. 1519 */ 1520 callout_schedule(&sc->sc_txfifo_ch, 1); 1521 } 1522 } 1523 1524 splx(s); 1525 } 1526 1527 /* 1528 * wm_82547_txfifo_bugchk: 1529 * 1530 * Check for bug condition in the 82547 Tx FIFO. We need to 1531 * prevent enqueueing a packet that would wrap around the end 1532 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1533 * 1534 * We do this by checking the amount of space before the end 1535 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1536 * the Tx FIFO, wait for all remaining packets to drain, reset 1537 * the internal FIFO pointers to the beginning, and restart 1538 * transmission on the interface. 1539 */ 1540 #define WM_FIFO_HDR 0x10 1541 #define WM_82547_PAD_LEN 0x3e0 1542 static int 1543 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1544 { 1545 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1546 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1547 1548 /* Just return if already stalled. */ 1549 if (sc->sc_txfifo_stall) 1550 return (1); 1551 1552 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1553 /* Stall only occurs in half-duplex mode. */ 1554 goto send_packet; 1555 } 1556 1557 if (len >= WM_82547_PAD_LEN + space) { 1558 sc->sc_txfifo_stall = 1; 1559 callout_schedule(&sc->sc_txfifo_ch, 1); 1560 return (1); 1561 } 1562 1563 send_packet: 1564 sc->sc_txfifo_head += len; 1565 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1566 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1567 1568 return (0); 1569 } 1570 1571 /* 1572 * wm_start: [ifnet interface function] 1573 * 1574 * Start packet transmission on the interface. 1575 */ 1576 static void 1577 wm_start(struct ifnet *ifp) 1578 { 1579 struct wm_softc *sc = ifp->if_softc; 1580 struct mbuf *m0; 1581 #if 0 /* XXXJRT */ 1582 struct m_tag *mtag; 1583 #endif 1584 struct wm_txsoft *txs; 1585 bus_dmamap_t dmamap; 1586 int error, nexttx, lasttx = -1, ofree, seg, segs_needed; 1587 bus_addr_t curaddr; 1588 bus_size_t seglen, curlen; 1589 uint32_t cksumcmd; 1590 uint8_t cksumfields; 1591 1592 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1593 return; 1594 1595 /* 1596 * Remember the previous number of free descriptors. 1597 */ 1598 ofree = sc->sc_txfree; 1599 1600 /* 1601 * Loop through the send queue, setting up transmit descriptors 1602 * until we drain the queue, or use up all available transmit 1603 * descriptors. 1604 */ 1605 for (;;) { 1606 /* Grab a packet off the queue. */ 1607 IFQ_POLL(&ifp->if_snd, m0); 1608 if (m0 == NULL) 1609 break; 1610 1611 DPRINTF(WM_DEBUG_TX, 1612 ("%s: TX: have packet to transmit: %p\n", 1613 sc->sc_dev.dv_xname, m0)); 1614 1615 /* Get a work queue entry. */ 1616 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1617 wm_txintr(sc); 1618 if (sc->sc_txsfree == 0) { 1619 DPRINTF(WM_DEBUG_TX, 1620 ("%s: TX: no free job descriptors\n", 1621 sc->sc_dev.dv_xname)); 1622 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1623 break; 1624 } 1625 } 1626 1627 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1628 dmamap = txs->txs_dmamap; 1629 1630 /* 1631 * Load the DMA map. If this fails, the packet either 1632 * didn't fit in the allotted number of segments, or we 1633 * were short on resources. For the too-many-segments 1634 * case, we simply report an error and drop the packet, 1635 * since we can't sanely copy a jumbo packet to a single 1636 * buffer. 1637 */ 1638 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1639 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1640 if (error) { 1641 if (error == EFBIG) { 1642 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1643 log(LOG_ERR, "%s: Tx packet consumes too many " 1644 "DMA segments, dropping...\n", 1645 sc->sc_dev.dv_xname); 1646 IFQ_DEQUEUE(&ifp->if_snd, m0); 1647 wm_dump_mbuf_chain(sc, m0); 1648 m_freem(m0); 1649 continue; 1650 } 1651 /* 1652 * Short on resources, just stop for now. 1653 */ 1654 DPRINTF(WM_DEBUG_TX, 1655 ("%s: TX: dmamap load failed: %d\n", 1656 sc->sc_dev.dv_xname, error)); 1657 break; 1658 } 1659 1660 segs_needed = dmamap->dm_nsegs; 1661 1662 /* 1663 * Ensure we have enough descriptors free to describe 1664 * the packet. Note, we always reserve one descriptor 1665 * at the end of the ring due to the semantics of the 1666 * TDT register, plus one more in the event we need 1667 * to load offload context. 1668 */ 1669 if (segs_needed > sc->sc_txfree - 2) { 1670 /* 1671 * Not enough free descriptors to transmit this 1672 * packet. We haven't committed anything yet, 1673 * so just unload the DMA map, put the packet 1674 * pack on the queue, and punt. Notify the upper 1675 * layer that there are no more slots left. 1676 */ 1677 DPRINTF(WM_DEBUG_TX, 1678 ("%s: TX: need %d (%) descriptors, have %d\n", 1679 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1680 sc->sc_txfree - 1)); 1681 ifp->if_flags |= IFF_OACTIVE; 1682 bus_dmamap_unload(sc->sc_dmat, dmamap); 1683 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1684 break; 1685 } 1686 1687 /* 1688 * Check for 82547 Tx FIFO bug. We need to do this 1689 * once we know we can transmit the packet, since we 1690 * do some internal FIFO space accounting here. 1691 */ 1692 if (sc->sc_type == WM_T_82547 && 1693 wm_82547_txfifo_bugchk(sc, m0)) { 1694 DPRINTF(WM_DEBUG_TX, 1695 ("%s: TX: 82547 Tx FIFO bug detected\n", 1696 sc->sc_dev.dv_xname)); 1697 ifp->if_flags |= IFF_OACTIVE; 1698 bus_dmamap_unload(sc->sc_dmat, dmamap); 1699 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1700 break; 1701 } 1702 1703 IFQ_DEQUEUE(&ifp->if_snd, m0); 1704 1705 /* 1706 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1707 */ 1708 1709 DPRINTF(WM_DEBUG_TX, 1710 ("%s: TX: packet has %d (%d) DMA segments\n", 1711 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1712 1713 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1714 1715 /* 1716 * Store a pointer to the packet so that we can free it 1717 * later. 1718 * 1719 * Initially, we consider the number of descriptors the 1720 * packet uses the number of DMA segments. This may be 1721 * incremented by 1 if we do checksum offload (a descriptor 1722 * is used to set the checksum context). 1723 */ 1724 txs->txs_mbuf = m0; 1725 txs->txs_firstdesc = sc->sc_txnext; 1726 txs->txs_ndesc = segs_needed; 1727 1728 /* Set up offload parameters for this packet. */ 1729 if (m0->m_pkthdr.csum_flags & 1730 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1731 if (wm_tx_offload(sc, txs, &cksumcmd, 1732 &cksumfields) != 0) { 1733 /* Error message already displayed. */ 1734 bus_dmamap_unload(sc->sc_dmat, dmamap); 1735 continue; 1736 } 1737 } else { 1738 cksumcmd = 0; 1739 cksumfields = 0; 1740 } 1741 1742 cksumcmd |= WTX_CMD_IDE; 1743 1744 /* Sync the DMA map. */ 1745 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1746 BUS_DMASYNC_PREWRITE); 1747 1748 /* 1749 * Initialize the transmit descriptor. 1750 */ 1751 for (nexttx = sc->sc_txnext, seg = 0; 1752 seg < dmamap->dm_nsegs; seg++) { 1753 for (seglen = dmamap->dm_segs[seg].ds_len, 1754 curaddr = dmamap->dm_segs[seg].ds_addr; 1755 seglen != 0; 1756 curaddr += curlen, seglen -= curlen, 1757 nexttx = WM_NEXTTX(sc, nexttx)) { 1758 curlen = seglen; 1759 1760 wm_set_dma_addr( 1761 &sc->sc_txdescs[nexttx].wtx_addr, 1762 curaddr); 1763 sc->sc_txdescs[nexttx].wtx_cmdlen = 1764 htole32(cksumcmd | curlen); 1765 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1766 0; 1767 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1768 cksumfields; 1769 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1770 lasttx = nexttx; 1771 1772 DPRINTF(WM_DEBUG_TX, 1773 ("%s: TX: desc %d: low 0x%08x, " 1774 "len 0x%04x\n", 1775 sc->sc_dev.dv_xname, nexttx, 1776 curaddr & 0xffffffffU, curlen, curlen)); 1777 } 1778 } 1779 1780 KASSERT(lasttx != -1); 1781 1782 /* 1783 * Set up the command byte on the last descriptor of 1784 * the packet. If we're in the interrupt delay window, 1785 * delay the interrupt. 1786 */ 1787 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1788 htole32(WTX_CMD_EOP | WTX_CMD_IFCS | WTX_CMD_RS); 1789 1790 #if 0 /* XXXJRT */ 1791 /* 1792 * If VLANs are enabled and the packet has a VLAN tag, set 1793 * up the descriptor to encapsulate the packet for us. 1794 * 1795 * This is only valid on the last descriptor of the packet. 1796 */ 1797 if (sc->sc_ethercom.ec_nvlans != 0 && 1798 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1799 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1800 htole32(WTX_CMD_VLE); 1801 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1802 = htole16(*(u_int *)(mtag + 1) & 0xffff); 1803 } 1804 #endif /* XXXJRT */ 1805 1806 txs->txs_lastdesc = lasttx; 1807 1808 DPRINTF(WM_DEBUG_TX, 1809 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1810 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1811 1812 /* Sync the descriptors we're using. */ 1813 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1814 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1815 1816 /* Give the packet to the chip. */ 1817 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1818 1819 DPRINTF(WM_DEBUG_TX, 1820 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1821 1822 DPRINTF(WM_DEBUG_TX, 1823 ("%s: TX: finished transmitting packet, job %d\n", 1824 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1825 1826 /* Advance the tx pointer. */ 1827 sc->sc_txfree -= txs->txs_ndesc; 1828 sc->sc_txnext = nexttx; 1829 1830 sc->sc_txsfree--; 1831 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1832 1833 #if NBPFILTER > 0 1834 /* Pass the packet to any BPF listeners. */ 1835 if (ifp->if_bpf) 1836 bpf_mtap(ifp->if_bpf, m0); 1837 #endif /* NBPFILTER > 0 */ 1838 } 1839 1840 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1841 /* No more slots; notify upper layer. */ 1842 ifp->if_flags |= IFF_OACTIVE; 1843 } 1844 1845 if (sc->sc_txfree != ofree) { 1846 /* Set a watchdog timer in case the chip flakes out. */ 1847 ifp->if_timer = 5; 1848 } 1849 } 1850 1851 /* 1852 * wm_watchdog: [ifnet interface function] 1853 * 1854 * Watchdog timer handler. 1855 */ 1856 static void 1857 wm_watchdog(struct ifnet *ifp) 1858 { 1859 struct wm_softc *sc = ifp->if_softc; 1860 1861 /* 1862 * Since we're using delayed interrupts, sweep up 1863 * before we report an error. 1864 */ 1865 wm_txintr(sc); 1866 1867 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1868 log(LOG_ERR, 1869 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1870 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1871 sc->sc_txnext); 1872 ifp->if_oerrors++; 1873 1874 /* Reset the interface. */ 1875 (void) wm_init(ifp); 1876 } 1877 1878 /* Try to get more packets going. */ 1879 wm_start(ifp); 1880 } 1881 1882 /* 1883 * wm_ioctl: [ifnet interface function] 1884 * 1885 * Handle control requests from the operator. 1886 */ 1887 static int 1888 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1889 { 1890 struct wm_softc *sc = ifp->if_softc; 1891 struct ifreq *ifr = (struct ifreq *) data; 1892 int s, error; 1893 1894 s = splnet(); 1895 1896 switch (cmd) { 1897 case SIOCSIFMEDIA: 1898 case SIOCGIFMEDIA: 1899 /* Flow control requires full-duplex mode. */ 1900 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1901 (ifr->ifr_media & IFM_FDX) == 0) 1902 ifr->ifr_media &= ~IFM_ETH_FMASK; 1903 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1904 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1905 /* We can do both TXPAUSE and RXPAUSE. */ 1906 ifr->ifr_media |= 1907 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1908 } 1909 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1910 } 1911 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1912 break; 1913 default: 1914 error = ether_ioctl(ifp, cmd, data); 1915 if (error == ENETRESET) { 1916 /* 1917 * Multicast list has changed; set the hardware filter 1918 * accordingly. 1919 */ 1920 if (ifp->if_flags & IFF_RUNNING) 1921 wm_set_filter(sc); 1922 error = 0; 1923 } 1924 break; 1925 } 1926 1927 /* Try to get more packets going. */ 1928 wm_start(ifp); 1929 1930 splx(s); 1931 return (error); 1932 } 1933 1934 /* 1935 * wm_intr: 1936 * 1937 * Interrupt service routine. 1938 */ 1939 static int 1940 wm_intr(void *arg) 1941 { 1942 struct wm_softc *sc = arg; 1943 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1944 uint32_t icr; 1945 int wantinit, handled = 0; 1946 1947 for (wantinit = 0; wantinit == 0;) { 1948 icr = CSR_READ(sc, WMREG_ICR); 1949 if ((icr & sc->sc_icr) == 0) 1950 break; 1951 1952 #if 0 /*NRND > 0*/ 1953 if (RND_ENABLED(&sc->rnd_source)) 1954 rnd_add_uint32(&sc->rnd_source, icr); 1955 #endif 1956 1957 handled = 1; 1958 1959 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1960 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1961 DPRINTF(WM_DEBUG_RX, 1962 ("%s: RX: got Rx intr 0x%08x\n", 1963 sc->sc_dev.dv_xname, 1964 icr & (ICR_RXDMT0|ICR_RXT0))); 1965 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 1966 } 1967 #endif 1968 wm_rxintr(sc); 1969 1970 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1971 if (icr & ICR_TXDW) { 1972 DPRINTF(WM_DEBUG_TX, 1973 ("%s: TX: got TXDW interrupt\n", 1974 sc->sc_dev.dv_xname)); 1975 WM_EVCNT_INCR(&sc->sc_ev_txdw); 1976 } 1977 #endif 1978 wm_txintr(sc); 1979 1980 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 1981 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 1982 wm_linkintr(sc, icr); 1983 } 1984 1985 if (icr & ICR_RXO) { 1986 log(LOG_WARNING, "%s: Receive overrun\n", 1987 sc->sc_dev.dv_xname); 1988 wantinit = 1; 1989 } 1990 } 1991 1992 if (handled) { 1993 if (wantinit) 1994 wm_init(ifp); 1995 1996 /* Try to get more packets going. */ 1997 wm_start(ifp); 1998 } 1999 2000 return (handled); 2001 } 2002 2003 /* 2004 * wm_txintr: 2005 * 2006 * Helper; handle transmit interrupts. 2007 */ 2008 static void 2009 wm_txintr(struct wm_softc *sc) 2010 { 2011 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2012 struct wm_txsoft *txs; 2013 uint8_t status; 2014 int i; 2015 2016 ifp->if_flags &= ~IFF_OACTIVE; 2017 2018 /* 2019 * Go through the Tx list and free mbufs for those 2020 * frames which have been transmitted. 2021 */ 2022 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2023 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2024 txs = &sc->sc_txsoft[i]; 2025 2026 DPRINTF(WM_DEBUG_TX, 2027 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2028 2029 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2030 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2031 2032 status = 2033 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2034 if ((status & WTX_ST_DD) == 0) { 2035 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2036 BUS_DMASYNC_PREREAD); 2037 break; 2038 } 2039 2040 DPRINTF(WM_DEBUG_TX, 2041 ("%s: TX: job %d done: descs %d..%d\n", 2042 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2043 txs->txs_lastdesc)); 2044 2045 /* 2046 * XXX We should probably be using the statistics 2047 * XXX registers, but I don't know if they exist 2048 * XXX on chips before the i82544. 2049 */ 2050 2051 #ifdef WM_EVENT_COUNTERS 2052 if (status & WTX_ST_TU) 2053 WM_EVCNT_INCR(&sc->sc_ev_tu); 2054 #endif /* WM_EVENT_COUNTERS */ 2055 2056 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2057 ifp->if_oerrors++; 2058 if (status & WTX_ST_LC) 2059 log(LOG_WARNING, "%s: late collision\n", 2060 sc->sc_dev.dv_xname); 2061 else if (status & WTX_ST_EC) { 2062 ifp->if_collisions += 16; 2063 log(LOG_WARNING, "%s: excessive collisions\n", 2064 sc->sc_dev.dv_xname); 2065 } 2066 } else 2067 ifp->if_opackets++; 2068 2069 sc->sc_txfree += txs->txs_ndesc; 2070 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2071 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2072 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2073 m_freem(txs->txs_mbuf); 2074 txs->txs_mbuf = NULL; 2075 } 2076 2077 /* Update the dirty transmit buffer pointer. */ 2078 sc->sc_txsdirty = i; 2079 DPRINTF(WM_DEBUG_TX, 2080 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2081 2082 /* 2083 * If there are no more pending transmissions, cancel the watchdog 2084 * timer. 2085 */ 2086 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2087 ifp->if_timer = 0; 2088 } 2089 2090 /* 2091 * wm_rxintr: 2092 * 2093 * Helper; handle receive interrupts. 2094 */ 2095 static void 2096 wm_rxintr(struct wm_softc *sc) 2097 { 2098 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2099 struct wm_rxsoft *rxs; 2100 struct mbuf *m; 2101 int i, len; 2102 uint8_t status, errors; 2103 2104 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2105 rxs = &sc->sc_rxsoft[i]; 2106 2107 DPRINTF(WM_DEBUG_RX, 2108 ("%s: RX: checking descriptor %d\n", 2109 sc->sc_dev.dv_xname, i)); 2110 2111 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2112 2113 status = sc->sc_rxdescs[i].wrx_status; 2114 errors = sc->sc_rxdescs[i].wrx_errors; 2115 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2116 2117 if ((status & WRX_ST_DD) == 0) { 2118 /* 2119 * We have processed all of the receive descriptors. 2120 */ 2121 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2122 break; 2123 } 2124 2125 if (__predict_false(sc->sc_rxdiscard)) { 2126 DPRINTF(WM_DEBUG_RX, 2127 ("%s: RX: discarding contents of descriptor %d\n", 2128 sc->sc_dev.dv_xname, i)); 2129 WM_INIT_RXDESC(sc, i); 2130 if (status & WRX_ST_EOP) { 2131 /* Reset our state. */ 2132 DPRINTF(WM_DEBUG_RX, 2133 ("%s: RX: resetting rxdiscard -> 0\n", 2134 sc->sc_dev.dv_xname)); 2135 sc->sc_rxdiscard = 0; 2136 } 2137 continue; 2138 } 2139 2140 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2141 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2142 2143 m = rxs->rxs_mbuf; 2144 2145 /* 2146 * Add a new receive buffer to the ring. 2147 */ 2148 if (wm_add_rxbuf(sc, i) != 0) { 2149 /* 2150 * Failed, throw away what we've done so 2151 * far, and discard the rest of the packet. 2152 */ 2153 ifp->if_ierrors++; 2154 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2155 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2156 WM_INIT_RXDESC(sc, i); 2157 if ((status & WRX_ST_EOP) == 0) 2158 sc->sc_rxdiscard = 1; 2159 if (sc->sc_rxhead != NULL) 2160 m_freem(sc->sc_rxhead); 2161 WM_RXCHAIN_RESET(sc); 2162 DPRINTF(WM_DEBUG_RX, 2163 ("%s: RX: Rx buffer allocation failed, " 2164 "dropping packet%s\n", sc->sc_dev.dv_xname, 2165 sc->sc_rxdiscard ? " (discard)" : "")); 2166 continue; 2167 } 2168 2169 WM_RXCHAIN_LINK(sc, m); 2170 2171 m->m_len = len; 2172 2173 DPRINTF(WM_DEBUG_RX, 2174 ("%s: RX: buffer at %p len %d\n", 2175 sc->sc_dev.dv_xname, m->m_data, len)); 2176 2177 /* 2178 * If this is not the end of the packet, keep 2179 * looking. 2180 */ 2181 if ((status & WRX_ST_EOP) == 0) { 2182 sc->sc_rxlen += len; 2183 DPRINTF(WM_DEBUG_RX, 2184 ("%s: RX: not yet EOP, rxlen -> %d\n", 2185 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2186 continue; 2187 } 2188 2189 /* 2190 * Okay, we have the entire packet now... 2191 */ 2192 *sc->sc_rxtailp = NULL; 2193 m = sc->sc_rxhead; 2194 len += sc->sc_rxlen; 2195 2196 WM_RXCHAIN_RESET(sc); 2197 2198 DPRINTF(WM_DEBUG_RX, 2199 ("%s: RX: have entire packet, len -> %d\n", 2200 sc->sc_dev.dv_xname, len)); 2201 2202 /* 2203 * If an error occurred, update stats and drop the packet. 2204 */ 2205 if (errors & 2206 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2207 ifp->if_ierrors++; 2208 if (errors & WRX_ER_SE) 2209 log(LOG_WARNING, "%s: symbol error\n", 2210 sc->sc_dev.dv_xname); 2211 else if (errors & WRX_ER_SEQ) 2212 log(LOG_WARNING, "%s: receive sequence error\n", 2213 sc->sc_dev.dv_xname); 2214 else if (errors & WRX_ER_CE) 2215 log(LOG_WARNING, "%s: CRC error\n", 2216 sc->sc_dev.dv_xname); 2217 m_freem(m); 2218 continue; 2219 } 2220 2221 /* 2222 * No errors. Receive the packet. 2223 * 2224 * Note, we have configured the chip to include the 2225 * CRC with every packet. 2226 */ 2227 m->m_flags |= M_HASFCS; 2228 m->m_pkthdr.rcvif = ifp; 2229 m->m_pkthdr.len = len; 2230 2231 #if 0 /* XXXJRT */ 2232 /* 2233 * If VLANs are enabled, VLAN packets have been unwrapped 2234 * for us. Associate the tag with the packet. 2235 */ 2236 if (sc->sc_ethercom.ec_nvlans != 0 && 2237 (status & WRX_ST_VP) != 0) { 2238 struct m_tag *vtag; 2239 2240 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2241 M_NOWAIT); 2242 if (vtag == NULL) { 2243 ifp->if_ierrors++; 2244 log(LOG_ERR, 2245 "%s: unable to allocate VLAN tag\n", 2246 sc->sc_dev.dv_xname); 2247 m_freem(m); 2248 continue; 2249 } 2250 2251 *(u_int *)(vtag + 1) = 2252 le16toh(sc->sc_rxdescs[i].wrx_special); 2253 } 2254 #endif /* XXXJRT */ 2255 2256 /* 2257 * Set up checksum info for this packet. 2258 */ 2259 if (status & WRX_ST_IPCS) { 2260 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2261 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2262 if (errors & WRX_ER_IPE) 2263 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2264 } 2265 if (status & WRX_ST_TCPCS) { 2266 /* 2267 * Note: we don't know if this was TCP or UDP, 2268 * so we just set both bits, and expect the 2269 * upper layers to deal. 2270 */ 2271 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2272 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2273 if (errors & WRX_ER_TCPE) 2274 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2275 } 2276 2277 ifp->if_ipackets++; 2278 2279 #if NBPFILTER > 0 2280 /* Pass this up to any BPF listeners. */ 2281 if (ifp->if_bpf) 2282 bpf_mtap(ifp->if_bpf, m); 2283 #endif /* NBPFILTER > 0 */ 2284 2285 /* Pass it on. */ 2286 (*ifp->if_input)(ifp, m); 2287 } 2288 2289 /* Update the receive pointer. */ 2290 sc->sc_rxptr = i; 2291 2292 DPRINTF(WM_DEBUG_RX, 2293 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2294 } 2295 2296 /* 2297 * wm_linkintr: 2298 * 2299 * Helper; handle link interrupts. 2300 */ 2301 static void 2302 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2303 { 2304 uint32_t status; 2305 2306 /* 2307 * If we get a link status interrupt on a 1000BASE-T 2308 * device, just fall into the normal MII tick path. 2309 */ 2310 if (sc->sc_flags & WM_F_HAS_MII) { 2311 if (icr & ICR_LSC) { 2312 DPRINTF(WM_DEBUG_LINK, 2313 ("%s: LINK: LSC -> mii_tick\n", 2314 sc->sc_dev.dv_xname)); 2315 mii_tick(&sc->sc_mii); 2316 } else if (icr & ICR_RXSEQ) { 2317 DPRINTF(WM_DEBUG_LINK, 2318 ("%s: LINK Receive sequence error\n", 2319 sc->sc_dev.dv_xname)); 2320 } 2321 return; 2322 } 2323 2324 /* 2325 * If we are now receiving /C/, check for link again in 2326 * a couple of link clock ticks. 2327 */ 2328 if (icr & ICR_RXCFG) { 2329 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2330 sc->sc_dev.dv_xname)); 2331 sc->sc_tbi_anstate = 2; 2332 } 2333 2334 if (icr & ICR_LSC) { 2335 status = CSR_READ(sc, WMREG_STATUS); 2336 if (status & STATUS_LU) { 2337 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2338 sc->sc_dev.dv_xname, 2339 (status & STATUS_FD) ? "FDX" : "HDX")); 2340 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2341 sc->sc_fcrtl &= ~FCRTL_XONE; 2342 if (status & STATUS_FD) 2343 sc->sc_tctl |= 2344 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2345 else 2346 sc->sc_tctl |= 2347 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2348 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2349 sc->sc_fcrtl |= FCRTL_XONE; 2350 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2351 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2352 WMREG_OLD_FCRTL : WMREG_FCRTL, 2353 sc->sc_fcrtl); 2354 sc->sc_tbi_linkup = 1; 2355 } else { 2356 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2357 sc->sc_dev.dv_xname)); 2358 sc->sc_tbi_linkup = 0; 2359 } 2360 sc->sc_tbi_anstate = 2; 2361 wm_tbi_set_linkled(sc); 2362 } else if (icr & ICR_RXSEQ) { 2363 DPRINTF(WM_DEBUG_LINK, 2364 ("%s: LINK: Receive sequence error\n", 2365 sc->sc_dev.dv_xname)); 2366 } 2367 } 2368 2369 /* 2370 * wm_tick: 2371 * 2372 * One second timer, used to check link status, sweep up 2373 * completed transmit jobs, etc. 2374 */ 2375 static void 2376 wm_tick(void *arg) 2377 { 2378 struct wm_softc *sc = arg; 2379 int s; 2380 2381 s = splnet(); 2382 2383 if (sc->sc_type >= WM_T_82542_2_1) { 2384 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2385 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2386 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2387 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2388 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2389 } 2390 2391 if (sc->sc_flags & WM_F_HAS_MII) 2392 mii_tick(&sc->sc_mii); 2393 else 2394 wm_tbi_check_link(sc); 2395 2396 splx(s); 2397 2398 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2399 } 2400 2401 /* 2402 * wm_reset: 2403 * 2404 * Reset the i82542 chip. 2405 */ 2406 static void 2407 wm_reset(struct wm_softc *sc) 2408 { 2409 int i; 2410 2411 /* 2412 * Allocate on-chip memory according to the MTU size. 2413 * The Packet Buffer Allocation register must be written 2414 * before the chip is reset. 2415 */ 2416 if (sc->sc_type < WM_T_82547) { 2417 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2418 PBA_40K : PBA_48K; 2419 } else { 2420 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2421 PBA_22K : PBA_30K; 2422 sc->sc_txfifo_head = 0; 2423 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2424 sc->sc_txfifo_size = 2425 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2426 sc->sc_txfifo_stall = 0; 2427 } 2428 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2429 2430 switch (sc->sc_type) { 2431 case WM_T_82544: 2432 case WM_T_82540: 2433 case WM_T_82545: 2434 case WM_T_82546: 2435 case WM_T_82541: 2436 case WM_T_82541_2: 2437 /* 2438 * On some chipsets, a reset through a memory-mapped write 2439 * cycle can cause the chip to reset before completing the 2440 * write cycle. This causes major headache that can be 2441 * avoided by issuing the reset via indirect register writes 2442 * through I/O space. 2443 * 2444 * So, if we successfully mapped the I/O BAR at attach time, 2445 * use that. Otherwise, try our luck with a memory-mapped 2446 * reset. 2447 */ 2448 if (sc->sc_flags & WM_F_IOH_VALID) 2449 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2450 else 2451 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2452 break; 2453 2454 case WM_T_82545_3: 2455 case WM_T_82546_3: 2456 /* Use the shadow control register on these chips. */ 2457 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2458 break; 2459 2460 default: 2461 /* Everything else can safely use the documented method. */ 2462 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2463 break; 2464 } 2465 delay(10000); 2466 2467 for (i = 0; i < 1000; i++) { 2468 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2469 return; 2470 delay(20); 2471 } 2472 2473 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2474 log(LOG_ERR, "%s: reset failed to complete\n", 2475 sc->sc_dev.dv_xname); 2476 } 2477 2478 /* 2479 * wm_init: [ifnet interface function] 2480 * 2481 * Initialize the interface. Must be called at splnet(). 2482 */ 2483 static int 2484 wm_init(struct ifnet *ifp) 2485 { 2486 struct wm_softc *sc = ifp->if_softc; 2487 struct wm_rxsoft *rxs; 2488 int i, error = 0; 2489 uint32_t reg; 2490 2491 /* 2492 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2493 * There is a small but measurable benefit to avoiding the adjusment 2494 * of the descriptor so that the headers are aligned, for normal mtu, 2495 * on such platforms. One possibility is that the DMA itself is 2496 * slightly more efficient if the front of the entire packet (instead 2497 * of the front of the headers) is aligned. 2498 * 2499 * Note we must always set align_tweak to 0 if we are using 2500 * jumbo frames. 2501 */ 2502 #ifdef __NO_STRICT_ALIGNMENT 2503 sc->sc_align_tweak = 0; 2504 #else 2505 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2506 sc->sc_align_tweak = 0; 2507 else 2508 sc->sc_align_tweak = 2; 2509 #endif /* __NO_STRICT_ALIGNMENT */ 2510 2511 /* Cancel any pending I/O. */ 2512 wm_stop(ifp, 0); 2513 2514 /* Reset the chip to a known state. */ 2515 wm_reset(sc); 2516 2517 /* Initialize the transmit descriptor ring. */ 2518 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2519 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2520 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2521 sc->sc_txfree = WM_NTXDESC(sc); 2522 sc->sc_txnext = 0; 2523 2524 if (sc->sc_type < WM_T_82543) { 2525 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2526 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2527 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2528 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2529 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2530 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2531 } else { 2532 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2533 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2534 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2535 CSR_WRITE(sc, WMREG_TDH, 0); 2536 CSR_WRITE(sc, WMREG_TDT, 0); 2537 CSR_WRITE(sc, WMREG_TIDV, 64); 2538 CSR_WRITE(sc, WMREG_TADV, 128); 2539 2540 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2541 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2542 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2543 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2544 } 2545 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2546 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2547 2548 /* Initialize the transmit job descriptors. */ 2549 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2550 sc->sc_txsoft[i].txs_mbuf = NULL; 2551 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2552 sc->sc_txsnext = 0; 2553 sc->sc_txsdirty = 0; 2554 2555 /* 2556 * Initialize the receive descriptor and receive job 2557 * descriptor rings. 2558 */ 2559 if (sc->sc_type < WM_T_82543) { 2560 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2561 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2562 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2563 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2564 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2565 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2566 2567 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2568 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2569 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2570 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2571 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2572 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2573 } else { 2574 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2575 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2576 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2577 CSR_WRITE(sc, WMREG_RDH, 0); 2578 CSR_WRITE(sc, WMREG_RDT, 0); 2579 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2580 CSR_WRITE(sc, WMREG_RADV, 128); 2581 } 2582 for (i = 0; i < WM_NRXDESC; i++) { 2583 rxs = &sc->sc_rxsoft[i]; 2584 if (rxs->rxs_mbuf == NULL) { 2585 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2586 log(LOG_ERR, "%s: unable to allocate or map rx " 2587 "buffer %d, error = %d\n", 2588 sc->sc_dev.dv_xname, i, error); 2589 /* 2590 * XXX Should attempt to run with fewer receive 2591 * XXX buffers instead of just failing. 2592 */ 2593 wm_rxdrain(sc); 2594 goto out; 2595 } 2596 } else 2597 WM_INIT_RXDESC(sc, i); 2598 } 2599 sc->sc_rxptr = 0; 2600 sc->sc_rxdiscard = 0; 2601 WM_RXCHAIN_RESET(sc); 2602 2603 /* 2604 * Clear out the VLAN table -- we don't use it (yet). 2605 */ 2606 CSR_WRITE(sc, WMREG_VET, 0); 2607 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2608 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2609 2610 /* 2611 * Set up flow-control parameters. 2612 * 2613 * XXX Values could probably stand some tuning. 2614 */ 2615 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2616 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2617 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2618 2619 sc->sc_fcrtl = FCRTL_DFLT; 2620 if (sc->sc_type < WM_T_82543) { 2621 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2622 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2623 } else { 2624 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2625 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2626 } 2627 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2628 2629 #if 0 /* XXXJRT */ 2630 /* Deal with VLAN enables. */ 2631 if (sc->sc_ethercom.ec_nvlans != 0) 2632 sc->sc_ctrl |= CTRL_VME; 2633 else 2634 #endif /* XXXJRT */ 2635 sc->sc_ctrl &= ~CTRL_VME; 2636 2637 /* Write the control registers. */ 2638 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2639 #if 0 2640 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2641 #endif 2642 2643 /* 2644 * Set up checksum offload parameters. 2645 */ 2646 reg = CSR_READ(sc, WMREG_RXCSUM); 2647 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2648 reg |= RXCSUM_IPOFL; 2649 else 2650 reg &= ~RXCSUM_IPOFL; 2651 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2652 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2653 else { 2654 reg &= ~RXCSUM_TUOFL; 2655 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2656 reg &= ~RXCSUM_IPOFL; 2657 } 2658 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2659 2660 /* 2661 * Set up the interrupt registers. 2662 */ 2663 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2664 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2665 ICR_RXO | ICR_RXT0; 2666 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2667 sc->sc_icr |= ICR_RXCFG; 2668 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2669 2670 /* Set up the inter-packet gap. */ 2671 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2672 2673 if (sc->sc_type >= WM_T_82543) { 2674 /* Set up the interrupt throttling register (units of 256ns) */ 2675 sc->sc_itr = 1000000000 / (7000 * 256); 2676 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2677 } 2678 2679 #if 0 /* XXXJRT */ 2680 /* Set the VLAN ethernetype. */ 2681 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2682 #endif 2683 2684 /* 2685 * Set up the transmit control register; we start out with 2686 * a collision distance suitable for FDX, but update it whe 2687 * we resolve the media type. 2688 */ 2689 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2690 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2691 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2692 2693 /* Set the media. */ 2694 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2695 2696 /* 2697 * Set up the receive control register; we actually program 2698 * the register when we set the receive filter. Use multicast 2699 * address offset type 0. 2700 * 2701 * Only the i82544 has the ability to strip the incoming 2702 * CRC, so we don't enable that feature. 2703 */ 2704 sc->sc_mchash_type = 0; 2705 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2706 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2707 2708 if(MCLBYTES == 2048) { 2709 sc->sc_rctl |= RCTL_2k; 2710 } else { 2711 if(sc->sc_type >= WM_T_82543) { 2712 switch(MCLBYTES) { 2713 case 4096: 2714 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2715 break; 2716 case 8192: 2717 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2718 break; 2719 case 16384: 2720 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2721 break; 2722 default: 2723 panic("wm_init: MCLBYTES %d unsupported", 2724 MCLBYTES); 2725 break; 2726 } 2727 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2728 } 2729 2730 /* Set the receive filter. */ 2731 wm_set_filter(sc); 2732 2733 /* Start the one second link check clock. */ 2734 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2735 2736 /* ...all done! */ 2737 ifp->if_flags |= IFF_RUNNING; 2738 ifp->if_flags &= ~IFF_OACTIVE; 2739 2740 out: 2741 if (error) 2742 log(LOG_ERR, "%s: interface not running\n", 2743 sc->sc_dev.dv_xname); 2744 return (error); 2745 } 2746 2747 /* 2748 * wm_rxdrain: 2749 * 2750 * Drain the receive queue. 2751 */ 2752 static void 2753 wm_rxdrain(struct wm_softc *sc) 2754 { 2755 struct wm_rxsoft *rxs; 2756 int i; 2757 2758 for (i = 0; i < WM_NRXDESC; i++) { 2759 rxs = &sc->sc_rxsoft[i]; 2760 if (rxs->rxs_mbuf != NULL) { 2761 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2762 m_freem(rxs->rxs_mbuf); 2763 rxs->rxs_mbuf = NULL; 2764 } 2765 } 2766 } 2767 2768 /* 2769 * wm_stop: [ifnet interface function] 2770 * 2771 * Stop transmission on the interface. 2772 */ 2773 static void 2774 wm_stop(struct ifnet *ifp, int disable) 2775 { 2776 struct wm_softc *sc = ifp->if_softc; 2777 struct wm_txsoft *txs; 2778 int i; 2779 2780 /* Stop the one second clock. */ 2781 callout_stop(&sc->sc_tick_ch); 2782 2783 /* Stop the 82547 Tx FIFO stall check timer. */ 2784 if (sc->sc_type == WM_T_82547) 2785 callout_stop(&sc->sc_txfifo_ch); 2786 2787 if (sc->sc_flags & WM_F_HAS_MII) { 2788 /* Down the MII. */ 2789 mii_down(&sc->sc_mii); 2790 } 2791 2792 /* Stop the transmit and receive processes. */ 2793 CSR_WRITE(sc, WMREG_TCTL, 0); 2794 CSR_WRITE(sc, WMREG_RCTL, 0); 2795 2796 /* Release any queued transmit buffers. */ 2797 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2798 txs = &sc->sc_txsoft[i]; 2799 if (txs->txs_mbuf != NULL) { 2800 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2801 m_freem(txs->txs_mbuf); 2802 txs->txs_mbuf = NULL; 2803 } 2804 } 2805 2806 if (disable) 2807 wm_rxdrain(sc); 2808 2809 /* Mark the interface as down and cancel the watchdog timer. */ 2810 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2811 ifp->if_timer = 0; 2812 } 2813 2814 /* 2815 * wm_acquire_eeprom: 2816 * 2817 * Perform the EEPROM handshake required on some chips. 2818 */ 2819 static int 2820 wm_acquire_eeprom(struct wm_softc *sc) 2821 { 2822 uint32_t reg; 2823 int x; 2824 2825 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2826 reg = CSR_READ(sc, WMREG_EECD); 2827 2828 /* Request EEPROM access. */ 2829 reg |= EECD_EE_REQ; 2830 CSR_WRITE(sc, WMREG_EECD, reg); 2831 2832 /* ..and wait for it to be granted. */ 2833 for (x = 0; x < 100; x++) { 2834 reg = CSR_READ(sc, WMREG_EECD); 2835 if (reg & EECD_EE_GNT) 2836 break; 2837 delay(5); 2838 } 2839 if ((reg & EECD_EE_GNT) == 0) { 2840 aprint_error("%s: could not acquire EEPROM GNT\n", 2841 sc->sc_dev.dv_xname); 2842 reg &= ~EECD_EE_REQ; 2843 CSR_WRITE(sc, WMREG_EECD, reg); 2844 return (1); 2845 } 2846 } 2847 2848 return (0); 2849 } 2850 2851 /* 2852 * wm_release_eeprom: 2853 * 2854 * Release the EEPROM mutex. 2855 */ 2856 static void 2857 wm_release_eeprom(struct wm_softc *sc) 2858 { 2859 uint32_t reg; 2860 2861 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2862 reg = CSR_READ(sc, WMREG_EECD); 2863 reg &= ~EECD_EE_REQ; 2864 CSR_WRITE(sc, WMREG_EECD, reg); 2865 } 2866 } 2867 2868 /* 2869 * wm_eeprom_sendbits: 2870 * 2871 * Send a series of bits to the EEPROM. 2872 */ 2873 static void 2874 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2875 { 2876 uint32_t reg; 2877 int x; 2878 2879 reg = CSR_READ(sc, WMREG_EECD); 2880 2881 for (x = nbits; x > 0; x--) { 2882 if (bits & (1U << (x - 1))) 2883 reg |= EECD_DI; 2884 else 2885 reg &= ~EECD_DI; 2886 CSR_WRITE(sc, WMREG_EECD, reg); 2887 delay(2); 2888 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2889 delay(2); 2890 CSR_WRITE(sc, WMREG_EECD, reg); 2891 delay(2); 2892 } 2893 } 2894 2895 /* 2896 * wm_eeprom_recvbits: 2897 * 2898 * Receive a series of bits from the EEPROM. 2899 */ 2900 static void 2901 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2902 { 2903 uint32_t reg, val; 2904 int x; 2905 2906 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2907 2908 val = 0; 2909 for (x = nbits; x > 0; x--) { 2910 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2911 delay(2); 2912 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2913 val |= (1U << (x - 1)); 2914 CSR_WRITE(sc, WMREG_EECD, reg); 2915 delay(2); 2916 } 2917 *valp = val; 2918 } 2919 2920 /* 2921 * wm_read_eeprom_uwire: 2922 * 2923 * Read a word from the EEPROM using the MicroWire protocol. 2924 */ 2925 static int 2926 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2927 { 2928 uint32_t reg, val; 2929 int i; 2930 2931 for (i = 0; i < wordcnt; i++) { 2932 /* Clear SK and DI. */ 2933 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2934 CSR_WRITE(sc, WMREG_EECD, reg); 2935 2936 /* Set CHIP SELECT. */ 2937 reg |= EECD_CS; 2938 CSR_WRITE(sc, WMREG_EECD, reg); 2939 delay(2); 2940 2941 /* Shift in the READ command. */ 2942 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2943 2944 /* Shift in address. */ 2945 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2946 2947 /* Shift out the data. */ 2948 wm_eeprom_recvbits(sc, &val, 16); 2949 data[i] = val & 0xffff; 2950 2951 /* Clear CHIP SELECT. */ 2952 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 2953 CSR_WRITE(sc, WMREG_EECD, reg); 2954 delay(2); 2955 } 2956 2957 return (0); 2958 } 2959 2960 /* 2961 * wm_spi_eeprom_ready: 2962 * 2963 * Wait for a SPI EEPROM to be ready for commands. 2964 */ 2965 static int 2966 wm_spi_eeprom_ready(struct wm_softc *sc) 2967 { 2968 uint32_t val; 2969 int usec; 2970 2971 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 2972 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 2973 wm_eeprom_recvbits(sc, &val, 8); 2974 if ((val & SPI_SR_RDY) == 0) 2975 break; 2976 } 2977 if (usec >= SPI_MAX_RETRIES) { 2978 aprint_error("%s: EEPROM failed to become ready\n", 2979 sc->sc_dev.dv_xname); 2980 return (1); 2981 } 2982 return (0); 2983 } 2984 2985 /* 2986 * wm_read_eeprom_spi: 2987 * 2988 * Read a work from the EEPROM using the SPI protocol. 2989 */ 2990 static int 2991 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2992 { 2993 uint32_t reg, val; 2994 int i; 2995 uint8_t opc; 2996 2997 /* Clear SK and CS. */ 2998 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 2999 CSR_WRITE(sc, WMREG_EECD, reg); 3000 delay(2); 3001 3002 if (wm_spi_eeprom_ready(sc)) 3003 return (1); 3004 3005 /* Toggle CS to flush commands. */ 3006 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3007 delay(2); 3008 CSR_WRITE(sc, WMREG_EECD, reg); 3009 delay(2); 3010 3011 opc = SPI_OPC_READ; 3012 if (sc->sc_ee_addrbits == 8 && word >= 128) 3013 opc |= SPI_OPC_A8; 3014 3015 wm_eeprom_sendbits(sc, opc, 8); 3016 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3017 3018 for (i = 0; i < wordcnt; i++) { 3019 wm_eeprom_recvbits(sc, &val, 16); 3020 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3021 } 3022 3023 /* Raise CS and clear SK. */ 3024 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3025 CSR_WRITE(sc, WMREG_EECD, reg); 3026 delay(2); 3027 3028 return (0); 3029 } 3030 3031 /* 3032 * wm_read_eeprom: 3033 * 3034 * Read data from the serial EEPROM. 3035 */ 3036 static int 3037 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3038 { 3039 int rv; 3040 3041 if (wm_acquire_eeprom(sc)) 3042 return (1); 3043 3044 if (sc->sc_flags & WM_F_EEPROM_SPI) 3045 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3046 else 3047 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3048 3049 wm_release_eeprom(sc); 3050 return (rv); 3051 } 3052 3053 /* 3054 * wm_add_rxbuf: 3055 * 3056 * Add a receive buffer to the indiciated descriptor. 3057 */ 3058 static int 3059 wm_add_rxbuf(struct wm_softc *sc, int idx) 3060 { 3061 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3062 struct mbuf *m; 3063 int error; 3064 3065 MGETHDR(m, M_DONTWAIT, MT_DATA); 3066 if (m == NULL) 3067 return (ENOBUFS); 3068 3069 MCLGET(m, M_DONTWAIT); 3070 if ((m->m_flags & M_EXT) == 0) { 3071 m_freem(m); 3072 return (ENOBUFS); 3073 } 3074 3075 if (rxs->rxs_mbuf != NULL) 3076 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3077 3078 rxs->rxs_mbuf = m; 3079 3080 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3081 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3082 BUS_DMA_READ|BUS_DMA_NOWAIT); 3083 if (error) { 3084 /* XXX XXX XXX */ 3085 printf("%s: unable to load rx DMA map %d, error = %d\n", 3086 sc->sc_dev.dv_xname, idx, error); 3087 panic("wm_add_rxbuf"); 3088 } 3089 3090 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3091 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3092 3093 WM_INIT_RXDESC(sc, idx); 3094 3095 return (0); 3096 } 3097 3098 /* 3099 * wm_set_ral: 3100 * 3101 * Set an entery in the receive address list. 3102 */ 3103 static void 3104 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3105 { 3106 uint32_t ral_lo, ral_hi; 3107 3108 if (enaddr != NULL) { 3109 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3110 (enaddr[3] << 24); 3111 ral_hi = enaddr[4] | (enaddr[5] << 8); 3112 ral_hi |= RAL_AV; 3113 } else { 3114 ral_lo = 0; 3115 ral_hi = 0; 3116 } 3117 3118 if (sc->sc_type >= WM_T_82544) { 3119 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3120 ral_lo); 3121 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3122 ral_hi); 3123 } else { 3124 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3125 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3126 } 3127 } 3128 3129 /* 3130 * wm_mchash: 3131 * 3132 * Compute the hash of the multicast address for the 4096-bit 3133 * multicast filter. 3134 */ 3135 static uint32_t 3136 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3137 { 3138 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3139 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3140 uint32_t hash; 3141 3142 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3143 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3144 3145 return (hash & 0xfff); 3146 } 3147 3148 /* 3149 * wm_set_filter: 3150 * 3151 * Set up the receive filter. 3152 */ 3153 static void 3154 wm_set_filter(struct wm_softc *sc) 3155 { 3156 struct ethercom *ec = &sc->sc_ethercom; 3157 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3158 struct ether_multi *enm; 3159 struct ether_multistep step; 3160 bus_addr_t mta_reg; 3161 uint32_t hash, reg, bit; 3162 int i; 3163 3164 if (sc->sc_type >= WM_T_82544) 3165 mta_reg = WMREG_CORDOVA_MTA; 3166 else 3167 mta_reg = WMREG_MTA; 3168 3169 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3170 3171 if (ifp->if_flags & IFF_BROADCAST) 3172 sc->sc_rctl |= RCTL_BAM; 3173 if (ifp->if_flags & IFF_PROMISC) { 3174 sc->sc_rctl |= RCTL_UPE; 3175 goto allmulti; 3176 } 3177 3178 /* 3179 * Set the station address in the first RAL slot, and 3180 * clear the remaining slots. 3181 */ 3182 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3183 for (i = 1; i < WM_RAL_TABSIZE; i++) 3184 wm_set_ral(sc, NULL, i); 3185 3186 /* Clear out the multicast table. */ 3187 for (i = 0; i < WM_MC_TABSIZE; i++) 3188 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3189 3190 ETHER_FIRST_MULTI(step, ec, enm); 3191 while (enm != NULL) { 3192 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3193 /* 3194 * We must listen to a range of multicast addresses. 3195 * For now, just accept all multicasts, rather than 3196 * trying to set only those filter bits needed to match 3197 * the range. (At this time, the only use of address 3198 * ranges is for IP multicast routing, for which the 3199 * range is big enough to require all bits set.) 3200 */ 3201 goto allmulti; 3202 } 3203 3204 hash = wm_mchash(sc, enm->enm_addrlo); 3205 3206 reg = (hash >> 5) & 0x7f; 3207 bit = hash & 0x1f; 3208 3209 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3210 hash |= 1U << bit; 3211 3212 /* XXX Hardware bug?? */ 3213 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3214 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3215 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3216 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3217 } else 3218 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3219 3220 ETHER_NEXT_MULTI(step, enm); 3221 } 3222 3223 ifp->if_flags &= ~IFF_ALLMULTI; 3224 goto setit; 3225 3226 allmulti: 3227 ifp->if_flags |= IFF_ALLMULTI; 3228 sc->sc_rctl |= RCTL_MPE; 3229 3230 setit: 3231 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3232 } 3233 3234 /* 3235 * wm_tbi_mediainit: 3236 * 3237 * Initialize media for use on 1000BASE-X devices. 3238 */ 3239 static void 3240 wm_tbi_mediainit(struct wm_softc *sc) 3241 { 3242 const char *sep = ""; 3243 3244 if (sc->sc_type < WM_T_82543) 3245 sc->sc_tipg = TIPG_WM_DFLT; 3246 else 3247 sc->sc_tipg = TIPG_LG_DFLT; 3248 3249 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3250 wm_tbi_mediastatus); 3251 3252 /* 3253 * SWD Pins: 3254 * 3255 * 0 = Link LED (output) 3256 * 1 = Loss Of Signal (input) 3257 */ 3258 sc->sc_ctrl |= CTRL_SWDPIO(0); 3259 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3260 3261 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3262 3263 #define ADD(ss, mm, dd) \ 3264 do { \ 3265 aprint_normal("%s%s", sep, ss); \ 3266 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3267 sep = ", "; \ 3268 } while (/*CONSTCOND*/0) 3269 3270 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3271 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3272 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3273 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3274 aprint_normal("\n"); 3275 3276 #undef ADD 3277 3278 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3279 } 3280 3281 /* 3282 * wm_tbi_mediastatus: [ifmedia interface function] 3283 * 3284 * Get the current interface media status on a 1000BASE-X device. 3285 */ 3286 static void 3287 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3288 { 3289 struct wm_softc *sc = ifp->if_softc; 3290 uint32_t ctrl; 3291 3292 ifmr->ifm_status = IFM_AVALID; 3293 ifmr->ifm_active = IFM_ETHER; 3294 3295 if (sc->sc_tbi_linkup == 0) { 3296 ifmr->ifm_active |= IFM_NONE; 3297 return; 3298 } 3299 3300 ifmr->ifm_status |= IFM_ACTIVE; 3301 ifmr->ifm_active |= IFM_1000_SX; 3302 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3303 ifmr->ifm_active |= IFM_FDX; 3304 ctrl = CSR_READ(sc, WMREG_CTRL); 3305 if (ctrl & CTRL_RFCE) 3306 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3307 if (ctrl & CTRL_TFCE) 3308 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3309 } 3310 3311 /* 3312 * wm_tbi_mediachange: [ifmedia interface function] 3313 * 3314 * Set hardware to newly-selected media on a 1000BASE-X device. 3315 */ 3316 static int 3317 wm_tbi_mediachange(struct ifnet *ifp) 3318 { 3319 struct wm_softc *sc = ifp->if_softc; 3320 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3321 uint32_t status; 3322 int i; 3323 3324 sc->sc_txcw = ife->ifm_data; 3325 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3326 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3327 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3328 sc->sc_txcw |= TXCW_ANE; 3329 3330 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3331 delay(10000); 3332 3333 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3334 3335 sc->sc_tbi_anstate = 0; 3336 3337 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3338 /* Have signal; wait for the link to come up. */ 3339 for (i = 0; i < 50; i++) { 3340 delay(10000); 3341 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3342 break; 3343 } 3344 3345 status = CSR_READ(sc, WMREG_STATUS); 3346 if (status & STATUS_LU) { 3347 /* Link is up. */ 3348 DPRINTF(WM_DEBUG_LINK, 3349 ("%s: LINK: set media -> link up %s\n", 3350 sc->sc_dev.dv_xname, 3351 (status & STATUS_FD) ? "FDX" : "HDX")); 3352 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3353 sc->sc_fcrtl &= ~FCRTL_XONE; 3354 if (status & STATUS_FD) 3355 sc->sc_tctl |= 3356 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3357 else 3358 sc->sc_tctl |= 3359 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3360 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3361 sc->sc_fcrtl |= FCRTL_XONE; 3362 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3363 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3364 WMREG_OLD_FCRTL : WMREG_FCRTL, 3365 sc->sc_fcrtl); 3366 sc->sc_tbi_linkup = 1; 3367 } else { 3368 /* Link is down. */ 3369 DPRINTF(WM_DEBUG_LINK, 3370 ("%s: LINK: set media -> link down\n", 3371 sc->sc_dev.dv_xname)); 3372 sc->sc_tbi_linkup = 0; 3373 } 3374 } else { 3375 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3376 sc->sc_dev.dv_xname)); 3377 sc->sc_tbi_linkup = 0; 3378 } 3379 3380 wm_tbi_set_linkled(sc); 3381 3382 return (0); 3383 } 3384 3385 /* 3386 * wm_tbi_set_linkled: 3387 * 3388 * Update the link LED on 1000BASE-X devices. 3389 */ 3390 static void 3391 wm_tbi_set_linkled(struct wm_softc *sc) 3392 { 3393 3394 if (sc->sc_tbi_linkup) 3395 sc->sc_ctrl |= CTRL_SWDPIN(0); 3396 else 3397 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3398 3399 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3400 } 3401 3402 /* 3403 * wm_tbi_check_link: 3404 * 3405 * Check the link on 1000BASE-X devices. 3406 */ 3407 static void 3408 wm_tbi_check_link(struct wm_softc *sc) 3409 { 3410 uint32_t rxcw, ctrl, status; 3411 3412 if (sc->sc_tbi_anstate == 0) 3413 return; 3414 else if (sc->sc_tbi_anstate > 1) { 3415 DPRINTF(WM_DEBUG_LINK, 3416 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3417 sc->sc_tbi_anstate)); 3418 sc->sc_tbi_anstate--; 3419 return; 3420 } 3421 3422 sc->sc_tbi_anstate = 0; 3423 3424 rxcw = CSR_READ(sc, WMREG_RXCW); 3425 ctrl = CSR_READ(sc, WMREG_CTRL); 3426 status = CSR_READ(sc, WMREG_STATUS); 3427 3428 if ((status & STATUS_LU) == 0) { 3429 DPRINTF(WM_DEBUG_LINK, 3430 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3431 sc->sc_tbi_linkup = 0; 3432 } else { 3433 DPRINTF(WM_DEBUG_LINK, 3434 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3435 (status & STATUS_FD) ? "FDX" : "HDX")); 3436 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3437 sc->sc_fcrtl &= ~FCRTL_XONE; 3438 if (status & STATUS_FD) 3439 sc->sc_tctl |= 3440 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3441 else 3442 sc->sc_tctl |= 3443 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3444 if (ctrl & CTRL_TFCE) 3445 sc->sc_fcrtl |= FCRTL_XONE; 3446 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3447 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3448 WMREG_OLD_FCRTL : WMREG_FCRTL, 3449 sc->sc_fcrtl); 3450 sc->sc_tbi_linkup = 1; 3451 } 3452 3453 wm_tbi_set_linkled(sc); 3454 } 3455 3456 /* 3457 * wm_gmii_reset: 3458 * 3459 * Reset the PHY. 3460 */ 3461 static void 3462 wm_gmii_reset(struct wm_softc *sc) 3463 { 3464 uint32_t reg; 3465 3466 if (sc->sc_type >= WM_T_82544) { 3467 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3468 delay(20000); 3469 3470 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3471 delay(20000); 3472 } else { 3473 /* The PHY reset pin is active-low. */ 3474 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3475 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3476 CTRL_EXT_SWDPIN(4)); 3477 reg |= CTRL_EXT_SWDPIO(4); 3478 3479 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3480 delay(10); 3481 3482 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3483 delay(10); 3484 3485 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3486 delay(10); 3487 #if 0 3488 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3489 #endif 3490 } 3491 } 3492 3493 /* 3494 * wm_gmii_mediainit: 3495 * 3496 * Initialize media for use on 1000BASE-T devices. 3497 */ 3498 static void 3499 wm_gmii_mediainit(struct wm_softc *sc) 3500 { 3501 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3502 3503 /* We have MII. */ 3504 sc->sc_flags |= WM_F_HAS_MII; 3505 3506 sc->sc_tipg = TIPG_1000T_DFLT; 3507 3508 /* 3509 * Let the chip set speed/duplex on its own based on 3510 * signals from the PHY. 3511 */ 3512 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3513 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3514 3515 /* Initialize our media structures and probe the GMII. */ 3516 sc->sc_mii.mii_ifp = ifp; 3517 3518 if (sc->sc_type >= WM_T_82544) { 3519 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3520 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3521 } else { 3522 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3523 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3524 } 3525 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3526 3527 wm_gmii_reset(sc); 3528 3529 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3530 wm_gmii_mediastatus); 3531 3532 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3533 MII_OFFSET_ANY, MIIF_DOPAUSE); 3534 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3535 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3536 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3537 } else 3538 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3539 } 3540 3541 /* 3542 * wm_gmii_mediastatus: [ifmedia interface function] 3543 * 3544 * Get the current interface media status on a 1000BASE-T device. 3545 */ 3546 static void 3547 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3548 { 3549 struct wm_softc *sc = ifp->if_softc; 3550 3551 mii_pollstat(&sc->sc_mii); 3552 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3553 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3554 sc->sc_flowflags; 3555 } 3556 3557 /* 3558 * wm_gmii_mediachange: [ifmedia interface function] 3559 * 3560 * Set hardware to newly-selected media on a 1000BASE-T device. 3561 */ 3562 static int 3563 wm_gmii_mediachange(struct ifnet *ifp) 3564 { 3565 struct wm_softc *sc = ifp->if_softc; 3566 3567 if (ifp->if_flags & IFF_UP) 3568 mii_mediachg(&sc->sc_mii); 3569 return (0); 3570 } 3571 3572 #define MDI_IO CTRL_SWDPIN(2) 3573 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3574 #define MDI_CLK CTRL_SWDPIN(3) 3575 3576 static void 3577 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3578 { 3579 uint32_t i, v; 3580 3581 v = CSR_READ(sc, WMREG_CTRL); 3582 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3583 v |= MDI_DIR | CTRL_SWDPIO(3); 3584 3585 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3586 if (data & i) 3587 v |= MDI_IO; 3588 else 3589 v &= ~MDI_IO; 3590 CSR_WRITE(sc, WMREG_CTRL, v); 3591 delay(10); 3592 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3593 delay(10); 3594 CSR_WRITE(sc, WMREG_CTRL, v); 3595 delay(10); 3596 } 3597 } 3598 3599 static uint32_t 3600 i82543_mii_recvbits(struct wm_softc *sc) 3601 { 3602 uint32_t v, i, data = 0; 3603 3604 v = CSR_READ(sc, WMREG_CTRL); 3605 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3606 v |= CTRL_SWDPIO(3); 3607 3608 CSR_WRITE(sc, WMREG_CTRL, v); 3609 delay(10); 3610 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3611 delay(10); 3612 CSR_WRITE(sc, WMREG_CTRL, v); 3613 delay(10); 3614 3615 for (i = 0; i < 16; i++) { 3616 data <<= 1; 3617 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3618 delay(10); 3619 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3620 data |= 1; 3621 CSR_WRITE(sc, WMREG_CTRL, v); 3622 delay(10); 3623 } 3624 3625 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3626 delay(10); 3627 CSR_WRITE(sc, WMREG_CTRL, v); 3628 delay(10); 3629 3630 return (data); 3631 } 3632 3633 #undef MDI_IO 3634 #undef MDI_DIR 3635 #undef MDI_CLK 3636 3637 /* 3638 * wm_gmii_i82543_readreg: [mii interface function] 3639 * 3640 * Read a PHY register on the GMII (i82543 version). 3641 */ 3642 static int 3643 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3644 { 3645 struct wm_softc *sc = (void *) self; 3646 int rv; 3647 3648 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3649 i82543_mii_sendbits(sc, reg | (phy << 5) | 3650 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3651 rv = i82543_mii_recvbits(sc) & 0xffff; 3652 3653 DPRINTF(WM_DEBUG_GMII, 3654 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3655 sc->sc_dev.dv_xname, phy, reg, rv)); 3656 3657 return (rv); 3658 } 3659 3660 /* 3661 * wm_gmii_i82543_writereg: [mii interface function] 3662 * 3663 * Write a PHY register on the GMII (i82543 version). 3664 */ 3665 static void 3666 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3667 { 3668 struct wm_softc *sc = (void *) self; 3669 3670 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3671 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3672 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3673 (MII_COMMAND_START << 30), 32); 3674 } 3675 3676 /* 3677 * wm_gmii_i82544_readreg: [mii interface function] 3678 * 3679 * Read a PHY register on the GMII. 3680 */ 3681 static int 3682 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3683 { 3684 struct wm_softc *sc = (void *) self; 3685 uint32_t mdic = 0; 3686 int i, rv; 3687 3688 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3689 MDIC_REGADD(reg)); 3690 3691 for (i = 0; i < 100; i++) { 3692 mdic = CSR_READ(sc, WMREG_MDIC); 3693 if (mdic & MDIC_READY) 3694 break; 3695 delay(10); 3696 } 3697 3698 if ((mdic & MDIC_READY) == 0) { 3699 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3700 sc->sc_dev.dv_xname, phy, reg); 3701 rv = 0; 3702 } else if (mdic & MDIC_E) { 3703 #if 0 /* This is normal if no PHY is present. */ 3704 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3705 sc->sc_dev.dv_xname, phy, reg); 3706 #endif 3707 rv = 0; 3708 } else { 3709 rv = MDIC_DATA(mdic); 3710 if (rv == 0xffff) 3711 rv = 0; 3712 } 3713 3714 return (rv); 3715 } 3716 3717 /* 3718 * wm_gmii_i82544_writereg: [mii interface function] 3719 * 3720 * Write a PHY register on the GMII. 3721 */ 3722 static void 3723 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3724 { 3725 struct wm_softc *sc = (void *) self; 3726 uint32_t mdic = 0; 3727 int i; 3728 3729 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3730 MDIC_REGADD(reg) | MDIC_DATA(val)); 3731 3732 for (i = 0; i < 100; i++) { 3733 mdic = CSR_READ(sc, WMREG_MDIC); 3734 if (mdic & MDIC_READY) 3735 break; 3736 delay(10); 3737 } 3738 3739 if ((mdic & MDIC_READY) == 0) 3740 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3741 sc->sc_dev.dv_xname, phy, reg); 3742 else if (mdic & MDIC_E) 3743 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3744 sc->sc_dev.dv_xname, phy, reg); 3745 } 3746 3747 /* 3748 * wm_gmii_statchg: [mii interface function] 3749 * 3750 * Callback from MII layer when media changes. 3751 */ 3752 static void 3753 wm_gmii_statchg(struct device *self) 3754 { 3755 struct wm_softc *sc = (void *) self; 3756 struct mii_data *mii = &sc->sc_mii; 3757 3758 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3759 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3760 sc->sc_fcrtl &= ~FCRTL_XONE; 3761 3762 /* 3763 * Get flow control negotiation result. 3764 */ 3765 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3766 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3767 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3768 mii->mii_media_active &= ~IFM_ETH_FMASK; 3769 } 3770 3771 if (sc->sc_flowflags & IFM_FLOW) { 3772 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3773 sc->sc_ctrl |= CTRL_TFCE; 3774 sc->sc_fcrtl |= FCRTL_XONE; 3775 } 3776 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3777 sc->sc_ctrl |= CTRL_RFCE; 3778 } 3779 3780 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3781 DPRINTF(WM_DEBUG_LINK, 3782 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3783 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3784 } else { 3785 DPRINTF(WM_DEBUG_LINK, 3786 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3787 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3788 } 3789 3790 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3791 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3792 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3793 : WMREG_FCRTL, sc->sc_fcrtl); 3794 } 3795
Indexes created Wed Sep 24 05:09:52 GMT 2025