if_wm.c revision 1.93
1 /* $NetBSD: if_wm.c,v 1.93 2005/02/18 05:58:31 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.93 2005/02/18 05:58:31 thorpej Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA ETHER_MAX_LEN_JUMBO 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make serveral things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 280 /* m_pullup() needed for Tx offload */ 281 struct evcnt sc_ev_txpullup_needed; 282 /* ...failed due to no memory */ 283 struct evcnt sc_ev_txpullup_nomem; 284 /* ...failed due to lack of space in first mbuf */ 285 struct evcnt sc_ev_txpullup_fail; 286 287 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 288 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 289 290 struct evcnt sc_ev_tu; /* Tx underrun */ 291 292 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 293 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 294 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 295 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 296 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 297 #endif /* WM_EVENT_COUNTERS */ 298 299 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 300 301 int sc_txfree; /* number of free Tx descriptors */ 302 int sc_txnext; /* next ready Tx descriptor */ 303 304 int sc_txsfree; /* number of free Tx jobs */ 305 int sc_txsnext; /* next free Tx job */ 306 int sc_txsdirty; /* dirty Tx jobs */ 307 308 /* These 5 variables are used only on the 82547. */ 309 int sc_txfifo_size; /* Tx FIFO size */ 310 int sc_txfifo_head; /* current head of FIFO */ 311 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 312 int sc_txfifo_stall; /* Tx FIFO is stalled */ 313 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 314 315 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 316 317 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 318 int sc_rxdiscard; 319 int sc_rxlen; 320 struct mbuf *sc_rxhead; 321 struct mbuf *sc_rxtail; 322 struct mbuf **sc_rxtailp; 323 324 uint32_t sc_ctrl; /* prototype CTRL register */ 325 #if 0 326 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 327 #endif 328 uint32_t sc_icr; /* prototype interrupt bits */ 329 uint32_t sc_itr; /* prototype intr throttling reg */ 330 uint32_t sc_tctl; /* prototype TCTL register */ 331 uint32_t sc_rctl; /* prototype RCTL register */ 332 uint32_t sc_txcw; /* prototype TXCW register */ 333 uint32_t sc_tipg; /* prototype TIPG register */ 334 uint32_t sc_fcrtl; /* prototype FCRTL register */ 335 uint32_t sc_pba; /* prototype PBA register */ 336 337 int sc_tbi_linkup; /* TBI link status */ 338 int sc_tbi_anstate; /* autonegotiation state */ 339 340 int sc_mchash_type; /* multicast filter offset */ 341 342 #if NRND > 0 343 rndsource_element_t rnd_source; /* random source */ 344 #endif 345 }; 346 347 #define WM_RXCHAIN_RESET(sc) \ 348 do { \ 349 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 350 *(sc)->sc_rxtailp = NULL; \ 351 (sc)->sc_rxlen = 0; \ 352 } while (/*CONSTCOND*/0) 353 354 #define WM_RXCHAIN_LINK(sc, m) \ 355 do { \ 356 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 357 (sc)->sc_rxtailp = &(m)->m_next; \ 358 } while (/*CONSTCOND*/0) 359 360 /* sc_flags */ 361 #define WM_F_HAS_MII 0x01 /* has MII */ 362 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 363 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 364 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 365 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 366 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 367 #define WM_F_CSA 0x80 /* bus is CSA */ 368 369 #ifdef WM_EVENT_COUNTERS 370 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 371 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 372 #else 373 #define WM_EVCNT_INCR(ev) /* nothing */ 374 #define WM_EVCNT_ADD(ev, val) /* nothing */ 375 #endif 376 377 #define CSR_READ(sc, reg) \ 378 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 379 #define CSR_WRITE(sc, reg, val) \ 380 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 381 #define CSR_WRITE_FLUSH(sc) \ 382 (void) CSR_READ((sc), WMREG_STATUS) 383 384 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 385 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 386 387 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 388 #define WM_CDTXADDR_HI(sc, x) \ 389 (sizeof(bus_addr_t) == 8 ? \ 390 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 391 392 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 393 #define WM_CDRXADDR_HI(sc, x) \ 394 (sizeof(bus_addr_t) == 8 ? \ 395 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 396 397 #define WM_CDTXSYNC(sc, x, n, ops) \ 398 do { \ 399 int __x, __n; \ 400 \ 401 __x = (x); \ 402 __n = (n); \ 403 \ 404 /* If it will wrap around, sync to the end of the ring. */ \ 405 if ((__x + __n) > WM_NTXDESC(sc)) { \ 406 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 407 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 408 (WM_NTXDESC(sc) - __x), (ops)); \ 409 __n -= (WM_NTXDESC(sc) - __x); \ 410 __x = 0; \ 411 } \ 412 \ 413 /* Now sync whatever is left. */ \ 414 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 415 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 416 } while (/*CONSTCOND*/0) 417 418 #define WM_CDRXSYNC(sc, x, ops) \ 419 do { \ 420 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 421 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 422 } while (/*CONSTCOND*/0) 423 424 #define WM_INIT_RXDESC(sc, x) \ 425 do { \ 426 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 427 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 428 struct mbuf *__m = __rxs->rxs_mbuf; \ 429 \ 430 /* \ 431 * Note: We scoot the packet forward 2 bytes in the buffer \ 432 * so that the payload after the Ethernet header is aligned \ 433 * to a 4-byte boundary. \ 434 * \ 435 * XXX BRAINDAMAGE ALERT! \ 436 * The stupid chip uses the same size for every buffer, which \ 437 * is set in the Receive Control register. We are using the 2K \ 438 * size option, but what we REALLY want is (2K - 2)! For this \ 439 * reason, we can't "scoot" packets longer than the standard \ 440 * Ethernet MTU. On strict-alignment platforms, if the total \ 441 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 442 * the upper layer copy the headers. \ 443 */ \ 444 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 445 \ 446 wm_set_dma_addr(&__rxd->wrx_addr, \ 447 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 448 __rxd->wrx_len = 0; \ 449 __rxd->wrx_cksum = 0; \ 450 __rxd->wrx_status = 0; \ 451 __rxd->wrx_errors = 0; \ 452 __rxd->wrx_special = 0; \ 453 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 454 \ 455 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 456 } while (/*CONSTCOND*/0) 457 458 static void wm_start(struct ifnet *); 459 static void wm_watchdog(struct ifnet *); 460 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 461 static int wm_init(struct ifnet *); 462 static void wm_stop(struct ifnet *, int); 463 464 static void wm_shutdown(void *); 465 466 static void wm_reset(struct wm_softc *); 467 static void wm_rxdrain(struct wm_softc *); 468 static int wm_add_rxbuf(struct wm_softc *, int); 469 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 470 static void wm_tick(void *); 471 472 static void wm_set_filter(struct wm_softc *); 473 474 static int wm_intr(void *); 475 static void wm_txintr(struct wm_softc *); 476 static void wm_rxintr(struct wm_softc *); 477 static void wm_linkintr(struct wm_softc *, uint32_t); 478 479 static void wm_tbi_mediainit(struct wm_softc *); 480 static int wm_tbi_mediachange(struct ifnet *); 481 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 482 483 static void wm_tbi_set_linkled(struct wm_softc *); 484 static void wm_tbi_check_link(struct wm_softc *); 485 486 static void wm_gmii_reset(struct wm_softc *); 487 488 static int wm_gmii_i82543_readreg(struct device *, int, int); 489 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 490 491 static int wm_gmii_i82544_readreg(struct device *, int, int); 492 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 493 494 static void wm_gmii_statchg(struct device *); 495 496 static void wm_gmii_mediainit(struct wm_softc *); 497 static int wm_gmii_mediachange(struct ifnet *); 498 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 499 500 static int wm_match(struct device *, struct cfdata *, void *); 501 static void wm_attach(struct device *, struct device *, void *); 502 503 CFATTACH_DECL(wm, sizeof(struct wm_softc), 504 wm_match, wm_attach, NULL, NULL); 505 506 static void wm_82547_txfifo_stall(void *); 507 508 /* 509 * Devices supported by this driver. 510 */ 511 static const struct wm_product { 512 pci_vendor_id_t wmp_vendor; 513 pci_product_id_t wmp_product; 514 const char *wmp_name; 515 wm_chip_type wmp_type; 516 int wmp_flags; 517 #define WMP_F_1000X 0x01 518 #define WMP_F_1000T 0x02 519 } wm_products[] = { 520 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 521 "Intel i82542 1000BASE-X Ethernet", 522 WM_T_82542_2_1, WMP_F_1000X }, 523 524 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 525 "Intel i82543GC 1000BASE-X Ethernet", 526 WM_T_82543, WMP_F_1000X }, 527 528 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 529 "Intel i82543GC 1000BASE-T Ethernet", 530 WM_T_82543, WMP_F_1000T }, 531 532 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 533 "Intel i82544EI 1000BASE-T Ethernet", 534 WM_T_82544, WMP_F_1000T }, 535 536 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 537 "Intel i82544EI 1000BASE-X Ethernet", 538 WM_T_82544, WMP_F_1000X }, 539 540 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 541 "Intel i82544GC 1000BASE-T Ethernet", 542 WM_T_82544, WMP_F_1000T }, 543 544 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 545 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 546 WM_T_82544, WMP_F_1000T }, 547 548 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 549 "Intel i82540EM 1000BASE-T Ethernet", 550 WM_T_82540, WMP_F_1000T }, 551 552 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 553 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 554 WM_T_82540, WMP_F_1000T }, 555 556 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 557 "Intel i82540EP 1000BASE-T Ethernet", 558 WM_T_82540, WMP_F_1000T }, 559 560 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 561 "Intel i82540EP 1000BASE-T Ethernet", 562 WM_T_82540, WMP_F_1000T }, 563 564 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 565 "Intel i82540EP 1000BASE-T Ethernet", 566 WM_T_82540, WMP_F_1000T }, 567 568 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 569 "Intel i82545EM 1000BASE-T Ethernet", 570 WM_T_82545, WMP_F_1000T }, 571 572 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 573 "Intel i82545GM 1000BASE-T Ethernet", 574 WM_T_82545_3, WMP_F_1000T }, 575 576 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 577 "Intel i82545GM 1000BASE-X Ethernet", 578 WM_T_82545_3, WMP_F_1000X }, 579 #if 0 580 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 581 "Intel i82545GM Gigabit Ethernet (SERDES)", 582 WM_T_82545_3, WMP_F_SERDES }, 583 #endif 584 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 585 "Intel i82546EB 1000BASE-T Ethernet", 586 WM_T_82546, WMP_F_1000T }, 587 588 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 589 "Intel i82546EB 1000BASE-T Ethernet", 590 WM_T_82546, WMP_F_1000T }, 591 592 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 593 "Intel i82545EM 1000BASE-X Ethernet", 594 WM_T_82545, WMP_F_1000X }, 595 596 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 597 "Intel i82546EB 1000BASE-X Ethernet", 598 WM_T_82546, WMP_F_1000X }, 599 600 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 601 "Intel i82546GB 1000BASE-T Ethernet", 602 WM_T_82546_3, WMP_F_1000T }, 603 604 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 605 "Intel i82546GB 1000BASE-X Ethernet", 606 WM_T_82546_3, WMP_F_1000X }, 607 #if 0 608 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 609 "Intel i82546GB Gigabit Ethernet (SERDES)", 610 WM_T_82546_3, WMP_F_SERDES }, 611 #endif 612 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 613 "Intel i82541EI 1000BASE-T Ethernet", 614 WM_T_82541, WMP_F_1000T }, 615 616 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 617 "Intel i82541EI Mobile 1000BASE-T Ethernet", 618 WM_T_82541, WMP_F_1000T }, 619 620 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 621 "Intel i82541ER 1000BASE-T Ethernet", 622 WM_T_82541_2, WMP_F_1000T }, 623 624 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 625 "Intel i82541GI 1000BASE-T Ethernet", 626 WM_T_82541_2, WMP_F_1000T }, 627 628 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 629 "Intel i82541GI Mobile 1000BASE-T Ethernet", 630 WM_T_82541_2, WMP_F_1000T }, 631 632 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 633 "Intel i82547EI 1000BASE-T Ethernet", 634 WM_T_82547, WMP_F_1000T }, 635 636 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 637 "Intel i82547GI 1000BASE-T Ethernet", 638 WM_T_82547_2, WMP_F_1000T }, 639 { 0, 0, 640 NULL, 641 0, 0 }, 642 }; 643 644 #ifdef WM_EVENT_COUNTERS 645 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 646 #endif /* WM_EVENT_COUNTERS */ 647 648 #if 0 /* Not currently used */ 649 static __inline uint32_t 650 wm_io_read(struct wm_softc *sc, int reg) 651 { 652 653 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 654 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 655 } 656 #endif 657 658 static __inline void 659 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 660 { 661 662 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 663 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 664 } 665 666 static __inline void 667 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 668 { 669 wa->wa_low = htole32(v & 0xffffffffU); 670 if (sizeof(bus_addr_t) == 8) 671 wa->wa_high = htole32((uint64_t) v >> 32); 672 else 673 wa->wa_high = 0; 674 } 675 676 static const struct wm_product * 677 wm_lookup(const struct pci_attach_args *pa) 678 { 679 const struct wm_product *wmp; 680 681 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 682 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 683 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 684 return (wmp); 685 } 686 return (NULL); 687 } 688 689 static int 690 wm_match(struct device *parent, struct cfdata *cf, void *aux) 691 { 692 struct pci_attach_args *pa = aux; 693 694 if (wm_lookup(pa) != NULL) 695 return (1); 696 697 return (0); 698 } 699 700 static void 701 wm_attach(struct device *parent, struct device *self, void *aux) 702 { 703 struct wm_softc *sc = (void *) self; 704 struct pci_attach_args *pa = aux; 705 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 706 pci_chipset_tag_t pc = pa->pa_pc; 707 pci_intr_handle_t ih; 708 size_t cdata_size; 709 const char *intrstr = NULL; 710 const char *eetype; 711 bus_space_tag_t memt; 712 bus_space_handle_t memh; 713 bus_dma_segment_t seg; 714 int memh_valid; 715 int i, rseg, error; 716 const struct wm_product *wmp; 717 uint8_t enaddr[ETHER_ADDR_LEN]; 718 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 719 pcireg_t preg, memtype; 720 uint32_t reg; 721 int pmreg; 722 723 callout_init(&sc->sc_tick_ch); 724 725 wmp = wm_lookup(pa); 726 if (wmp == NULL) { 727 printf("\n"); 728 panic("wm_attach: impossible"); 729 } 730 731 if (pci_dma64_available(pa)) 732 sc->sc_dmat = pa->pa_dmat64; 733 else 734 sc->sc_dmat = pa->pa_dmat; 735 736 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 737 aprint_naive(": Ethernet controller\n"); 738 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 739 740 sc->sc_type = wmp->wmp_type; 741 if (sc->sc_type < WM_T_82543) { 742 if (preg < 2) { 743 aprint_error("%s: i82542 must be at least rev. 2\n", 744 sc->sc_dev.dv_xname); 745 return; 746 } 747 if (preg < 3) 748 sc->sc_type = WM_T_82542_2_0; 749 } 750 751 /* 752 * Map the device. All devices support memory-mapped acccess, 753 * and it is really required for normal operation. 754 */ 755 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 756 switch (memtype) { 757 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 758 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 759 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 760 memtype, 0, &memt, &memh, NULL, NULL) == 0); 761 break; 762 default: 763 memh_valid = 0; 764 } 765 766 if (memh_valid) { 767 sc->sc_st = memt; 768 sc->sc_sh = memh; 769 } else { 770 aprint_error("%s: unable to map device registers\n", 771 sc->sc_dev.dv_xname); 772 return; 773 } 774 775 /* 776 * In addition, i82544 and later support I/O mapped indirect 777 * register access. It is not desirable (nor supported in 778 * this driver) to use it for normal operation, though it is 779 * required to work around bugs in some chip versions. 780 */ 781 if (sc->sc_type >= WM_T_82544) { 782 /* First we have to find the I/O BAR. */ 783 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 784 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 785 PCI_MAPREG_TYPE_IO) 786 break; 787 } 788 if (i == PCI_MAPREG_END) 789 aprint_error("%s: WARNING: unable to find I/O BAR\n", 790 sc->sc_dev.dv_xname); 791 else { 792 /* 793 * The i8254x doesn't apparently respond when the 794 * I/O BAR is 0, which looks somewhat like it's not 795 * been configured. 796 */ 797 preg = pci_conf_read(pc, pa->pa_tag, i); 798 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 799 aprint_error("%s: WARNING: I/O BAR at zero.\n", 800 sc->sc_dev.dv_xname); 801 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 802 0, &sc->sc_iot, &sc->sc_ioh, 803 NULL, NULL) == 0) { 804 sc->sc_flags |= WM_F_IOH_VALID; 805 } else { 806 aprint_error("%s: WARNING: unable to map " 807 "I/O space\n", sc->sc_dev.dv_xname); 808 } 809 } 810 811 } 812 813 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 814 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 815 preg |= PCI_COMMAND_MASTER_ENABLE; 816 if (sc->sc_type < WM_T_82542_2_1) 817 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 818 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 819 820 /* Get it out of power save mode, if needed. */ 821 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 822 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 823 PCI_PMCSR_STATE_MASK; 824 if (preg == PCI_PMCSR_STATE_D3) { 825 /* 826 * The card has lost all configuration data in 827 * this state, so punt. 828 */ 829 aprint_error("%s: unable to wake from power state D3\n", 830 sc->sc_dev.dv_xname); 831 return; 832 } 833 if (preg != PCI_PMCSR_STATE_D0) { 834 aprint_normal("%s: waking up from power state D%d\n", 835 sc->sc_dev.dv_xname, preg); 836 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 837 PCI_PMCSR_STATE_D0); 838 } 839 } 840 841 /* 842 * Map and establish our interrupt. 843 */ 844 if (pci_intr_map(pa, &ih)) { 845 aprint_error("%s: unable to map interrupt\n", 846 sc->sc_dev.dv_xname); 847 return; 848 } 849 intrstr = pci_intr_string(pc, ih); 850 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 851 if (sc->sc_ih == NULL) { 852 aprint_error("%s: unable to establish interrupt", 853 sc->sc_dev.dv_xname); 854 if (intrstr != NULL) 855 aprint_normal(" at %s", intrstr); 856 aprint_normal("\n"); 857 return; 858 } 859 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 860 861 /* 862 * Determine a few things about the bus we're connected to. 863 */ 864 if (sc->sc_type < WM_T_82543) { 865 /* We don't really know the bus characteristics here. */ 866 sc->sc_bus_speed = 33; 867 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 868 /* 869 * CSA (Communication Streaming Architecture) is about as fast 870 * a 32-bit 66MHz PCI Bus. 871 */ 872 sc->sc_flags |= WM_F_CSA; 873 sc->sc_bus_speed = 66; 874 aprint_verbose("%s: Communication Streaming Architecture\n", 875 sc->sc_dev.dv_xname); 876 if (sc->sc_type == WM_T_82547) { 877 callout_init(&sc->sc_txfifo_ch); 878 callout_setfunc(&sc->sc_txfifo_ch, 879 wm_82547_txfifo_stall, sc); 880 aprint_verbose("%s: using 82547 Tx FIFO stall " 881 "work-around\n", sc->sc_dev.dv_xname); 882 } 883 } else { 884 reg = CSR_READ(sc, WMREG_STATUS); 885 if (reg & STATUS_BUS64) 886 sc->sc_flags |= WM_F_BUS64; 887 if (sc->sc_type >= WM_T_82544 && 888 (reg & STATUS_PCIX_MODE) != 0) { 889 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 890 891 sc->sc_flags |= WM_F_PCIX; 892 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 893 PCI_CAP_PCIX, 894 &sc->sc_pcix_offset, NULL) == 0) 895 aprint_error("%s: unable to find PCIX " 896 "capability\n", sc->sc_dev.dv_xname); 897 else if (sc->sc_type != WM_T_82545_3 && 898 sc->sc_type != WM_T_82546_3) { 899 /* 900 * Work around a problem caused by the BIOS 901 * setting the max memory read byte count 902 * incorrectly. 903 */ 904 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 905 sc->sc_pcix_offset + PCI_PCIX_CMD); 906 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 907 sc->sc_pcix_offset + PCI_PCIX_STATUS); 908 909 bytecnt = 910 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 911 PCI_PCIX_CMD_BYTECNT_SHIFT; 912 maxb = 913 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 914 PCI_PCIX_STATUS_MAXB_SHIFT; 915 if (bytecnt > maxb) { 916 aprint_verbose("%s: resetting PCI-X " 917 "MMRBC: %d -> %d\n", 918 sc->sc_dev.dv_xname, 919 512 << bytecnt, 512 << maxb); 920 pcix_cmd = (pcix_cmd & 921 ~PCI_PCIX_CMD_BYTECNT_MASK) | 922 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 923 pci_conf_write(pa->pa_pc, pa->pa_tag, 924 sc->sc_pcix_offset + PCI_PCIX_CMD, 925 pcix_cmd); 926 } 927 } 928 } 929 /* 930 * The quad port adapter is special; it has a PCIX-PCIX 931 * bridge on the board, and can run the secondary bus at 932 * a higher speed. 933 */ 934 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 935 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 936 : 66; 937 } else if (sc->sc_flags & WM_F_PCIX) { 938 switch (reg & STATUS_PCIXSPD_MASK) { 939 case STATUS_PCIXSPD_50_66: 940 sc->sc_bus_speed = 66; 941 break; 942 case STATUS_PCIXSPD_66_100: 943 sc->sc_bus_speed = 100; 944 break; 945 case STATUS_PCIXSPD_100_133: 946 sc->sc_bus_speed = 133; 947 break; 948 default: 949 aprint_error( 950 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 951 sc->sc_dev.dv_xname, 952 reg & STATUS_PCIXSPD_MASK); 953 sc->sc_bus_speed = 66; 954 } 955 } else 956 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 957 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 958 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 959 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 960 } 961 962 /* 963 * Allocate the control data structures, and create and load the 964 * DMA map for it. 965 * 966 * NOTE: All Tx descriptors must be in the same 4G segment of 967 * memory. So must Rx descriptors. We simplify by allocating 968 * both sets within the same 4G segment. 969 */ 970 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 971 WM_NTXDESC_82542 : WM_NTXDESC_82544; 972 cdata_size = sc->sc_type < WM_T_82544 ? 973 sizeof(struct wm_control_data_82542) : 974 sizeof(struct wm_control_data_82544); 975 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 976 (bus_size_t) 0x100000000ULL, 977 &seg, 1, &rseg, 0)) != 0) { 978 aprint_error( 979 "%s: unable to allocate control data, error = %d\n", 980 sc->sc_dev.dv_xname, error); 981 goto fail_0; 982 } 983 984 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 985 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 986 aprint_error("%s: unable to map control data, error = %d\n", 987 sc->sc_dev.dv_xname, error); 988 goto fail_1; 989 } 990 991 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 992 0, 0, &sc->sc_cddmamap)) != 0) { 993 aprint_error("%s: unable to create control data DMA map, " 994 "error = %d\n", sc->sc_dev.dv_xname, error); 995 goto fail_2; 996 } 997 998 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 999 sc->sc_control_data, cdata_size, NULL, 1000 0)) != 0) { 1001 aprint_error( 1002 "%s: unable to load control data DMA map, error = %d\n", 1003 sc->sc_dev.dv_xname, error); 1004 goto fail_3; 1005 } 1006 1007 1008 /* 1009 * Create the transmit buffer DMA maps. 1010 */ 1011 WM_TXQUEUELEN(sc) = 1012 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1013 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1014 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1015 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1016 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1017 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1018 aprint_error("%s: unable to create Tx DMA map %d, " 1019 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1020 goto fail_4; 1021 } 1022 } 1023 1024 /* 1025 * Create the receive buffer DMA maps. 1026 */ 1027 for (i = 0; i < WM_NRXDESC; i++) { 1028 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1029 MCLBYTES, 0, 0, 1030 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1031 aprint_error("%s: unable to create Rx DMA map %d, " 1032 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1033 goto fail_5; 1034 } 1035 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1036 } 1037 1038 /* 1039 * Reset the chip to a known state. 1040 */ 1041 wm_reset(sc); 1042 1043 /* 1044 * Get some information about the EEPROM. 1045 */ 1046 if (sc->sc_type >= WM_T_82540) 1047 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1048 if (sc->sc_type <= WM_T_82544) 1049 sc->sc_ee_addrbits = 6; 1050 else if (sc->sc_type <= WM_T_82546_3) { 1051 reg = CSR_READ(sc, WMREG_EECD); 1052 if (reg & EECD_EE_SIZE) 1053 sc->sc_ee_addrbits = 8; 1054 else 1055 sc->sc_ee_addrbits = 6; 1056 } else if (sc->sc_type <= WM_T_82547_2) { 1057 reg = CSR_READ(sc, WMREG_EECD); 1058 if (reg & EECD_EE_TYPE) { 1059 sc->sc_flags |= WM_F_EEPROM_SPI; 1060 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1061 } else 1062 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1063 } else { 1064 /* Assume everything else is SPI. */ 1065 reg = CSR_READ(sc, WMREG_EECD); 1066 sc->sc_flags |= WM_F_EEPROM_SPI; 1067 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1068 } 1069 if (sc->sc_flags & WM_F_EEPROM_SPI) 1070 eetype = "SPI"; 1071 else 1072 eetype = "MicroWire"; 1073 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1074 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1075 sc->sc_ee_addrbits, eetype); 1076 1077 /* 1078 * Read the Ethernet address from the EEPROM. 1079 */ 1080 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1081 sizeof(myea) / sizeof(myea[0]), myea)) { 1082 aprint_error("%s: unable to read Ethernet address\n", 1083 sc->sc_dev.dv_xname); 1084 return; 1085 } 1086 enaddr[0] = myea[0] & 0xff; 1087 enaddr[1] = myea[0] >> 8; 1088 enaddr[2] = myea[1] & 0xff; 1089 enaddr[3] = myea[1] >> 8; 1090 enaddr[4] = myea[2] & 0xff; 1091 enaddr[5] = myea[2] >> 8; 1092 1093 /* 1094 * Toggle the LSB of the MAC address on the second port 1095 * of the i82546. 1096 */ 1097 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1098 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1099 enaddr[5] ^= 1; 1100 } 1101 1102 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1103 ether_sprintf(enaddr)); 1104 1105 /* 1106 * Read the config info from the EEPROM, and set up various 1107 * bits in the control registers based on their contents. 1108 */ 1109 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1110 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1111 sc->sc_dev.dv_xname); 1112 return; 1113 } 1114 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1115 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1116 sc->sc_dev.dv_xname); 1117 return; 1118 } 1119 if (sc->sc_type >= WM_T_82544) { 1120 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1121 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1122 sc->sc_dev.dv_xname); 1123 return; 1124 } 1125 } 1126 1127 if (cfg1 & EEPROM_CFG1_ILOS) 1128 sc->sc_ctrl |= CTRL_ILOS; 1129 if (sc->sc_type >= WM_T_82544) { 1130 sc->sc_ctrl |= 1131 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1132 CTRL_SWDPIO_SHIFT; 1133 sc->sc_ctrl |= 1134 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1135 CTRL_SWDPINS_SHIFT; 1136 } else { 1137 sc->sc_ctrl |= 1138 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1139 CTRL_SWDPIO_SHIFT; 1140 } 1141 1142 #if 0 1143 if (sc->sc_type >= WM_T_82544) { 1144 if (cfg1 & EEPROM_CFG1_IPS0) 1145 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1146 if (cfg1 & EEPROM_CFG1_IPS1) 1147 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1148 sc->sc_ctrl_ext |= 1149 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1150 CTRL_EXT_SWDPIO_SHIFT; 1151 sc->sc_ctrl_ext |= 1152 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1153 CTRL_EXT_SWDPINS_SHIFT; 1154 } else { 1155 sc->sc_ctrl_ext |= 1156 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1157 CTRL_EXT_SWDPIO_SHIFT; 1158 } 1159 #endif 1160 1161 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1162 #if 0 1163 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1164 #endif 1165 1166 /* 1167 * Set up some register offsets that are different between 1168 * the i82542 and the i82543 and later chips. 1169 */ 1170 if (sc->sc_type < WM_T_82543) { 1171 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1172 sc->sc_tdt_reg = WMREG_OLD_TDT; 1173 } else { 1174 sc->sc_rdt_reg = WMREG_RDT; 1175 sc->sc_tdt_reg = WMREG_TDT; 1176 } 1177 1178 /* 1179 * Determine if we're TBI or GMII mode, and initialize the 1180 * media structures accordingly. 1181 */ 1182 if (sc->sc_type < WM_T_82543 || 1183 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1184 if (wmp->wmp_flags & WMP_F_1000T) 1185 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1186 "product!\n", sc->sc_dev.dv_xname); 1187 wm_tbi_mediainit(sc); 1188 } else { 1189 if (wmp->wmp_flags & WMP_F_1000X) 1190 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1191 "product!\n", sc->sc_dev.dv_xname); 1192 wm_gmii_mediainit(sc); 1193 } 1194 1195 ifp = &sc->sc_ethercom.ec_if; 1196 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1197 ifp->if_softc = sc; 1198 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1199 ifp->if_ioctl = wm_ioctl; 1200 ifp->if_start = wm_start; 1201 ifp->if_watchdog = wm_watchdog; 1202 ifp->if_init = wm_init; 1203 ifp->if_stop = wm_stop; 1204 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1205 IFQ_SET_READY(&ifp->if_snd); 1206 1207 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1208 1209 /* 1210 * If we're a i82543 or greater, we can support VLANs. 1211 */ 1212 if (sc->sc_type >= WM_T_82543) 1213 sc->sc_ethercom.ec_capabilities |= 1214 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1215 1216 /* 1217 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1218 * on i82543 and later. 1219 */ 1220 if (sc->sc_type >= WM_T_82543) 1221 ifp->if_capabilities |= 1222 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1223 1224 /* 1225 * Attach the interface. 1226 */ 1227 if_attach(ifp); 1228 ether_ifattach(ifp, enaddr); 1229 #if NRND > 0 1230 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1231 RND_TYPE_NET, 0); 1232 #endif 1233 1234 #ifdef WM_EVENT_COUNTERS 1235 /* Attach event counters. */ 1236 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1237 NULL, sc->sc_dev.dv_xname, "txsstall"); 1238 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1239 NULL, sc->sc_dev.dv_xname, "txdstall"); 1240 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1241 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1242 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1243 NULL, sc->sc_dev.dv_xname, "txdw"); 1244 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1245 NULL, sc->sc_dev.dv_xname, "txqe"); 1246 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1247 NULL, sc->sc_dev.dv_xname, "rxintr"); 1248 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1249 NULL, sc->sc_dev.dv_xname, "linkintr"); 1250 1251 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1252 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1253 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1254 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1255 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1256 NULL, sc->sc_dev.dv_xname, "txipsum"); 1257 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1258 NULL, sc->sc_dev.dv_xname, "txtusum"); 1259 1260 evcnt_attach_dynamic(&sc->sc_ev_txpullup_needed, EVCNT_TYPE_MISC, 1261 NULL, sc->sc_dev.dv_xname, "txpullup needed"); 1262 evcnt_attach_dynamic(&sc->sc_ev_txpullup_nomem, EVCNT_TYPE_MISC, 1263 NULL, sc->sc_dev.dv_xname, "txpullup nomem"); 1264 evcnt_attach_dynamic(&sc->sc_ev_txpullup_fail, EVCNT_TYPE_MISC, 1265 NULL, sc->sc_dev.dv_xname, "txpullup fail"); 1266 1267 for (i = 0; i < WM_NTXSEGS; i++) { 1268 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1269 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1270 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1271 } 1272 1273 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1274 NULL, sc->sc_dev.dv_xname, "txdrop"); 1275 1276 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1277 NULL, sc->sc_dev.dv_xname, "tu"); 1278 1279 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1280 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1281 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1282 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1283 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1284 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1285 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1286 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1287 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1288 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1289 #endif /* WM_EVENT_COUNTERS */ 1290 1291 /* 1292 * Make sure the interface is shutdown during reboot. 1293 */ 1294 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1295 if (sc->sc_sdhook == NULL) 1296 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1297 sc->sc_dev.dv_xname); 1298 return; 1299 1300 /* 1301 * Free any resources we've allocated during the failed attach 1302 * attempt. Do this in reverse order and fall through. 1303 */ 1304 fail_5: 1305 for (i = 0; i < WM_NRXDESC; i++) { 1306 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1307 bus_dmamap_destroy(sc->sc_dmat, 1308 sc->sc_rxsoft[i].rxs_dmamap); 1309 } 1310 fail_4: 1311 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1312 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1313 bus_dmamap_destroy(sc->sc_dmat, 1314 sc->sc_txsoft[i].txs_dmamap); 1315 } 1316 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1317 fail_3: 1318 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1319 fail_2: 1320 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1321 cdata_size); 1322 fail_1: 1323 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1324 fail_0: 1325 return; 1326 } 1327 1328 /* 1329 * wm_shutdown: 1330 * 1331 * Make sure the interface is stopped at reboot time. 1332 */ 1333 static void 1334 wm_shutdown(void *arg) 1335 { 1336 struct wm_softc *sc = arg; 1337 1338 wm_stop(&sc->sc_ethercom.ec_if, 1); 1339 } 1340 1341 /* 1342 * wm_tx_offload: 1343 * 1344 * Set up TCP/IP checksumming parameters for the 1345 * specified packet. 1346 */ 1347 static int 1348 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1349 uint8_t *fieldsp) 1350 { 1351 struct mbuf *m0 = txs->txs_mbuf; 1352 struct livengood_tcpip_ctxdesc *t; 1353 uint32_t ipcs, tucs; 1354 struct ether_header *eh; 1355 int offset, iphl; 1356 uint8_t fields = 0; 1357 1358 /* 1359 * XXX It would be nice if the mbuf pkthdr had offset 1360 * fields for the protocol headers. 1361 */ 1362 1363 eh = mtod(m0, struct ether_header *); 1364 switch (htons(eh->ether_type)) { 1365 case ETHERTYPE_IP: 1366 offset = ETHER_HDR_LEN; 1367 break; 1368 1369 case ETHERTYPE_VLAN: 1370 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1371 break; 1372 1373 default: 1374 /* 1375 * Don't support this protocol or encapsulation. 1376 */ 1377 *fieldsp = 0; 1378 *cmdp = 0; 1379 return (0); 1380 } 1381 1382 iphl = m0->m_pkthdr.csum_data >> 16; 1383 1384 /* 1385 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1386 * offload feature, if we load the context descriptor, we 1387 * MUST provide valid values for IPCSS and TUCSS fields. 1388 */ 1389 1390 ipcs = WTX_TCPIP_IPCSS(offset) | 1391 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1392 WTX_TCPIP_IPCSE(offset + iphl - 1); 1393 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1394 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1395 fields |= WTX_IXSM; 1396 } 1397 1398 offset += iphl; 1399 1400 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1401 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1402 fields |= WTX_TXSM; 1403 tucs = WTX_TCPIP_TUCSS(offset) | 1404 WTX_TCPIP_TUCSO(offset + (m0->m_pkthdr.csum_data & 0xffff)) | 1405 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1406 } else { 1407 /* Just initialize it to a valid TCP context. */ 1408 tucs = WTX_TCPIP_TUCSS(offset) | 1409 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1410 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1411 } 1412 1413 /* Fill in the context descriptor. */ 1414 t = (struct livengood_tcpip_ctxdesc *) 1415 &sc->sc_txdescs[sc->sc_txnext]; 1416 t->tcpip_ipcs = htole32(ipcs); 1417 t->tcpip_tucs = htole32(tucs); 1418 t->tcpip_cmdlen = htole32(WTX_CMD_DEXT | WTX_DTYP_C); 1419 t->tcpip_seg = 0; 1420 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1421 1422 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1423 txs->txs_ndesc++; 1424 1425 *cmdp = WTX_CMD_DEXT | WTX_DTYP_D; 1426 *fieldsp = fields; 1427 1428 return (0); 1429 } 1430 1431 static void 1432 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1433 { 1434 struct mbuf *m; 1435 int i; 1436 1437 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1438 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1439 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1440 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1441 m->m_data, m->m_len, m->m_flags); 1442 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1443 i, i == 1 ? "" : "s"); 1444 } 1445 1446 /* 1447 * wm_82547_txfifo_stall: 1448 * 1449 * Callout used to wait for the 82547 Tx FIFO to drain, 1450 * reset the FIFO pointers, and restart packet transmission. 1451 */ 1452 static void 1453 wm_82547_txfifo_stall(void *arg) 1454 { 1455 struct wm_softc *sc = arg; 1456 int s; 1457 1458 s = splnet(); 1459 1460 if (sc->sc_txfifo_stall) { 1461 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1462 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1463 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1464 /* 1465 * Packets have drained. Stop transmitter, reset 1466 * FIFO pointers, restart transmitter, and kick 1467 * the packet queue. 1468 */ 1469 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1470 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1471 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1472 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1473 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1474 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1475 CSR_WRITE(sc, WMREG_TCTL, tctl); 1476 CSR_WRITE_FLUSH(sc); 1477 1478 sc->sc_txfifo_head = 0; 1479 sc->sc_txfifo_stall = 0; 1480 wm_start(&sc->sc_ethercom.ec_if); 1481 } else { 1482 /* 1483 * Still waiting for packets to drain; try again in 1484 * another tick. 1485 */ 1486 callout_schedule(&sc->sc_txfifo_ch, 1); 1487 } 1488 } 1489 1490 splx(s); 1491 } 1492 1493 /* 1494 * wm_82547_txfifo_bugchk: 1495 * 1496 * Check for bug condition in the 82547 Tx FIFO. We need to 1497 * prevent enqueueing a packet that would wrap around the end 1498 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1499 * 1500 * We do this by checking the amount of space before the end 1501 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1502 * the Tx FIFO, wait for all remaining packets to drain, reset 1503 * the internal FIFO pointers to the beginning, and restart 1504 * transmission on the interface. 1505 */ 1506 #define WM_FIFO_HDR 0x10 1507 #define WM_82547_PAD_LEN 0x3e0 1508 static int 1509 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1510 { 1511 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1512 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1513 1514 /* Just return if already stalled. */ 1515 if (sc->sc_txfifo_stall) 1516 return (1); 1517 1518 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1519 /* Stall only occurs in half-duplex mode. */ 1520 goto send_packet; 1521 } 1522 1523 if (len >= WM_82547_PAD_LEN + space) { 1524 sc->sc_txfifo_stall = 1; 1525 callout_schedule(&sc->sc_txfifo_ch, 1); 1526 return (1); 1527 } 1528 1529 send_packet: 1530 sc->sc_txfifo_head += len; 1531 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1532 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1533 1534 return (0); 1535 } 1536 1537 /* 1538 * wm_start: [ifnet interface function] 1539 * 1540 * Start packet transmission on the interface. 1541 */ 1542 static void 1543 wm_start(struct ifnet *ifp) 1544 { 1545 struct wm_softc *sc = ifp->if_softc; 1546 struct mbuf *m0; 1547 #if 0 /* XXXJRT */ 1548 struct m_tag *mtag; 1549 #endif 1550 struct wm_txsoft *txs; 1551 bus_dmamap_t dmamap; 1552 int error, nexttx, lasttx = -1, ofree, seg, segs_needed; 1553 bus_addr_t curaddr; 1554 bus_size_t seglen, curlen; 1555 uint32_t cksumcmd; 1556 uint8_t cksumfields; 1557 1558 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1559 return; 1560 1561 /* 1562 * Remember the previous number of free descriptors. 1563 */ 1564 ofree = sc->sc_txfree; 1565 1566 /* 1567 * Loop through the send queue, setting up transmit descriptors 1568 * until we drain the queue, or use up all available transmit 1569 * descriptors. 1570 */ 1571 for (;;) { 1572 /* Grab a packet off the queue. */ 1573 IFQ_POLL(&ifp->if_snd, m0); 1574 if (m0 == NULL) 1575 break; 1576 1577 DPRINTF(WM_DEBUG_TX, 1578 ("%s: TX: have packet to transmit: %p\n", 1579 sc->sc_dev.dv_xname, m0)); 1580 1581 /* Get a work queue entry. */ 1582 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1583 wm_txintr(sc); 1584 if (sc->sc_txsfree == 0) { 1585 DPRINTF(WM_DEBUG_TX, 1586 ("%s: TX: no free job descriptors\n", 1587 sc->sc_dev.dv_xname)); 1588 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1589 break; 1590 } 1591 } 1592 1593 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1594 dmamap = txs->txs_dmamap; 1595 1596 /* 1597 * Load the DMA map. If this fails, the packet either 1598 * didn't fit in the allotted number of segments, or we 1599 * were short on resources. For the too-many-segments 1600 * case, we simply report an error and drop the packet, 1601 * since we can't sanely copy a jumbo packet to a single 1602 * buffer. 1603 */ 1604 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1605 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1606 if (error) { 1607 if (error == EFBIG) { 1608 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1609 log(LOG_ERR, "%s: Tx packet consumes too many " 1610 "DMA segments, dropping...\n", 1611 sc->sc_dev.dv_xname); 1612 IFQ_DEQUEUE(&ifp->if_snd, m0); 1613 wm_dump_mbuf_chain(sc, m0); 1614 m_freem(m0); 1615 continue; 1616 } 1617 /* 1618 * Short on resources, just stop for now. 1619 */ 1620 DPRINTF(WM_DEBUG_TX, 1621 ("%s: TX: dmamap load failed: %d\n", 1622 sc->sc_dev.dv_xname, error)); 1623 break; 1624 } 1625 1626 segs_needed = dmamap->dm_nsegs; 1627 1628 /* 1629 * Ensure we have enough descriptors free to describe 1630 * the packet. Note, we always reserve one descriptor 1631 * at the end of the ring due to the semantics of the 1632 * TDT register, plus one more in the event we need 1633 * to load offload context. 1634 */ 1635 if (segs_needed > sc->sc_txfree - 2) { 1636 /* 1637 * Not enough free descriptors to transmit this 1638 * packet. We haven't committed anything yet, 1639 * so just unload the DMA map, put the packet 1640 * pack on the queue, and punt. Notify the upper 1641 * layer that there are no more slots left. 1642 */ 1643 DPRINTF(WM_DEBUG_TX, 1644 ("%s: TX: need %d (%) descriptors, have %d\n", 1645 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1646 sc->sc_txfree - 1)); 1647 ifp->if_flags |= IFF_OACTIVE; 1648 bus_dmamap_unload(sc->sc_dmat, dmamap); 1649 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1650 break; 1651 } 1652 1653 /* 1654 * Check for 82547 Tx FIFO bug. We need to do this 1655 * once we know we can transmit the packet, since we 1656 * do some internal FIFO space accounting here. 1657 */ 1658 if (sc->sc_type == WM_T_82547 && 1659 wm_82547_txfifo_bugchk(sc, m0)) { 1660 DPRINTF(WM_DEBUG_TX, 1661 ("%s: TX: 82547 Tx FIFO bug detected\n", 1662 sc->sc_dev.dv_xname)); 1663 ifp->if_flags |= IFF_OACTIVE; 1664 bus_dmamap_unload(sc->sc_dmat, dmamap); 1665 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1666 break; 1667 } 1668 1669 IFQ_DEQUEUE(&ifp->if_snd, m0); 1670 1671 /* 1672 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1673 */ 1674 1675 DPRINTF(WM_DEBUG_TX, 1676 ("%s: TX: packet has %d (%d) DMA segments\n", 1677 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1678 1679 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1680 1681 /* 1682 * Store a pointer to the packet so that we can free it 1683 * later. 1684 * 1685 * Initially, we consider the number of descriptors the 1686 * packet uses the number of DMA segments. This may be 1687 * incremented by 1 if we do checksum offload (a descriptor 1688 * is used to set the checksum context). 1689 */ 1690 txs->txs_mbuf = m0; 1691 txs->txs_firstdesc = sc->sc_txnext; 1692 txs->txs_ndesc = segs_needed; 1693 1694 /* Set up offload parameters for this packet. */ 1695 if (m0->m_pkthdr.csum_flags & 1696 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1697 if (wm_tx_offload(sc, txs, &cksumcmd, 1698 &cksumfields) != 0) { 1699 /* Error message already displayed. */ 1700 bus_dmamap_unload(sc->sc_dmat, dmamap); 1701 continue; 1702 } 1703 } else { 1704 cksumcmd = 0; 1705 cksumfields = 0; 1706 } 1707 1708 cksumcmd |= WTX_CMD_IDE; 1709 1710 /* Sync the DMA map. */ 1711 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1712 BUS_DMASYNC_PREWRITE); 1713 1714 /* 1715 * Initialize the transmit descriptor. 1716 */ 1717 for (nexttx = sc->sc_txnext, seg = 0; 1718 seg < dmamap->dm_nsegs; seg++) { 1719 for (seglen = dmamap->dm_segs[seg].ds_len, 1720 curaddr = dmamap->dm_segs[seg].ds_addr; 1721 seglen != 0; 1722 curaddr += curlen, seglen -= curlen, 1723 nexttx = WM_NEXTTX(sc, nexttx)) { 1724 curlen = seglen; 1725 1726 wm_set_dma_addr( 1727 &sc->sc_txdescs[nexttx].wtx_addr, 1728 curaddr); 1729 sc->sc_txdescs[nexttx].wtx_cmdlen = 1730 htole32(cksumcmd | curlen); 1731 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1732 0; 1733 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1734 cksumfields; 1735 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1736 lasttx = nexttx; 1737 1738 DPRINTF(WM_DEBUG_TX, 1739 ("%s: TX: desc %d: low 0x%08x, " 1740 "len 0x%04x\n", 1741 sc->sc_dev.dv_xname, nexttx, 1742 curaddr & 0xffffffffU, curlen, curlen)); 1743 } 1744 } 1745 1746 KASSERT(lasttx != -1); 1747 1748 /* 1749 * Set up the command byte on the last descriptor of 1750 * the packet. If we're in the interrupt delay window, 1751 * delay the interrupt. 1752 */ 1753 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1754 htole32(WTX_CMD_EOP | WTX_CMD_IFCS | WTX_CMD_RS); 1755 1756 #if 0 /* XXXJRT */ 1757 /* 1758 * If VLANs are enabled and the packet has a VLAN tag, set 1759 * up the descriptor to encapsulate the packet for us. 1760 * 1761 * This is only valid on the last descriptor of the packet. 1762 */ 1763 if (sc->sc_ethercom.ec_nvlans != 0 && 1764 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1765 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1766 htole32(WTX_CMD_VLE); 1767 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1768 = htole16(*(u_int *)(mtag + 1) & 0xffff); 1769 } 1770 #endif /* XXXJRT */ 1771 1772 txs->txs_lastdesc = lasttx; 1773 1774 DPRINTF(WM_DEBUG_TX, 1775 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1776 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1777 1778 /* Sync the descriptors we're using. */ 1779 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1780 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1781 1782 /* Give the packet to the chip. */ 1783 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1784 1785 DPRINTF(WM_DEBUG_TX, 1786 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1787 1788 DPRINTF(WM_DEBUG_TX, 1789 ("%s: TX: finished transmitting packet, job %d\n", 1790 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1791 1792 /* Advance the tx pointer. */ 1793 sc->sc_txfree -= txs->txs_ndesc; 1794 sc->sc_txnext = nexttx; 1795 1796 sc->sc_txsfree--; 1797 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1798 1799 #if NBPFILTER > 0 1800 /* Pass the packet to any BPF listeners. */ 1801 if (ifp->if_bpf) 1802 bpf_mtap(ifp->if_bpf, m0); 1803 #endif /* NBPFILTER > 0 */ 1804 } 1805 1806 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1807 /* No more slots; notify upper layer. */ 1808 ifp->if_flags |= IFF_OACTIVE; 1809 } 1810 1811 if (sc->sc_txfree != ofree) { 1812 /* Set a watchdog timer in case the chip flakes out. */ 1813 ifp->if_timer = 5; 1814 } 1815 } 1816 1817 /* 1818 * wm_watchdog: [ifnet interface function] 1819 * 1820 * Watchdog timer handler. 1821 */ 1822 static void 1823 wm_watchdog(struct ifnet *ifp) 1824 { 1825 struct wm_softc *sc = ifp->if_softc; 1826 1827 /* 1828 * Since we're using delayed interrupts, sweep up 1829 * before we report an error. 1830 */ 1831 wm_txintr(sc); 1832 1833 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1834 log(LOG_ERR, 1835 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1836 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1837 sc->sc_txnext); 1838 ifp->if_oerrors++; 1839 1840 /* Reset the interface. */ 1841 (void) wm_init(ifp); 1842 } 1843 1844 /* Try to get more packets going. */ 1845 wm_start(ifp); 1846 } 1847 1848 /* 1849 * wm_ioctl: [ifnet interface function] 1850 * 1851 * Handle control requests from the operator. 1852 */ 1853 static int 1854 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1855 { 1856 struct wm_softc *sc = ifp->if_softc; 1857 struct ifreq *ifr = (struct ifreq *) data; 1858 int s, error; 1859 1860 s = splnet(); 1861 1862 switch (cmd) { 1863 case SIOCSIFMEDIA: 1864 case SIOCGIFMEDIA: 1865 /* Flow control requires full-duplex mode. */ 1866 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1867 (ifr->ifr_media & IFM_FDX) == 0) 1868 ifr->ifr_media &= ~IFM_ETH_FMASK; 1869 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1870 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1871 /* We can do both TXPAUSE and RXPAUSE. */ 1872 ifr->ifr_media |= 1873 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1874 } 1875 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1876 } 1877 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1878 break; 1879 default: 1880 error = ether_ioctl(ifp, cmd, data); 1881 if (error == ENETRESET) { 1882 /* 1883 * Multicast list has changed; set the hardware filter 1884 * accordingly. 1885 */ 1886 if (ifp->if_flags & IFF_RUNNING) 1887 wm_set_filter(sc); 1888 error = 0; 1889 } 1890 break; 1891 } 1892 1893 /* Try to get more packets going. */ 1894 wm_start(ifp); 1895 1896 splx(s); 1897 return (error); 1898 } 1899 1900 /* 1901 * wm_intr: 1902 * 1903 * Interrupt service routine. 1904 */ 1905 static int 1906 wm_intr(void *arg) 1907 { 1908 struct wm_softc *sc = arg; 1909 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1910 uint32_t icr; 1911 int wantinit, handled = 0; 1912 1913 for (wantinit = 0; wantinit == 0;) { 1914 icr = CSR_READ(sc, WMREG_ICR); 1915 if ((icr & sc->sc_icr) == 0) 1916 break; 1917 1918 #if 0 /*NRND > 0*/ 1919 if (RND_ENABLED(&sc->rnd_source)) 1920 rnd_add_uint32(&sc->rnd_source, icr); 1921 #endif 1922 1923 handled = 1; 1924 1925 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1926 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1927 DPRINTF(WM_DEBUG_RX, 1928 ("%s: RX: got Rx intr 0x%08x\n", 1929 sc->sc_dev.dv_xname, 1930 icr & (ICR_RXDMT0|ICR_RXT0))); 1931 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 1932 } 1933 #endif 1934 wm_rxintr(sc); 1935 1936 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1937 if (icr & ICR_TXDW) { 1938 DPRINTF(WM_DEBUG_TX, 1939 ("%s: TX: got TXDW interrupt\n", 1940 sc->sc_dev.dv_xname)); 1941 WM_EVCNT_INCR(&sc->sc_ev_txdw); 1942 } 1943 #endif 1944 wm_txintr(sc); 1945 1946 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 1947 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 1948 wm_linkintr(sc, icr); 1949 } 1950 1951 if (icr & ICR_RXO) { 1952 log(LOG_WARNING, "%s: Receive overrun\n", 1953 sc->sc_dev.dv_xname); 1954 wantinit = 1; 1955 } 1956 } 1957 1958 if (handled) { 1959 if (wantinit) 1960 wm_init(ifp); 1961 1962 /* Try to get more packets going. */ 1963 wm_start(ifp); 1964 } 1965 1966 return (handled); 1967 } 1968 1969 /* 1970 * wm_txintr: 1971 * 1972 * Helper; handle transmit interrupts. 1973 */ 1974 static void 1975 wm_txintr(struct wm_softc *sc) 1976 { 1977 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1978 struct wm_txsoft *txs; 1979 uint8_t status; 1980 int i; 1981 1982 ifp->if_flags &= ~IFF_OACTIVE; 1983 1984 /* 1985 * Go through the Tx list and free mbufs for those 1986 * frames which have been transmitted. 1987 */ 1988 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 1989 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 1990 txs = &sc->sc_txsoft[i]; 1991 1992 DPRINTF(WM_DEBUG_TX, 1993 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 1994 1995 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1996 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1997 1998 status = 1999 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2000 if ((status & WTX_ST_DD) == 0) { 2001 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2002 BUS_DMASYNC_PREREAD); 2003 break; 2004 } 2005 2006 DPRINTF(WM_DEBUG_TX, 2007 ("%s: TX: job %d done: descs %d..%d\n", 2008 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2009 txs->txs_lastdesc)); 2010 2011 /* 2012 * XXX We should probably be using the statistics 2013 * XXX registers, but I don't know if they exist 2014 * XXX on chips before the i82544. 2015 */ 2016 2017 #ifdef WM_EVENT_COUNTERS 2018 if (status & WTX_ST_TU) 2019 WM_EVCNT_INCR(&sc->sc_ev_tu); 2020 #endif /* WM_EVENT_COUNTERS */ 2021 2022 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2023 ifp->if_oerrors++; 2024 if (status & WTX_ST_LC) 2025 log(LOG_WARNING, "%s: late collision\n", 2026 sc->sc_dev.dv_xname); 2027 else if (status & WTX_ST_EC) { 2028 ifp->if_collisions += 16; 2029 log(LOG_WARNING, "%s: excessive collisions\n", 2030 sc->sc_dev.dv_xname); 2031 } 2032 } else 2033 ifp->if_opackets++; 2034 2035 sc->sc_txfree += txs->txs_ndesc; 2036 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2037 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2038 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2039 m_freem(txs->txs_mbuf); 2040 txs->txs_mbuf = NULL; 2041 } 2042 2043 /* Update the dirty transmit buffer pointer. */ 2044 sc->sc_txsdirty = i; 2045 DPRINTF(WM_DEBUG_TX, 2046 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2047 2048 /* 2049 * If there are no more pending transmissions, cancel the watchdog 2050 * timer. 2051 */ 2052 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2053 ifp->if_timer = 0; 2054 } 2055 2056 /* 2057 * wm_rxintr: 2058 * 2059 * Helper; handle receive interrupts. 2060 */ 2061 static void 2062 wm_rxintr(struct wm_softc *sc) 2063 { 2064 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2065 struct wm_rxsoft *rxs; 2066 struct mbuf *m; 2067 int i, len; 2068 uint8_t status, errors; 2069 2070 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2071 rxs = &sc->sc_rxsoft[i]; 2072 2073 DPRINTF(WM_DEBUG_RX, 2074 ("%s: RX: checking descriptor %d\n", 2075 sc->sc_dev.dv_xname, i)); 2076 2077 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2078 2079 status = sc->sc_rxdescs[i].wrx_status; 2080 errors = sc->sc_rxdescs[i].wrx_errors; 2081 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2082 2083 if ((status & WRX_ST_DD) == 0) { 2084 /* 2085 * We have processed all of the receive descriptors. 2086 */ 2087 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2088 break; 2089 } 2090 2091 if (__predict_false(sc->sc_rxdiscard)) { 2092 DPRINTF(WM_DEBUG_RX, 2093 ("%s: RX: discarding contents of descriptor %d\n", 2094 sc->sc_dev.dv_xname, i)); 2095 WM_INIT_RXDESC(sc, i); 2096 if (status & WRX_ST_EOP) { 2097 /* Reset our state. */ 2098 DPRINTF(WM_DEBUG_RX, 2099 ("%s: RX: resetting rxdiscard -> 0\n", 2100 sc->sc_dev.dv_xname)); 2101 sc->sc_rxdiscard = 0; 2102 } 2103 continue; 2104 } 2105 2106 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2107 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2108 2109 m = rxs->rxs_mbuf; 2110 2111 /* 2112 * Add a new receive buffer to the ring. 2113 */ 2114 if (wm_add_rxbuf(sc, i) != 0) { 2115 /* 2116 * Failed, throw away what we've done so 2117 * far, and discard the rest of the packet. 2118 */ 2119 ifp->if_ierrors++; 2120 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2121 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2122 WM_INIT_RXDESC(sc, i); 2123 if ((status & WRX_ST_EOP) == 0) 2124 sc->sc_rxdiscard = 1; 2125 if (sc->sc_rxhead != NULL) 2126 m_freem(sc->sc_rxhead); 2127 WM_RXCHAIN_RESET(sc); 2128 DPRINTF(WM_DEBUG_RX, 2129 ("%s: RX: Rx buffer allocation failed, " 2130 "dropping packet%s\n", sc->sc_dev.dv_xname, 2131 sc->sc_rxdiscard ? " (discard)" : "")); 2132 continue; 2133 } 2134 2135 WM_RXCHAIN_LINK(sc, m); 2136 2137 m->m_len = len; 2138 2139 DPRINTF(WM_DEBUG_RX, 2140 ("%s: RX: buffer at %p len %d\n", 2141 sc->sc_dev.dv_xname, m->m_data, len)); 2142 2143 /* 2144 * If this is not the end of the packet, keep 2145 * looking. 2146 */ 2147 if ((status & WRX_ST_EOP) == 0) { 2148 sc->sc_rxlen += len; 2149 DPRINTF(WM_DEBUG_RX, 2150 ("%s: RX: not yet EOP, rxlen -> %d\n", 2151 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2152 continue; 2153 } 2154 2155 /* 2156 * Okay, we have the entire packet now. The chip is 2157 * configured to include the FCS (not all chips can 2158 * be configured to strip it), so we need to trim it. 2159 */ 2160 m->m_len -= ETHER_CRC_LEN; 2161 2162 *sc->sc_rxtailp = NULL; 2163 m = sc->sc_rxhead; 2164 len = m->m_len + sc->sc_rxlen; 2165 2166 WM_RXCHAIN_RESET(sc); 2167 2168 DPRINTF(WM_DEBUG_RX, 2169 ("%s: RX: have entire packet, len -> %d\n", 2170 sc->sc_dev.dv_xname, len)); 2171 2172 /* 2173 * If an error occurred, update stats and drop the packet. 2174 */ 2175 if (errors & 2176 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2177 ifp->if_ierrors++; 2178 if (errors & WRX_ER_SE) 2179 log(LOG_WARNING, "%s: symbol error\n", 2180 sc->sc_dev.dv_xname); 2181 else if (errors & WRX_ER_SEQ) 2182 log(LOG_WARNING, "%s: receive sequence error\n", 2183 sc->sc_dev.dv_xname); 2184 else if (errors & WRX_ER_CE) 2185 log(LOG_WARNING, "%s: CRC error\n", 2186 sc->sc_dev.dv_xname); 2187 m_freem(m); 2188 continue; 2189 } 2190 2191 /* 2192 * No errors. Receive the packet. 2193 */ 2194 m->m_pkthdr.rcvif = ifp; 2195 m->m_pkthdr.len = len; 2196 2197 #if 0 /* XXXJRT */ 2198 /* 2199 * If VLANs are enabled, VLAN packets have been unwrapped 2200 * for us. Associate the tag with the packet. 2201 */ 2202 if (sc->sc_ethercom.ec_nvlans != 0 && 2203 (status & WRX_ST_VP) != 0) { 2204 struct m_tag *vtag; 2205 2206 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2207 M_NOWAIT); 2208 if (vtag == NULL) { 2209 ifp->if_ierrors++; 2210 log(LOG_ERR, 2211 "%s: unable to allocate VLAN tag\n", 2212 sc->sc_dev.dv_xname); 2213 m_freem(m); 2214 continue; 2215 } 2216 2217 *(u_int *)(vtag + 1) = 2218 le16toh(sc->sc_rxdescs[i].wrx_special); 2219 } 2220 #endif /* XXXJRT */ 2221 2222 /* 2223 * Set up checksum info for this packet. 2224 */ 2225 if (status & WRX_ST_IPCS) { 2226 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2227 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2228 if (errors & WRX_ER_IPE) 2229 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2230 } 2231 if (status & WRX_ST_TCPCS) { 2232 /* 2233 * Note: we don't know if this was TCP or UDP, 2234 * so we just set both bits, and expect the 2235 * upper layers to deal. 2236 */ 2237 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2238 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2239 if (errors & WRX_ER_TCPE) 2240 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2241 } 2242 2243 ifp->if_ipackets++; 2244 2245 #if NBPFILTER > 0 2246 /* Pass this up to any BPF listeners. */ 2247 if (ifp->if_bpf) 2248 bpf_mtap(ifp->if_bpf, m); 2249 #endif /* NBPFILTER > 0 */ 2250 2251 /* Pass it on. */ 2252 (*ifp->if_input)(ifp, m); 2253 } 2254 2255 /* Update the receive pointer. */ 2256 sc->sc_rxptr = i; 2257 2258 DPRINTF(WM_DEBUG_RX, 2259 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2260 } 2261 2262 /* 2263 * wm_linkintr: 2264 * 2265 * Helper; handle link interrupts. 2266 */ 2267 static void 2268 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2269 { 2270 uint32_t status; 2271 2272 /* 2273 * If we get a link status interrupt on a 1000BASE-T 2274 * device, just fall into the normal MII tick path. 2275 */ 2276 if (sc->sc_flags & WM_F_HAS_MII) { 2277 if (icr & ICR_LSC) { 2278 DPRINTF(WM_DEBUG_LINK, 2279 ("%s: LINK: LSC -> mii_tick\n", 2280 sc->sc_dev.dv_xname)); 2281 mii_tick(&sc->sc_mii); 2282 } else if (icr & ICR_RXSEQ) { 2283 DPRINTF(WM_DEBUG_LINK, 2284 ("%s: LINK Receive sequence error\n", 2285 sc->sc_dev.dv_xname)); 2286 } 2287 return; 2288 } 2289 2290 /* 2291 * If we are now receiving /C/, check for link again in 2292 * a couple of link clock ticks. 2293 */ 2294 if (icr & ICR_RXCFG) { 2295 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2296 sc->sc_dev.dv_xname)); 2297 sc->sc_tbi_anstate = 2; 2298 } 2299 2300 if (icr & ICR_LSC) { 2301 status = CSR_READ(sc, WMREG_STATUS); 2302 if (status & STATUS_LU) { 2303 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2304 sc->sc_dev.dv_xname, 2305 (status & STATUS_FD) ? "FDX" : "HDX")); 2306 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2307 sc->sc_fcrtl &= ~FCRTL_XONE; 2308 if (status & STATUS_FD) 2309 sc->sc_tctl |= 2310 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2311 else 2312 sc->sc_tctl |= 2313 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2314 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2315 sc->sc_fcrtl |= FCRTL_XONE; 2316 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2317 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2318 WMREG_OLD_FCRTL : WMREG_FCRTL, 2319 sc->sc_fcrtl); 2320 sc->sc_tbi_linkup = 1; 2321 } else { 2322 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2323 sc->sc_dev.dv_xname)); 2324 sc->sc_tbi_linkup = 0; 2325 } 2326 sc->sc_tbi_anstate = 2; 2327 wm_tbi_set_linkled(sc); 2328 } else if (icr & ICR_RXSEQ) { 2329 DPRINTF(WM_DEBUG_LINK, 2330 ("%s: LINK: Receive sequence error\n", 2331 sc->sc_dev.dv_xname)); 2332 } 2333 } 2334 2335 /* 2336 * wm_tick: 2337 * 2338 * One second timer, used to check link status, sweep up 2339 * completed transmit jobs, etc. 2340 */ 2341 static void 2342 wm_tick(void *arg) 2343 { 2344 struct wm_softc *sc = arg; 2345 int s; 2346 2347 s = splnet(); 2348 2349 if (sc->sc_type >= WM_T_82542_2_1) { 2350 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2351 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2352 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2353 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2354 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2355 } 2356 2357 if (sc->sc_flags & WM_F_HAS_MII) 2358 mii_tick(&sc->sc_mii); 2359 else 2360 wm_tbi_check_link(sc); 2361 2362 splx(s); 2363 2364 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2365 } 2366 2367 /* 2368 * wm_reset: 2369 * 2370 * Reset the i82542 chip. 2371 */ 2372 static void 2373 wm_reset(struct wm_softc *sc) 2374 { 2375 int i; 2376 2377 /* 2378 * Allocate on-chip memory according to the MTU size. 2379 * The Packet Buffer Allocation register must be written 2380 * before the chip is reset. 2381 */ 2382 if (sc->sc_type < WM_T_82547) { 2383 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2384 PBA_40K : PBA_48K; 2385 } else { 2386 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2387 PBA_22K : PBA_30K; 2388 sc->sc_txfifo_head = 0; 2389 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2390 sc->sc_txfifo_size = 2391 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2392 sc->sc_txfifo_stall = 0; 2393 } 2394 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2395 2396 switch (sc->sc_type) { 2397 case WM_T_82544: 2398 case WM_T_82540: 2399 case WM_T_82545: 2400 case WM_T_82546: 2401 case WM_T_82541: 2402 case WM_T_82541_2: 2403 /* 2404 * On some chipsets, a reset through a memory-mapped write 2405 * cycle can cause the chip to reset before completing the 2406 * write cycle. This causes major headache that can be 2407 * avoided by issuing the reset via indirect register writes 2408 * through I/O space. 2409 * 2410 * So, if we successfully mapped the I/O BAR at attach time, 2411 * use that. Otherwise, try our luck with a memory-mapped 2412 * reset. 2413 */ 2414 if (sc->sc_flags & WM_F_IOH_VALID) 2415 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2416 else 2417 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2418 break; 2419 2420 case WM_T_82545_3: 2421 case WM_T_82546_3: 2422 /* Use the shadow control register on these chips. */ 2423 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2424 break; 2425 2426 default: 2427 /* Everything else can safely use the documented method. */ 2428 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2429 break; 2430 } 2431 delay(10000); 2432 2433 for (i = 0; i < 1000; i++) { 2434 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2435 return; 2436 delay(20); 2437 } 2438 2439 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2440 log(LOG_ERR, "%s: reset failed to complete\n", 2441 sc->sc_dev.dv_xname); 2442 } 2443 2444 /* 2445 * wm_init: [ifnet interface function] 2446 * 2447 * Initialize the interface. Must be called at splnet(). 2448 */ 2449 static int 2450 wm_init(struct ifnet *ifp) 2451 { 2452 struct wm_softc *sc = ifp->if_softc; 2453 struct wm_rxsoft *rxs; 2454 int i, error = 0; 2455 uint32_t reg; 2456 2457 /* 2458 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2459 * There is a small but measurable benefit to avoiding the adjusment 2460 * of the descriptor so that the headers are aligned, for normal mtu, 2461 * on such platforms. One possibility is that the DMA itself is 2462 * slightly more efficient if the front of the entire packet (instead 2463 * of the front of the headers) is aligned. 2464 * 2465 * Note we must always set align_tweak to 0 if we are using 2466 * jumbo frames. 2467 */ 2468 #ifdef __NO_STRICT_ALIGNMENT 2469 sc->sc_align_tweak = 0; 2470 #else 2471 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2472 sc->sc_align_tweak = 0; 2473 else 2474 sc->sc_align_tweak = 2; 2475 #endif /* __NO_STRICT_ALIGNMENT */ 2476 2477 /* Cancel any pending I/O. */ 2478 wm_stop(ifp, 0); 2479 2480 /* Reset the chip to a known state. */ 2481 wm_reset(sc); 2482 2483 /* Initialize the transmit descriptor ring. */ 2484 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2485 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2486 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2487 sc->sc_txfree = WM_NTXDESC(sc); 2488 sc->sc_txnext = 0; 2489 2490 if (sc->sc_type < WM_T_82543) { 2491 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2492 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2493 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2494 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2495 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2496 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2497 } else { 2498 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2499 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2500 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2501 CSR_WRITE(sc, WMREG_TDH, 0); 2502 CSR_WRITE(sc, WMREG_TDT, 0); 2503 CSR_WRITE(sc, WMREG_TIDV, 64); 2504 CSR_WRITE(sc, WMREG_TADV, 128); 2505 2506 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2507 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2508 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2509 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2510 } 2511 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2512 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2513 2514 /* Initialize the transmit job descriptors. */ 2515 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2516 sc->sc_txsoft[i].txs_mbuf = NULL; 2517 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2518 sc->sc_txsnext = 0; 2519 sc->sc_txsdirty = 0; 2520 2521 /* 2522 * Initialize the receive descriptor and receive job 2523 * descriptor rings. 2524 */ 2525 if (sc->sc_type < WM_T_82543) { 2526 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2527 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2528 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2529 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2530 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2531 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2532 2533 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2534 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2535 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2536 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2537 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2538 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2539 } else { 2540 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2541 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2542 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2543 CSR_WRITE(sc, WMREG_RDH, 0); 2544 CSR_WRITE(sc, WMREG_RDT, 0); 2545 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2546 CSR_WRITE(sc, WMREG_RADV, 128); 2547 } 2548 for (i = 0; i < WM_NRXDESC; i++) { 2549 rxs = &sc->sc_rxsoft[i]; 2550 if (rxs->rxs_mbuf == NULL) { 2551 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2552 log(LOG_ERR, "%s: unable to allocate or map rx " 2553 "buffer %d, error = %d\n", 2554 sc->sc_dev.dv_xname, i, error); 2555 /* 2556 * XXX Should attempt to run with fewer receive 2557 * XXX buffers instead of just failing. 2558 */ 2559 wm_rxdrain(sc); 2560 goto out; 2561 } 2562 } else 2563 WM_INIT_RXDESC(sc, i); 2564 } 2565 sc->sc_rxptr = 0; 2566 sc->sc_rxdiscard = 0; 2567 WM_RXCHAIN_RESET(sc); 2568 2569 /* 2570 * Clear out the VLAN table -- we don't use it (yet). 2571 */ 2572 CSR_WRITE(sc, WMREG_VET, 0); 2573 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2574 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2575 2576 /* 2577 * Set up flow-control parameters. 2578 * 2579 * XXX Values could probably stand some tuning. 2580 */ 2581 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2582 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2583 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2584 2585 sc->sc_fcrtl = FCRTL_DFLT; 2586 if (sc->sc_type < WM_T_82543) { 2587 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2588 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2589 } else { 2590 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2591 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2592 } 2593 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2594 2595 #if 0 /* XXXJRT */ 2596 /* Deal with VLAN enables. */ 2597 if (sc->sc_ethercom.ec_nvlans != 0) 2598 sc->sc_ctrl |= CTRL_VME; 2599 else 2600 #endif /* XXXJRT */ 2601 sc->sc_ctrl &= ~CTRL_VME; 2602 2603 /* Write the control registers. */ 2604 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2605 #if 0 2606 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2607 #endif 2608 2609 /* 2610 * Set up checksum offload parameters. 2611 */ 2612 reg = CSR_READ(sc, WMREG_RXCSUM); 2613 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2614 reg |= RXCSUM_IPOFL; 2615 else 2616 reg &= ~RXCSUM_IPOFL; 2617 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2618 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2619 else { 2620 reg &= ~RXCSUM_TUOFL; 2621 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2622 reg &= ~RXCSUM_IPOFL; 2623 } 2624 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2625 2626 /* 2627 * Set up the interrupt registers. 2628 */ 2629 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2630 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2631 ICR_RXO | ICR_RXT0; 2632 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2633 sc->sc_icr |= ICR_RXCFG; 2634 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2635 2636 /* Set up the inter-packet gap. */ 2637 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2638 2639 if (sc->sc_type >= WM_T_82543) { 2640 /* Set up the interrupt throttling register (units of 256ns) */ 2641 sc->sc_itr = 1000000000 / (7000 * 256); 2642 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2643 } 2644 2645 #if 0 /* XXXJRT */ 2646 /* Set the VLAN ethernetype. */ 2647 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2648 #endif 2649 2650 /* 2651 * Set up the transmit control register; we start out with 2652 * a collision distance suitable for FDX, but update it whe 2653 * we resolve the media type. 2654 */ 2655 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2656 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2657 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2658 2659 /* Set the media. */ 2660 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2661 2662 /* 2663 * Set up the receive control register; we actually program 2664 * the register when we set the receive filter. Use multicast 2665 * address offset type 0. 2666 * 2667 * Only the i82544 has the ability to strip the incoming 2668 * CRC, so we don't enable that feature. 2669 */ 2670 sc->sc_mchash_type = 0; 2671 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2672 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2673 2674 if(MCLBYTES == 2048) { 2675 sc->sc_rctl |= RCTL_2k; 2676 } else { 2677 if(sc->sc_type >= WM_T_82543) { 2678 switch(MCLBYTES) { 2679 case 4096: 2680 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2681 break; 2682 case 8192: 2683 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2684 break; 2685 case 16384: 2686 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2687 break; 2688 default: 2689 panic("wm_init: MCLBYTES %d unsupported", 2690 MCLBYTES); 2691 break; 2692 } 2693 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2694 } 2695 2696 /* Set the receive filter. */ 2697 wm_set_filter(sc); 2698 2699 /* Start the one second link check clock. */ 2700 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2701 2702 /* ...all done! */ 2703 ifp->if_flags |= IFF_RUNNING; 2704 ifp->if_flags &= ~IFF_OACTIVE; 2705 2706 out: 2707 if (error) 2708 log(LOG_ERR, "%s: interface not running\n", 2709 sc->sc_dev.dv_xname); 2710 return (error); 2711 } 2712 2713 /* 2714 * wm_rxdrain: 2715 * 2716 * Drain the receive queue. 2717 */ 2718 static void 2719 wm_rxdrain(struct wm_softc *sc) 2720 { 2721 struct wm_rxsoft *rxs; 2722 int i; 2723 2724 for (i = 0; i < WM_NRXDESC; i++) { 2725 rxs = &sc->sc_rxsoft[i]; 2726 if (rxs->rxs_mbuf != NULL) { 2727 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2728 m_freem(rxs->rxs_mbuf); 2729 rxs->rxs_mbuf = NULL; 2730 } 2731 } 2732 } 2733 2734 /* 2735 * wm_stop: [ifnet interface function] 2736 * 2737 * Stop transmission on the interface. 2738 */ 2739 static void 2740 wm_stop(struct ifnet *ifp, int disable) 2741 { 2742 struct wm_softc *sc = ifp->if_softc; 2743 struct wm_txsoft *txs; 2744 int i; 2745 2746 /* Stop the one second clock. */ 2747 callout_stop(&sc->sc_tick_ch); 2748 2749 /* Stop the 82547 Tx FIFO stall check timer. */ 2750 if (sc->sc_type == WM_T_82547) 2751 callout_stop(&sc->sc_txfifo_ch); 2752 2753 if (sc->sc_flags & WM_F_HAS_MII) { 2754 /* Down the MII. */ 2755 mii_down(&sc->sc_mii); 2756 } 2757 2758 /* Stop the transmit and receive processes. */ 2759 CSR_WRITE(sc, WMREG_TCTL, 0); 2760 CSR_WRITE(sc, WMREG_RCTL, 0); 2761 2762 /* Release any queued transmit buffers. */ 2763 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2764 txs = &sc->sc_txsoft[i]; 2765 if (txs->txs_mbuf != NULL) { 2766 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2767 m_freem(txs->txs_mbuf); 2768 txs->txs_mbuf = NULL; 2769 } 2770 } 2771 2772 if (disable) 2773 wm_rxdrain(sc); 2774 2775 /* Mark the interface as down and cancel the watchdog timer. */ 2776 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2777 ifp->if_timer = 0; 2778 } 2779 2780 /* 2781 * wm_acquire_eeprom: 2782 * 2783 * Perform the EEPROM handshake required on some chips. 2784 */ 2785 static int 2786 wm_acquire_eeprom(struct wm_softc *sc) 2787 { 2788 uint32_t reg; 2789 int x; 2790 2791 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2792 reg = CSR_READ(sc, WMREG_EECD); 2793 2794 /* Request EEPROM access. */ 2795 reg |= EECD_EE_REQ; 2796 CSR_WRITE(sc, WMREG_EECD, reg); 2797 2798 /* ..and wait for it to be granted. */ 2799 for (x = 0; x < 100; x++) { 2800 reg = CSR_READ(sc, WMREG_EECD); 2801 if (reg & EECD_EE_GNT) 2802 break; 2803 delay(5); 2804 } 2805 if ((reg & EECD_EE_GNT) == 0) { 2806 aprint_error("%s: could not acquire EEPROM GNT\n", 2807 sc->sc_dev.dv_xname); 2808 reg &= ~EECD_EE_REQ; 2809 CSR_WRITE(sc, WMREG_EECD, reg); 2810 return (1); 2811 } 2812 } 2813 2814 return (0); 2815 } 2816 2817 /* 2818 * wm_release_eeprom: 2819 * 2820 * Release the EEPROM mutex. 2821 */ 2822 static void 2823 wm_release_eeprom(struct wm_softc *sc) 2824 { 2825 uint32_t reg; 2826 2827 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2828 reg = CSR_READ(sc, WMREG_EECD); 2829 reg &= ~EECD_EE_REQ; 2830 CSR_WRITE(sc, WMREG_EECD, reg); 2831 } 2832 } 2833 2834 /* 2835 * wm_eeprom_sendbits: 2836 * 2837 * Send a series of bits to the EEPROM. 2838 */ 2839 static void 2840 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2841 { 2842 uint32_t reg; 2843 int x; 2844 2845 reg = CSR_READ(sc, WMREG_EECD); 2846 2847 for (x = nbits; x > 0; x--) { 2848 if (bits & (1U << (x - 1))) 2849 reg |= EECD_DI; 2850 else 2851 reg &= ~EECD_DI; 2852 CSR_WRITE(sc, WMREG_EECD, reg); 2853 delay(2); 2854 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2855 delay(2); 2856 CSR_WRITE(sc, WMREG_EECD, reg); 2857 delay(2); 2858 } 2859 } 2860 2861 /* 2862 * wm_eeprom_recvbits: 2863 * 2864 * Receive a series of bits from the EEPROM. 2865 */ 2866 static void 2867 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2868 { 2869 uint32_t reg, val; 2870 int x; 2871 2872 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2873 2874 val = 0; 2875 for (x = nbits; x > 0; x--) { 2876 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2877 delay(2); 2878 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2879 val |= (1U << (x - 1)); 2880 CSR_WRITE(sc, WMREG_EECD, reg); 2881 delay(2); 2882 } 2883 *valp = val; 2884 } 2885 2886 /* 2887 * wm_read_eeprom_uwire: 2888 * 2889 * Read a word from the EEPROM using the MicroWire protocol. 2890 */ 2891 static int 2892 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2893 { 2894 uint32_t reg, val; 2895 int i; 2896 2897 for (i = 0; i < wordcnt; i++) { 2898 /* Clear SK and DI. */ 2899 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2900 CSR_WRITE(sc, WMREG_EECD, reg); 2901 2902 /* Set CHIP SELECT. */ 2903 reg |= EECD_CS; 2904 CSR_WRITE(sc, WMREG_EECD, reg); 2905 delay(2); 2906 2907 /* Shift in the READ command. */ 2908 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2909 2910 /* Shift in address. */ 2911 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2912 2913 /* Shift out the data. */ 2914 wm_eeprom_recvbits(sc, &val, 16); 2915 data[i] = val & 0xffff; 2916 2917 /* Clear CHIP SELECT. */ 2918 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 2919 CSR_WRITE(sc, WMREG_EECD, reg); 2920 delay(2); 2921 } 2922 2923 return (0); 2924 } 2925 2926 /* 2927 * wm_spi_eeprom_ready: 2928 * 2929 * Wait for a SPI EEPROM to be ready for commands. 2930 */ 2931 static int 2932 wm_spi_eeprom_ready(struct wm_softc *sc) 2933 { 2934 uint32_t val; 2935 int usec; 2936 2937 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 2938 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 2939 wm_eeprom_recvbits(sc, &val, 8); 2940 if ((val & SPI_SR_RDY) == 0) 2941 break; 2942 } 2943 if (usec >= SPI_MAX_RETRIES) { 2944 aprint_error("%s: EEPROM failed to become ready\n", 2945 sc->sc_dev.dv_xname); 2946 return (1); 2947 } 2948 return (0); 2949 } 2950 2951 /* 2952 * wm_read_eeprom_spi: 2953 * 2954 * Read a work from the EEPROM using the SPI protocol. 2955 */ 2956 static int 2957 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2958 { 2959 uint32_t reg, val; 2960 int i; 2961 uint8_t opc; 2962 2963 /* Clear SK and CS. */ 2964 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 2965 CSR_WRITE(sc, WMREG_EECD, reg); 2966 delay(2); 2967 2968 if (wm_spi_eeprom_ready(sc)) 2969 return (1); 2970 2971 /* Toggle CS to flush commands. */ 2972 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 2973 delay(2); 2974 CSR_WRITE(sc, WMREG_EECD, reg); 2975 delay(2); 2976 2977 opc = SPI_OPC_READ; 2978 if (sc->sc_ee_addrbits == 8 && word >= 128) 2979 opc |= SPI_OPC_A8; 2980 2981 wm_eeprom_sendbits(sc, opc, 8); 2982 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 2983 2984 for (i = 0; i < wordcnt; i++) { 2985 wm_eeprom_recvbits(sc, &val, 16); 2986 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 2987 } 2988 2989 /* Raise CS and clear SK. */ 2990 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 2991 CSR_WRITE(sc, WMREG_EECD, reg); 2992 delay(2); 2993 2994 return (0); 2995 } 2996 2997 /* 2998 * wm_read_eeprom: 2999 * 3000 * Read data from the serial EEPROM. 3001 */ 3002 static int 3003 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3004 { 3005 int rv; 3006 3007 if (wm_acquire_eeprom(sc)) 3008 return (1); 3009 3010 if (sc->sc_flags & WM_F_EEPROM_SPI) 3011 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3012 else 3013 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3014 3015 wm_release_eeprom(sc); 3016 return (rv); 3017 } 3018 3019 /* 3020 * wm_add_rxbuf: 3021 * 3022 * Add a receive buffer to the indiciated descriptor. 3023 */ 3024 static int 3025 wm_add_rxbuf(struct wm_softc *sc, int idx) 3026 { 3027 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3028 struct mbuf *m; 3029 int error; 3030 3031 MGETHDR(m, M_DONTWAIT, MT_DATA); 3032 if (m == NULL) 3033 return (ENOBUFS); 3034 3035 MCLGET(m, M_DONTWAIT); 3036 if ((m->m_flags & M_EXT) == 0) { 3037 m_freem(m); 3038 return (ENOBUFS); 3039 } 3040 3041 if (rxs->rxs_mbuf != NULL) 3042 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3043 3044 rxs->rxs_mbuf = m; 3045 3046 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3047 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3048 BUS_DMA_READ|BUS_DMA_NOWAIT); 3049 if (error) { 3050 /* XXX XXX XXX */ 3051 printf("%s: unable to load rx DMA map %d, error = %d\n", 3052 sc->sc_dev.dv_xname, idx, error); 3053 panic("wm_add_rxbuf"); 3054 } 3055 3056 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3057 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3058 3059 WM_INIT_RXDESC(sc, idx); 3060 3061 return (0); 3062 } 3063 3064 /* 3065 * wm_set_ral: 3066 * 3067 * Set an entery in the receive address list. 3068 */ 3069 static void 3070 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3071 { 3072 uint32_t ral_lo, ral_hi; 3073 3074 if (enaddr != NULL) { 3075 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3076 (enaddr[3] << 24); 3077 ral_hi = enaddr[4] | (enaddr[5] << 8); 3078 ral_hi |= RAL_AV; 3079 } else { 3080 ral_lo = 0; 3081 ral_hi = 0; 3082 } 3083 3084 if (sc->sc_type >= WM_T_82544) { 3085 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3086 ral_lo); 3087 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3088 ral_hi); 3089 } else { 3090 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3091 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3092 } 3093 } 3094 3095 /* 3096 * wm_mchash: 3097 * 3098 * Compute the hash of the multicast address for the 4096-bit 3099 * multicast filter. 3100 */ 3101 static uint32_t 3102 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3103 { 3104 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3105 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3106 uint32_t hash; 3107 3108 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3109 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3110 3111 return (hash & 0xfff); 3112 } 3113 3114 /* 3115 * wm_set_filter: 3116 * 3117 * Set up the receive filter. 3118 */ 3119 static void 3120 wm_set_filter(struct wm_softc *sc) 3121 { 3122 struct ethercom *ec = &sc->sc_ethercom; 3123 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3124 struct ether_multi *enm; 3125 struct ether_multistep step; 3126 bus_addr_t mta_reg; 3127 uint32_t hash, reg, bit; 3128 int i; 3129 3130 if (sc->sc_type >= WM_T_82544) 3131 mta_reg = WMREG_CORDOVA_MTA; 3132 else 3133 mta_reg = WMREG_MTA; 3134 3135 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3136 3137 if (ifp->if_flags & IFF_BROADCAST) 3138 sc->sc_rctl |= RCTL_BAM; 3139 if (ifp->if_flags & IFF_PROMISC) { 3140 sc->sc_rctl |= RCTL_UPE; 3141 goto allmulti; 3142 } 3143 3144 /* 3145 * Set the station address in the first RAL slot, and 3146 * clear the remaining slots. 3147 */ 3148 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3149 for (i = 1; i < WM_RAL_TABSIZE; i++) 3150 wm_set_ral(sc, NULL, i); 3151 3152 /* Clear out the multicast table. */ 3153 for (i = 0; i < WM_MC_TABSIZE; i++) 3154 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3155 3156 ETHER_FIRST_MULTI(step, ec, enm); 3157 while (enm != NULL) { 3158 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3159 /* 3160 * We must listen to a range of multicast addresses. 3161 * For now, just accept all multicasts, rather than 3162 * trying to set only those filter bits needed to match 3163 * the range. (At this time, the only use of address 3164 * ranges is for IP multicast routing, for which the 3165 * range is big enough to require all bits set.) 3166 */ 3167 goto allmulti; 3168 } 3169 3170 hash = wm_mchash(sc, enm->enm_addrlo); 3171 3172 reg = (hash >> 5) & 0x7f; 3173 bit = hash & 0x1f; 3174 3175 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3176 hash |= 1U << bit; 3177 3178 /* XXX Hardware bug?? */ 3179 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3180 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3181 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3182 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3183 } else 3184 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3185 3186 ETHER_NEXT_MULTI(step, enm); 3187 } 3188 3189 ifp->if_flags &= ~IFF_ALLMULTI; 3190 goto setit; 3191 3192 allmulti: 3193 ifp->if_flags |= IFF_ALLMULTI; 3194 sc->sc_rctl |= RCTL_MPE; 3195 3196 setit: 3197 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3198 } 3199 3200 /* 3201 * wm_tbi_mediainit: 3202 * 3203 * Initialize media for use on 1000BASE-X devices. 3204 */ 3205 static void 3206 wm_tbi_mediainit(struct wm_softc *sc) 3207 { 3208 const char *sep = ""; 3209 3210 if (sc->sc_type < WM_T_82543) 3211 sc->sc_tipg = TIPG_WM_DFLT; 3212 else 3213 sc->sc_tipg = TIPG_LG_DFLT; 3214 3215 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3216 wm_tbi_mediastatus); 3217 3218 /* 3219 * SWD Pins: 3220 * 3221 * 0 = Link LED (output) 3222 * 1 = Loss Of Signal (input) 3223 */ 3224 sc->sc_ctrl |= CTRL_SWDPIO(0); 3225 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3226 3227 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3228 3229 #define ADD(ss, mm, dd) \ 3230 do { \ 3231 aprint_normal("%s%s", sep, ss); \ 3232 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3233 sep = ", "; \ 3234 } while (/*CONSTCOND*/0) 3235 3236 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3237 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3238 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3239 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3240 aprint_normal("\n"); 3241 3242 #undef ADD 3243 3244 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3245 } 3246 3247 /* 3248 * wm_tbi_mediastatus: [ifmedia interface function] 3249 * 3250 * Get the current interface media status on a 1000BASE-X device. 3251 */ 3252 static void 3253 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3254 { 3255 struct wm_softc *sc = ifp->if_softc; 3256 uint32_t ctrl; 3257 3258 ifmr->ifm_status = IFM_AVALID; 3259 ifmr->ifm_active = IFM_ETHER; 3260 3261 if (sc->sc_tbi_linkup == 0) { 3262 ifmr->ifm_active |= IFM_NONE; 3263 return; 3264 } 3265 3266 ifmr->ifm_status |= IFM_ACTIVE; 3267 ifmr->ifm_active |= IFM_1000_SX; 3268 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3269 ifmr->ifm_active |= IFM_FDX; 3270 ctrl = CSR_READ(sc, WMREG_CTRL); 3271 if (ctrl & CTRL_RFCE) 3272 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3273 if (ctrl & CTRL_TFCE) 3274 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3275 } 3276 3277 /* 3278 * wm_tbi_mediachange: [ifmedia interface function] 3279 * 3280 * Set hardware to newly-selected media on a 1000BASE-X device. 3281 */ 3282 static int 3283 wm_tbi_mediachange(struct ifnet *ifp) 3284 { 3285 struct wm_softc *sc = ifp->if_softc; 3286 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3287 uint32_t status; 3288 int i; 3289 3290 sc->sc_txcw = ife->ifm_data; 3291 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3292 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3293 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3294 sc->sc_txcw |= TXCW_ANE; 3295 3296 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3297 delay(10000); 3298 3299 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3300 3301 sc->sc_tbi_anstate = 0; 3302 3303 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3304 /* Have signal; wait for the link to come up. */ 3305 for (i = 0; i < 50; i++) { 3306 delay(10000); 3307 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3308 break; 3309 } 3310 3311 status = CSR_READ(sc, WMREG_STATUS); 3312 if (status & STATUS_LU) { 3313 /* Link is up. */ 3314 DPRINTF(WM_DEBUG_LINK, 3315 ("%s: LINK: set media -> link up %s\n", 3316 sc->sc_dev.dv_xname, 3317 (status & STATUS_FD) ? "FDX" : "HDX")); 3318 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3319 sc->sc_fcrtl &= ~FCRTL_XONE; 3320 if (status & STATUS_FD) 3321 sc->sc_tctl |= 3322 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3323 else 3324 sc->sc_tctl |= 3325 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3326 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3327 sc->sc_fcrtl |= FCRTL_XONE; 3328 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3329 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3330 WMREG_OLD_FCRTL : WMREG_FCRTL, 3331 sc->sc_fcrtl); 3332 sc->sc_tbi_linkup = 1; 3333 } else { 3334 /* Link is down. */ 3335 DPRINTF(WM_DEBUG_LINK, 3336 ("%s: LINK: set media -> link down\n", 3337 sc->sc_dev.dv_xname)); 3338 sc->sc_tbi_linkup = 0; 3339 } 3340 } else { 3341 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3342 sc->sc_dev.dv_xname)); 3343 sc->sc_tbi_linkup = 0; 3344 } 3345 3346 wm_tbi_set_linkled(sc); 3347 3348 return (0); 3349 } 3350 3351 /* 3352 * wm_tbi_set_linkled: 3353 * 3354 * Update the link LED on 1000BASE-X devices. 3355 */ 3356 static void 3357 wm_tbi_set_linkled(struct wm_softc *sc) 3358 { 3359 3360 if (sc->sc_tbi_linkup) 3361 sc->sc_ctrl |= CTRL_SWDPIN(0); 3362 else 3363 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3364 3365 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3366 } 3367 3368 /* 3369 * wm_tbi_check_link: 3370 * 3371 * Check the link on 1000BASE-X devices. 3372 */ 3373 static void 3374 wm_tbi_check_link(struct wm_softc *sc) 3375 { 3376 uint32_t rxcw, ctrl, status; 3377 3378 if (sc->sc_tbi_anstate == 0) 3379 return; 3380 else if (sc->sc_tbi_anstate > 1) { 3381 DPRINTF(WM_DEBUG_LINK, 3382 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3383 sc->sc_tbi_anstate)); 3384 sc->sc_tbi_anstate--; 3385 return; 3386 } 3387 3388 sc->sc_tbi_anstate = 0; 3389 3390 rxcw = CSR_READ(sc, WMREG_RXCW); 3391 ctrl = CSR_READ(sc, WMREG_CTRL); 3392 status = CSR_READ(sc, WMREG_STATUS); 3393 3394 if ((status & STATUS_LU) == 0) { 3395 DPRINTF(WM_DEBUG_LINK, 3396 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3397 sc->sc_tbi_linkup = 0; 3398 } else { 3399 DPRINTF(WM_DEBUG_LINK, 3400 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3401 (status & STATUS_FD) ? "FDX" : "HDX")); 3402 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3403 sc->sc_fcrtl &= ~FCRTL_XONE; 3404 if (status & STATUS_FD) 3405 sc->sc_tctl |= 3406 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3407 else 3408 sc->sc_tctl |= 3409 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3410 if (ctrl & CTRL_TFCE) 3411 sc->sc_fcrtl |= FCRTL_XONE; 3412 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3413 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3414 WMREG_OLD_FCRTL : WMREG_FCRTL, 3415 sc->sc_fcrtl); 3416 sc->sc_tbi_linkup = 1; 3417 } 3418 3419 wm_tbi_set_linkled(sc); 3420 } 3421 3422 /* 3423 * wm_gmii_reset: 3424 * 3425 * Reset the PHY. 3426 */ 3427 static void 3428 wm_gmii_reset(struct wm_softc *sc) 3429 { 3430 uint32_t reg; 3431 3432 if (sc->sc_type >= WM_T_82544) { 3433 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3434 delay(20000); 3435 3436 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3437 delay(20000); 3438 } else { 3439 /* The PHY reset pin is active-low. */ 3440 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3441 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3442 CTRL_EXT_SWDPIN(4)); 3443 reg |= CTRL_EXT_SWDPIO(4); 3444 3445 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3446 delay(10); 3447 3448 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3449 delay(10); 3450 3451 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3452 delay(10); 3453 #if 0 3454 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3455 #endif 3456 } 3457 } 3458 3459 /* 3460 * wm_gmii_mediainit: 3461 * 3462 * Initialize media for use on 1000BASE-T devices. 3463 */ 3464 static void 3465 wm_gmii_mediainit(struct wm_softc *sc) 3466 { 3467 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3468 3469 /* We have MII. */ 3470 sc->sc_flags |= WM_F_HAS_MII; 3471 3472 sc->sc_tipg = TIPG_1000T_DFLT; 3473 3474 /* 3475 * Let the chip set speed/duplex on its own based on 3476 * signals from the PHY. 3477 */ 3478 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3479 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3480 3481 /* Initialize our media structures and probe the GMII. */ 3482 sc->sc_mii.mii_ifp = ifp; 3483 3484 if (sc->sc_type >= WM_T_82544) { 3485 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3486 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3487 } else { 3488 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3489 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3490 } 3491 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3492 3493 wm_gmii_reset(sc); 3494 3495 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3496 wm_gmii_mediastatus); 3497 3498 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3499 MII_OFFSET_ANY, MIIF_DOPAUSE); 3500 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3501 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3502 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3503 } else 3504 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3505 } 3506 3507 /* 3508 * wm_gmii_mediastatus: [ifmedia interface function] 3509 * 3510 * Get the current interface media status on a 1000BASE-T device. 3511 */ 3512 static void 3513 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3514 { 3515 struct wm_softc *sc = ifp->if_softc; 3516 3517 mii_pollstat(&sc->sc_mii); 3518 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3519 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3520 sc->sc_flowflags; 3521 } 3522 3523 /* 3524 * wm_gmii_mediachange: [ifmedia interface function] 3525 * 3526 * Set hardware to newly-selected media on a 1000BASE-T device. 3527 */ 3528 static int 3529 wm_gmii_mediachange(struct ifnet *ifp) 3530 { 3531 struct wm_softc *sc = ifp->if_softc; 3532 3533 if (ifp->if_flags & IFF_UP) 3534 mii_mediachg(&sc->sc_mii); 3535 return (0); 3536 } 3537 3538 #define MDI_IO CTRL_SWDPIN(2) 3539 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3540 #define MDI_CLK CTRL_SWDPIN(3) 3541 3542 static void 3543 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3544 { 3545 uint32_t i, v; 3546 3547 v = CSR_READ(sc, WMREG_CTRL); 3548 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3549 v |= MDI_DIR | CTRL_SWDPIO(3); 3550 3551 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3552 if (data & i) 3553 v |= MDI_IO; 3554 else 3555 v &= ~MDI_IO; 3556 CSR_WRITE(sc, WMREG_CTRL, v); 3557 delay(10); 3558 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3559 delay(10); 3560 CSR_WRITE(sc, WMREG_CTRL, v); 3561 delay(10); 3562 } 3563 } 3564 3565 static uint32_t 3566 i82543_mii_recvbits(struct wm_softc *sc) 3567 { 3568 uint32_t v, i, data = 0; 3569 3570 v = CSR_READ(sc, WMREG_CTRL); 3571 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3572 v |= CTRL_SWDPIO(3); 3573 3574 CSR_WRITE(sc, WMREG_CTRL, v); 3575 delay(10); 3576 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3577 delay(10); 3578 CSR_WRITE(sc, WMREG_CTRL, v); 3579 delay(10); 3580 3581 for (i = 0; i < 16; i++) { 3582 data <<= 1; 3583 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3584 delay(10); 3585 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3586 data |= 1; 3587 CSR_WRITE(sc, WMREG_CTRL, v); 3588 delay(10); 3589 } 3590 3591 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3592 delay(10); 3593 CSR_WRITE(sc, WMREG_CTRL, v); 3594 delay(10); 3595 3596 return (data); 3597 } 3598 3599 #undef MDI_IO 3600 #undef MDI_DIR 3601 #undef MDI_CLK 3602 3603 /* 3604 * wm_gmii_i82543_readreg: [mii interface function] 3605 * 3606 * Read a PHY register on the GMII (i82543 version). 3607 */ 3608 static int 3609 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3610 { 3611 struct wm_softc *sc = (void *) self; 3612 int rv; 3613 3614 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3615 i82543_mii_sendbits(sc, reg | (phy << 5) | 3616 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3617 rv = i82543_mii_recvbits(sc) & 0xffff; 3618 3619 DPRINTF(WM_DEBUG_GMII, 3620 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3621 sc->sc_dev.dv_xname, phy, reg, rv)); 3622 3623 return (rv); 3624 } 3625 3626 /* 3627 * wm_gmii_i82543_writereg: [mii interface function] 3628 * 3629 * Write a PHY register on the GMII (i82543 version). 3630 */ 3631 static void 3632 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3633 { 3634 struct wm_softc *sc = (void *) self; 3635 3636 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3637 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3638 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3639 (MII_COMMAND_START << 30), 32); 3640 } 3641 3642 /* 3643 * wm_gmii_i82544_readreg: [mii interface function] 3644 * 3645 * Read a PHY register on the GMII. 3646 */ 3647 static int 3648 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3649 { 3650 struct wm_softc *sc = (void *) self; 3651 uint32_t mdic = 0; 3652 int i, rv; 3653 3654 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3655 MDIC_REGADD(reg)); 3656 3657 for (i = 0; i < 100; i++) { 3658 mdic = CSR_READ(sc, WMREG_MDIC); 3659 if (mdic & MDIC_READY) 3660 break; 3661 delay(10); 3662 } 3663 3664 if ((mdic & MDIC_READY) == 0) { 3665 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3666 sc->sc_dev.dv_xname, phy, reg); 3667 rv = 0; 3668 } else if (mdic & MDIC_E) { 3669 #if 0 /* This is normal if no PHY is present. */ 3670 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3671 sc->sc_dev.dv_xname, phy, reg); 3672 #endif 3673 rv = 0; 3674 } else { 3675 rv = MDIC_DATA(mdic); 3676 if (rv == 0xffff) 3677 rv = 0; 3678 } 3679 3680 return (rv); 3681 } 3682 3683 /* 3684 * wm_gmii_i82544_writereg: [mii interface function] 3685 * 3686 * Write a PHY register on the GMII. 3687 */ 3688 static void 3689 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3690 { 3691 struct wm_softc *sc = (void *) self; 3692 uint32_t mdic = 0; 3693 int i; 3694 3695 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3696 MDIC_REGADD(reg) | MDIC_DATA(val)); 3697 3698 for (i = 0; i < 100; i++) { 3699 mdic = CSR_READ(sc, WMREG_MDIC); 3700 if (mdic & MDIC_READY) 3701 break; 3702 delay(10); 3703 } 3704 3705 if ((mdic & MDIC_READY) == 0) 3706 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3707 sc->sc_dev.dv_xname, phy, reg); 3708 else if (mdic & MDIC_E) 3709 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3710 sc->sc_dev.dv_xname, phy, reg); 3711 } 3712 3713 /* 3714 * wm_gmii_statchg: [mii interface function] 3715 * 3716 * Callback from MII layer when media changes. 3717 */ 3718 static void 3719 wm_gmii_statchg(struct device *self) 3720 { 3721 struct wm_softc *sc = (void *) self; 3722 struct mii_data *mii = &sc->sc_mii; 3723 3724 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3725 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3726 sc->sc_fcrtl &= ~FCRTL_XONE; 3727 3728 /* 3729 * Get flow control negotiation result. 3730 */ 3731 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3732 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3733 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3734 mii->mii_media_active &= ~IFM_ETH_FMASK; 3735 } 3736 3737 if (sc->sc_flowflags & IFM_FLOW) { 3738 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3739 sc->sc_ctrl |= CTRL_TFCE; 3740 sc->sc_fcrtl |= FCRTL_XONE; 3741 } 3742 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3743 sc->sc_ctrl |= CTRL_RFCE; 3744 } 3745 3746 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3747 DPRINTF(WM_DEBUG_LINK, 3748 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3749 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3750 } else { 3751 DPRINTF(WM_DEBUG_LINK, 3752 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3753 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3754 } 3755 3756 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3757 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3758 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3759 : WMREG_FCRTL, sc->sc_fcrtl); 3760 } 3761
Indexes created Tue Sep 23 07:09:52 GMT 2025