if_wm.c revision 1.98
1 /* $NetBSD: if_wm.c,v 1.98 2005/03/05 21:37:07 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.98 2005/03/05 21:37:07 thorpej Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA ETHER_MAX_LEN_JUMBO 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make serveral things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 280 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 281 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 282 283 struct evcnt sc_ev_tu; /* Tx underrun */ 284 285 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 286 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 287 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 288 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 289 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 290 #endif /* WM_EVENT_COUNTERS */ 291 292 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 293 294 int sc_txfree; /* number of free Tx descriptors */ 295 int sc_txnext; /* next ready Tx descriptor */ 296 297 int sc_txsfree; /* number of free Tx jobs */ 298 int sc_txsnext; /* next free Tx job */ 299 int sc_txsdirty; /* dirty Tx jobs */ 300 301 /* These 5 variables are used only on the 82547. */ 302 int sc_txfifo_size; /* Tx FIFO size */ 303 int sc_txfifo_head; /* current head of FIFO */ 304 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 305 int sc_txfifo_stall; /* Tx FIFO is stalled */ 306 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 307 308 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 309 310 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 311 int sc_rxdiscard; 312 int sc_rxlen; 313 struct mbuf *sc_rxhead; 314 struct mbuf *sc_rxtail; 315 struct mbuf **sc_rxtailp; 316 317 uint32_t sc_ctrl; /* prototype CTRL register */ 318 #if 0 319 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 320 #endif 321 uint32_t sc_icr; /* prototype interrupt bits */ 322 uint32_t sc_itr; /* prototype intr throttling reg */ 323 uint32_t sc_tctl; /* prototype TCTL register */ 324 uint32_t sc_rctl; /* prototype RCTL register */ 325 uint32_t sc_txcw; /* prototype TXCW register */ 326 uint32_t sc_tipg; /* prototype TIPG register */ 327 uint32_t sc_fcrtl; /* prototype FCRTL register */ 328 uint32_t sc_pba; /* prototype PBA register */ 329 330 int sc_tbi_linkup; /* TBI link status */ 331 int sc_tbi_anstate; /* autonegotiation state */ 332 333 int sc_mchash_type; /* multicast filter offset */ 334 335 #if NRND > 0 336 rndsource_element_t rnd_source; /* random source */ 337 #endif 338 }; 339 340 #define WM_RXCHAIN_RESET(sc) \ 341 do { \ 342 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 343 *(sc)->sc_rxtailp = NULL; \ 344 (sc)->sc_rxlen = 0; \ 345 } while (/*CONSTCOND*/0) 346 347 #define WM_RXCHAIN_LINK(sc, m) \ 348 do { \ 349 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 350 (sc)->sc_rxtailp = &(m)->m_next; \ 351 } while (/*CONSTCOND*/0) 352 353 /* sc_flags */ 354 #define WM_F_HAS_MII 0x01 /* has MII */ 355 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 356 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 357 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 358 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 359 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 360 #define WM_F_CSA 0x80 /* bus is CSA */ 361 362 #ifdef WM_EVENT_COUNTERS 363 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 364 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 365 #else 366 #define WM_EVCNT_INCR(ev) /* nothing */ 367 #define WM_EVCNT_ADD(ev, val) /* nothing */ 368 #endif 369 370 #define CSR_READ(sc, reg) \ 371 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 372 #define CSR_WRITE(sc, reg, val) \ 373 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 374 #define CSR_WRITE_FLUSH(sc) \ 375 (void) CSR_READ((sc), WMREG_STATUS) 376 377 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 378 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 379 380 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 381 #define WM_CDTXADDR_HI(sc, x) \ 382 (sizeof(bus_addr_t) == 8 ? \ 383 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 384 385 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 386 #define WM_CDRXADDR_HI(sc, x) \ 387 (sizeof(bus_addr_t) == 8 ? \ 388 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 389 390 #define WM_CDTXSYNC(sc, x, n, ops) \ 391 do { \ 392 int __x, __n; \ 393 \ 394 __x = (x); \ 395 __n = (n); \ 396 \ 397 /* If it will wrap around, sync to the end of the ring. */ \ 398 if ((__x + __n) > WM_NTXDESC(sc)) { \ 399 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 400 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 401 (WM_NTXDESC(sc) - __x), (ops)); \ 402 __n -= (WM_NTXDESC(sc) - __x); \ 403 __x = 0; \ 404 } \ 405 \ 406 /* Now sync whatever is left. */ \ 407 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 408 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 409 } while (/*CONSTCOND*/0) 410 411 #define WM_CDRXSYNC(sc, x, ops) \ 412 do { \ 413 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 414 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 415 } while (/*CONSTCOND*/0) 416 417 #define WM_INIT_RXDESC(sc, x) \ 418 do { \ 419 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 420 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 421 struct mbuf *__m = __rxs->rxs_mbuf; \ 422 \ 423 /* \ 424 * Note: We scoot the packet forward 2 bytes in the buffer \ 425 * so that the payload after the Ethernet header is aligned \ 426 * to a 4-byte boundary. \ 427 * \ 428 * XXX BRAINDAMAGE ALERT! \ 429 * The stupid chip uses the same size for every buffer, which \ 430 * is set in the Receive Control register. We are using the 2K \ 431 * size option, but what we REALLY want is (2K - 2)! For this \ 432 * reason, we can't "scoot" packets longer than the standard \ 433 * Ethernet MTU. On strict-alignment platforms, if the total \ 434 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 435 * the upper layer copy the headers. \ 436 */ \ 437 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 438 \ 439 wm_set_dma_addr(&__rxd->wrx_addr, \ 440 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 441 __rxd->wrx_len = 0; \ 442 __rxd->wrx_cksum = 0; \ 443 __rxd->wrx_status = 0; \ 444 __rxd->wrx_errors = 0; \ 445 __rxd->wrx_special = 0; \ 446 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 447 \ 448 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 449 } while (/*CONSTCOND*/0) 450 451 static void wm_start(struct ifnet *); 452 static void wm_watchdog(struct ifnet *); 453 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 454 static int wm_init(struct ifnet *); 455 static void wm_stop(struct ifnet *, int); 456 457 static void wm_shutdown(void *); 458 459 static void wm_reset(struct wm_softc *); 460 static void wm_rxdrain(struct wm_softc *); 461 static int wm_add_rxbuf(struct wm_softc *, int); 462 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 463 static void wm_tick(void *); 464 465 static void wm_set_filter(struct wm_softc *); 466 467 static int wm_intr(void *); 468 static void wm_txintr(struct wm_softc *); 469 static void wm_rxintr(struct wm_softc *); 470 static void wm_linkintr(struct wm_softc *, uint32_t); 471 472 static void wm_tbi_mediainit(struct wm_softc *); 473 static int wm_tbi_mediachange(struct ifnet *); 474 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 475 476 static void wm_tbi_set_linkled(struct wm_softc *); 477 static void wm_tbi_check_link(struct wm_softc *); 478 479 static void wm_gmii_reset(struct wm_softc *); 480 481 static int wm_gmii_i82543_readreg(struct device *, int, int); 482 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 483 484 static int wm_gmii_i82544_readreg(struct device *, int, int); 485 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 486 487 static void wm_gmii_statchg(struct device *); 488 489 static void wm_gmii_mediainit(struct wm_softc *); 490 static int wm_gmii_mediachange(struct ifnet *); 491 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 492 493 static int wm_match(struct device *, struct cfdata *, void *); 494 static void wm_attach(struct device *, struct device *, void *); 495 496 CFATTACH_DECL(wm, sizeof(struct wm_softc), 497 wm_match, wm_attach, NULL, NULL); 498 499 static void wm_82547_txfifo_stall(void *); 500 501 /* 502 * Devices supported by this driver. 503 */ 504 static const struct wm_product { 505 pci_vendor_id_t wmp_vendor; 506 pci_product_id_t wmp_product; 507 const char *wmp_name; 508 wm_chip_type wmp_type; 509 int wmp_flags; 510 #define WMP_F_1000X 0x01 511 #define WMP_F_1000T 0x02 512 } wm_products[] = { 513 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 514 "Intel i82542 1000BASE-X Ethernet", 515 WM_T_82542_2_1, WMP_F_1000X }, 516 517 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 518 "Intel i82543GC 1000BASE-X Ethernet", 519 WM_T_82543, WMP_F_1000X }, 520 521 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 522 "Intel i82543GC 1000BASE-T Ethernet", 523 WM_T_82543, WMP_F_1000T }, 524 525 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 526 "Intel i82544EI 1000BASE-T Ethernet", 527 WM_T_82544, WMP_F_1000T }, 528 529 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 530 "Intel i82544EI 1000BASE-X Ethernet", 531 WM_T_82544, WMP_F_1000X }, 532 533 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 534 "Intel i82544GC 1000BASE-T Ethernet", 535 WM_T_82544, WMP_F_1000T }, 536 537 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 538 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 539 WM_T_82544, WMP_F_1000T }, 540 541 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 542 "Intel i82540EM 1000BASE-T Ethernet", 543 WM_T_82540, WMP_F_1000T }, 544 545 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 546 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 547 WM_T_82540, WMP_F_1000T }, 548 549 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 550 "Intel i82540EP 1000BASE-T Ethernet", 551 WM_T_82540, WMP_F_1000T }, 552 553 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 554 "Intel i82540EP 1000BASE-T Ethernet", 555 WM_T_82540, WMP_F_1000T }, 556 557 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 558 "Intel i82540EP 1000BASE-T Ethernet", 559 WM_T_82540, WMP_F_1000T }, 560 561 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 562 "Intel i82545EM 1000BASE-T Ethernet", 563 WM_T_82545, WMP_F_1000T }, 564 565 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 566 "Intel i82545GM 1000BASE-T Ethernet", 567 WM_T_82545_3, WMP_F_1000T }, 568 569 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 570 "Intel i82545GM 1000BASE-X Ethernet", 571 WM_T_82545_3, WMP_F_1000X }, 572 #if 0 573 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 574 "Intel i82545GM Gigabit Ethernet (SERDES)", 575 WM_T_82545_3, WMP_F_SERDES }, 576 #endif 577 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 578 "Intel i82546EB 1000BASE-T Ethernet", 579 WM_T_82546, WMP_F_1000T }, 580 581 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 582 "Intel i82546EB 1000BASE-T Ethernet", 583 WM_T_82546, WMP_F_1000T }, 584 585 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 586 "Intel i82545EM 1000BASE-X Ethernet", 587 WM_T_82545, WMP_F_1000X }, 588 589 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 590 "Intel i82546EB 1000BASE-X Ethernet", 591 WM_T_82546, WMP_F_1000X }, 592 593 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 594 "Intel i82546GB 1000BASE-T Ethernet", 595 WM_T_82546_3, WMP_F_1000T }, 596 597 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 598 "Intel i82546GB 1000BASE-X Ethernet", 599 WM_T_82546_3, WMP_F_1000X }, 600 #if 0 601 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 602 "Intel i82546GB Gigabit Ethernet (SERDES)", 603 WM_T_82546_3, WMP_F_SERDES }, 604 #endif 605 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 606 "Intel i82541EI 1000BASE-T Ethernet", 607 WM_T_82541, WMP_F_1000T }, 608 609 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 610 "Intel i82541EI Mobile 1000BASE-T Ethernet", 611 WM_T_82541, WMP_F_1000T }, 612 613 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 614 "Intel i82541ER 1000BASE-T Ethernet", 615 WM_T_82541_2, WMP_F_1000T }, 616 617 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 618 "Intel i82541GI 1000BASE-T Ethernet", 619 WM_T_82541_2, WMP_F_1000T }, 620 621 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 622 "Intel i82541GI Mobile 1000BASE-T Ethernet", 623 WM_T_82541_2, WMP_F_1000T }, 624 625 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 626 "Intel i82547EI 1000BASE-T Ethernet", 627 WM_T_82547, WMP_F_1000T }, 628 629 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 630 "Intel i82547GI 1000BASE-T Ethernet", 631 WM_T_82547_2, WMP_F_1000T }, 632 { 0, 0, 633 NULL, 634 0, 0 }, 635 }; 636 637 #ifdef WM_EVENT_COUNTERS 638 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 639 #endif /* WM_EVENT_COUNTERS */ 640 641 #if 0 /* Not currently used */ 642 static __inline uint32_t 643 wm_io_read(struct wm_softc *sc, int reg) 644 { 645 646 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 647 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 648 } 649 #endif 650 651 static __inline void 652 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 653 { 654 655 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 656 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 657 } 658 659 static __inline void 660 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 661 { 662 wa->wa_low = htole32(v & 0xffffffffU); 663 if (sizeof(bus_addr_t) == 8) 664 wa->wa_high = htole32((uint64_t) v >> 32); 665 else 666 wa->wa_high = 0; 667 } 668 669 static const struct wm_product * 670 wm_lookup(const struct pci_attach_args *pa) 671 { 672 const struct wm_product *wmp; 673 674 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 675 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 676 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 677 return (wmp); 678 } 679 return (NULL); 680 } 681 682 static int 683 wm_match(struct device *parent, struct cfdata *cf, void *aux) 684 { 685 struct pci_attach_args *pa = aux; 686 687 if (wm_lookup(pa) != NULL) 688 return (1); 689 690 return (0); 691 } 692 693 static void 694 wm_attach(struct device *parent, struct device *self, void *aux) 695 { 696 struct wm_softc *sc = (void *) self; 697 struct pci_attach_args *pa = aux; 698 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 699 pci_chipset_tag_t pc = pa->pa_pc; 700 pci_intr_handle_t ih; 701 size_t cdata_size; 702 const char *intrstr = NULL; 703 const char *eetype; 704 bus_space_tag_t memt; 705 bus_space_handle_t memh; 706 bus_dma_segment_t seg; 707 int memh_valid; 708 int i, rseg, error; 709 const struct wm_product *wmp; 710 uint8_t enaddr[ETHER_ADDR_LEN]; 711 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 712 pcireg_t preg, memtype; 713 uint32_t reg; 714 int pmreg; 715 716 callout_init(&sc->sc_tick_ch); 717 718 wmp = wm_lookup(pa); 719 if (wmp == NULL) { 720 printf("\n"); 721 panic("wm_attach: impossible"); 722 } 723 724 if (pci_dma64_available(pa)) 725 sc->sc_dmat = pa->pa_dmat64; 726 else 727 sc->sc_dmat = pa->pa_dmat; 728 729 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 730 aprint_naive(": Ethernet controller\n"); 731 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 732 733 sc->sc_type = wmp->wmp_type; 734 if (sc->sc_type < WM_T_82543) { 735 if (preg < 2) { 736 aprint_error("%s: i82542 must be at least rev. 2\n", 737 sc->sc_dev.dv_xname); 738 return; 739 } 740 if (preg < 3) 741 sc->sc_type = WM_T_82542_2_0; 742 } 743 744 /* 745 * Map the device. All devices support memory-mapped acccess, 746 * and it is really required for normal operation. 747 */ 748 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 749 switch (memtype) { 750 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 751 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 752 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 753 memtype, 0, &memt, &memh, NULL, NULL) == 0); 754 break; 755 default: 756 memh_valid = 0; 757 } 758 759 if (memh_valid) { 760 sc->sc_st = memt; 761 sc->sc_sh = memh; 762 } else { 763 aprint_error("%s: unable to map device registers\n", 764 sc->sc_dev.dv_xname); 765 return; 766 } 767 768 /* 769 * In addition, i82544 and later support I/O mapped indirect 770 * register access. It is not desirable (nor supported in 771 * this driver) to use it for normal operation, though it is 772 * required to work around bugs in some chip versions. 773 */ 774 if (sc->sc_type >= WM_T_82544) { 775 /* First we have to find the I/O BAR. */ 776 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 777 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 778 PCI_MAPREG_TYPE_IO) 779 break; 780 } 781 if (i == PCI_MAPREG_END) 782 aprint_error("%s: WARNING: unable to find I/O BAR\n", 783 sc->sc_dev.dv_xname); 784 else { 785 /* 786 * The i8254x doesn't apparently respond when the 787 * I/O BAR is 0, which looks somewhat like it's not 788 * been configured. 789 */ 790 preg = pci_conf_read(pc, pa->pa_tag, i); 791 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 792 aprint_error("%s: WARNING: I/O BAR at zero.\n", 793 sc->sc_dev.dv_xname); 794 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 795 0, &sc->sc_iot, &sc->sc_ioh, 796 NULL, NULL) == 0) { 797 sc->sc_flags |= WM_F_IOH_VALID; 798 } else { 799 aprint_error("%s: WARNING: unable to map " 800 "I/O space\n", sc->sc_dev.dv_xname); 801 } 802 } 803 804 } 805 806 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 807 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 808 preg |= PCI_COMMAND_MASTER_ENABLE; 809 if (sc->sc_type < WM_T_82542_2_1) 810 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 811 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 812 813 /* Get it out of power save mode, if needed. */ 814 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 815 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 816 PCI_PMCSR_STATE_MASK; 817 if (preg == PCI_PMCSR_STATE_D3) { 818 /* 819 * The card has lost all configuration data in 820 * this state, so punt. 821 */ 822 aprint_error("%s: unable to wake from power state D3\n", 823 sc->sc_dev.dv_xname); 824 return; 825 } 826 if (preg != PCI_PMCSR_STATE_D0) { 827 aprint_normal("%s: waking up from power state D%d\n", 828 sc->sc_dev.dv_xname, preg); 829 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 830 PCI_PMCSR_STATE_D0); 831 } 832 } 833 834 /* 835 * Map and establish our interrupt. 836 */ 837 if (pci_intr_map(pa, &ih)) { 838 aprint_error("%s: unable to map interrupt\n", 839 sc->sc_dev.dv_xname); 840 return; 841 } 842 intrstr = pci_intr_string(pc, ih); 843 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 844 if (sc->sc_ih == NULL) { 845 aprint_error("%s: unable to establish interrupt", 846 sc->sc_dev.dv_xname); 847 if (intrstr != NULL) 848 aprint_normal(" at %s", intrstr); 849 aprint_normal("\n"); 850 return; 851 } 852 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 853 854 /* 855 * Determine a few things about the bus we're connected to. 856 */ 857 if (sc->sc_type < WM_T_82543) { 858 /* We don't really know the bus characteristics here. */ 859 sc->sc_bus_speed = 33; 860 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 861 /* 862 * CSA (Communication Streaming Architecture) is about as fast 863 * a 32-bit 66MHz PCI Bus. 864 */ 865 sc->sc_flags |= WM_F_CSA; 866 sc->sc_bus_speed = 66; 867 aprint_verbose("%s: Communication Streaming Architecture\n", 868 sc->sc_dev.dv_xname); 869 if (sc->sc_type == WM_T_82547) { 870 callout_init(&sc->sc_txfifo_ch); 871 callout_setfunc(&sc->sc_txfifo_ch, 872 wm_82547_txfifo_stall, sc); 873 aprint_verbose("%s: using 82547 Tx FIFO stall " 874 "work-around\n", sc->sc_dev.dv_xname); 875 } 876 } else { 877 reg = CSR_READ(sc, WMREG_STATUS); 878 if (reg & STATUS_BUS64) 879 sc->sc_flags |= WM_F_BUS64; 880 if (sc->sc_type >= WM_T_82544 && 881 (reg & STATUS_PCIX_MODE) != 0) { 882 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 883 884 sc->sc_flags |= WM_F_PCIX; 885 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 886 PCI_CAP_PCIX, 887 &sc->sc_pcix_offset, NULL) == 0) 888 aprint_error("%s: unable to find PCIX " 889 "capability\n", sc->sc_dev.dv_xname); 890 else if (sc->sc_type != WM_T_82545_3 && 891 sc->sc_type != WM_T_82546_3) { 892 /* 893 * Work around a problem caused by the BIOS 894 * setting the max memory read byte count 895 * incorrectly. 896 */ 897 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 898 sc->sc_pcix_offset + PCI_PCIX_CMD); 899 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 900 sc->sc_pcix_offset + PCI_PCIX_STATUS); 901 902 bytecnt = 903 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 904 PCI_PCIX_CMD_BYTECNT_SHIFT; 905 maxb = 906 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 907 PCI_PCIX_STATUS_MAXB_SHIFT; 908 if (bytecnt > maxb) { 909 aprint_verbose("%s: resetting PCI-X " 910 "MMRBC: %d -> %d\n", 911 sc->sc_dev.dv_xname, 912 512 << bytecnt, 512 << maxb); 913 pcix_cmd = (pcix_cmd & 914 ~PCI_PCIX_CMD_BYTECNT_MASK) | 915 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 916 pci_conf_write(pa->pa_pc, pa->pa_tag, 917 sc->sc_pcix_offset + PCI_PCIX_CMD, 918 pcix_cmd); 919 } 920 } 921 } 922 /* 923 * The quad port adapter is special; it has a PCIX-PCIX 924 * bridge on the board, and can run the secondary bus at 925 * a higher speed. 926 */ 927 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 928 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 929 : 66; 930 } else if (sc->sc_flags & WM_F_PCIX) { 931 switch (reg & STATUS_PCIXSPD_MASK) { 932 case STATUS_PCIXSPD_50_66: 933 sc->sc_bus_speed = 66; 934 break; 935 case STATUS_PCIXSPD_66_100: 936 sc->sc_bus_speed = 100; 937 break; 938 case STATUS_PCIXSPD_100_133: 939 sc->sc_bus_speed = 133; 940 break; 941 default: 942 aprint_error( 943 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 944 sc->sc_dev.dv_xname, 945 reg & STATUS_PCIXSPD_MASK); 946 sc->sc_bus_speed = 66; 947 } 948 } else 949 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 950 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 951 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 952 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 953 } 954 955 /* 956 * Allocate the control data structures, and create and load the 957 * DMA map for it. 958 * 959 * NOTE: All Tx descriptors must be in the same 4G segment of 960 * memory. So must Rx descriptors. We simplify by allocating 961 * both sets within the same 4G segment. 962 */ 963 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 964 WM_NTXDESC_82542 : WM_NTXDESC_82544; 965 cdata_size = sc->sc_type < WM_T_82544 ? 966 sizeof(struct wm_control_data_82542) : 967 sizeof(struct wm_control_data_82544); 968 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 969 (bus_size_t) 0x100000000ULL, 970 &seg, 1, &rseg, 0)) != 0) { 971 aprint_error( 972 "%s: unable to allocate control data, error = %d\n", 973 sc->sc_dev.dv_xname, error); 974 goto fail_0; 975 } 976 977 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 978 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 979 aprint_error("%s: unable to map control data, error = %d\n", 980 sc->sc_dev.dv_xname, error); 981 goto fail_1; 982 } 983 984 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 985 0, 0, &sc->sc_cddmamap)) != 0) { 986 aprint_error("%s: unable to create control data DMA map, " 987 "error = %d\n", sc->sc_dev.dv_xname, error); 988 goto fail_2; 989 } 990 991 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 992 sc->sc_control_data, cdata_size, NULL, 993 0)) != 0) { 994 aprint_error( 995 "%s: unable to load control data DMA map, error = %d\n", 996 sc->sc_dev.dv_xname, error); 997 goto fail_3; 998 } 999 1000 1001 /* 1002 * Create the transmit buffer DMA maps. 1003 */ 1004 WM_TXQUEUELEN(sc) = 1005 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1006 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1007 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1008 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1009 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1010 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1011 aprint_error("%s: unable to create Tx DMA map %d, " 1012 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1013 goto fail_4; 1014 } 1015 } 1016 1017 /* 1018 * Create the receive buffer DMA maps. 1019 */ 1020 for (i = 0; i < WM_NRXDESC; i++) { 1021 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1022 MCLBYTES, 0, 0, 1023 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1024 aprint_error("%s: unable to create Rx DMA map %d, " 1025 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1026 goto fail_5; 1027 } 1028 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1029 } 1030 1031 /* 1032 * Reset the chip to a known state. 1033 */ 1034 wm_reset(sc); 1035 1036 /* 1037 * Get some information about the EEPROM. 1038 */ 1039 if (sc->sc_type >= WM_T_82540) 1040 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1041 if (sc->sc_type <= WM_T_82544) 1042 sc->sc_ee_addrbits = 6; 1043 else if (sc->sc_type <= WM_T_82546_3) { 1044 reg = CSR_READ(sc, WMREG_EECD); 1045 if (reg & EECD_EE_SIZE) 1046 sc->sc_ee_addrbits = 8; 1047 else 1048 sc->sc_ee_addrbits = 6; 1049 } else if (sc->sc_type <= WM_T_82547_2) { 1050 reg = CSR_READ(sc, WMREG_EECD); 1051 if (reg & EECD_EE_TYPE) { 1052 sc->sc_flags |= WM_F_EEPROM_SPI; 1053 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1054 } else 1055 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1056 } else { 1057 /* Assume everything else is SPI. */ 1058 reg = CSR_READ(sc, WMREG_EECD); 1059 sc->sc_flags |= WM_F_EEPROM_SPI; 1060 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1061 } 1062 if (sc->sc_flags & WM_F_EEPROM_SPI) 1063 eetype = "SPI"; 1064 else 1065 eetype = "MicroWire"; 1066 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1067 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1068 sc->sc_ee_addrbits, eetype); 1069 1070 /* 1071 * Read the Ethernet address from the EEPROM. 1072 */ 1073 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1074 sizeof(myea) / sizeof(myea[0]), myea)) { 1075 aprint_error("%s: unable to read Ethernet address\n", 1076 sc->sc_dev.dv_xname); 1077 return; 1078 } 1079 enaddr[0] = myea[0] & 0xff; 1080 enaddr[1] = myea[0] >> 8; 1081 enaddr[2] = myea[1] & 0xff; 1082 enaddr[3] = myea[1] >> 8; 1083 enaddr[4] = myea[2] & 0xff; 1084 enaddr[5] = myea[2] >> 8; 1085 1086 /* 1087 * Toggle the LSB of the MAC address on the second port 1088 * of the i82546. 1089 */ 1090 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1091 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1092 enaddr[5] ^= 1; 1093 } 1094 1095 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1096 ether_sprintf(enaddr)); 1097 1098 /* 1099 * Read the config info from the EEPROM, and set up various 1100 * bits in the control registers based on their contents. 1101 */ 1102 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1103 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1104 sc->sc_dev.dv_xname); 1105 return; 1106 } 1107 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1108 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1109 sc->sc_dev.dv_xname); 1110 return; 1111 } 1112 if (sc->sc_type >= WM_T_82544) { 1113 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1114 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1115 sc->sc_dev.dv_xname); 1116 return; 1117 } 1118 } 1119 1120 if (cfg1 & EEPROM_CFG1_ILOS) 1121 sc->sc_ctrl |= CTRL_ILOS; 1122 if (sc->sc_type >= WM_T_82544) { 1123 sc->sc_ctrl |= 1124 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1125 CTRL_SWDPIO_SHIFT; 1126 sc->sc_ctrl |= 1127 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1128 CTRL_SWDPINS_SHIFT; 1129 } else { 1130 sc->sc_ctrl |= 1131 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1132 CTRL_SWDPIO_SHIFT; 1133 } 1134 1135 #if 0 1136 if (sc->sc_type >= WM_T_82544) { 1137 if (cfg1 & EEPROM_CFG1_IPS0) 1138 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1139 if (cfg1 & EEPROM_CFG1_IPS1) 1140 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1141 sc->sc_ctrl_ext |= 1142 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1143 CTRL_EXT_SWDPIO_SHIFT; 1144 sc->sc_ctrl_ext |= 1145 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1146 CTRL_EXT_SWDPINS_SHIFT; 1147 } else { 1148 sc->sc_ctrl_ext |= 1149 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1150 CTRL_EXT_SWDPIO_SHIFT; 1151 } 1152 #endif 1153 1154 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1155 #if 0 1156 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1157 #endif 1158 1159 /* 1160 * Set up some register offsets that are different between 1161 * the i82542 and the i82543 and later chips. 1162 */ 1163 if (sc->sc_type < WM_T_82543) { 1164 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1165 sc->sc_tdt_reg = WMREG_OLD_TDT; 1166 } else { 1167 sc->sc_rdt_reg = WMREG_RDT; 1168 sc->sc_tdt_reg = WMREG_TDT; 1169 } 1170 1171 /* 1172 * Determine if we're TBI or GMII mode, and initialize the 1173 * media structures accordingly. 1174 */ 1175 if (sc->sc_type < WM_T_82543 || 1176 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1177 if (wmp->wmp_flags & WMP_F_1000T) 1178 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1179 "product!\n", sc->sc_dev.dv_xname); 1180 wm_tbi_mediainit(sc); 1181 } else { 1182 if (wmp->wmp_flags & WMP_F_1000X) 1183 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1184 "product!\n", sc->sc_dev.dv_xname); 1185 wm_gmii_mediainit(sc); 1186 } 1187 1188 ifp = &sc->sc_ethercom.ec_if; 1189 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1190 ifp->if_softc = sc; 1191 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1192 ifp->if_ioctl = wm_ioctl; 1193 ifp->if_start = wm_start; 1194 ifp->if_watchdog = wm_watchdog; 1195 ifp->if_init = wm_init; 1196 ifp->if_stop = wm_stop; 1197 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1198 IFQ_SET_READY(&ifp->if_snd); 1199 1200 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1201 1202 /* 1203 * If we're a i82543 or greater, we can support VLANs. 1204 */ 1205 if (sc->sc_type >= WM_T_82543) 1206 sc->sc_ethercom.ec_capabilities |= 1207 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1208 1209 /* 1210 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1211 * on i82543 and later. 1212 */ 1213 if (sc->sc_type >= WM_T_82543) 1214 ifp->if_capabilities |= 1215 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1216 1217 /* 1218 * Attach the interface. 1219 */ 1220 if_attach(ifp); 1221 ether_ifattach(ifp, enaddr); 1222 #if NRND > 0 1223 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1224 RND_TYPE_NET, 0); 1225 #endif 1226 1227 #ifdef WM_EVENT_COUNTERS 1228 /* Attach event counters. */ 1229 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1230 NULL, sc->sc_dev.dv_xname, "txsstall"); 1231 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1232 NULL, sc->sc_dev.dv_xname, "txdstall"); 1233 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1234 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1235 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1236 NULL, sc->sc_dev.dv_xname, "txdw"); 1237 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1238 NULL, sc->sc_dev.dv_xname, "txqe"); 1239 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1240 NULL, sc->sc_dev.dv_xname, "rxintr"); 1241 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1242 NULL, sc->sc_dev.dv_xname, "linkintr"); 1243 1244 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1245 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1246 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1247 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1248 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1249 NULL, sc->sc_dev.dv_xname, "txipsum"); 1250 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1251 NULL, sc->sc_dev.dv_xname, "txtusum"); 1252 1253 for (i = 0; i < WM_NTXSEGS; i++) { 1254 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1255 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1256 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1257 } 1258 1259 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1260 NULL, sc->sc_dev.dv_xname, "txdrop"); 1261 1262 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1263 NULL, sc->sc_dev.dv_xname, "tu"); 1264 1265 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1266 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1267 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1268 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1269 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1270 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1271 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1272 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1273 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1274 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1275 #endif /* WM_EVENT_COUNTERS */ 1276 1277 /* 1278 * Make sure the interface is shutdown during reboot. 1279 */ 1280 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1281 if (sc->sc_sdhook == NULL) 1282 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1283 sc->sc_dev.dv_xname); 1284 return; 1285 1286 /* 1287 * Free any resources we've allocated during the failed attach 1288 * attempt. Do this in reverse order and fall through. 1289 */ 1290 fail_5: 1291 for (i = 0; i < WM_NRXDESC; i++) { 1292 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1293 bus_dmamap_destroy(sc->sc_dmat, 1294 sc->sc_rxsoft[i].rxs_dmamap); 1295 } 1296 fail_4: 1297 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1298 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1299 bus_dmamap_destroy(sc->sc_dmat, 1300 sc->sc_txsoft[i].txs_dmamap); 1301 } 1302 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1303 fail_3: 1304 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1305 fail_2: 1306 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1307 cdata_size); 1308 fail_1: 1309 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1310 fail_0: 1311 return; 1312 } 1313 1314 /* 1315 * wm_shutdown: 1316 * 1317 * Make sure the interface is stopped at reboot time. 1318 */ 1319 static void 1320 wm_shutdown(void *arg) 1321 { 1322 struct wm_softc *sc = arg; 1323 1324 wm_stop(&sc->sc_ethercom.ec_if, 1); 1325 } 1326 1327 /* 1328 * wm_tx_offload: 1329 * 1330 * Set up TCP/IP checksumming parameters for the 1331 * specified packet. 1332 */ 1333 static int 1334 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1335 uint8_t *fieldsp) 1336 { 1337 struct mbuf *m0 = txs->txs_mbuf; 1338 struct livengood_tcpip_ctxdesc *t; 1339 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1340 struct ether_header *eh; 1341 int offset, iphl; 1342 uint8_t fields; 1343 1344 /* 1345 * XXX It would be nice if the mbuf pkthdr had offset 1346 * fields for the protocol headers. 1347 */ 1348 1349 eh = mtod(m0, struct ether_header *); 1350 switch (htons(eh->ether_type)) { 1351 case ETHERTYPE_IP: 1352 offset = ETHER_HDR_LEN; 1353 break; 1354 1355 case ETHERTYPE_VLAN: 1356 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1357 break; 1358 1359 default: 1360 /* 1361 * Don't support this protocol or encapsulation. 1362 */ 1363 *fieldsp = 0; 1364 *cmdp = 0; 1365 return (0); 1366 } 1367 1368 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1369 1370 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1371 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1372 seg = 0; 1373 fields = 0; 1374 1375 /* 1376 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1377 * offload feature, if we load the context descriptor, we 1378 * MUST provide valid values for IPCSS and TUCSS fields. 1379 */ 1380 1381 ipcs = WTX_TCPIP_IPCSS(offset) | 1382 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1383 WTX_TCPIP_IPCSE(offset + iphl - 1); 1384 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1385 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1386 fields |= WTX_IXSM; 1387 } 1388 1389 offset += iphl; 1390 1391 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1392 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1393 fields |= WTX_TXSM; 1394 tucs = WTX_TCPIP_TUCSS(offset) | 1395 WTX_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1396 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1397 } else { 1398 /* Just initialize it to a valid TCP context. */ 1399 tucs = WTX_TCPIP_TUCSS(offset) | 1400 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1401 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1402 } 1403 1404 /* Fill in the context descriptor. */ 1405 t = (struct livengood_tcpip_ctxdesc *) 1406 &sc->sc_txdescs[sc->sc_txnext]; 1407 t->tcpip_ipcs = htole32(ipcs); 1408 t->tcpip_tucs = htole32(tucs); 1409 t->tcpip_cmdlen = htole32(cmdlen); 1410 t->tcpip_seg = htole32(seg); 1411 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1412 1413 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1414 txs->txs_ndesc++; 1415 1416 *cmdp = cmd; 1417 *fieldsp = fields; 1418 1419 return (0); 1420 } 1421 1422 static void 1423 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1424 { 1425 struct mbuf *m; 1426 int i; 1427 1428 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1429 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1430 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1431 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1432 m->m_data, m->m_len, m->m_flags); 1433 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1434 i, i == 1 ? "" : "s"); 1435 } 1436 1437 /* 1438 * wm_82547_txfifo_stall: 1439 * 1440 * Callout used to wait for the 82547 Tx FIFO to drain, 1441 * reset the FIFO pointers, and restart packet transmission. 1442 */ 1443 static void 1444 wm_82547_txfifo_stall(void *arg) 1445 { 1446 struct wm_softc *sc = arg; 1447 int s; 1448 1449 s = splnet(); 1450 1451 if (sc->sc_txfifo_stall) { 1452 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1453 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1454 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1455 /* 1456 * Packets have drained. Stop transmitter, reset 1457 * FIFO pointers, restart transmitter, and kick 1458 * the packet queue. 1459 */ 1460 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1461 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1462 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1463 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1464 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1465 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1466 CSR_WRITE(sc, WMREG_TCTL, tctl); 1467 CSR_WRITE_FLUSH(sc); 1468 1469 sc->sc_txfifo_head = 0; 1470 sc->sc_txfifo_stall = 0; 1471 wm_start(&sc->sc_ethercom.ec_if); 1472 } else { 1473 /* 1474 * Still waiting for packets to drain; try again in 1475 * another tick. 1476 */ 1477 callout_schedule(&sc->sc_txfifo_ch, 1); 1478 } 1479 } 1480 1481 splx(s); 1482 } 1483 1484 /* 1485 * wm_82547_txfifo_bugchk: 1486 * 1487 * Check for bug condition in the 82547 Tx FIFO. We need to 1488 * prevent enqueueing a packet that would wrap around the end 1489 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1490 * 1491 * We do this by checking the amount of space before the end 1492 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1493 * the Tx FIFO, wait for all remaining packets to drain, reset 1494 * the internal FIFO pointers to the beginning, and restart 1495 * transmission on the interface. 1496 */ 1497 #define WM_FIFO_HDR 0x10 1498 #define WM_82547_PAD_LEN 0x3e0 1499 static int 1500 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1501 { 1502 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1503 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1504 1505 /* Just return if already stalled. */ 1506 if (sc->sc_txfifo_stall) 1507 return (1); 1508 1509 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1510 /* Stall only occurs in half-duplex mode. */ 1511 goto send_packet; 1512 } 1513 1514 if (len >= WM_82547_PAD_LEN + space) { 1515 sc->sc_txfifo_stall = 1; 1516 callout_schedule(&sc->sc_txfifo_ch, 1); 1517 return (1); 1518 } 1519 1520 send_packet: 1521 sc->sc_txfifo_head += len; 1522 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1523 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1524 1525 return (0); 1526 } 1527 1528 /* 1529 * wm_start: [ifnet interface function] 1530 * 1531 * Start packet transmission on the interface. 1532 */ 1533 static void 1534 wm_start(struct ifnet *ifp) 1535 { 1536 struct wm_softc *sc = ifp->if_softc; 1537 struct mbuf *m0; 1538 #if 0 /* XXXJRT */ 1539 struct m_tag *mtag; 1540 #endif 1541 struct wm_txsoft *txs; 1542 bus_dmamap_t dmamap; 1543 int error, nexttx, lasttx = -1, ofree, seg, segs_needed; 1544 bus_addr_t curaddr; 1545 bus_size_t seglen, curlen; 1546 uint32_t cksumcmd; 1547 uint8_t cksumfields; 1548 1549 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1550 return; 1551 1552 /* 1553 * Remember the previous number of free descriptors. 1554 */ 1555 ofree = sc->sc_txfree; 1556 1557 /* 1558 * Loop through the send queue, setting up transmit descriptors 1559 * until we drain the queue, or use up all available transmit 1560 * descriptors. 1561 */ 1562 for (;;) { 1563 /* Grab a packet off the queue. */ 1564 IFQ_POLL(&ifp->if_snd, m0); 1565 if (m0 == NULL) 1566 break; 1567 1568 DPRINTF(WM_DEBUG_TX, 1569 ("%s: TX: have packet to transmit: %p\n", 1570 sc->sc_dev.dv_xname, m0)); 1571 1572 /* Get a work queue entry. */ 1573 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1574 wm_txintr(sc); 1575 if (sc->sc_txsfree == 0) { 1576 DPRINTF(WM_DEBUG_TX, 1577 ("%s: TX: no free job descriptors\n", 1578 sc->sc_dev.dv_xname)); 1579 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1580 break; 1581 } 1582 } 1583 1584 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1585 dmamap = txs->txs_dmamap; 1586 1587 /* 1588 * Load the DMA map. If this fails, the packet either 1589 * didn't fit in the allotted number of segments, or we 1590 * were short on resources. For the too-many-segments 1591 * case, we simply report an error and drop the packet, 1592 * since we can't sanely copy a jumbo packet to a single 1593 * buffer. 1594 */ 1595 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1596 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1597 if (error) { 1598 if (error == EFBIG) { 1599 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1600 log(LOG_ERR, "%s: Tx packet consumes too many " 1601 "DMA segments, dropping...\n", 1602 sc->sc_dev.dv_xname); 1603 IFQ_DEQUEUE(&ifp->if_snd, m0); 1604 wm_dump_mbuf_chain(sc, m0); 1605 m_freem(m0); 1606 continue; 1607 } 1608 /* 1609 * Short on resources, just stop for now. 1610 */ 1611 DPRINTF(WM_DEBUG_TX, 1612 ("%s: TX: dmamap load failed: %d\n", 1613 sc->sc_dev.dv_xname, error)); 1614 break; 1615 } 1616 1617 segs_needed = dmamap->dm_nsegs; 1618 1619 /* 1620 * Ensure we have enough descriptors free to describe 1621 * the packet. Note, we always reserve one descriptor 1622 * at the end of the ring due to the semantics of the 1623 * TDT register, plus one more in the event we need 1624 * to load offload context. 1625 */ 1626 if (segs_needed > sc->sc_txfree - 2) { 1627 /* 1628 * Not enough free descriptors to transmit this 1629 * packet. We haven't committed anything yet, 1630 * so just unload the DMA map, put the packet 1631 * pack on the queue, and punt. Notify the upper 1632 * layer that there are no more slots left. 1633 */ 1634 DPRINTF(WM_DEBUG_TX, 1635 ("%s: TX: need %d (%) descriptors, have %d\n", 1636 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1637 sc->sc_txfree - 1)); 1638 ifp->if_flags |= IFF_OACTIVE; 1639 bus_dmamap_unload(sc->sc_dmat, dmamap); 1640 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1641 break; 1642 } 1643 1644 /* 1645 * Check for 82547 Tx FIFO bug. We need to do this 1646 * once we know we can transmit the packet, since we 1647 * do some internal FIFO space accounting here. 1648 */ 1649 if (sc->sc_type == WM_T_82547 && 1650 wm_82547_txfifo_bugchk(sc, m0)) { 1651 DPRINTF(WM_DEBUG_TX, 1652 ("%s: TX: 82547 Tx FIFO bug detected\n", 1653 sc->sc_dev.dv_xname)); 1654 ifp->if_flags |= IFF_OACTIVE; 1655 bus_dmamap_unload(sc->sc_dmat, dmamap); 1656 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1657 break; 1658 } 1659 1660 IFQ_DEQUEUE(&ifp->if_snd, m0); 1661 1662 /* 1663 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1664 */ 1665 1666 DPRINTF(WM_DEBUG_TX, 1667 ("%s: TX: packet has %d (%d) DMA segments\n", 1668 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1669 1670 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1671 1672 /* 1673 * Store a pointer to the packet so that we can free it 1674 * later. 1675 * 1676 * Initially, we consider the number of descriptors the 1677 * packet uses the number of DMA segments. This may be 1678 * incremented by 1 if we do checksum offload (a descriptor 1679 * is used to set the checksum context). 1680 */ 1681 txs->txs_mbuf = m0; 1682 txs->txs_firstdesc = sc->sc_txnext; 1683 txs->txs_ndesc = segs_needed; 1684 1685 /* Set up offload parameters for this packet. */ 1686 if (m0->m_pkthdr.csum_flags & 1687 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1688 if (wm_tx_offload(sc, txs, &cksumcmd, 1689 &cksumfields) != 0) { 1690 /* Error message already displayed. */ 1691 bus_dmamap_unload(sc->sc_dmat, dmamap); 1692 continue; 1693 } 1694 } else { 1695 cksumcmd = 0; 1696 cksumfields = 0; 1697 } 1698 1699 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1700 1701 /* Sync the DMA map. */ 1702 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1703 BUS_DMASYNC_PREWRITE); 1704 1705 /* 1706 * Initialize the transmit descriptor. 1707 */ 1708 for (nexttx = sc->sc_txnext, seg = 0; 1709 seg < dmamap->dm_nsegs; seg++) { 1710 for (seglen = dmamap->dm_segs[seg].ds_len, 1711 curaddr = dmamap->dm_segs[seg].ds_addr; 1712 seglen != 0; 1713 curaddr += curlen, seglen -= curlen, 1714 nexttx = WM_NEXTTX(sc, nexttx)) { 1715 curlen = seglen; 1716 1717 wm_set_dma_addr( 1718 &sc->sc_txdescs[nexttx].wtx_addr, 1719 curaddr); 1720 sc->sc_txdescs[nexttx].wtx_cmdlen = 1721 htole32(cksumcmd | curlen); 1722 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1723 0; 1724 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1725 cksumfields; 1726 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1727 lasttx = nexttx; 1728 1729 DPRINTF(WM_DEBUG_TX, 1730 ("%s: TX: desc %d: low 0x%08x, " 1731 "len 0x%04x\n", 1732 sc->sc_dev.dv_xname, nexttx, 1733 curaddr & 0xffffffffU, curlen, curlen)); 1734 } 1735 } 1736 1737 KASSERT(lasttx != -1); 1738 1739 /* 1740 * Set up the command byte on the last descriptor of 1741 * the packet. If we're in the interrupt delay window, 1742 * delay the interrupt. 1743 */ 1744 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1745 htole32(WTX_CMD_EOP | WTX_CMD_RS); 1746 1747 #if 0 /* XXXJRT */ 1748 /* 1749 * If VLANs are enabled and the packet has a VLAN tag, set 1750 * up the descriptor to encapsulate the packet for us. 1751 * 1752 * This is only valid on the last descriptor of the packet. 1753 */ 1754 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1755 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1756 htole32(WTX_CMD_VLE); 1757 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1758 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 1759 } 1760 #endif /* XXXJRT */ 1761 1762 txs->txs_lastdesc = lasttx; 1763 1764 DPRINTF(WM_DEBUG_TX, 1765 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1766 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1767 1768 /* Sync the descriptors we're using. */ 1769 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1770 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1771 1772 /* Give the packet to the chip. */ 1773 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1774 1775 DPRINTF(WM_DEBUG_TX, 1776 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1777 1778 DPRINTF(WM_DEBUG_TX, 1779 ("%s: TX: finished transmitting packet, job %d\n", 1780 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1781 1782 /* Advance the tx pointer. */ 1783 sc->sc_txfree -= txs->txs_ndesc; 1784 sc->sc_txnext = nexttx; 1785 1786 sc->sc_txsfree--; 1787 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1788 1789 #if NBPFILTER > 0 1790 /* Pass the packet to any BPF listeners. */ 1791 if (ifp->if_bpf) 1792 bpf_mtap(ifp->if_bpf, m0); 1793 #endif /* NBPFILTER > 0 */ 1794 } 1795 1796 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1797 /* No more slots; notify upper layer. */ 1798 ifp->if_flags |= IFF_OACTIVE; 1799 } 1800 1801 if (sc->sc_txfree != ofree) { 1802 /* Set a watchdog timer in case the chip flakes out. */ 1803 ifp->if_timer = 5; 1804 } 1805 } 1806 1807 /* 1808 * wm_watchdog: [ifnet interface function] 1809 * 1810 * Watchdog timer handler. 1811 */ 1812 static void 1813 wm_watchdog(struct ifnet *ifp) 1814 { 1815 struct wm_softc *sc = ifp->if_softc; 1816 1817 /* 1818 * Since we're using delayed interrupts, sweep up 1819 * before we report an error. 1820 */ 1821 wm_txintr(sc); 1822 1823 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1824 log(LOG_ERR, 1825 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1826 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1827 sc->sc_txnext); 1828 ifp->if_oerrors++; 1829 1830 /* Reset the interface. */ 1831 (void) wm_init(ifp); 1832 } 1833 1834 /* Try to get more packets going. */ 1835 wm_start(ifp); 1836 } 1837 1838 /* 1839 * wm_ioctl: [ifnet interface function] 1840 * 1841 * Handle control requests from the operator. 1842 */ 1843 static int 1844 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1845 { 1846 struct wm_softc *sc = ifp->if_softc; 1847 struct ifreq *ifr = (struct ifreq *) data; 1848 int s, error; 1849 1850 s = splnet(); 1851 1852 switch (cmd) { 1853 case SIOCSIFMEDIA: 1854 case SIOCGIFMEDIA: 1855 /* Flow control requires full-duplex mode. */ 1856 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1857 (ifr->ifr_media & IFM_FDX) == 0) 1858 ifr->ifr_media &= ~IFM_ETH_FMASK; 1859 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1860 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1861 /* We can do both TXPAUSE and RXPAUSE. */ 1862 ifr->ifr_media |= 1863 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1864 } 1865 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1866 } 1867 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1868 break; 1869 default: 1870 error = ether_ioctl(ifp, cmd, data); 1871 if (error == ENETRESET) { 1872 /* 1873 * Multicast list has changed; set the hardware filter 1874 * accordingly. 1875 */ 1876 if (ifp->if_flags & IFF_RUNNING) 1877 wm_set_filter(sc); 1878 error = 0; 1879 } 1880 break; 1881 } 1882 1883 /* Try to get more packets going. */ 1884 wm_start(ifp); 1885 1886 splx(s); 1887 return (error); 1888 } 1889 1890 /* 1891 * wm_intr: 1892 * 1893 * Interrupt service routine. 1894 */ 1895 static int 1896 wm_intr(void *arg) 1897 { 1898 struct wm_softc *sc = arg; 1899 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1900 uint32_t icr; 1901 int wantinit, handled = 0; 1902 1903 for (wantinit = 0; wantinit == 0;) { 1904 icr = CSR_READ(sc, WMREG_ICR); 1905 if ((icr & sc->sc_icr) == 0) 1906 break; 1907 1908 #if 0 /*NRND > 0*/ 1909 if (RND_ENABLED(&sc->rnd_source)) 1910 rnd_add_uint32(&sc->rnd_source, icr); 1911 #endif 1912 1913 handled = 1; 1914 1915 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1916 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1917 DPRINTF(WM_DEBUG_RX, 1918 ("%s: RX: got Rx intr 0x%08x\n", 1919 sc->sc_dev.dv_xname, 1920 icr & (ICR_RXDMT0|ICR_RXT0))); 1921 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 1922 } 1923 #endif 1924 wm_rxintr(sc); 1925 1926 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1927 if (icr & ICR_TXDW) { 1928 DPRINTF(WM_DEBUG_TX, 1929 ("%s: TX: got TXDW interrupt\n", 1930 sc->sc_dev.dv_xname)); 1931 WM_EVCNT_INCR(&sc->sc_ev_txdw); 1932 } 1933 #endif 1934 wm_txintr(sc); 1935 1936 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 1937 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 1938 wm_linkintr(sc, icr); 1939 } 1940 1941 if (icr & ICR_RXO) { 1942 log(LOG_WARNING, "%s: Receive overrun\n", 1943 sc->sc_dev.dv_xname); 1944 wantinit = 1; 1945 } 1946 } 1947 1948 if (handled) { 1949 if (wantinit) 1950 wm_init(ifp); 1951 1952 /* Try to get more packets going. */ 1953 wm_start(ifp); 1954 } 1955 1956 return (handled); 1957 } 1958 1959 /* 1960 * wm_txintr: 1961 * 1962 * Helper; handle transmit interrupts. 1963 */ 1964 static void 1965 wm_txintr(struct wm_softc *sc) 1966 { 1967 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1968 struct wm_txsoft *txs; 1969 uint8_t status; 1970 int i; 1971 1972 ifp->if_flags &= ~IFF_OACTIVE; 1973 1974 /* 1975 * Go through the Tx list and free mbufs for those 1976 * frames which have been transmitted. 1977 */ 1978 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 1979 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 1980 txs = &sc->sc_txsoft[i]; 1981 1982 DPRINTF(WM_DEBUG_TX, 1983 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 1984 1985 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 1986 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1987 1988 status = 1989 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 1990 if ((status & WTX_ST_DD) == 0) { 1991 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1992 BUS_DMASYNC_PREREAD); 1993 break; 1994 } 1995 1996 DPRINTF(WM_DEBUG_TX, 1997 ("%s: TX: job %d done: descs %d..%d\n", 1998 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 1999 txs->txs_lastdesc)); 2000 2001 /* 2002 * XXX We should probably be using the statistics 2003 * XXX registers, but I don't know if they exist 2004 * XXX on chips before the i82544. 2005 */ 2006 2007 #ifdef WM_EVENT_COUNTERS 2008 if (status & WTX_ST_TU) 2009 WM_EVCNT_INCR(&sc->sc_ev_tu); 2010 #endif /* WM_EVENT_COUNTERS */ 2011 2012 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2013 ifp->if_oerrors++; 2014 if (status & WTX_ST_LC) 2015 log(LOG_WARNING, "%s: late collision\n", 2016 sc->sc_dev.dv_xname); 2017 else if (status & WTX_ST_EC) { 2018 ifp->if_collisions += 16; 2019 log(LOG_WARNING, "%s: excessive collisions\n", 2020 sc->sc_dev.dv_xname); 2021 } 2022 } else 2023 ifp->if_opackets++; 2024 2025 sc->sc_txfree += txs->txs_ndesc; 2026 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2027 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2028 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2029 m_freem(txs->txs_mbuf); 2030 txs->txs_mbuf = NULL; 2031 } 2032 2033 /* Update the dirty transmit buffer pointer. */ 2034 sc->sc_txsdirty = i; 2035 DPRINTF(WM_DEBUG_TX, 2036 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2037 2038 /* 2039 * If there are no more pending transmissions, cancel the watchdog 2040 * timer. 2041 */ 2042 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2043 ifp->if_timer = 0; 2044 } 2045 2046 /* 2047 * wm_rxintr: 2048 * 2049 * Helper; handle receive interrupts. 2050 */ 2051 static void 2052 wm_rxintr(struct wm_softc *sc) 2053 { 2054 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2055 struct wm_rxsoft *rxs; 2056 struct mbuf *m; 2057 int i, len; 2058 uint8_t status, errors; 2059 2060 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2061 rxs = &sc->sc_rxsoft[i]; 2062 2063 DPRINTF(WM_DEBUG_RX, 2064 ("%s: RX: checking descriptor %d\n", 2065 sc->sc_dev.dv_xname, i)); 2066 2067 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2068 2069 status = sc->sc_rxdescs[i].wrx_status; 2070 errors = sc->sc_rxdescs[i].wrx_errors; 2071 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2072 2073 if ((status & WRX_ST_DD) == 0) { 2074 /* 2075 * We have processed all of the receive descriptors. 2076 */ 2077 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2078 break; 2079 } 2080 2081 if (__predict_false(sc->sc_rxdiscard)) { 2082 DPRINTF(WM_DEBUG_RX, 2083 ("%s: RX: discarding contents of descriptor %d\n", 2084 sc->sc_dev.dv_xname, i)); 2085 WM_INIT_RXDESC(sc, i); 2086 if (status & WRX_ST_EOP) { 2087 /* Reset our state. */ 2088 DPRINTF(WM_DEBUG_RX, 2089 ("%s: RX: resetting rxdiscard -> 0\n", 2090 sc->sc_dev.dv_xname)); 2091 sc->sc_rxdiscard = 0; 2092 } 2093 continue; 2094 } 2095 2096 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2097 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2098 2099 m = rxs->rxs_mbuf; 2100 2101 /* 2102 * Add a new receive buffer to the ring. 2103 */ 2104 if (wm_add_rxbuf(sc, i) != 0) { 2105 /* 2106 * Failed, throw away what we've done so 2107 * far, and discard the rest of the packet. 2108 */ 2109 ifp->if_ierrors++; 2110 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2111 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2112 WM_INIT_RXDESC(sc, i); 2113 if ((status & WRX_ST_EOP) == 0) 2114 sc->sc_rxdiscard = 1; 2115 if (sc->sc_rxhead != NULL) 2116 m_freem(sc->sc_rxhead); 2117 WM_RXCHAIN_RESET(sc); 2118 DPRINTF(WM_DEBUG_RX, 2119 ("%s: RX: Rx buffer allocation failed, " 2120 "dropping packet%s\n", sc->sc_dev.dv_xname, 2121 sc->sc_rxdiscard ? " (discard)" : "")); 2122 continue; 2123 } 2124 2125 WM_RXCHAIN_LINK(sc, m); 2126 2127 m->m_len = len; 2128 2129 DPRINTF(WM_DEBUG_RX, 2130 ("%s: RX: buffer at %p len %d\n", 2131 sc->sc_dev.dv_xname, m->m_data, len)); 2132 2133 /* 2134 * If this is not the end of the packet, keep 2135 * looking. 2136 */ 2137 if ((status & WRX_ST_EOP) == 0) { 2138 sc->sc_rxlen += len; 2139 DPRINTF(WM_DEBUG_RX, 2140 ("%s: RX: not yet EOP, rxlen -> %d\n", 2141 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2142 continue; 2143 } 2144 2145 /* 2146 * Okay, we have the entire packet now. The chip is 2147 * configured to include the FCS (not all chips can 2148 * be configured to strip it), so we need to trim it. 2149 */ 2150 m->m_len -= ETHER_CRC_LEN; 2151 2152 *sc->sc_rxtailp = NULL; 2153 m = sc->sc_rxhead; 2154 len = m->m_len + sc->sc_rxlen; 2155 2156 WM_RXCHAIN_RESET(sc); 2157 2158 DPRINTF(WM_DEBUG_RX, 2159 ("%s: RX: have entire packet, len -> %d\n", 2160 sc->sc_dev.dv_xname, len)); 2161 2162 /* 2163 * If an error occurred, update stats and drop the packet. 2164 */ 2165 if (errors & 2166 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2167 ifp->if_ierrors++; 2168 if (errors & WRX_ER_SE) 2169 log(LOG_WARNING, "%s: symbol error\n", 2170 sc->sc_dev.dv_xname); 2171 else if (errors & WRX_ER_SEQ) 2172 log(LOG_WARNING, "%s: receive sequence error\n", 2173 sc->sc_dev.dv_xname); 2174 else if (errors & WRX_ER_CE) 2175 log(LOG_WARNING, "%s: CRC error\n", 2176 sc->sc_dev.dv_xname); 2177 m_freem(m); 2178 continue; 2179 } 2180 2181 /* 2182 * No errors. Receive the packet. 2183 */ 2184 m->m_pkthdr.rcvif = ifp; 2185 m->m_pkthdr.len = len; 2186 2187 #if 0 /* XXXJRT */ 2188 /* 2189 * If VLANs are enabled, VLAN packets have been unwrapped 2190 * for us. Associate the tag with the packet. 2191 */ 2192 if ((status & WRX_ST_VP) != 0) { 2193 VLAN_INPUT_TAG(ifp, m, 2194 le16toh(sc->sc_rxdescs[i].wrx_special, 2195 continue); 2196 } 2197 #endif /* XXXJRT */ 2198 2199 /* 2200 * Set up checksum info for this packet. 2201 */ 2202 if (status & WRX_ST_IPCS) { 2203 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2204 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2205 if (errors & WRX_ER_IPE) 2206 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2207 } 2208 if (status & WRX_ST_TCPCS) { 2209 /* 2210 * Note: we don't know if this was TCP or UDP, 2211 * so we just set both bits, and expect the 2212 * upper layers to deal. 2213 */ 2214 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2215 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2216 if (errors & WRX_ER_TCPE) 2217 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2218 } 2219 2220 ifp->if_ipackets++; 2221 2222 #if NBPFILTER > 0 2223 /* Pass this up to any BPF listeners. */ 2224 if (ifp->if_bpf) 2225 bpf_mtap(ifp->if_bpf, m); 2226 #endif /* NBPFILTER > 0 */ 2227 2228 /* Pass it on. */ 2229 (*ifp->if_input)(ifp, m); 2230 } 2231 2232 /* Update the receive pointer. */ 2233 sc->sc_rxptr = i; 2234 2235 DPRINTF(WM_DEBUG_RX, 2236 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2237 } 2238 2239 /* 2240 * wm_linkintr: 2241 * 2242 * Helper; handle link interrupts. 2243 */ 2244 static void 2245 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2246 { 2247 uint32_t status; 2248 2249 /* 2250 * If we get a link status interrupt on a 1000BASE-T 2251 * device, just fall into the normal MII tick path. 2252 */ 2253 if (sc->sc_flags & WM_F_HAS_MII) { 2254 if (icr & ICR_LSC) { 2255 DPRINTF(WM_DEBUG_LINK, 2256 ("%s: LINK: LSC -> mii_tick\n", 2257 sc->sc_dev.dv_xname)); 2258 mii_tick(&sc->sc_mii); 2259 } else if (icr & ICR_RXSEQ) { 2260 DPRINTF(WM_DEBUG_LINK, 2261 ("%s: LINK Receive sequence error\n", 2262 sc->sc_dev.dv_xname)); 2263 } 2264 return; 2265 } 2266 2267 /* 2268 * If we are now receiving /C/, check for link again in 2269 * a couple of link clock ticks. 2270 */ 2271 if (icr & ICR_RXCFG) { 2272 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2273 sc->sc_dev.dv_xname)); 2274 sc->sc_tbi_anstate = 2; 2275 } 2276 2277 if (icr & ICR_LSC) { 2278 status = CSR_READ(sc, WMREG_STATUS); 2279 if (status & STATUS_LU) { 2280 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2281 sc->sc_dev.dv_xname, 2282 (status & STATUS_FD) ? "FDX" : "HDX")); 2283 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2284 sc->sc_fcrtl &= ~FCRTL_XONE; 2285 if (status & STATUS_FD) 2286 sc->sc_tctl |= 2287 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2288 else 2289 sc->sc_tctl |= 2290 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2291 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2292 sc->sc_fcrtl |= FCRTL_XONE; 2293 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2294 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2295 WMREG_OLD_FCRTL : WMREG_FCRTL, 2296 sc->sc_fcrtl); 2297 sc->sc_tbi_linkup = 1; 2298 } else { 2299 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2300 sc->sc_dev.dv_xname)); 2301 sc->sc_tbi_linkup = 0; 2302 } 2303 sc->sc_tbi_anstate = 2; 2304 wm_tbi_set_linkled(sc); 2305 } else if (icr & ICR_RXSEQ) { 2306 DPRINTF(WM_DEBUG_LINK, 2307 ("%s: LINK: Receive sequence error\n", 2308 sc->sc_dev.dv_xname)); 2309 } 2310 } 2311 2312 /* 2313 * wm_tick: 2314 * 2315 * One second timer, used to check link status, sweep up 2316 * completed transmit jobs, etc. 2317 */ 2318 static void 2319 wm_tick(void *arg) 2320 { 2321 struct wm_softc *sc = arg; 2322 int s; 2323 2324 s = splnet(); 2325 2326 if (sc->sc_type >= WM_T_82542_2_1) { 2327 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2328 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2329 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2330 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2331 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2332 } 2333 2334 if (sc->sc_flags & WM_F_HAS_MII) 2335 mii_tick(&sc->sc_mii); 2336 else 2337 wm_tbi_check_link(sc); 2338 2339 splx(s); 2340 2341 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2342 } 2343 2344 /* 2345 * wm_reset: 2346 * 2347 * Reset the i82542 chip. 2348 */ 2349 static void 2350 wm_reset(struct wm_softc *sc) 2351 { 2352 int i; 2353 2354 /* 2355 * Allocate on-chip memory according to the MTU size. 2356 * The Packet Buffer Allocation register must be written 2357 * before the chip is reset. 2358 */ 2359 if (sc->sc_type < WM_T_82547) { 2360 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2361 PBA_40K : PBA_48K; 2362 } else { 2363 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2364 PBA_22K : PBA_30K; 2365 sc->sc_txfifo_head = 0; 2366 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2367 sc->sc_txfifo_size = 2368 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2369 sc->sc_txfifo_stall = 0; 2370 } 2371 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2372 2373 switch (sc->sc_type) { 2374 case WM_T_82544: 2375 case WM_T_82540: 2376 case WM_T_82545: 2377 case WM_T_82546: 2378 case WM_T_82541: 2379 case WM_T_82541_2: 2380 /* 2381 * On some chipsets, a reset through a memory-mapped write 2382 * cycle can cause the chip to reset before completing the 2383 * write cycle. This causes major headache that can be 2384 * avoided by issuing the reset via indirect register writes 2385 * through I/O space. 2386 * 2387 * So, if we successfully mapped the I/O BAR at attach time, 2388 * use that. Otherwise, try our luck with a memory-mapped 2389 * reset. 2390 */ 2391 if (sc->sc_flags & WM_F_IOH_VALID) 2392 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2393 else 2394 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2395 break; 2396 2397 case WM_T_82545_3: 2398 case WM_T_82546_3: 2399 /* Use the shadow control register on these chips. */ 2400 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2401 break; 2402 2403 default: 2404 /* Everything else can safely use the documented method. */ 2405 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2406 break; 2407 } 2408 delay(10000); 2409 2410 for (i = 0; i < 1000; i++) { 2411 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2412 return; 2413 delay(20); 2414 } 2415 2416 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2417 log(LOG_ERR, "%s: reset failed to complete\n", 2418 sc->sc_dev.dv_xname); 2419 } 2420 2421 /* 2422 * wm_init: [ifnet interface function] 2423 * 2424 * Initialize the interface. Must be called at splnet(). 2425 */ 2426 static int 2427 wm_init(struct ifnet *ifp) 2428 { 2429 struct wm_softc *sc = ifp->if_softc; 2430 struct wm_rxsoft *rxs; 2431 int i, error = 0; 2432 uint32_t reg; 2433 2434 /* 2435 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2436 * There is a small but measurable benefit to avoiding the adjusment 2437 * of the descriptor so that the headers are aligned, for normal mtu, 2438 * on such platforms. One possibility is that the DMA itself is 2439 * slightly more efficient if the front of the entire packet (instead 2440 * of the front of the headers) is aligned. 2441 * 2442 * Note we must always set align_tweak to 0 if we are using 2443 * jumbo frames. 2444 */ 2445 #ifdef __NO_STRICT_ALIGNMENT 2446 sc->sc_align_tweak = 0; 2447 #else 2448 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2449 sc->sc_align_tweak = 0; 2450 else 2451 sc->sc_align_tweak = 2; 2452 #endif /* __NO_STRICT_ALIGNMENT */ 2453 2454 /* Cancel any pending I/O. */ 2455 wm_stop(ifp, 0); 2456 2457 /* Reset the chip to a known state. */ 2458 wm_reset(sc); 2459 2460 /* Initialize the transmit descriptor ring. */ 2461 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2462 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2463 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2464 sc->sc_txfree = WM_NTXDESC(sc); 2465 sc->sc_txnext = 0; 2466 2467 if (sc->sc_type < WM_T_82543) { 2468 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2469 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2470 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2471 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2472 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2473 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2474 } else { 2475 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2476 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2477 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2478 CSR_WRITE(sc, WMREG_TDH, 0); 2479 CSR_WRITE(sc, WMREG_TDT, 0); 2480 CSR_WRITE(sc, WMREG_TIDV, 64); 2481 CSR_WRITE(sc, WMREG_TADV, 128); 2482 2483 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2484 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2485 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2486 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2487 } 2488 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2489 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2490 2491 /* Initialize the transmit job descriptors. */ 2492 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2493 sc->sc_txsoft[i].txs_mbuf = NULL; 2494 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2495 sc->sc_txsnext = 0; 2496 sc->sc_txsdirty = 0; 2497 2498 /* 2499 * Initialize the receive descriptor and receive job 2500 * descriptor rings. 2501 */ 2502 if (sc->sc_type < WM_T_82543) { 2503 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2504 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2505 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2506 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2507 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2508 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2509 2510 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2511 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2512 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2513 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2514 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2515 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2516 } else { 2517 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2518 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2519 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2520 CSR_WRITE(sc, WMREG_RDH, 0); 2521 CSR_WRITE(sc, WMREG_RDT, 0); 2522 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2523 CSR_WRITE(sc, WMREG_RADV, 128); 2524 } 2525 for (i = 0; i < WM_NRXDESC; i++) { 2526 rxs = &sc->sc_rxsoft[i]; 2527 if (rxs->rxs_mbuf == NULL) { 2528 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2529 log(LOG_ERR, "%s: unable to allocate or map rx " 2530 "buffer %d, error = %d\n", 2531 sc->sc_dev.dv_xname, i, error); 2532 /* 2533 * XXX Should attempt to run with fewer receive 2534 * XXX buffers instead of just failing. 2535 */ 2536 wm_rxdrain(sc); 2537 goto out; 2538 } 2539 } else 2540 WM_INIT_RXDESC(sc, i); 2541 } 2542 sc->sc_rxptr = 0; 2543 sc->sc_rxdiscard = 0; 2544 WM_RXCHAIN_RESET(sc); 2545 2546 /* 2547 * Clear out the VLAN table -- we don't use it (yet). 2548 */ 2549 CSR_WRITE(sc, WMREG_VET, 0); 2550 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2551 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2552 2553 /* 2554 * Set up flow-control parameters. 2555 * 2556 * XXX Values could probably stand some tuning. 2557 */ 2558 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2559 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2560 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2561 2562 sc->sc_fcrtl = FCRTL_DFLT; 2563 if (sc->sc_type < WM_T_82543) { 2564 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2565 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2566 } else { 2567 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2568 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2569 } 2570 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2571 2572 #if 0 /* XXXJRT */ 2573 /* Deal with VLAN enables. */ 2574 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2575 sc->sc_ctrl |= CTRL_VME; 2576 else 2577 #endif /* XXXJRT */ 2578 sc->sc_ctrl &= ~CTRL_VME; 2579 2580 /* Write the control registers. */ 2581 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2582 #if 0 2583 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2584 #endif 2585 2586 /* 2587 * Set up checksum offload parameters. 2588 */ 2589 reg = CSR_READ(sc, WMREG_RXCSUM); 2590 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2591 reg |= RXCSUM_IPOFL; 2592 else 2593 reg &= ~RXCSUM_IPOFL; 2594 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2595 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2596 else { 2597 reg &= ~RXCSUM_TUOFL; 2598 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2599 reg &= ~RXCSUM_IPOFL; 2600 } 2601 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2602 2603 /* 2604 * Set up the interrupt registers. 2605 */ 2606 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2607 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2608 ICR_RXO | ICR_RXT0; 2609 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2610 sc->sc_icr |= ICR_RXCFG; 2611 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2612 2613 /* Set up the inter-packet gap. */ 2614 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2615 2616 if (sc->sc_type >= WM_T_82543) { 2617 /* Set up the interrupt throttling register (units of 256ns) */ 2618 sc->sc_itr = 1000000000 / (7000 * 256); 2619 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2620 } 2621 2622 #if 0 /* XXXJRT */ 2623 /* Set the VLAN ethernetype. */ 2624 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2625 #endif 2626 2627 /* 2628 * Set up the transmit control register; we start out with 2629 * a collision distance suitable for FDX, but update it whe 2630 * we resolve the media type. 2631 */ 2632 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2633 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2634 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2635 2636 /* Set the media. */ 2637 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2638 2639 /* 2640 * Set up the receive control register; we actually program 2641 * the register when we set the receive filter. Use multicast 2642 * address offset type 0. 2643 * 2644 * Only the i82544 has the ability to strip the incoming 2645 * CRC, so we don't enable that feature. 2646 */ 2647 sc->sc_mchash_type = 0; 2648 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2649 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2650 2651 if(MCLBYTES == 2048) { 2652 sc->sc_rctl |= RCTL_2k; 2653 } else { 2654 if(sc->sc_type >= WM_T_82543) { 2655 switch(MCLBYTES) { 2656 case 4096: 2657 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2658 break; 2659 case 8192: 2660 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2661 break; 2662 case 16384: 2663 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2664 break; 2665 default: 2666 panic("wm_init: MCLBYTES %d unsupported", 2667 MCLBYTES); 2668 break; 2669 } 2670 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2671 } 2672 2673 /* Set the receive filter. */ 2674 wm_set_filter(sc); 2675 2676 /* Start the one second link check clock. */ 2677 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2678 2679 /* ...all done! */ 2680 ifp->if_flags |= IFF_RUNNING; 2681 ifp->if_flags &= ~IFF_OACTIVE; 2682 2683 out: 2684 if (error) 2685 log(LOG_ERR, "%s: interface not running\n", 2686 sc->sc_dev.dv_xname); 2687 return (error); 2688 } 2689 2690 /* 2691 * wm_rxdrain: 2692 * 2693 * Drain the receive queue. 2694 */ 2695 static void 2696 wm_rxdrain(struct wm_softc *sc) 2697 { 2698 struct wm_rxsoft *rxs; 2699 int i; 2700 2701 for (i = 0; i < WM_NRXDESC; i++) { 2702 rxs = &sc->sc_rxsoft[i]; 2703 if (rxs->rxs_mbuf != NULL) { 2704 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2705 m_freem(rxs->rxs_mbuf); 2706 rxs->rxs_mbuf = NULL; 2707 } 2708 } 2709 } 2710 2711 /* 2712 * wm_stop: [ifnet interface function] 2713 * 2714 * Stop transmission on the interface. 2715 */ 2716 static void 2717 wm_stop(struct ifnet *ifp, int disable) 2718 { 2719 struct wm_softc *sc = ifp->if_softc; 2720 struct wm_txsoft *txs; 2721 int i; 2722 2723 /* Stop the one second clock. */ 2724 callout_stop(&sc->sc_tick_ch); 2725 2726 /* Stop the 82547 Tx FIFO stall check timer. */ 2727 if (sc->sc_type == WM_T_82547) 2728 callout_stop(&sc->sc_txfifo_ch); 2729 2730 if (sc->sc_flags & WM_F_HAS_MII) { 2731 /* Down the MII. */ 2732 mii_down(&sc->sc_mii); 2733 } 2734 2735 /* Stop the transmit and receive processes. */ 2736 CSR_WRITE(sc, WMREG_TCTL, 0); 2737 CSR_WRITE(sc, WMREG_RCTL, 0); 2738 2739 /* Release any queued transmit buffers. */ 2740 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2741 txs = &sc->sc_txsoft[i]; 2742 if (txs->txs_mbuf != NULL) { 2743 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2744 m_freem(txs->txs_mbuf); 2745 txs->txs_mbuf = NULL; 2746 } 2747 } 2748 2749 if (disable) 2750 wm_rxdrain(sc); 2751 2752 /* Mark the interface as down and cancel the watchdog timer. */ 2753 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2754 ifp->if_timer = 0; 2755 } 2756 2757 /* 2758 * wm_acquire_eeprom: 2759 * 2760 * Perform the EEPROM handshake required on some chips. 2761 */ 2762 static int 2763 wm_acquire_eeprom(struct wm_softc *sc) 2764 { 2765 uint32_t reg; 2766 int x; 2767 2768 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2769 reg = CSR_READ(sc, WMREG_EECD); 2770 2771 /* Request EEPROM access. */ 2772 reg |= EECD_EE_REQ; 2773 CSR_WRITE(sc, WMREG_EECD, reg); 2774 2775 /* ..and wait for it to be granted. */ 2776 for (x = 0; x < 100; x++) { 2777 reg = CSR_READ(sc, WMREG_EECD); 2778 if (reg & EECD_EE_GNT) 2779 break; 2780 delay(5); 2781 } 2782 if ((reg & EECD_EE_GNT) == 0) { 2783 aprint_error("%s: could not acquire EEPROM GNT\n", 2784 sc->sc_dev.dv_xname); 2785 reg &= ~EECD_EE_REQ; 2786 CSR_WRITE(sc, WMREG_EECD, reg); 2787 return (1); 2788 } 2789 } 2790 2791 return (0); 2792 } 2793 2794 /* 2795 * wm_release_eeprom: 2796 * 2797 * Release the EEPROM mutex. 2798 */ 2799 static void 2800 wm_release_eeprom(struct wm_softc *sc) 2801 { 2802 uint32_t reg; 2803 2804 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2805 reg = CSR_READ(sc, WMREG_EECD); 2806 reg &= ~EECD_EE_REQ; 2807 CSR_WRITE(sc, WMREG_EECD, reg); 2808 } 2809 } 2810 2811 /* 2812 * wm_eeprom_sendbits: 2813 * 2814 * Send a series of bits to the EEPROM. 2815 */ 2816 static void 2817 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2818 { 2819 uint32_t reg; 2820 int x; 2821 2822 reg = CSR_READ(sc, WMREG_EECD); 2823 2824 for (x = nbits; x > 0; x--) { 2825 if (bits & (1U << (x - 1))) 2826 reg |= EECD_DI; 2827 else 2828 reg &= ~EECD_DI; 2829 CSR_WRITE(sc, WMREG_EECD, reg); 2830 delay(2); 2831 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2832 delay(2); 2833 CSR_WRITE(sc, WMREG_EECD, reg); 2834 delay(2); 2835 } 2836 } 2837 2838 /* 2839 * wm_eeprom_recvbits: 2840 * 2841 * Receive a series of bits from the EEPROM. 2842 */ 2843 static void 2844 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2845 { 2846 uint32_t reg, val; 2847 int x; 2848 2849 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2850 2851 val = 0; 2852 for (x = nbits; x > 0; x--) { 2853 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2854 delay(2); 2855 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2856 val |= (1U << (x - 1)); 2857 CSR_WRITE(sc, WMREG_EECD, reg); 2858 delay(2); 2859 } 2860 *valp = val; 2861 } 2862 2863 /* 2864 * wm_read_eeprom_uwire: 2865 * 2866 * Read a word from the EEPROM using the MicroWire protocol. 2867 */ 2868 static int 2869 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2870 { 2871 uint32_t reg, val; 2872 int i; 2873 2874 for (i = 0; i < wordcnt; i++) { 2875 /* Clear SK and DI. */ 2876 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2877 CSR_WRITE(sc, WMREG_EECD, reg); 2878 2879 /* Set CHIP SELECT. */ 2880 reg |= EECD_CS; 2881 CSR_WRITE(sc, WMREG_EECD, reg); 2882 delay(2); 2883 2884 /* Shift in the READ command. */ 2885 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2886 2887 /* Shift in address. */ 2888 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2889 2890 /* Shift out the data. */ 2891 wm_eeprom_recvbits(sc, &val, 16); 2892 data[i] = val & 0xffff; 2893 2894 /* Clear CHIP SELECT. */ 2895 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 2896 CSR_WRITE(sc, WMREG_EECD, reg); 2897 delay(2); 2898 } 2899 2900 return (0); 2901 } 2902 2903 /* 2904 * wm_spi_eeprom_ready: 2905 * 2906 * Wait for a SPI EEPROM to be ready for commands. 2907 */ 2908 static int 2909 wm_spi_eeprom_ready(struct wm_softc *sc) 2910 { 2911 uint32_t val; 2912 int usec; 2913 2914 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 2915 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 2916 wm_eeprom_recvbits(sc, &val, 8); 2917 if ((val & SPI_SR_RDY) == 0) 2918 break; 2919 } 2920 if (usec >= SPI_MAX_RETRIES) { 2921 aprint_error("%s: EEPROM failed to become ready\n", 2922 sc->sc_dev.dv_xname); 2923 return (1); 2924 } 2925 return (0); 2926 } 2927 2928 /* 2929 * wm_read_eeprom_spi: 2930 * 2931 * Read a work from the EEPROM using the SPI protocol. 2932 */ 2933 static int 2934 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2935 { 2936 uint32_t reg, val; 2937 int i; 2938 uint8_t opc; 2939 2940 /* Clear SK and CS. */ 2941 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 2942 CSR_WRITE(sc, WMREG_EECD, reg); 2943 delay(2); 2944 2945 if (wm_spi_eeprom_ready(sc)) 2946 return (1); 2947 2948 /* Toggle CS to flush commands. */ 2949 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 2950 delay(2); 2951 CSR_WRITE(sc, WMREG_EECD, reg); 2952 delay(2); 2953 2954 opc = SPI_OPC_READ; 2955 if (sc->sc_ee_addrbits == 8 && word >= 128) 2956 opc |= SPI_OPC_A8; 2957 2958 wm_eeprom_sendbits(sc, opc, 8); 2959 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 2960 2961 for (i = 0; i < wordcnt; i++) { 2962 wm_eeprom_recvbits(sc, &val, 16); 2963 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 2964 } 2965 2966 /* Raise CS and clear SK. */ 2967 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 2968 CSR_WRITE(sc, WMREG_EECD, reg); 2969 delay(2); 2970 2971 return (0); 2972 } 2973 2974 /* 2975 * wm_read_eeprom: 2976 * 2977 * Read data from the serial EEPROM. 2978 */ 2979 static int 2980 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2981 { 2982 int rv; 2983 2984 if (wm_acquire_eeprom(sc)) 2985 return (1); 2986 2987 if (sc->sc_flags & WM_F_EEPROM_SPI) 2988 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 2989 else 2990 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 2991 2992 wm_release_eeprom(sc); 2993 return (rv); 2994 } 2995 2996 /* 2997 * wm_add_rxbuf: 2998 * 2999 * Add a receive buffer to the indiciated descriptor. 3000 */ 3001 static int 3002 wm_add_rxbuf(struct wm_softc *sc, int idx) 3003 { 3004 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3005 struct mbuf *m; 3006 int error; 3007 3008 MGETHDR(m, M_DONTWAIT, MT_DATA); 3009 if (m == NULL) 3010 return (ENOBUFS); 3011 3012 MCLGET(m, M_DONTWAIT); 3013 if ((m->m_flags & M_EXT) == 0) { 3014 m_freem(m); 3015 return (ENOBUFS); 3016 } 3017 3018 if (rxs->rxs_mbuf != NULL) 3019 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3020 3021 rxs->rxs_mbuf = m; 3022 3023 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3024 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3025 BUS_DMA_READ|BUS_DMA_NOWAIT); 3026 if (error) { 3027 /* XXX XXX XXX */ 3028 printf("%s: unable to load rx DMA map %d, error = %d\n", 3029 sc->sc_dev.dv_xname, idx, error); 3030 panic("wm_add_rxbuf"); 3031 } 3032 3033 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3034 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3035 3036 WM_INIT_RXDESC(sc, idx); 3037 3038 return (0); 3039 } 3040 3041 /* 3042 * wm_set_ral: 3043 * 3044 * Set an entery in the receive address list. 3045 */ 3046 static void 3047 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3048 { 3049 uint32_t ral_lo, ral_hi; 3050 3051 if (enaddr != NULL) { 3052 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3053 (enaddr[3] << 24); 3054 ral_hi = enaddr[4] | (enaddr[5] << 8); 3055 ral_hi |= RAL_AV; 3056 } else { 3057 ral_lo = 0; 3058 ral_hi = 0; 3059 } 3060 3061 if (sc->sc_type >= WM_T_82544) { 3062 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3063 ral_lo); 3064 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3065 ral_hi); 3066 } else { 3067 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3068 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3069 } 3070 } 3071 3072 /* 3073 * wm_mchash: 3074 * 3075 * Compute the hash of the multicast address for the 4096-bit 3076 * multicast filter. 3077 */ 3078 static uint32_t 3079 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3080 { 3081 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3082 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3083 uint32_t hash; 3084 3085 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3086 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3087 3088 return (hash & 0xfff); 3089 } 3090 3091 /* 3092 * wm_set_filter: 3093 * 3094 * Set up the receive filter. 3095 */ 3096 static void 3097 wm_set_filter(struct wm_softc *sc) 3098 { 3099 struct ethercom *ec = &sc->sc_ethercom; 3100 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3101 struct ether_multi *enm; 3102 struct ether_multistep step; 3103 bus_addr_t mta_reg; 3104 uint32_t hash, reg, bit; 3105 int i; 3106 3107 if (sc->sc_type >= WM_T_82544) 3108 mta_reg = WMREG_CORDOVA_MTA; 3109 else 3110 mta_reg = WMREG_MTA; 3111 3112 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3113 3114 if (ifp->if_flags & IFF_BROADCAST) 3115 sc->sc_rctl |= RCTL_BAM; 3116 if (ifp->if_flags & IFF_PROMISC) { 3117 sc->sc_rctl |= RCTL_UPE; 3118 goto allmulti; 3119 } 3120 3121 /* 3122 * Set the station address in the first RAL slot, and 3123 * clear the remaining slots. 3124 */ 3125 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3126 for (i = 1; i < WM_RAL_TABSIZE; i++) 3127 wm_set_ral(sc, NULL, i); 3128 3129 /* Clear out the multicast table. */ 3130 for (i = 0; i < WM_MC_TABSIZE; i++) 3131 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3132 3133 ETHER_FIRST_MULTI(step, ec, enm); 3134 while (enm != NULL) { 3135 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3136 /* 3137 * We must listen to a range of multicast addresses. 3138 * For now, just accept all multicasts, rather than 3139 * trying to set only those filter bits needed to match 3140 * the range. (At this time, the only use of address 3141 * ranges is for IP multicast routing, for which the 3142 * range is big enough to require all bits set.) 3143 */ 3144 goto allmulti; 3145 } 3146 3147 hash = wm_mchash(sc, enm->enm_addrlo); 3148 3149 reg = (hash >> 5) & 0x7f; 3150 bit = hash & 0x1f; 3151 3152 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3153 hash |= 1U << bit; 3154 3155 /* XXX Hardware bug?? */ 3156 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3157 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3158 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3159 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3160 } else 3161 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3162 3163 ETHER_NEXT_MULTI(step, enm); 3164 } 3165 3166 ifp->if_flags &= ~IFF_ALLMULTI; 3167 goto setit; 3168 3169 allmulti: 3170 ifp->if_flags |= IFF_ALLMULTI; 3171 sc->sc_rctl |= RCTL_MPE; 3172 3173 setit: 3174 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3175 } 3176 3177 /* 3178 * wm_tbi_mediainit: 3179 * 3180 * Initialize media for use on 1000BASE-X devices. 3181 */ 3182 static void 3183 wm_tbi_mediainit(struct wm_softc *sc) 3184 { 3185 const char *sep = ""; 3186 3187 if (sc->sc_type < WM_T_82543) 3188 sc->sc_tipg = TIPG_WM_DFLT; 3189 else 3190 sc->sc_tipg = TIPG_LG_DFLT; 3191 3192 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3193 wm_tbi_mediastatus); 3194 3195 /* 3196 * SWD Pins: 3197 * 3198 * 0 = Link LED (output) 3199 * 1 = Loss Of Signal (input) 3200 */ 3201 sc->sc_ctrl |= CTRL_SWDPIO(0); 3202 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3203 3204 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3205 3206 #define ADD(ss, mm, dd) \ 3207 do { \ 3208 aprint_normal("%s%s", sep, ss); \ 3209 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3210 sep = ", "; \ 3211 } while (/*CONSTCOND*/0) 3212 3213 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3214 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3215 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3216 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3217 aprint_normal("\n"); 3218 3219 #undef ADD 3220 3221 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3222 } 3223 3224 /* 3225 * wm_tbi_mediastatus: [ifmedia interface function] 3226 * 3227 * Get the current interface media status on a 1000BASE-X device. 3228 */ 3229 static void 3230 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3231 { 3232 struct wm_softc *sc = ifp->if_softc; 3233 uint32_t ctrl; 3234 3235 ifmr->ifm_status = IFM_AVALID; 3236 ifmr->ifm_active = IFM_ETHER; 3237 3238 if (sc->sc_tbi_linkup == 0) { 3239 ifmr->ifm_active |= IFM_NONE; 3240 return; 3241 } 3242 3243 ifmr->ifm_status |= IFM_ACTIVE; 3244 ifmr->ifm_active |= IFM_1000_SX; 3245 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3246 ifmr->ifm_active |= IFM_FDX; 3247 ctrl = CSR_READ(sc, WMREG_CTRL); 3248 if (ctrl & CTRL_RFCE) 3249 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3250 if (ctrl & CTRL_TFCE) 3251 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3252 } 3253 3254 /* 3255 * wm_tbi_mediachange: [ifmedia interface function] 3256 * 3257 * Set hardware to newly-selected media on a 1000BASE-X device. 3258 */ 3259 static int 3260 wm_tbi_mediachange(struct ifnet *ifp) 3261 { 3262 struct wm_softc *sc = ifp->if_softc; 3263 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3264 uint32_t status; 3265 int i; 3266 3267 sc->sc_txcw = ife->ifm_data; 3268 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3269 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3270 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3271 sc->sc_txcw |= TXCW_ANE; 3272 3273 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3274 delay(10000); 3275 3276 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3277 3278 sc->sc_tbi_anstate = 0; 3279 3280 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3281 /* Have signal; wait for the link to come up. */ 3282 for (i = 0; i < 50; i++) { 3283 delay(10000); 3284 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3285 break; 3286 } 3287 3288 status = CSR_READ(sc, WMREG_STATUS); 3289 if (status & STATUS_LU) { 3290 /* Link is up. */ 3291 DPRINTF(WM_DEBUG_LINK, 3292 ("%s: LINK: set media -> link up %s\n", 3293 sc->sc_dev.dv_xname, 3294 (status & STATUS_FD) ? "FDX" : "HDX")); 3295 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3296 sc->sc_fcrtl &= ~FCRTL_XONE; 3297 if (status & STATUS_FD) 3298 sc->sc_tctl |= 3299 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3300 else 3301 sc->sc_tctl |= 3302 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3303 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3304 sc->sc_fcrtl |= FCRTL_XONE; 3305 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3306 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3307 WMREG_OLD_FCRTL : WMREG_FCRTL, 3308 sc->sc_fcrtl); 3309 sc->sc_tbi_linkup = 1; 3310 } else { 3311 /* Link is down. */ 3312 DPRINTF(WM_DEBUG_LINK, 3313 ("%s: LINK: set media -> link down\n", 3314 sc->sc_dev.dv_xname)); 3315 sc->sc_tbi_linkup = 0; 3316 } 3317 } else { 3318 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3319 sc->sc_dev.dv_xname)); 3320 sc->sc_tbi_linkup = 0; 3321 } 3322 3323 wm_tbi_set_linkled(sc); 3324 3325 return (0); 3326 } 3327 3328 /* 3329 * wm_tbi_set_linkled: 3330 * 3331 * Update the link LED on 1000BASE-X devices. 3332 */ 3333 static void 3334 wm_tbi_set_linkled(struct wm_softc *sc) 3335 { 3336 3337 if (sc->sc_tbi_linkup) 3338 sc->sc_ctrl |= CTRL_SWDPIN(0); 3339 else 3340 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3341 3342 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3343 } 3344 3345 /* 3346 * wm_tbi_check_link: 3347 * 3348 * Check the link on 1000BASE-X devices. 3349 */ 3350 static void 3351 wm_tbi_check_link(struct wm_softc *sc) 3352 { 3353 uint32_t rxcw, ctrl, status; 3354 3355 if (sc->sc_tbi_anstate == 0) 3356 return; 3357 else if (sc->sc_tbi_anstate > 1) { 3358 DPRINTF(WM_DEBUG_LINK, 3359 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3360 sc->sc_tbi_anstate)); 3361 sc->sc_tbi_anstate--; 3362 return; 3363 } 3364 3365 sc->sc_tbi_anstate = 0; 3366 3367 rxcw = CSR_READ(sc, WMREG_RXCW); 3368 ctrl = CSR_READ(sc, WMREG_CTRL); 3369 status = CSR_READ(sc, WMREG_STATUS); 3370 3371 if ((status & STATUS_LU) == 0) { 3372 DPRINTF(WM_DEBUG_LINK, 3373 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3374 sc->sc_tbi_linkup = 0; 3375 } else { 3376 DPRINTF(WM_DEBUG_LINK, 3377 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3378 (status & STATUS_FD) ? "FDX" : "HDX")); 3379 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3380 sc->sc_fcrtl &= ~FCRTL_XONE; 3381 if (status & STATUS_FD) 3382 sc->sc_tctl |= 3383 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3384 else 3385 sc->sc_tctl |= 3386 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3387 if (ctrl & CTRL_TFCE) 3388 sc->sc_fcrtl |= FCRTL_XONE; 3389 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3390 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3391 WMREG_OLD_FCRTL : WMREG_FCRTL, 3392 sc->sc_fcrtl); 3393 sc->sc_tbi_linkup = 1; 3394 } 3395 3396 wm_tbi_set_linkled(sc); 3397 } 3398 3399 /* 3400 * wm_gmii_reset: 3401 * 3402 * Reset the PHY. 3403 */ 3404 static void 3405 wm_gmii_reset(struct wm_softc *sc) 3406 { 3407 uint32_t reg; 3408 3409 if (sc->sc_type >= WM_T_82544) { 3410 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3411 delay(20000); 3412 3413 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3414 delay(20000); 3415 } else { 3416 /* The PHY reset pin is active-low. */ 3417 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3418 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3419 CTRL_EXT_SWDPIN(4)); 3420 reg |= CTRL_EXT_SWDPIO(4); 3421 3422 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3423 delay(10); 3424 3425 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3426 delay(10); 3427 3428 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3429 delay(10); 3430 #if 0 3431 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3432 #endif 3433 } 3434 } 3435 3436 /* 3437 * wm_gmii_mediainit: 3438 * 3439 * Initialize media for use on 1000BASE-T devices. 3440 */ 3441 static void 3442 wm_gmii_mediainit(struct wm_softc *sc) 3443 { 3444 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3445 3446 /* We have MII. */ 3447 sc->sc_flags |= WM_F_HAS_MII; 3448 3449 sc->sc_tipg = TIPG_1000T_DFLT; 3450 3451 /* 3452 * Let the chip set speed/duplex on its own based on 3453 * signals from the PHY. 3454 */ 3455 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3456 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3457 3458 /* Initialize our media structures and probe the GMII. */ 3459 sc->sc_mii.mii_ifp = ifp; 3460 3461 if (sc->sc_type >= WM_T_82544) { 3462 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3463 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3464 } else { 3465 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3466 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3467 } 3468 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3469 3470 wm_gmii_reset(sc); 3471 3472 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3473 wm_gmii_mediastatus); 3474 3475 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3476 MII_OFFSET_ANY, MIIF_DOPAUSE); 3477 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3478 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3479 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3480 } else 3481 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3482 } 3483 3484 /* 3485 * wm_gmii_mediastatus: [ifmedia interface function] 3486 * 3487 * Get the current interface media status on a 1000BASE-T device. 3488 */ 3489 static void 3490 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3491 { 3492 struct wm_softc *sc = ifp->if_softc; 3493 3494 mii_pollstat(&sc->sc_mii); 3495 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3496 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3497 sc->sc_flowflags; 3498 } 3499 3500 /* 3501 * wm_gmii_mediachange: [ifmedia interface function] 3502 * 3503 * Set hardware to newly-selected media on a 1000BASE-T device. 3504 */ 3505 static int 3506 wm_gmii_mediachange(struct ifnet *ifp) 3507 { 3508 struct wm_softc *sc = ifp->if_softc; 3509 3510 if (ifp->if_flags & IFF_UP) 3511 mii_mediachg(&sc->sc_mii); 3512 return (0); 3513 } 3514 3515 #define MDI_IO CTRL_SWDPIN(2) 3516 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3517 #define MDI_CLK CTRL_SWDPIN(3) 3518 3519 static void 3520 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3521 { 3522 uint32_t i, v; 3523 3524 v = CSR_READ(sc, WMREG_CTRL); 3525 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3526 v |= MDI_DIR | CTRL_SWDPIO(3); 3527 3528 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3529 if (data & i) 3530 v |= MDI_IO; 3531 else 3532 v &= ~MDI_IO; 3533 CSR_WRITE(sc, WMREG_CTRL, v); 3534 delay(10); 3535 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3536 delay(10); 3537 CSR_WRITE(sc, WMREG_CTRL, v); 3538 delay(10); 3539 } 3540 } 3541 3542 static uint32_t 3543 i82543_mii_recvbits(struct wm_softc *sc) 3544 { 3545 uint32_t v, i, data = 0; 3546 3547 v = CSR_READ(sc, WMREG_CTRL); 3548 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3549 v |= CTRL_SWDPIO(3); 3550 3551 CSR_WRITE(sc, WMREG_CTRL, v); 3552 delay(10); 3553 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3554 delay(10); 3555 CSR_WRITE(sc, WMREG_CTRL, v); 3556 delay(10); 3557 3558 for (i = 0; i < 16; i++) { 3559 data <<= 1; 3560 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3561 delay(10); 3562 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3563 data |= 1; 3564 CSR_WRITE(sc, WMREG_CTRL, v); 3565 delay(10); 3566 } 3567 3568 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3569 delay(10); 3570 CSR_WRITE(sc, WMREG_CTRL, v); 3571 delay(10); 3572 3573 return (data); 3574 } 3575 3576 #undef MDI_IO 3577 #undef MDI_DIR 3578 #undef MDI_CLK 3579 3580 /* 3581 * wm_gmii_i82543_readreg: [mii interface function] 3582 * 3583 * Read a PHY register on the GMII (i82543 version). 3584 */ 3585 static int 3586 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3587 { 3588 struct wm_softc *sc = (void *) self; 3589 int rv; 3590 3591 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3592 i82543_mii_sendbits(sc, reg | (phy << 5) | 3593 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3594 rv = i82543_mii_recvbits(sc) & 0xffff; 3595 3596 DPRINTF(WM_DEBUG_GMII, 3597 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3598 sc->sc_dev.dv_xname, phy, reg, rv)); 3599 3600 return (rv); 3601 } 3602 3603 /* 3604 * wm_gmii_i82543_writereg: [mii interface function] 3605 * 3606 * Write a PHY register on the GMII (i82543 version). 3607 */ 3608 static void 3609 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3610 { 3611 struct wm_softc *sc = (void *) self; 3612 3613 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3614 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3615 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3616 (MII_COMMAND_START << 30), 32); 3617 } 3618 3619 /* 3620 * wm_gmii_i82544_readreg: [mii interface function] 3621 * 3622 * Read a PHY register on the GMII. 3623 */ 3624 static int 3625 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3626 { 3627 struct wm_softc *sc = (void *) self; 3628 uint32_t mdic = 0; 3629 int i, rv; 3630 3631 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3632 MDIC_REGADD(reg)); 3633 3634 for (i = 0; i < 100; i++) { 3635 mdic = CSR_READ(sc, WMREG_MDIC); 3636 if (mdic & MDIC_READY) 3637 break; 3638 delay(10); 3639 } 3640 3641 if ((mdic & MDIC_READY) == 0) { 3642 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3643 sc->sc_dev.dv_xname, phy, reg); 3644 rv = 0; 3645 } else if (mdic & MDIC_E) { 3646 #if 0 /* This is normal if no PHY is present. */ 3647 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3648 sc->sc_dev.dv_xname, phy, reg); 3649 #endif 3650 rv = 0; 3651 } else { 3652 rv = MDIC_DATA(mdic); 3653 if (rv == 0xffff) 3654 rv = 0; 3655 } 3656 3657 return (rv); 3658 } 3659 3660 /* 3661 * wm_gmii_i82544_writereg: [mii interface function] 3662 * 3663 * Write a PHY register on the GMII. 3664 */ 3665 static void 3666 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3667 { 3668 struct wm_softc *sc = (void *) self; 3669 uint32_t mdic = 0; 3670 int i; 3671 3672 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3673 MDIC_REGADD(reg) | MDIC_DATA(val)); 3674 3675 for (i = 0; i < 100; i++) { 3676 mdic = CSR_READ(sc, WMREG_MDIC); 3677 if (mdic & MDIC_READY) 3678 break; 3679 delay(10); 3680 } 3681 3682 if ((mdic & MDIC_READY) == 0) 3683 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3684 sc->sc_dev.dv_xname, phy, reg); 3685 else if (mdic & MDIC_E) 3686 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3687 sc->sc_dev.dv_xname, phy, reg); 3688 } 3689 3690 /* 3691 * wm_gmii_statchg: [mii interface function] 3692 * 3693 * Callback from MII layer when media changes. 3694 */ 3695 static void 3696 wm_gmii_statchg(struct device *self) 3697 { 3698 struct wm_softc *sc = (void *) self; 3699 struct mii_data *mii = &sc->sc_mii; 3700 3701 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3702 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3703 sc->sc_fcrtl &= ~FCRTL_XONE; 3704 3705 /* 3706 * Get flow control negotiation result. 3707 */ 3708 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3709 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3710 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3711 mii->mii_media_active &= ~IFM_ETH_FMASK; 3712 } 3713 3714 if (sc->sc_flowflags & IFM_FLOW) { 3715 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3716 sc->sc_ctrl |= CTRL_TFCE; 3717 sc->sc_fcrtl |= FCRTL_XONE; 3718 } 3719 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3720 sc->sc_ctrl |= CTRL_RFCE; 3721 } 3722 3723 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3724 DPRINTF(WM_DEBUG_LINK, 3725 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3726 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3727 } else { 3728 DPRINTF(WM_DEBUG_LINK, 3729 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3730 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3731 } 3732 3733 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3734 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3735 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3736 : WMREG_FCRTL, sc->sc_fcrtl); 3737 } 3738
Indexes created Tue Sep 23 07:09:52 GMT 2025