if_wm.c revision 1.99
1 /* $NetBSD: if_wm.c,v 1.99 2005/03/09 19:06:19 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.99 2005/03/09 19:06:19 matt Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make serveral things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 280 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 281 282 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 283 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 284 285 struct evcnt sc_ev_tu; /* Tx underrun */ 286 287 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 288 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 289 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 290 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 291 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 292 #endif /* WM_EVENT_COUNTERS */ 293 294 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 295 296 int sc_txfree; /* number of free Tx descriptors */ 297 int sc_txnext; /* next ready Tx descriptor */ 298 299 int sc_txsfree; /* number of free Tx jobs */ 300 int sc_txsnext; /* next free Tx job */ 301 int sc_txsdirty; /* dirty Tx jobs */ 302 303 /* These 5 variables are used only on the 82547. */ 304 int sc_txfifo_size; /* Tx FIFO size */ 305 int sc_txfifo_head; /* current head of FIFO */ 306 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 307 int sc_txfifo_stall; /* Tx FIFO is stalled */ 308 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 309 310 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 311 312 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 313 int sc_rxdiscard; 314 int sc_rxlen; 315 struct mbuf *sc_rxhead; 316 struct mbuf *sc_rxtail; 317 struct mbuf **sc_rxtailp; 318 319 uint32_t sc_ctrl; /* prototype CTRL register */ 320 #if 0 321 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 322 #endif 323 uint32_t sc_icr; /* prototype interrupt bits */ 324 uint32_t sc_itr; /* prototype intr throttling reg */ 325 uint32_t sc_tctl; /* prototype TCTL register */ 326 uint32_t sc_rctl; /* prototype RCTL register */ 327 uint32_t sc_txcw; /* prototype TXCW register */ 328 uint32_t sc_tipg; /* prototype TIPG register */ 329 uint32_t sc_fcrtl; /* prototype FCRTL register */ 330 uint32_t sc_pba; /* prototype PBA register */ 331 332 int sc_tbi_linkup; /* TBI link status */ 333 int sc_tbi_anstate; /* autonegotiation state */ 334 335 int sc_mchash_type; /* multicast filter offset */ 336 337 #if NRND > 0 338 rndsource_element_t rnd_source; /* random source */ 339 #endif 340 }; 341 342 #define WM_RXCHAIN_RESET(sc) \ 343 do { \ 344 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 345 *(sc)->sc_rxtailp = NULL; \ 346 (sc)->sc_rxlen = 0; \ 347 } while (/*CONSTCOND*/0) 348 349 #define WM_RXCHAIN_LINK(sc, m) \ 350 do { \ 351 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 352 (sc)->sc_rxtailp = &(m)->m_next; \ 353 } while (/*CONSTCOND*/0) 354 355 /* sc_flags */ 356 #define WM_F_HAS_MII 0x01 /* has MII */ 357 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 358 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 359 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 360 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 361 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 362 #define WM_F_CSA 0x80 /* bus is CSA */ 363 364 #ifdef WM_EVENT_COUNTERS 365 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 366 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 367 #else 368 #define WM_EVCNT_INCR(ev) /* nothing */ 369 #define WM_EVCNT_ADD(ev, val) /* nothing */ 370 #endif 371 372 #define CSR_READ(sc, reg) \ 373 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 374 #define CSR_WRITE(sc, reg, val) \ 375 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 376 #define CSR_WRITE_FLUSH(sc) \ 377 (void) CSR_READ((sc), WMREG_STATUS) 378 379 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 380 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 381 382 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 383 #define WM_CDTXADDR_HI(sc, x) \ 384 (sizeof(bus_addr_t) == 8 ? \ 385 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 386 387 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 388 #define WM_CDRXADDR_HI(sc, x) \ 389 (sizeof(bus_addr_t) == 8 ? \ 390 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 391 392 #define WM_CDTXSYNC(sc, x, n, ops) \ 393 do { \ 394 int __x, __n; \ 395 \ 396 __x = (x); \ 397 __n = (n); \ 398 \ 399 /* If it will wrap around, sync to the end of the ring. */ \ 400 if ((__x + __n) > WM_NTXDESC(sc)) { \ 401 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 402 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 403 (WM_NTXDESC(sc) - __x), (ops)); \ 404 __n -= (WM_NTXDESC(sc) - __x); \ 405 __x = 0; \ 406 } \ 407 \ 408 /* Now sync whatever is left. */ \ 409 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 410 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 411 } while (/*CONSTCOND*/0) 412 413 #define WM_CDRXSYNC(sc, x, ops) \ 414 do { \ 415 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 416 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 417 } while (/*CONSTCOND*/0) 418 419 #define WM_INIT_RXDESC(sc, x) \ 420 do { \ 421 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 422 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 423 struct mbuf *__m = __rxs->rxs_mbuf; \ 424 \ 425 /* \ 426 * Note: We scoot the packet forward 2 bytes in the buffer \ 427 * so that the payload after the Ethernet header is aligned \ 428 * to a 4-byte boundary. \ 429 * \ 430 * XXX BRAINDAMAGE ALERT! \ 431 * The stupid chip uses the same size for every buffer, which \ 432 * is set in the Receive Control register. We are using the 2K \ 433 * size option, but what we REALLY want is (2K - 2)! For this \ 434 * reason, we can't "scoot" packets longer than the standard \ 435 * Ethernet MTU. On strict-alignment platforms, if the total \ 436 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 437 * the upper layer copy the headers. \ 438 */ \ 439 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 440 \ 441 wm_set_dma_addr(&__rxd->wrx_addr, \ 442 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 443 __rxd->wrx_len = 0; \ 444 __rxd->wrx_cksum = 0; \ 445 __rxd->wrx_status = 0; \ 446 __rxd->wrx_errors = 0; \ 447 __rxd->wrx_special = 0; \ 448 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 449 \ 450 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 451 } while (/*CONSTCOND*/0) 452 453 static void wm_start(struct ifnet *); 454 static void wm_watchdog(struct ifnet *); 455 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 456 static int wm_init(struct ifnet *); 457 static void wm_stop(struct ifnet *, int); 458 459 static void wm_shutdown(void *); 460 461 static void wm_reset(struct wm_softc *); 462 static void wm_rxdrain(struct wm_softc *); 463 static int wm_add_rxbuf(struct wm_softc *, int); 464 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 465 static void wm_tick(void *); 466 467 static void wm_set_filter(struct wm_softc *); 468 469 static int wm_intr(void *); 470 static void wm_txintr(struct wm_softc *); 471 static void wm_rxintr(struct wm_softc *); 472 static void wm_linkintr(struct wm_softc *, uint32_t); 473 474 static void wm_tbi_mediainit(struct wm_softc *); 475 static int wm_tbi_mediachange(struct ifnet *); 476 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 477 478 static void wm_tbi_set_linkled(struct wm_softc *); 479 static void wm_tbi_check_link(struct wm_softc *); 480 481 static void wm_gmii_reset(struct wm_softc *); 482 483 static int wm_gmii_i82543_readreg(struct device *, int, int); 484 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 485 486 static int wm_gmii_i82544_readreg(struct device *, int, int); 487 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 488 489 static void wm_gmii_statchg(struct device *); 490 491 static void wm_gmii_mediainit(struct wm_softc *); 492 static int wm_gmii_mediachange(struct ifnet *); 493 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 494 495 static int wm_match(struct device *, struct cfdata *, void *); 496 static void wm_attach(struct device *, struct device *, void *); 497 498 CFATTACH_DECL(wm, sizeof(struct wm_softc), 499 wm_match, wm_attach, NULL, NULL); 500 501 static void wm_82547_txfifo_stall(void *); 502 503 /* 504 * Devices supported by this driver. 505 */ 506 static const struct wm_product { 507 pci_vendor_id_t wmp_vendor; 508 pci_product_id_t wmp_product; 509 const char *wmp_name; 510 wm_chip_type wmp_type; 511 int wmp_flags; 512 #define WMP_F_1000X 0x01 513 #define WMP_F_1000T 0x02 514 } wm_products[] = { 515 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 516 "Intel i82542 1000BASE-X Ethernet", 517 WM_T_82542_2_1, WMP_F_1000X }, 518 519 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 520 "Intel i82543GC 1000BASE-X Ethernet", 521 WM_T_82543, WMP_F_1000X }, 522 523 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 524 "Intel i82543GC 1000BASE-T Ethernet", 525 WM_T_82543, WMP_F_1000T }, 526 527 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 528 "Intel i82544EI 1000BASE-T Ethernet", 529 WM_T_82544, WMP_F_1000T }, 530 531 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 532 "Intel i82544EI 1000BASE-X Ethernet", 533 WM_T_82544, WMP_F_1000X }, 534 535 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 536 "Intel i82544GC 1000BASE-T Ethernet", 537 WM_T_82544, WMP_F_1000T }, 538 539 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 540 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 541 WM_T_82544, WMP_F_1000T }, 542 543 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 544 "Intel i82540EM 1000BASE-T Ethernet", 545 WM_T_82540, WMP_F_1000T }, 546 547 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 548 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 549 WM_T_82540, WMP_F_1000T }, 550 551 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 552 "Intel i82540EP 1000BASE-T Ethernet", 553 WM_T_82540, WMP_F_1000T }, 554 555 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 556 "Intel i82540EP 1000BASE-T Ethernet", 557 WM_T_82540, WMP_F_1000T }, 558 559 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 560 "Intel i82540EP 1000BASE-T Ethernet", 561 WM_T_82540, WMP_F_1000T }, 562 563 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 564 "Intel i82545EM 1000BASE-T Ethernet", 565 WM_T_82545, WMP_F_1000T }, 566 567 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 568 "Intel i82545GM 1000BASE-T Ethernet", 569 WM_T_82545_3, WMP_F_1000T }, 570 571 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 572 "Intel i82545GM 1000BASE-X Ethernet", 573 WM_T_82545_3, WMP_F_1000X }, 574 #if 0 575 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 576 "Intel i82545GM Gigabit Ethernet (SERDES)", 577 WM_T_82545_3, WMP_F_SERDES }, 578 #endif 579 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 580 "Intel i82546EB 1000BASE-T Ethernet", 581 WM_T_82546, WMP_F_1000T }, 582 583 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 584 "Intel i82546EB 1000BASE-T Ethernet", 585 WM_T_82546, WMP_F_1000T }, 586 587 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 588 "Intel i82545EM 1000BASE-X Ethernet", 589 WM_T_82545, WMP_F_1000X }, 590 591 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 592 "Intel i82546EB 1000BASE-X Ethernet", 593 WM_T_82546, WMP_F_1000X }, 594 595 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 596 "Intel i82546GB 1000BASE-T Ethernet", 597 WM_T_82546_3, WMP_F_1000T }, 598 599 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 600 "Intel i82546GB 1000BASE-X Ethernet", 601 WM_T_82546_3, WMP_F_1000X }, 602 #if 0 603 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 604 "Intel i82546GB Gigabit Ethernet (SERDES)", 605 WM_T_82546_3, WMP_F_SERDES }, 606 #endif 607 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 608 "Intel i82541EI 1000BASE-T Ethernet", 609 WM_T_82541, WMP_F_1000T }, 610 611 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 612 "Intel i82541EI Mobile 1000BASE-T Ethernet", 613 WM_T_82541, WMP_F_1000T }, 614 615 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 616 "Intel i82541ER 1000BASE-T Ethernet", 617 WM_T_82541_2, WMP_F_1000T }, 618 619 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 620 "Intel i82541GI 1000BASE-T Ethernet", 621 WM_T_82541_2, WMP_F_1000T }, 622 623 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 624 "Intel i82541GI Mobile 1000BASE-T Ethernet", 625 WM_T_82541_2, WMP_F_1000T }, 626 627 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 628 "Intel i82547EI 1000BASE-T Ethernet", 629 WM_T_82547, WMP_F_1000T }, 630 631 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 632 "Intel i82547GI 1000BASE-T Ethernet", 633 WM_T_82547_2, WMP_F_1000T }, 634 { 0, 0, 635 NULL, 636 0, 0 }, 637 }; 638 639 #ifdef WM_EVENT_COUNTERS 640 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 641 #endif /* WM_EVENT_COUNTERS */ 642 643 #if 0 /* Not currently used */ 644 static __inline uint32_t 645 wm_io_read(struct wm_softc *sc, int reg) 646 { 647 648 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 649 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 650 } 651 #endif 652 653 static __inline void 654 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 655 { 656 657 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 658 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 659 } 660 661 static __inline void 662 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 663 { 664 wa->wa_low = htole32(v & 0xffffffffU); 665 if (sizeof(bus_addr_t) == 8) 666 wa->wa_high = htole32((uint64_t) v >> 32); 667 else 668 wa->wa_high = 0; 669 } 670 671 static const struct wm_product * 672 wm_lookup(const struct pci_attach_args *pa) 673 { 674 const struct wm_product *wmp; 675 676 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 677 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 678 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 679 return (wmp); 680 } 681 return (NULL); 682 } 683 684 static int 685 wm_match(struct device *parent, struct cfdata *cf, void *aux) 686 { 687 struct pci_attach_args *pa = aux; 688 689 if (wm_lookup(pa) != NULL) 690 return (1); 691 692 return (0); 693 } 694 695 static void 696 wm_attach(struct device *parent, struct device *self, void *aux) 697 { 698 struct wm_softc *sc = (void *) self; 699 struct pci_attach_args *pa = aux; 700 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 701 pci_chipset_tag_t pc = pa->pa_pc; 702 pci_intr_handle_t ih; 703 size_t cdata_size; 704 const char *intrstr = NULL; 705 const char *eetype; 706 bus_space_tag_t memt; 707 bus_space_handle_t memh; 708 bus_dma_segment_t seg; 709 int memh_valid; 710 int i, rseg, error; 711 const struct wm_product *wmp; 712 uint8_t enaddr[ETHER_ADDR_LEN]; 713 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 714 pcireg_t preg, memtype; 715 uint32_t reg; 716 int pmreg; 717 718 callout_init(&sc->sc_tick_ch); 719 720 wmp = wm_lookup(pa); 721 if (wmp == NULL) { 722 printf("\n"); 723 panic("wm_attach: impossible"); 724 } 725 726 if (pci_dma64_available(pa)) 727 sc->sc_dmat = pa->pa_dmat64; 728 else 729 sc->sc_dmat = pa->pa_dmat; 730 731 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 732 aprint_naive(": Ethernet controller\n"); 733 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 734 735 sc->sc_type = wmp->wmp_type; 736 if (sc->sc_type < WM_T_82543) { 737 if (preg < 2) { 738 aprint_error("%s: i82542 must be at least rev. 2\n", 739 sc->sc_dev.dv_xname); 740 return; 741 } 742 if (preg < 3) 743 sc->sc_type = WM_T_82542_2_0; 744 } 745 746 /* 747 * Map the device. All devices support memory-mapped acccess, 748 * and it is really required for normal operation. 749 */ 750 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 751 switch (memtype) { 752 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 753 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 754 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 755 memtype, 0, &memt, &memh, NULL, NULL) == 0); 756 break; 757 default: 758 memh_valid = 0; 759 } 760 761 if (memh_valid) { 762 sc->sc_st = memt; 763 sc->sc_sh = memh; 764 } else { 765 aprint_error("%s: unable to map device registers\n", 766 sc->sc_dev.dv_xname); 767 return; 768 } 769 770 /* 771 * In addition, i82544 and later support I/O mapped indirect 772 * register access. It is not desirable (nor supported in 773 * this driver) to use it for normal operation, though it is 774 * required to work around bugs in some chip versions. 775 */ 776 if (sc->sc_type >= WM_T_82544) { 777 /* First we have to find the I/O BAR. */ 778 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 779 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 780 PCI_MAPREG_TYPE_IO) 781 break; 782 } 783 if (i == PCI_MAPREG_END) 784 aprint_error("%s: WARNING: unable to find I/O BAR\n", 785 sc->sc_dev.dv_xname); 786 else { 787 /* 788 * The i8254x doesn't apparently respond when the 789 * I/O BAR is 0, which looks somewhat like it's not 790 * been configured. 791 */ 792 preg = pci_conf_read(pc, pa->pa_tag, i); 793 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 794 aprint_error("%s: WARNING: I/O BAR at zero.\n", 795 sc->sc_dev.dv_xname); 796 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 797 0, &sc->sc_iot, &sc->sc_ioh, 798 NULL, NULL) == 0) { 799 sc->sc_flags |= WM_F_IOH_VALID; 800 } else { 801 aprint_error("%s: WARNING: unable to map " 802 "I/O space\n", sc->sc_dev.dv_xname); 803 } 804 } 805 806 } 807 808 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 809 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 810 preg |= PCI_COMMAND_MASTER_ENABLE; 811 if (sc->sc_type < WM_T_82542_2_1) 812 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 813 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 814 815 /* Get it out of power save mode, if needed. */ 816 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 817 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 818 PCI_PMCSR_STATE_MASK; 819 if (preg == PCI_PMCSR_STATE_D3) { 820 /* 821 * The card has lost all configuration data in 822 * this state, so punt. 823 */ 824 aprint_error("%s: unable to wake from power state D3\n", 825 sc->sc_dev.dv_xname); 826 return; 827 } 828 if (preg != PCI_PMCSR_STATE_D0) { 829 aprint_normal("%s: waking up from power state D%d\n", 830 sc->sc_dev.dv_xname, preg); 831 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 832 PCI_PMCSR_STATE_D0); 833 } 834 } 835 836 /* 837 * Map and establish our interrupt. 838 */ 839 if (pci_intr_map(pa, &ih)) { 840 aprint_error("%s: unable to map interrupt\n", 841 sc->sc_dev.dv_xname); 842 return; 843 } 844 intrstr = pci_intr_string(pc, ih); 845 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 846 if (sc->sc_ih == NULL) { 847 aprint_error("%s: unable to establish interrupt", 848 sc->sc_dev.dv_xname); 849 if (intrstr != NULL) 850 aprint_normal(" at %s", intrstr); 851 aprint_normal("\n"); 852 return; 853 } 854 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 855 856 /* 857 * Determine a few things about the bus we're connected to. 858 */ 859 if (sc->sc_type < WM_T_82543) { 860 /* We don't really know the bus characteristics here. */ 861 sc->sc_bus_speed = 33; 862 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 863 /* 864 * CSA (Communication Streaming Architecture) is about as fast 865 * a 32-bit 66MHz PCI Bus. 866 */ 867 sc->sc_flags |= WM_F_CSA; 868 sc->sc_bus_speed = 66; 869 aprint_verbose("%s: Communication Streaming Architecture\n", 870 sc->sc_dev.dv_xname); 871 if (sc->sc_type == WM_T_82547) { 872 callout_init(&sc->sc_txfifo_ch); 873 callout_setfunc(&sc->sc_txfifo_ch, 874 wm_82547_txfifo_stall, sc); 875 aprint_verbose("%s: using 82547 Tx FIFO stall " 876 "work-around\n", sc->sc_dev.dv_xname); 877 } 878 } else { 879 reg = CSR_READ(sc, WMREG_STATUS); 880 if (reg & STATUS_BUS64) 881 sc->sc_flags |= WM_F_BUS64; 882 if (sc->sc_type >= WM_T_82544 && 883 (reg & STATUS_PCIX_MODE) != 0) { 884 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 885 886 sc->sc_flags |= WM_F_PCIX; 887 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 888 PCI_CAP_PCIX, 889 &sc->sc_pcix_offset, NULL) == 0) 890 aprint_error("%s: unable to find PCIX " 891 "capability\n", sc->sc_dev.dv_xname); 892 else if (sc->sc_type != WM_T_82545_3 && 893 sc->sc_type != WM_T_82546_3) { 894 /* 895 * Work around a problem caused by the BIOS 896 * setting the max memory read byte count 897 * incorrectly. 898 */ 899 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 900 sc->sc_pcix_offset + PCI_PCIX_CMD); 901 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 902 sc->sc_pcix_offset + PCI_PCIX_STATUS); 903 904 bytecnt = 905 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 906 PCI_PCIX_CMD_BYTECNT_SHIFT; 907 maxb = 908 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 909 PCI_PCIX_STATUS_MAXB_SHIFT; 910 if (bytecnt > maxb) { 911 aprint_verbose("%s: resetting PCI-X " 912 "MMRBC: %d -> %d\n", 913 sc->sc_dev.dv_xname, 914 512 << bytecnt, 512 << maxb); 915 pcix_cmd = (pcix_cmd & 916 ~PCI_PCIX_CMD_BYTECNT_MASK) | 917 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 918 pci_conf_write(pa->pa_pc, pa->pa_tag, 919 sc->sc_pcix_offset + PCI_PCIX_CMD, 920 pcix_cmd); 921 } 922 } 923 } 924 /* 925 * The quad port adapter is special; it has a PCIX-PCIX 926 * bridge on the board, and can run the secondary bus at 927 * a higher speed. 928 */ 929 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 930 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 931 : 66; 932 } else if (sc->sc_flags & WM_F_PCIX) { 933 switch (reg & STATUS_PCIXSPD_MASK) { 934 case STATUS_PCIXSPD_50_66: 935 sc->sc_bus_speed = 66; 936 break; 937 case STATUS_PCIXSPD_66_100: 938 sc->sc_bus_speed = 100; 939 break; 940 case STATUS_PCIXSPD_100_133: 941 sc->sc_bus_speed = 133; 942 break; 943 default: 944 aprint_error( 945 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 946 sc->sc_dev.dv_xname, 947 reg & STATUS_PCIXSPD_MASK); 948 sc->sc_bus_speed = 66; 949 } 950 } else 951 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 952 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 953 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 954 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 955 } 956 957 /* 958 * Allocate the control data structures, and create and load the 959 * DMA map for it. 960 * 961 * NOTE: All Tx descriptors must be in the same 4G segment of 962 * memory. So must Rx descriptors. We simplify by allocating 963 * both sets within the same 4G segment. 964 */ 965 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 966 WM_NTXDESC_82542 : WM_NTXDESC_82544; 967 cdata_size = sc->sc_type < WM_T_82544 ? 968 sizeof(struct wm_control_data_82542) : 969 sizeof(struct wm_control_data_82544); 970 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 971 (bus_size_t) 0x100000000ULL, 972 &seg, 1, &rseg, 0)) != 0) { 973 aprint_error( 974 "%s: unable to allocate control data, error = %d\n", 975 sc->sc_dev.dv_xname, error); 976 goto fail_0; 977 } 978 979 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 980 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 981 aprint_error("%s: unable to map control data, error = %d\n", 982 sc->sc_dev.dv_xname, error); 983 goto fail_1; 984 } 985 986 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 987 0, 0, &sc->sc_cddmamap)) != 0) { 988 aprint_error("%s: unable to create control data DMA map, " 989 "error = %d\n", sc->sc_dev.dv_xname, error); 990 goto fail_2; 991 } 992 993 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 994 sc->sc_control_data, cdata_size, NULL, 995 0)) != 0) { 996 aprint_error( 997 "%s: unable to load control data DMA map, error = %d\n", 998 sc->sc_dev.dv_xname, error); 999 goto fail_3; 1000 } 1001 1002 1003 /* 1004 * Create the transmit buffer DMA maps. 1005 */ 1006 WM_TXQUEUELEN(sc) = 1007 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1008 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1009 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1010 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1011 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1012 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1013 aprint_error("%s: unable to create Tx DMA map %d, " 1014 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1015 goto fail_4; 1016 } 1017 } 1018 1019 /* 1020 * Create the receive buffer DMA maps. 1021 */ 1022 for (i = 0; i < WM_NRXDESC; i++) { 1023 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1024 MCLBYTES, 0, 0, 1025 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1026 aprint_error("%s: unable to create Rx DMA map %d, " 1027 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1028 goto fail_5; 1029 } 1030 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1031 } 1032 1033 /* 1034 * Reset the chip to a known state. 1035 */ 1036 wm_reset(sc); 1037 1038 /* 1039 * Get some information about the EEPROM. 1040 */ 1041 if (sc->sc_type >= WM_T_82540) 1042 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1043 if (sc->sc_type <= WM_T_82544) 1044 sc->sc_ee_addrbits = 6; 1045 else if (sc->sc_type <= WM_T_82546_3) { 1046 reg = CSR_READ(sc, WMREG_EECD); 1047 if (reg & EECD_EE_SIZE) 1048 sc->sc_ee_addrbits = 8; 1049 else 1050 sc->sc_ee_addrbits = 6; 1051 } else if (sc->sc_type <= WM_T_82547_2) { 1052 reg = CSR_READ(sc, WMREG_EECD); 1053 if (reg & EECD_EE_TYPE) { 1054 sc->sc_flags |= WM_F_EEPROM_SPI; 1055 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1056 } else 1057 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1058 } else { 1059 /* Assume everything else is SPI. */ 1060 reg = CSR_READ(sc, WMREG_EECD); 1061 sc->sc_flags |= WM_F_EEPROM_SPI; 1062 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1063 } 1064 if (sc->sc_flags & WM_F_EEPROM_SPI) 1065 eetype = "SPI"; 1066 else 1067 eetype = "MicroWire"; 1068 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1069 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1070 sc->sc_ee_addrbits, eetype); 1071 1072 /* 1073 * Read the Ethernet address from the EEPROM. 1074 */ 1075 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1076 sizeof(myea) / sizeof(myea[0]), myea)) { 1077 aprint_error("%s: unable to read Ethernet address\n", 1078 sc->sc_dev.dv_xname); 1079 return; 1080 } 1081 enaddr[0] = myea[0] & 0xff; 1082 enaddr[1] = myea[0] >> 8; 1083 enaddr[2] = myea[1] & 0xff; 1084 enaddr[3] = myea[1] >> 8; 1085 enaddr[4] = myea[2] & 0xff; 1086 enaddr[5] = myea[2] >> 8; 1087 1088 /* 1089 * Toggle the LSB of the MAC address on the second port 1090 * of the i82546. 1091 */ 1092 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1093 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1094 enaddr[5] ^= 1; 1095 } 1096 1097 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1098 ether_sprintf(enaddr)); 1099 1100 /* 1101 * Read the config info from the EEPROM, and set up various 1102 * bits in the control registers based on their contents. 1103 */ 1104 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1105 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1106 sc->sc_dev.dv_xname); 1107 return; 1108 } 1109 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1110 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1111 sc->sc_dev.dv_xname); 1112 return; 1113 } 1114 if (sc->sc_type >= WM_T_82544) { 1115 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1116 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1117 sc->sc_dev.dv_xname); 1118 return; 1119 } 1120 } 1121 1122 if (cfg1 & EEPROM_CFG1_ILOS) 1123 sc->sc_ctrl |= CTRL_ILOS; 1124 if (sc->sc_type >= WM_T_82544) { 1125 sc->sc_ctrl |= 1126 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1127 CTRL_SWDPIO_SHIFT; 1128 sc->sc_ctrl |= 1129 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1130 CTRL_SWDPINS_SHIFT; 1131 } else { 1132 sc->sc_ctrl |= 1133 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1134 CTRL_SWDPIO_SHIFT; 1135 } 1136 1137 #if 0 1138 if (sc->sc_type >= WM_T_82544) { 1139 if (cfg1 & EEPROM_CFG1_IPS0) 1140 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1141 if (cfg1 & EEPROM_CFG1_IPS1) 1142 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1143 sc->sc_ctrl_ext |= 1144 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1145 CTRL_EXT_SWDPIO_SHIFT; 1146 sc->sc_ctrl_ext |= 1147 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1148 CTRL_EXT_SWDPINS_SHIFT; 1149 } else { 1150 sc->sc_ctrl_ext |= 1151 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1152 CTRL_EXT_SWDPIO_SHIFT; 1153 } 1154 #endif 1155 1156 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1157 #if 0 1158 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1159 #endif 1160 1161 /* 1162 * Set up some register offsets that are different between 1163 * the i82542 and the i82543 and later chips. 1164 */ 1165 if (sc->sc_type < WM_T_82543) { 1166 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1167 sc->sc_tdt_reg = WMREG_OLD_TDT; 1168 } else { 1169 sc->sc_rdt_reg = WMREG_RDT; 1170 sc->sc_tdt_reg = WMREG_TDT; 1171 } 1172 1173 /* 1174 * Determine if we're TBI or GMII mode, and initialize the 1175 * media structures accordingly. 1176 */ 1177 if (sc->sc_type < WM_T_82543 || 1178 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1179 if (wmp->wmp_flags & WMP_F_1000T) 1180 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1181 "product!\n", sc->sc_dev.dv_xname); 1182 wm_tbi_mediainit(sc); 1183 } else { 1184 if (wmp->wmp_flags & WMP_F_1000X) 1185 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1186 "product!\n", sc->sc_dev.dv_xname); 1187 wm_gmii_mediainit(sc); 1188 } 1189 1190 ifp = &sc->sc_ethercom.ec_if; 1191 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1192 ifp->if_softc = sc; 1193 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1194 ifp->if_ioctl = wm_ioctl; 1195 ifp->if_start = wm_start; 1196 ifp->if_watchdog = wm_watchdog; 1197 ifp->if_init = wm_init; 1198 ifp->if_stop = wm_stop; 1199 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1200 IFQ_SET_READY(&ifp->if_snd); 1201 1202 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1203 1204 /* 1205 * If we're a i82543 or greater, we can support VLANs. 1206 */ 1207 if (sc->sc_type >= WM_T_82543) 1208 sc->sc_ethercom.ec_capabilities |= 1209 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1210 1211 /* 1212 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1213 * on i82543 and later. 1214 */ 1215 if (sc->sc_type >= WM_T_82543) 1216 ifp->if_capabilities |= 1217 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1218 1219 /* 1220 * If we're a i82544 or greater (except i82547), we can do 1221 * TCP segmentation offload. 1222 */ 1223 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1224 ifp->if_capabilities |= IFCAP_TSOv4; 1225 1226 /* 1227 * Attach the interface. 1228 */ 1229 if_attach(ifp); 1230 ether_ifattach(ifp, enaddr); 1231 #if NRND > 0 1232 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1233 RND_TYPE_NET, 0); 1234 #endif 1235 1236 #ifdef WM_EVENT_COUNTERS 1237 /* Attach event counters. */ 1238 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1239 NULL, sc->sc_dev.dv_xname, "txsstall"); 1240 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1241 NULL, sc->sc_dev.dv_xname, "txdstall"); 1242 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1243 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1244 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1245 NULL, sc->sc_dev.dv_xname, "txdw"); 1246 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1247 NULL, sc->sc_dev.dv_xname, "txqe"); 1248 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1249 NULL, sc->sc_dev.dv_xname, "rxintr"); 1250 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1251 NULL, sc->sc_dev.dv_xname, "linkintr"); 1252 1253 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1254 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1255 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1256 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1257 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1258 NULL, sc->sc_dev.dv_xname, "txipsum"); 1259 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1260 NULL, sc->sc_dev.dv_xname, "txtusum"); 1261 1262 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1263 NULL, sc->sc_dev.dv_xname, "txtso"); 1264 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1265 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1266 1267 for (i = 0; i < WM_NTXSEGS; i++) { 1268 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1269 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1270 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1271 } 1272 1273 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1274 NULL, sc->sc_dev.dv_xname, "txdrop"); 1275 1276 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1277 NULL, sc->sc_dev.dv_xname, "tu"); 1278 1279 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1280 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1281 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1282 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1283 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1284 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1285 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1286 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1287 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1288 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1289 #endif /* WM_EVENT_COUNTERS */ 1290 1291 /* 1292 * Make sure the interface is shutdown during reboot. 1293 */ 1294 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1295 if (sc->sc_sdhook == NULL) 1296 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1297 sc->sc_dev.dv_xname); 1298 return; 1299 1300 /* 1301 * Free any resources we've allocated during the failed attach 1302 * attempt. Do this in reverse order and fall through. 1303 */ 1304 fail_5: 1305 for (i = 0; i < WM_NRXDESC; i++) { 1306 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1307 bus_dmamap_destroy(sc->sc_dmat, 1308 sc->sc_rxsoft[i].rxs_dmamap); 1309 } 1310 fail_4: 1311 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1312 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1313 bus_dmamap_destroy(sc->sc_dmat, 1314 sc->sc_txsoft[i].txs_dmamap); 1315 } 1316 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1317 fail_3: 1318 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1319 fail_2: 1320 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1321 cdata_size); 1322 fail_1: 1323 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1324 fail_0: 1325 return; 1326 } 1327 1328 /* 1329 * wm_shutdown: 1330 * 1331 * Make sure the interface is stopped at reboot time. 1332 */ 1333 static void 1334 wm_shutdown(void *arg) 1335 { 1336 struct wm_softc *sc = arg; 1337 1338 wm_stop(&sc->sc_ethercom.ec_if, 1); 1339 } 1340 1341 /* 1342 * wm_tx_offload: 1343 * 1344 * Set up TCP/IP checksumming parameters for the 1345 * specified packet. 1346 */ 1347 static int 1348 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1349 uint8_t *fieldsp) 1350 { 1351 struct mbuf *m0 = txs->txs_mbuf; 1352 struct livengood_tcpip_ctxdesc *t; 1353 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1354 struct ether_header *eh; 1355 int offset, iphl; 1356 uint8_t fields; 1357 1358 /* 1359 * XXX It would be nice if the mbuf pkthdr had offset 1360 * fields for the protocol headers. 1361 */ 1362 1363 eh = mtod(m0, struct ether_header *); 1364 switch (htons(eh->ether_type)) { 1365 case ETHERTYPE_IP: 1366 offset = ETHER_HDR_LEN; 1367 break; 1368 1369 case ETHERTYPE_VLAN: 1370 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1371 break; 1372 1373 default: 1374 /* 1375 * Don't support this protocol or encapsulation. 1376 */ 1377 *fieldsp = 0; 1378 *cmdp = 0; 1379 return (0); 1380 } 1381 1382 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1383 1384 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1385 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1386 seg = 0; 1387 fields = 0; 1388 1389 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1390 int hlen = offset + iphl; 1391 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1392 if (__predict_false(m0->m_len < 1393 (hlen + sizeof(struct tcphdr)))) { 1394 /* 1395 * TCP/IP headers are not in the first mbuf; we need 1396 * to do this the slow and painful way. Let's just 1397 * hope this doesn't happen very often. 1398 */ 1399 struct ip ip; 1400 struct tcphdr th; 1401 1402 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1403 1404 m_copydata(m0, offset, sizeof(ip), &ip); 1405 m_copydata(m0, hlen, sizeof(th), &th); 1406 1407 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1408 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1409 1410 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1411 sizeof(th.th_sum), &th.th_sum); 1412 1413 hlen += th.th_off << 2; 1414 } else { 1415 /* 1416 * TCP/IP headers are in the first mbuf; we can do 1417 * this the easy way. 1418 */ 1419 struct ip *ip = 1420 (struct ip *) (mtod(m0, caddr_t) + offset); 1421 struct tcphdr *th = 1422 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1423 1424 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1425 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1426 1427 hlen += th->th_off << 2; 1428 } 1429 1430 cmd |= WTX_TCPIP_CMD_TSE; 1431 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1432 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1433 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1434 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1435 } 1436 1437 /* 1438 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1439 * offload feature, if we load the context descriptor, we 1440 * MUST provide valid values for IPCSS and TUCSS fields. 1441 */ 1442 1443 ipcs = WTX_TCPIP_IPCSS(offset) | 1444 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1445 WTX_TCPIP_IPCSE(offset + iphl - 1); 1446 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1447 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1448 fields |= WTX_IXSM; 1449 } 1450 1451 offset += iphl; 1452 1453 if (m0->m_pkthdr.csum_flags & 1454 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1455 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1456 fields |= WTX_TXSM; 1457 tucs = WTX_TCPIP_TUCSS(offset) | 1458 WTX_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1459 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1460 } else { 1461 /* Just initialize it to a valid TCP context. */ 1462 tucs = WTX_TCPIP_TUCSS(offset) | 1463 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1464 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1465 } 1466 1467 /* Fill in the context descriptor. */ 1468 t = (struct livengood_tcpip_ctxdesc *) 1469 &sc->sc_txdescs[sc->sc_txnext]; 1470 t->tcpip_ipcs = htole32(ipcs); 1471 t->tcpip_tucs = htole32(tucs); 1472 t->tcpip_cmdlen = htole32(cmdlen); 1473 t->tcpip_seg = htole32(seg); 1474 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1475 1476 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1477 txs->txs_ndesc++; 1478 1479 *cmdp = cmd; 1480 *fieldsp = fields; 1481 1482 return (0); 1483 } 1484 1485 static void 1486 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1487 { 1488 struct mbuf *m; 1489 int i; 1490 1491 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1492 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1493 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1494 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1495 m->m_data, m->m_len, m->m_flags); 1496 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1497 i, i == 1 ? "" : "s"); 1498 } 1499 1500 /* 1501 * wm_82547_txfifo_stall: 1502 * 1503 * Callout used to wait for the 82547 Tx FIFO to drain, 1504 * reset the FIFO pointers, and restart packet transmission. 1505 */ 1506 static void 1507 wm_82547_txfifo_stall(void *arg) 1508 { 1509 struct wm_softc *sc = arg; 1510 int s; 1511 1512 s = splnet(); 1513 1514 if (sc->sc_txfifo_stall) { 1515 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1516 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1517 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1518 /* 1519 * Packets have drained. Stop transmitter, reset 1520 * FIFO pointers, restart transmitter, and kick 1521 * the packet queue. 1522 */ 1523 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1524 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1525 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1526 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1527 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1528 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1529 CSR_WRITE(sc, WMREG_TCTL, tctl); 1530 CSR_WRITE_FLUSH(sc); 1531 1532 sc->sc_txfifo_head = 0; 1533 sc->sc_txfifo_stall = 0; 1534 wm_start(&sc->sc_ethercom.ec_if); 1535 } else { 1536 /* 1537 * Still waiting for packets to drain; try again in 1538 * another tick. 1539 */ 1540 callout_schedule(&sc->sc_txfifo_ch, 1); 1541 } 1542 } 1543 1544 splx(s); 1545 } 1546 1547 /* 1548 * wm_82547_txfifo_bugchk: 1549 * 1550 * Check for bug condition in the 82547 Tx FIFO. We need to 1551 * prevent enqueueing a packet that would wrap around the end 1552 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1553 * 1554 * We do this by checking the amount of space before the end 1555 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1556 * the Tx FIFO, wait for all remaining packets to drain, reset 1557 * the internal FIFO pointers to the beginning, and restart 1558 * transmission on the interface. 1559 */ 1560 #define WM_FIFO_HDR 0x10 1561 #define WM_82547_PAD_LEN 0x3e0 1562 static int 1563 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1564 { 1565 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1566 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1567 1568 /* Just return if already stalled. */ 1569 if (sc->sc_txfifo_stall) 1570 return (1); 1571 1572 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1573 /* Stall only occurs in half-duplex mode. */ 1574 goto send_packet; 1575 } 1576 1577 if (len >= WM_82547_PAD_LEN + space) { 1578 sc->sc_txfifo_stall = 1; 1579 callout_schedule(&sc->sc_txfifo_ch, 1); 1580 return (1); 1581 } 1582 1583 send_packet: 1584 sc->sc_txfifo_head += len; 1585 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1586 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1587 1588 return (0); 1589 } 1590 1591 /* 1592 * wm_start: [ifnet interface function] 1593 * 1594 * Start packet transmission on the interface. 1595 */ 1596 static void 1597 wm_start(struct ifnet *ifp) 1598 { 1599 struct wm_softc *sc = ifp->if_softc; 1600 struct mbuf *m0; 1601 #if 0 /* XXXJRT */ 1602 struct m_tag *mtag; 1603 #endif 1604 struct wm_txsoft *txs; 1605 bus_dmamap_t dmamap; 1606 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1607 bus_addr_t curaddr; 1608 bus_size_t seglen, curlen; 1609 uint32_t cksumcmd; 1610 uint8_t cksumfields; 1611 1612 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1613 return; 1614 1615 /* 1616 * Remember the previous number of free descriptors. 1617 */ 1618 ofree = sc->sc_txfree; 1619 1620 /* 1621 * Loop through the send queue, setting up transmit descriptors 1622 * until we drain the queue, or use up all available transmit 1623 * descriptors. 1624 */ 1625 for (;;) { 1626 /* Grab a packet off the queue. */ 1627 IFQ_POLL(&ifp->if_snd, m0); 1628 if (m0 == NULL) 1629 break; 1630 1631 DPRINTF(WM_DEBUG_TX, 1632 ("%s: TX: have packet to transmit: %p\n", 1633 sc->sc_dev.dv_xname, m0)); 1634 1635 /* Get a work queue entry. */ 1636 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1637 wm_txintr(sc); 1638 if (sc->sc_txsfree == 0) { 1639 DPRINTF(WM_DEBUG_TX, 1640 ("%s: TX: no free job descriptors\n", 1641 sc->sc_dev.dv_xname)); 1642 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1643 break; 1644 } 1645 } 1646 1647 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1648 dmamap = txs->txs_dmamap; 1649 1650 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1651 1652 /* 1653 * So says the Linux driver: 1654 * The controller does a simple calculation to make sure 1655 * there is enough room in the FIFO before initiating the 1656 * DMA for each buffer. The calc is: 1657 * 4 = ceil(buffer len / MSS) 1658 * To make sure we don't overrun the FIFO, adjust the max 1659 * buffer len if the MSS drops. 1660 */ 1661 dmamap->dm_maxsegsz = 1662 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1663 ? m0->m_pkthdr.segsz << 2 1664 : WTX_MAX_LEN; 1665 1666 /* 1667 * Load the DMA map. If this fails, the packet either 1668 * didn't fit in the allotted number of segments, or we 1669 * were short on resources. For the too-many-segments 1670 * case, we simply report an error and drop the packet, 1671 * since we can't sanely copy a jumbo packet to a single 1672 * buffer. 1673 */ 1674 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1675 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1676 if (error) { 1677 if (error == EFBIG) { 1678 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1679 log(LOG_ERR, "%s: Tx packet consumes too many " 1680 "DMA segments, dropping...\n", 1681 sc->sc_dev.dv_xname); 1682 IFQ_DEQUEUE(&ifp->if_snd, m0); 1683 wm_dump_mbuf_chain(sc, m0); 1684 m_freem(m0); 1685 continue; 1686 } 1687 /* 1688 * Short on resources, just stop for now. 1689 */ 1690 DPRINTF(WM_DEBUG_TX, 1691 ("%s: TX: dmamap load failed: %d\n", 1692 sc->sc_dev.dv_xname, error)); 1693 break; 1694 } 1695 1696 segs_needed = dmamap->dm_nsegs; 1697 if (use_tso) { 1698 /* For sentinel descriptor; see below. */ 1699 segs_needed++; 1700 } 1701 1702 /* 1703 * Ensure we have enough descriptors free to describe 1704 * the packet. Note, we always reserve one descriptor 1705 * at the end of the ring due to the semantics of the 1706 * TDT register, plus one more in the event we need 1707 * to load offload context. 1708 */ 1709 if (segs_needed > sc->sc_txfree - 2) { 1710 /* 1711 * Not enough free descriptors to transmit this 1712 * packet. We haven't committed anything yet, 1713 * so just unload the DMA map, put the packet 1714 * pack on the queue, and punt. Notify the upper 1715 * layer that there are no more slots left. 1716 */ 1717 DPRINTF(WM_DEBUG_TX, 1718 ("%s: TX: need %d (%) descriptors, have %d\n", 1719 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1720 sc->sc_txfree - 1)); 1721 ifp->if_flags |= IFF_OACTIVE; 1722 bus_dmamap_unload(sc->sc_dmat, dmamap); 1723 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1724 break; 1725 } 1726 1727 /* 1728 * Check for 82547 Tx FIFO bug. We need to do this 1729 * once we know we can transmit the packet, since we 1730 * do some internal FIFO space accounting here. 1731 */ 1732 if (sc->sc_type == WM_T_82547 && 1733 wm_82547_txfifo_bugchk(sc, m0)) { 1734 DPRINTF(WM_DEBUG_TX, 1735 ("%s: TX: 82547 Tx FIFO bug detected\n", 1736 sc->sc_dev.dv_xname)); 1737 ifp->if_flags |= IFF_OACTIVE; 1738 bus_dmamap_unload(sc->sc_dmat, dmamap); 1739 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1740 break; 1741 } 1742 1743 IFQ_DEQUEUE(&ifp->if_snd, m0); 1744 1745 /* 1746 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1747 */ 1748 1749 DPRINTF(WM_DEBUG_TX, 1750 ("%s: TX: packet has %d (%d) DMA segments\n", 1751 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1752 1753 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1754 1755 /* 1756 * Store a pointer to the packet so that we can free it 1757 * later. 1758 * 1759 * Initially, we consider the number of descriptors the 1760 * packet uses the number of DMA segments. This may be 1761 * incremented by 1 if we do checksum offload (a descriptor 1762 * is used to set the checksum context). 1763 */ 1764 txs->txs_mbuf = m0; 1765 txs->txs_firstdesc = sc->sc_txnext; 1766 txs->txs_ndesc = segs_needed; 1767 1768 /* Set up offload parameters for this packet. */ 1769 if (m0->m_pkthdr.csum_flags & 1770 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1771 if (wm_tx_offload(sc, txs, &cksumcmd, 1772 &cksumfields) != 0) { 1773 /* Error message already displayed. */ 1774 bus_dmamap_unload(sc->sc_dmat, dmamap); 1775 continue; 1776 } 1777 } else { 1778 cksumcmd = 0; 1779 cksumfields = 0; 1780 } 1781 1782 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1783 1784 /* Sync the DMA map. */ 1785 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1786 BUS_DMASYNC_PREWRITE); 1787 1788 /* 1789 * Initialize the transmit descriptor. 1790 */ 1791 for (nexttx = sc->sc_txnext, seg = 0; 1792 seg < dmamap->dm_nsegs; seg++) { 1793 for (seglen = dmamap->dm_segs[seg].ds_len, 1794 curaddr = dmamap->dm_segs[seg].ds_addr; 1795 seglen != 0; 1796 curaddr += curlen, seglen -= curlen, 1797 nexttx = WM_NEXTTX(sc, nexttx)) { 1798 curlen = seglen; 1799 1800 /* 1801 * So says the Linux driver: 1802 * Work around for premature descriptor 1803 * write-backs in TSO mode. Append a 1804 * 4-byte sentinel descriptor. 1805 */ 1806 if (use_tso && 1807 seg == dmamap->dm_nsegs - 1 && 1808 curlen > 8) 1809 curlen -= 4; 1810 1811 wm_set_dma_addr( 1812 &sc->sc_txdescs[nexttx].wtx_addr, 1813 curaddr); 1814 sc->sc_txdescs[nexttx].wtx_cmdlen = 1815 htole32(cksumcmd | curlen); 1816 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1817 0; 1818 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1819 cksumfields; 1820 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1821 lasttx = nexttx; 1822 1823 DPRINTF(WM_DEBUG_TX, 1824 ("%s: TX: desc %d: low 0x%08x, " 1825 "len 0x%04x\n", 1826 sc->sc_dev.dv_xname, nexttx, 1827 curaddr & 0xffffffffU, curlen, curlen)); 1828 } 1829 } 1830 1831 KASSERT(lasttx != -1); 1832 1833 /* 1834 * Set up the command byte on the last descriptor of 1835 * the packet. If we're in the interrupt delay window, 1836 * delay the interrupt. 1837 */ 1838 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1839 htole32(WTX_CMD_EOP | WTX_CMD_RS); 1840 1841 #if 0 /* XXXJRT */ 1842 /* 1843 * If VLANs are enabled and the packet has a VLAN tag, set 1844 * up the descriptor to encapsulate the packet for us. 1845 * 1846 * This is only valid on the last descriptor of the packet. 1847 */ 1848 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1849 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1850 htole32(WTX_CMD_VLE); 1851 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1852 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 1853 } 1854 #endif /* XXXJRT */ 1855 1856 txs->txs_lastdesc = lasttx; 1857 1858 DPRINTF(WM_DEBUG_TX, 1859 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1860 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1861 1862 /* Sync the descriptors we're using. */ 1863 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1864 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1865 1866 /* Give the packet to the chip. */ 1867 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1868 1869 DPRINTF(WM_DEBUG_TX, 1870 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1871 1872 DPRINTF(WM_DEBUG_TX, 1873 ("%s: TX: finished transmitting packet, job %d\n", 1874 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1875 1876 /* Advance the tx pointer. */ 1877 sc->sc_txfree -= txs->txs_ndesc; 1878 sc->sc_txnext = nexttx; 1879 1880 sc->sc_txsfree--; 1881 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1882 1883 #if NBPFILTER > 0 1884 /* Pass the packet to any BPF listeners. */ 1885 if (ifp->if_bpf) 1886 bpf_mtap(ifp->if_bpf, m0); 1887 #endif /* NBPFILTER > 0 */ 1888 } 1889 1890 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1891 /* No more slots; notify upper layer. */ 1892 ifp->if_flags |= IFF_OACTIVE; 1893 } 1894 1895 if (sc->sc_txfree != ofree) { 1896 /* Set a watchdog timer in case the chip flakes out. */ 1897 ifp->if_timer = 5; 1898 } 1899 } 1900 1901 /* 1902 * wm_watchdog: [ifnet interface function] 1903 * 1904 * Watchdog timer handler. 1905 */ 1906 static void 1907 wm_watchdog(struct ifnet *ifp) 1908 { 1909 struct wm_softc *sc = ifp->if_softc; 1910 1911 /* 1912 * Since we're using delayed interrupts, sweep up 1913 * before we report an error. 1914 */ 1915 wm_txintr(sc); 1916 1917 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1918 log(LOG_ERR, 1919 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1920 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1921 sc->sc_txnext); 1922 ifp->if_oerrors++; 1923 1924 /* Reset the interface. */ 1925 (void) wm_init(ifp); 1926 } 1927 1928 /* Try to get more packets going. */ 1929 wm_start(ifp); 1930 } 1931 1932 /* 1933 * wm_ioctl: [ifnet interface function] 1934 * 1935 * Handle control requests from the operator. 1936 */ 1937 static int 1938 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1939 { 1940 struct wm_softc *sc = ifp->if_softc; 1941 struct ifreq *ifr = (struct ifreq *) data; 1942 int s, error; 1943 1944 s = splnet(); 1945 1946 switch (cmd) { 1947 case SIOCSIFMEDIA: 1948 case SIOCGIFMEDIA: 1949 /* Flow control requires full-duplex mode. */ 1950 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1951 (ifr->ifr_media & IFM_FDX) == 0) 1952 ifr->ifr_media &= ~IFM_ETH_FMASK; 1953 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1954 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1955 /* We can do both TXPAUSE and RXPAUSE. */ 1956 ifr->ifr_media |= 1957 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1958 } 1959 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1960 } 1961 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1962 break; 1963 default: 1964 error = ether_ioctl(ifp, cmd, data); 1965 if (error == ENETRESET) { 1966 /* 1967 * Multicast list has changed; set the hardware filter 1968 * accordingly. 1969 */ 1970 if (ifp->if_flags & IFF_RUNNING) 1971 wm_set_filter(sc); 1972 error = 0; 1973 } 1974 break; 1975 } 1976 1977 /* Try to get more packets going. */ 1978 wm_start(ifp); 1979 1980 splx(s); 1981 return (error); 1982 } 1983 1984 /* 1985 * wm_intr: 1986 * 1987 * Interrupt service routine. 1988 */ 1989 static int 1990 wm_intr(void *arg) 1991 { 1992 struct wm_softc *sc = arg; 1993 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1994 uint32_t icr; 1995 int wantinit, handled = 0; 1996 1997 for (wantinit = 0; wantinit == 0;) { 1998 icr = CSR_READ(sc, WMREG_ICR); 1999 if ((icr & sc->sc_icr) == 0) 2000 break; 2001 2002 #if 0 /*NRND > 0*/ 2003 if (RND_ENABLED(&sc->rnd_source)) 2004 rnd_add_uint32(&sc->rnd_source, icr); 2005 #endif 2006 2007 handled = 1; 2008 2009 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2010 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2011 DPRINTF(WM_DEBUG_RX, 2012 ("%s: RX: got Rx intr 0x%08x\n", 2013 sc->sc_dev.dv_xname, 2014 icr & (ICR_RXDMT0|ICR_RXT0))); 2015 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2016 } 2017 #endif 2018 wm_rxintr(sc); 2019 2020 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2021 if (icr & ICR_TXDW) { 2022 DPRINTF(WM_DEBUG_TX, 2023 ("%s: TX: got TXDW interrupt\n", 2024 sc->sc_dev.dv_xname)); 2025 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2026 } 2027 #endif 2028 wm_txintr(sc); 2029 2030 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2031 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2032 wm_linkintr(sc, icr); 2033 } 2034 2035 if (icr & ICR_RXO) { 2036 log(LOG_WARNING, "%s: Receive overrun\n", 2037 sc->sc_dev.dv_xname); 2038 wantinit = 1; 2039 } 2040 } 2041 2042 if (handled) { 2043 if (wantinit) 2044 wm_init(ifp); 2045 2046 /* Try to get more packets going. */ 2047 wm_start(ifp); 2048 } 2049 2050 return (handled); 2051 } 2052 2053 /* 2054 * wm_txintr: 2055 * 2056 * Helper; handle transmit interrupts. 2057 */ 2058 static void 2059 wm_txintr(struct wm_softc *sc) 2060 { 2061 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2062 struct wm_txsoft *txs; 2063 uint8_t status; 2064 int i; 2065 2066 ifp->if_flags &= ~IFF_OACTIVE; 2067 2068 /* 2069 * Go through the Tx list and free mbufs for those 2070 * frames which have been transmitted. 2071 */ 2072 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2073 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2074 txs = &sc->sc_txsoft[i]; 2075 2076 DPRINTF(WM_DEBUG_TX, 2077 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2078 2079 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2080 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2081 2082 status = 2083 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2084 if ((status & WTX_ST_DD) == 0) { 2085 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2086 BUS_DMASYNC_PREREAD); 2087 break; 2088 } 2089 2090 DPRINTF(WM_DEBUG_TX, 2091 ("%s: TX: job %d done: descs %d..%d\n", 2092 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2093 txs->txs_lastdesc)); 2094 2095 /* 2096 * XXX We should probably be using the statistics 2097 * XXX registers, but I don't know if they exist 2098 * XXX on chips before the i82544. 2099 */ 2100 2101 #ifdef WM_EVENT_COUNTERS 2102 if (status & WTX_ST_TU) 2103 WM_EVCNT_INCR(&sc->sc_ev_tu); 2104 #endif /* WM_EVENT_COUNTERS */ 2105 2106 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2107 ifp->if_oerrors++; 2108 if (status & WTX_ST_LC) 2109 log(LOG_WARNING, "%s: late collision\n", 2110 sc->sc_dev.dv_xname); 2111 else if (status & WTX_ST_EC) { 2112 ifp->if_collisions += 16; 2113 log(LOG_WARNING, "%s: excessive collisions\n", 2114 sc->sc_dev.dv_xname); 2115 } 2116 } else 2117 ifp->if_opackets++; 2118 2119 sc->sc_txfree += txs->txs_ndesc; 2120 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2121 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2122 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2123 m_freem(txs->txs_mbuf); 2124 txs->txs_mbuf = NULL; 2125 } 2126 2127 /* Update the dirty transmit buffer pointer. */ 2128 sc->sc_txsdirty = i; 2129 DPRINTF(WM_DEBUG_TX, 2130 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2131 2132 /* 2133 * If there are no more pending transmissions, cancel the watchdog 2134 * timer. 2135 */ 2136 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2137 ifp->if_timer = 0; 2138 } 2139 2140 /* 2141 * wm_rxintr: 2142 * 2143 * Helper; handle receive interrupts. 2144 */ 2145 static void 2146 wm_rxintr(struct wm_softc *sc) 2147 { 2148 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2149 struct wm_rxsoft *rxs; 2150 struct mbuf *m; 2151 int i, len; 2152 uint8_t status, errors; 2153 2154 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2155 rxs = &sc->sc_rxsoft[i]; 2156 2157 DPRINTF(WM_DEBUG_RX, 2158 ("%s: RX: checking descriptor %d\n", 2159 sc->sc_dev.dv_xname, i)); 2160 2161 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2162 2163 status = sc->sc_rxdescs[i].wrx_status; 2164 errors = sc->sc_rxdescs[i].wrx_errors; 2165 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2166 2167 if ((status & WRX_ST_DD) == 0) { 2168 /* 2169 * We have processed all of the receive descriptors. 2170 */ 2171 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2172 break; 2173 } 2174 2175 if (__predict_false(sc->sc_rxdiscard)) { 2176 DPRINTF(WM_DEBUG_RX, 2177 ("%s: RX: discarding contents of descriptor %d\n", 2178 sc->sc_dev.dv_xname, i)); 2179 WM_INIT_RXDESC(sc, i); 2180 if (status & WRX_ST_EOP) { 2181 /* Reset our state. */ 2182 DPRINTF(WM_DEBUG_RX, 2183 ("%s: RX: resetting rxdiscard -> 0\n", 2184 sc->sc_dev.dv_xname)); 2185 sc->sc_rxdiscard = 0; 2186 } 2187 continue; 2188 } 2189 2190 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2191 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2192 2193 m = rxs->rxs_mbuf; 2194 2195 /* 2196 * Add a new receive buffer to the ring. 2197 */ 2198 if (wm_add_rxbuf(sc, i) != 0) { 2199 /* 2200 * Failed, throw away what we've done so 2201 * far, and discard the rest of the packet. 2202 */ 2203 ifp->if_ierrors++; 2204 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2205 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2206 WM_INIT_RXDESC(sc, i); 2207 if ((status & WRX_ST_EOP) == 0) 2208 sc->sc_rxdiscard = 1; 2209 if (sc->sc_rxhead != NULL) 2210 m_freem(sc->sc_rxhead); 2211 WM_RXCHAIN_RESET(sc); 2212 DPRINTF(WM_DEBUG_RX, 2213 ("%s: RX: Rx buffer allocation failed, " 2214 "dropping packet%s\n", sc->sc_dev.dv_xname, 2215 sc->sc_rxdiscard ? " (discard)" : "")); 2216 continue; 2217 } 2218 2219 WM_RXCHAIN_LINK(sc, m); 2220 2221 m->m_len = len; 2222 2223 DPRINTF(WM_DEBUG_RX, 2224 ("%s: RX: buffer at %p len %d\n", 2225 sc->sc_dev.dv_xname, m->m_data, len)); 2226 2227 /* 2228 * If this is not the end of the packet, keep 2229 * looking. 2230 */ 2231 if ((status & WRX_ST_EOP) == 0) { 2232 sc->sc_rxlen += len; 2233 DPRINTF(WM_DEBUG_RX, 2234 ("%s: RX: not yet EOP, rxlen -> %d\n", 2235 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2236 continue; 2237 } 2238 2239 /* 2240 * Okay, we have the entire packet now. The chip is 2241 * configured to include the FCS (not all chips can 2242 * be configured to strip it), so we need to trim it. 2243 */ 2244 m->m_len -= ETHER_CRC_LEN; 2245 2246 *sc->sc_rxtailp = NULL; 2247 m = sc->sc_rxhead; 2248 len = m->m_len + sc->sc_rxlen; 2249 2250 WM_RXCHAIN_RESET(sc); 2251 2252 DPRINTF(WM_DEBUG_RX, 2253 ("%s: RX: have entire packet, len -> %d\n", 2254 sc->sc_dev.dv_xname, len)); 2255 2256 /* 2257 * If an error occurred, update stats and drop the packet. 2258 */ 2259 if (errors & 2260 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2261 ifp->if_ierrors++; 2262 if (errors & WRX_ER_SE) 2263 log(LOG_WARNING, "%s: symbol error\n", 2264 sc->sc_dev.dv_xname); 2265 else if (errors & WRX_ER_SEQ) 2266 log(LOG_WARNING, "%s: receive sequence error\n", 2267 sc->sc_dev.dv_xname); 2268 else if (errors & WRX_ER_CE) 2269 log(LOG_WARNING, "%s: CRC error\n", 2270 sc->sc_dev.dv_xname); 2271 m_freem(m); 2272 continue; 2273 } 2274 2275 /* 2276 * No errors. Receive the packet. 2277 */ 2278 m->m_pkthdr.rcvif = ifp; 2279 m->m_pkthdr.len = len; 2280 2281 #if 0 /* XXXJRT */ 2282 /* 2283 * If VLANs are enabled, VLAN packets have been unwrapped 2284 * for us. Associate the tag with the packet. 2285 */ 2286 if ((status & WRX_ST_VP) != 0) { 2287 VLAN_INPUT_TAG(ifp, m, 2288 le16toh(sc->sc_rxdescs[i].wrx_special, 2289 continue); 2290 } 2291 #endif /* XXXJRT */ 2292 2293 /* 2294 * Set up checksum info for this packet. 2295 */ 2296 if (status & WRX_ST_IPCS) { 2297 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2298 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2299 if (errors & WRX_ER_IPE) 2300 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2301 } 2302 if (status & WRX_ST_TCPCS) { 2303 /* 2304 * Note: we don't know if this was TCP or UDP, 2305 * so we just set both bits, and expect the 2306 * upper layers to deal. 2307 */ 2308 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2309 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2310 if (errors & WRX_ER_TCPE) 2311 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2312 } 2313 2314 ifp->if_ipackets++; 2315 2316 #if NBPFILTER > 0 2317 /* Pass this up to any BPF listeners. */ 2318 if (ifp->if_bpf) 2319 bpf_mtap(ifp->if_bpf, m); 2320 #endif /* NBPFILTER > 0 */ 2321 2322 /* Pass it on. */ 2323 (*ifp->if_input)(ifp, m); 2324 } 2325 2326 /* Update the receive pointer. */ 2327 sc->sc_rxptr = i; 2328 2329 DPRINTF(WM_DEBUG_RX, 2330 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2331 } 2332 2333 /* 2334 * wm_linkintr: 2335 * 2336 * Helper; handle link interrupts. 2337 */ 2338 static void 2339 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2340 { 2341 uint32_t status; 2342 2343 /* 2344 * If we get a link status interrupt on a 1000BASE-T 2345 * device, just fall into the normal MII tick path. 2346 */ 2347 if (sc->sc_flags & WM_F_HAS_MII) { 2348 if (icr & ICR_LSC) { 2349 DPRINTF(WM_DEBUG_LINK, 2350 ("%s: LINK: LSC -> mii_tick\n", 2351 sc->sc_dev.dv_xname)); 2352 mii_tick(&sc->sc_mii); 2353 } else if (icr & ICR_RXSEQ) { 2354 DPRINTF(WM_DEBUG_LINK, 2355 ("%s: LINK Receive sequence error\n", 2356 sc->sc_dev.dv_xname)); 2357 } 2358 return; 2359 } 2360 2361 /* 2362 * If we are now receiving /C/, check for link again in 2363 * a couple of link clock ticks. 2364 */ 2365 if (icr & ICR_RXCFG) { 2366 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2367 sc->sc_dev.dv_xname)); 2368 sc->sc_tbi_anstate = 2; 2369 } 2370 2371 if (icr & ICR_LSC) { 2372 status = CSR_READ(sc, WMREG_STATUS); 2373 if (status & STATUS_LU) { 2374 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2375 sc->sc_dev.dv_xname, 2376 (status & STATUS_FD) ? "FDX" : "HDX")); 2377 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2378 sc->sc_fcrtl &= ~FCRTL_XONE; 2379 if (status & STATUS_FD) 2380 sc->sc_tctl |= 2381 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2382 else 2383 sc->sc_tctl |= 2384 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2385 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2386 sc->sc_fcrtl |= FCRTL_XONE; 2387 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2388 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2389 WMREG_OLD_FCRTL : WMREG_FCRTL, 2390 sc->sc_fcrtl); 2391 sc->sc_tbi_linkup = 1; 2392 } else { 2393 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2394 sc->sc_dev.dv_xname)); 2395 sc->sc_tbi_linkup = 0; 2396 } 2397 sc->sc_tbi_anstate = 2; 2398 wm_tbi_set_linkled(sc); 2399 } else if (icr & ICR_RXSEQ) { 2400 DPRINTF(WM_DEBUG_LINK, 2401 ("%s: LINK: Receive sequence error\n", 2402 sc->sc_dev.dv_xname)); 2403 } 2404 } 2405 2406 /* 2407 * wm_tick: 2408 * 2409 * One second timer, used to check link status, sweep up 2410 * completed transmit jobs, etc. 2411 */ 2412 static void 2413 wm_tick(void *arg) 2414 { 2415 struct wm_softc *sc = arg; 2416 int s; 2417 2418 s = splnet(); 2419 2420 if (sc->sc_type >= WM_T_82542_2_1) { 2421 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2422 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2423 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2424 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2425 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2426 } 2427 2428 if (sc->sc_flags & WM_F_HAS_MII) 2429 mii_tick(&sc->sc_mii); 2430 else 2431 wm_tbi_check_link(sc); 2432 2433 splx(s); 2434 2435 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2436 } 2437 2438 /* 2439 * wm_reset: 2440 * 2441 * Reset the i82542 chip. 2442 */ 2443 static void 2444 wm_reset(struct wm_softc *sc) 2445 { 2446 int i; 2447 2448 /* 2449 * Allocate on-chip memory according to the MTU size. 2450 * The Packet Buffer Allocation register must be written 2451 * before the chip is reset. 2452 */ 2453 if (sc->sc_type < WM_T_82547) { 2454 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2455 PBA_40K : PBA_48K; 2456 } else { 2457 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2458 PBA_22K : PBA_30K; 2459 sc->sc_txfifo_head = 0; 2460 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2461 sc->sc_txfifo_size = 2462 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2463 sc->sc_txfifo_stall = 0; 2464 } 2465 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2466 2467 switch (sc->sc_type) { 2468 case WM_T_82544: 2469 case WM_T_82540: 2470 case WM_T_82545: 2471 case WM_T_82546: 2472 case WM_T_82541: 2473 case WM_T_82541_2: 2474 /* 2475 * On some chipsets, a reset through a memory-mapped write 2476 * cycle can cause the chip to reset before completing the 2477 * write cycle. This causes major headache that can be 2478 * avoided by issuing the reset via indirect register writes 2479 * through I/O space. 2480 * 2481 * So, if we successfully mapped the I/O BAR at attach time, 2482 * use that. Otherwise, try our luck with a memory-mapped 2483 * reset. 2484 */ 2485 if (sc->sc_flags & WM_F_IOH_VALID) 2486 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2487 else 2488 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2489 break; 2490 2491 case WM_T_82545_3: 2492 case WM_T_82546_3: 2493 /* Use the shadow control register on these chips. */ 2494 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2495 break; 2496 2497 default: 2498 /* Everything else can safely use the documented method. */ 2499 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2500 break; 2501 } 2502 delay(10000); 2503 2504 for (i = 0; i < 1000; i++) { 2505 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2506 return; 2507 delay(20); 2508 } 2509 2510 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2511 log(LOG_ERR, "%s: reset failed to complete\n", 2512 sc->sc_dev.dv_xname); 2513 } 2514 2515 /* 2516 * wm_init: [ifnet interface function] 2517 * 2518 * Initialize the interface. Must be called at splnet(). 2519 */ 2520 static int 2521 wm_init(struct ifnet *ifp) 2522 { 2523 struct wm_softc *sc = ifp->if_softc; 2524 struct wm_rxsoft *rxs; 2525 int i, error = 0; 2526 uint32_t reg; 2527 2528 /* 2529 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2530 * There is a small but measurable benefit to avoiding the adjusment 2531 * of the descriptor so that the headers are aligned, for normal mtu, 2532 * on such platforms. One possibility is that the DMA itself is 2533 * slightly more efficient if the front of the entire packet (instead 2534 * of the front of the headers) is aligned. 2535 * 2536 * Note we must always set align_tweak to 0 if we are using 2537 * jumbo frames. 2538 */ 2539 #ifdef __NO_STRICT_ALIGNMENT 2540 sc->sc_align_tweak = 0; 2541 #else 2542 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2543 sc->sc_align_tweak = 0; 2544 else 2545 sc->sc_align_tweak = 2; 2546 #endif /* __NO_STRICT_ALIGNMENT */ 2547 2548 /* Cancel any pending I/O. */ 2549 wm_stop(ifp, 0); 2550 2551 /* Reset the chip to a known state. */ 2552 wm_reset(sc); 2553 2554 /* Initialize the transmit descriptor ring. */ 2555 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2556 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2557 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2558 sc->sc_txfree = WM_NTXDESC(sc); 2559 sc->sc_txnext = 0; 2560 2561 if (sc->sc_type < WM_T_82543) { 2562 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2563 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2564 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2565 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2566 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2567 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2568 } else { 2569 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2570 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2571 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2572 CSR_WRITE(sc, WMREG_TDH, 0); 2573 CSR_WRITE(sc, WMREG_TDT, 0); 2574 CSR_WRITE(sc, WMREG_TIDV, 64); 2575 CSR_WRITE(sc, WMREG_TADV, 128); 2576 2577 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2578 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2579 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2580 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2581 } 2582 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2583 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2584 2585 /* Initialize the transmit job descriptors. */ 2586 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2587 sc->sc_txsoft[i].txs_mbuf = NULL; 2588 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2589 sc->sc_txsnext = 0; 2590 sc->sc_txsdirty = 0; 2591 2592 /* 2593 * Initialize the receive descriptor and receive job 2594 * descriptor rings. 2595 */ 2596 if (sc->sc_type < WM_T_82543) { 2597 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2598 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2599 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2600 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2601 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2602 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2603 2604 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2605 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2606 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2607 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2608 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2609 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2610 } else { 2611 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2612 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2613 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2614 CSR_WRITE(sc, WMREG_RDH, 0); 2615 CSR_WRITE(sc, WMREG_RDT, 0); 2616 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2617 CSR_WRITE(sc, WMREG_RADV, 128); 2618 } 2619 for (i = 0; i < WM_NRXDESC; i++) { 2620 rxs = &sc->sc_rxsoft[i]; 2621 if (rxs->rxs_mbuf == NULL) { 2622 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2623 log(LOG_ERR, "%s: unable to allocate or map rx " 2624 "buffer %d, error = %d\n", 2625 sc->sc_dev.dv_xname, i, error); 2626 /* 2627 * XXX Should attempt to run with fewer receive 2628 * XXX buffers instead of just failing. 2629 */ 2630 wm_rxdrain(sc); 2631 goto out; 2632 } 2633 } else 2634 WM_INIT_RXDESC(sc, i); 2635 } 2636 sc->sc_rxptr = 0; 2637 sc->sc_rxdiscard = 0; 2638 WM_RXCHAIN_RESET(sc); 2639 2640 /* 2641 * Clear out the VLAN table -- we don't use it (yet). 2642 */ 2643 CSR_WRITE(sc, WMREG_VET, 0); 2644 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2645 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2646 2647 /* 2648 * Set up flow-control parameters. 2649 * 2650 * XXX Values could probably stand some tuning. 2651 */ 2652 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2653 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2654 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2655 2656 sc->sc_fcrtl = FCRTL_DFLT; 2657 if (sc->sc_type < WM_T_82543) { 2658 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2659 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2660 } else { 2661 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2662 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2663 } 2664 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2665 2666 #if 0 /* XXXJRT */ 2667 /* Deal with VLAN enables. */ 2668 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2669 sc->sc_ctrl |= CTRL_VME; 2670 else 2671 #endif /* XXXJRT */ 2672 sc->sc_ctrl &= ~CTRL_VME; 2673 2674 /* Write the control registers. */ 2675 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2676 #if 0 2677 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2678 #endif 2679 2680 /* 2681 * Set up checksum offload parameters. 2682 */ 2683 reg = CSR_READ(sc, WMREG_RXCSUM); 2684 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2685 reg |= RXCSUM_IPOFL; 2686 else 2687 reg &= ~RXCSUM_IPOFL; 2688 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2689 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2690 else { 2691 reg &= ~RXCSUM_TUOFL; 2692 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2693 reg &= ~RXCSUM_IPOFL; 2694 } 2695 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2696 2697 /* 2698 * Set up the interrupt registers. 2699 */ 2700 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2701 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2702 ICR_RXO | ICR_RXT0; 2703 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2704 sc->sc_icr |= ICR_RXCFG; 2705 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2706 2707 /* Set up the inter-packet gap. */ 2708 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2709 2710 if (sc->sc_type >= WM_T_82543) { 2711 /* Set up the interrupt throttling register (units of 256ns) */ 2712 sc->sc_itr = 1000000000 / (7000 * 256); 2713 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2714 } 2715 2716 #if 0 /* XXXJRT */ 2717 /* Set the VLAN ethernetype. */ 2718 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2719 #endif 2720 2721 /* 2722 * Set up the transmit control register; we start out with 2723 * a collision distance suitable for FDX, but update it whe 2724 * we resolve the media type. 2725 */ 2726 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2727 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2728 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2729 2730 /* Set the media. */ 2731 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2732 2733 /* 2734 * Set up the receive control register; we actually program 2735 * the register when we set the receive filter. Use multicast 2736 * address offset type 0. 2737 * 2738 * Only the i82544 has the ability to strip the incoming 2739 * CRC, so we don't enable that feature. 2740 */ 2741 sc->sc_mchash_type = 0; 2742 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2743 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2744 2745 if(MCLBYTES == 2048) { 2746 sc->sc_rctl |= RCTL_2k; 2747 } else { 2748 if(sc->sc_type >= WM_T_82543) { 2749 switch(MCLBYTES) { 2750 case 4096: 2751 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2752 break; 2753 case 8192: 2754 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2755 break; 2756 case 16384: 2757 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2758 break; 2759 default: 2760 panic("wm_init: MCLBYTES %d unsupported", 2761 MCLBYTES); 2762 break; 2763 } 2764 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2765 } 2766 2767 /* Set the receive filter. */ 2768 wm_set_filter(sc); 2769 2770 /* Start the one second link check clock. */ 2771 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2772 2773 /* ...all done! */ 2774 ifp->if_flags |= IFF_RUNNING; 2775 ifp->if_flags &= ~IFF_OACTIVE; 2776 2777 out: 2778 if (error) 2779 log(LOG_ERR, "%s: interface not running\n", 2780 sc->sc_dev.dv_xname); 2781 return (error); 2782 } 2783 2784 /* 2785 * wm_rxdrain: 2786 * 2787 * Drain the receive queue. 2788 */ 2789 static void 2790 wm_rxdrain(struct wm_softc *sc) 2791 { 2792 struct wm_rxsoft *rxs; 2793 int i; 2794 2795 for (i = 0; i < WM_NRXDESC; i++) { 2796 rxs = &sc->sc_rxsoft[i]; 2797 if (rxs->rxs_mbuf != NULL) { 2798 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2799 m_freem(rxs->rxs_mbuf); 2800 rxs->rxs_mbuf = NULL; 2801 } 2802 } 2803 } 2804 2805 /* 2806 * wm_stop: [ifnet interface function] 2807 * 2808 * Stop transmission on the interface. 2809 */ 2810 static void 2811 wm_stop(struct ifnet *ifp, int disable) 2812 { 2813 struct wm_softc *sc = ifp->if_softc; 2814 struct wm_txsoft *txs; 2815 int i; 2816 2817 /* Stop the one second clock. */ 2818 callout_stop(&sc->sc_tick_ch); 2819 2820 /* Stop the 82547 Tx FIFO stall check timer. */ 2821 if (sc->sc_type == WM_T_82547) 2822 callout_stop(&sc->sc_txfifo_ch); 2823 2824 if (sc->sc_flags & WM_F_HAS_MII) { 2825 /* Down the MII. */ 2826 mii_down(&sc->sc_mii); 2827 } 2828 2829 /* Stop the transmit and receive processes. */ 2830 CSR_WRITE(sc, WMREG_TCTL, 0); 2831 CSR_WRITE(sc, WMREG_RCTL, 0); 2832 2833 /* Release any queued transmit buffers. */ 2834 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2835 txs = &sc->sc_txsoft[i]; 2836 if (txs->txs_mbuf != NULL) { 2837 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2838 m_freem(txs->txs_mbuf); 2839 txs->txs_mbuf = NULL; 2840 } 2841 } 2842 2843 if (disable) 2844 wm_rxdrain(sc); 2845 2846 /* Mark the interface as down and cancel the watchdog timer. */ 2847 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2848 ifp->if_timer = 0; 2849 } 2850 2851 /* 2852 * wm_acquire_eeprom: 2853 * 2854 * Perform the EEPROM handshake required on some chips. 2855 */ 2856 static int 2857 wm_acquire_eeprom(struct wm_softc *sc) 2858 { 2859 uint32_t reg; 2860 int x; 2861 2862 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2863 reg = CSR_READ(sc, WMREG_EECD); 2864 2865 /* Request EEPROM access. */ 2866 reg |= EECD_EE_REQ; 2867 CSR_WRITE(sc, WMREG_EECD, reg); 2868 2869 /* ..and wait for it to be granted. */ 2870 for (x = 0; x < 100; x++) { 2871 reg = CSR_READ(sc, WMREG_EECD); 2872 if (reg & EECD_EE_GNT) 2873 break; 2874 delay(5); 2875 } 2876 if ((reg & EECD_EE_GNT) == 0) { 2877 aprint_error("%s: could not acquire EEPROM GNT\n", 2878 sc->sc_dev.dv_xname); 2879 reg &= ~EECD_EE_REQ; 2880 CSR_WRITE(sc, WMREG_EECD, reg); 2881 return (1); 2882 } 2883 } 2884 2885 return (0); 2886 } 2887 2888 /* 2889 * wm_release_eeprom: 2890 * 2891 * Release the EEPROM mutex. 2892 */ 2893 static void 2894 wm_release_eeprom(struct wm_softc *sc) 2895 { 2896 uint32_t reg; 2897 2898 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2899 reg = CSR_READ(sc, WMREG_EECD); 2900 reg &= ~EECD_EE_REQ; 2901 CSR_WRITE(sc, WMREG_EECD, reg); 2902 } 2903 } 2904 2905 /* 2906 * wm_eeprom_sendbits: 2907 * 2908 * Send a series of bits to the EEPROM. 2909 */ 2910 static void 2911 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2912 { 2913 uint32_t reg; 2914 int x; 2915 2916 reg = CSR_READ(sc, WMREG_EECD); 2917 2918 for (x = nbits; x > 0; x--) { 2919 if (bits & (1U << (x - 1))) 2920 reg |= EECD_DI; 2921 else 2922 reg &= ~EECD_DI; 2923 CSR_WRITE(sc, WMREG_EECD, reg); 2924 delay(2); 2925 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2926 delay(2); 2927 CSR_WRITE(sc, WMREG_EECD, reg); 2928 delay(2); 2929 } 2930 } 2931 2932 /* 2933 * wm_eeprom_recvbits: 2934 * 2935 * Receive a series of bits from the EEPROM. 2936 */ 2937 static void 2938 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2939 { 2940 uint32_t reg, val; 2941 int x; 2942 2943 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2944 2945 val = 0; 2946 for (x = nbits; x > 0; x--) { 2947 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2948 delay(2); 2949 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2950 val |= (1U << (x - 1)); 2951 CSR_WRITE(sc, WMREG_EECD, reg); 2952 delay(2); 2953 } 2954 *valp = val; 2955 } 2956 2957 /* 2958 * wm_read_eeprom_uwire: 2959 * 2960 * Read a word from the EEPROM using the MicroWire protocol. 2961 */ 2962 static int 2963 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2964 { 2965 uint32_t reg, val; 2966 int i; 2967 2968 for (i = 0; i < wordcnt; i++) { 2969 /* Clear SK and DI. */ 2970 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2971 CSR_WRITE(sc, WMREG_EECD, reg); 2972 2973 /* Set CHIP SELECT. */ 2974 reg |= EECD_CS; 2975 CSR_WRITE(sc, WMREG_EECD, reg); 2976 delay(2); 2977 2978 /* Shift in the READ command. */ 2979 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2980 2981 /* Shift in address. */ 2982 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2983 2984 /* Shift out the data. */ 2985 wm_eeprom_recvbits(sc, &val, 16); 2986 data[i] = val & 0xffff; 2987 2988 /* Clear CHIP SELECT. */ 2989 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 2990 CSR_WRITE(sc, WMREG_EECD, reg); 2991 delay(2); 2992 } 2993 2994 return (0); 2995 } 2996 2997 /* 2998 * wm_spi_eeprom_ready: 2999 * 3000 * Wait for a SPI EEPROM to be ready for commands. 3001 */ 3002 static int 3003 wm_spi_eeprom_ready(struct wm_softc *sc) 3004 { 3005 uint32_t val; 3006 int usec; 3007 3008 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3009 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3010 wm_eeprom_recvbits(sc, &val, 8); 3011 if ((val & SPI_SR_RDY) == 0) 3012 break; 3013 } 3014 if (usec >= SPI_MAX_RETRIES) { 3015 aprint_error("%s: EEPROM failed to become ready\n", 3016 sc->sc_dev.dv_xname); 3017 return (1); 3018 } 3019 return (0); 3020 } 3021 3022 /* 3023 * wm_read_eeprom_spi: 3024 * 3025 * Read a work from the EEPROM using the SPI protocol. 3026 */ 3027 static int 3028 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3029 { 3030 uint32_t reg, val; 3031 int i; 3032 uint8_t opc; 3033 3034 /* Clear SK and CS. */ 3035 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3036 CSR_WRITE(sc, WMREG_EECD, reg); 3037 delay(2); 3038 3039 if (wm_spi_eeprom_ready(sc)) 3040 return (1); 3041 3042 /* Toggle CS to flush commands. */ 3043 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3044 delay(2); 3045 CSR_WRITE(sc, WMREG_EECD, reg); 3046 delay(2); 3047 3048 opc = SPI_OPC_READ; 3049 if (sc->sc_ee_addrbits == 8 && word >= 128) 3050 opc |= SPI_OPC_A8; 3051 3052 wm_eeprom_sendbits(sc, opc, 8); 3053 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3054 3055 for (i = 0; i < wordcnt; i++) { 3056 wm_eeprom_recvbits(sc, &val, 16); 3057 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3058 } 3059 3060 /* Raise CS and clear SK. */ 3061 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3062 CSR_WRITE(sc, WMREG_EECD, reg); 3063 delay(2); 3064 3065 return (0); 3066 } 3067 3068 /* 3069 * wm_read_eeprom: 3070 * 3071 * Read data from the serial EEPROM. 3072 */ 3073 static int 3074 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3075 { 3076 int rv; 3077 3078 if (wm_acquire_eeprom(sc)) 3079 return (1); 3080 3081 if (sc->sc_flags & WM_F_EEPROM_SPI) 3082 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3083 else 3084 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3085 3086 wm_release_eeprom(sc); 3087 return (rv); 3088 } 3089 3090 /* 3091 * wm_add_rxbuf: 3092 * 3093 * Add a receive buffer to the indiciated descriptor. 3094 */ 3095 static int 3096 wm_add_rxbuf(struct wm_softc *sc, int idx) 3097 { 3098 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3099 struct mbuf *m; 3100 int error; 3101 3102 MGETHDR(m, M_DONTWAIT, MT_DATA); 3103 if (m == NULL) 3104 return (ENOBUFS); 3105 3106 MCLGET(m, M_DONTWAIT); 3107 if ((m->m_flags & M_EXT) == 0) { 3108 m_freem(m); 3109 return (ENOBUFS); 3110 } 3111 3112 if (rxs->rxs_mbuf != NULL) 3113 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3114 3115 rxs->rxs_mbuf = m; 3116 3117 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3118 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3119 BUS_DMA_READ|BUS_DMA_NOWAIT); 3120 if (error) { 3121 /* XXX XXX XXX */ 3122 printf("%s: unable to load rx DMA map %d, error = %d\n", 3123 sc->sc_dev.dv_xname, idx, error); 3124 panic("wm_add_rxbuf"); 3125 } 3126 3127 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3128 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3129 3130 WM_INIT_RXDESC(sc, idx); 3131 3132 return (0); 3133 } 3134 3135 /* 3136 * wm_set_ral: 3137 * 3138 * Set an entery in the receive address list. 3139 */ 3140 static void 3141 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3142 { 3143 uint32_t ral_lo, ral_hi; 3144 3145 if (enaddr != NULL) { 3146 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3147 (enaddr[3] << 24); 3148 ral_hi = enaddr[4] | (enaddr[5] << 8); 3149 ral_hi |= RAL_AV; 3150 } else { 3151 ral_lo = 0; 3152 ral_hi = 0; 3153 } 3154 3155 if (sc->sc_type >= WM_T_82544) { 3156 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3157 ral_lo); 3158 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3159 ral_hi); 3160 } else { 3161 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3162 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3163 } 3164 } 3165 3166 /* 3167 * wm_mchash: 3168 * 3169 * Compute the hash of the multicast address for the 4096-bit 3170 * multicast filter. 3171 */ 3172 static uint32_t 3173 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3174 { 3175 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3176 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3177 uint32_t hash; 3178 3179 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3180 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3181 3182 return (hash & 0xfff); 3183 } 3184 3185 /* 3186 * wm_set_filter: 3187 * 3188 * Set up the receive filter. 3189 */ 3190 static void 3191 wm_set_filter(struct wm_softc *sc) 3192 { 3193 struct ethercom *ec = &sc->sc_ethercom; 3194 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3195 struct ether_multi *enm; 3196 struct ether_multistep step; 3197 bus_addr_t mta_reg; 3198 uint32_t hash, reg, bit; 3199 int i; 3200 3201 if (sc->sc_type >= WM_T_82544) 3202 mta_reg = WMREG_CORDOVA_MTA; 3203 else 3204 mta_reg = WMREG_MTA; 3205 3206 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3207 3208 if (ifp->if_flags & IFF_BROADCAST) 3209 sc->sc_rctl |= RCTL_BAM; 3210 if (ifp->if_flags & IFF_PROMISC) { 3211 sc->sc_rctl |= RCTL_UPE; 3212 goto allmulti; 3213 } 3214 3215 /* 3216 * Set the station address in the first RAL slot, and 3217 * clear the remaining slots. 3218 */ 3219 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3220 for (i = 1; i < WM_RAL_TABSIZE; i++) 3221 wm_set_ral(sc, NULL, i); 3222 3223 /* Clear out the multicast table. */ 3224 for (i = 0; i < WM_MC_TABSIZE; i++) 3225 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3226 3227 ETHER_FIRST_MULTI(step, ec, enm); 3228 while (enm != NULL) { 3229 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3230 /* 3231 * We must listen to a range of multicast addresses. 3232 * For now, just accept all multicasts, rather than 3233 * trying to set only those filter bits needed to match 3234 * the range. (At this time, the only use of address 3235 * ranges is for IP multicast routing, for which the 3236 * range is big enough to require all bits set.) 3237 */ 3238 goto allmulti; 3239 } 3240 3241 hash = wm_mchash(sc, enm->enm_addrlo); 3242 3243 reg = (hash >> 5) & 0x7f; 3244 bit = hash & 0x1f; 3245 3246 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3247 hash |= 1U << bit; 3248 3249 /* XXX Hardware bug?? */ 3250 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3251 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3252 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3253 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3254 } else 3255 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3256 3257 ETHER_NEXT_MULTI(step, enm); 3258 } 3259 3260 ifp->if_flags &= ~IFF_ALLMULTI; 3261 goto setit; 3262 3263 allmulti: 3264 ifp->if_flags |= IFF_ALLMULTI; 3265 sc->sc_rctl |= RCTL_MPE; 3266 3267 setit: 3268 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3269 } 3270 3271 /* 3272 * wm_tbi_mediainit: 3273 * 3274 * Initialize media for use on 1000BASE-X devices. 3275 */ 3276 static void 3277 wm_tbi_mediainit(struct wm_softc *sc) 3278 { 3279 const char *sep = ""; 3280 3281 if (sc->sc_type < WM_T_82543) 3282 sc->sc_tipg = TIPG_WM_DFLT; 3283 else 3284 sc->sc_tipg = TIPG_LG_DFLT; 3285 3286 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3287 wm_tbi_mediastatus); 3288 3289 /* 3290 * SWD Pins: 3291 * 3292 * 0 = Link LED (output) 3293 * 1 = Loss Of Signal (input) 3294 */ 3295 sc->sc_ctrl |= CTRL_SWDPIO(0); 3296 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3297 3298 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3299 3300 #define ADD(ss, mm, dd) \ 3301 do { \ 3302 aprint_normal("%s%s", sep, ss); \ 3303 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3304 sep = ", "; \ 3305 } while (/*CONSTCOND*/0) 3306 3307 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3308 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3309 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3310 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3311 aprint_normal("\n"); 3312 3313 #undef ADD 3314 3315 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3316 } 3317 3318 /* 3319 * wm_tbi_mediastatus: [ifmedia interface function] 3320 * 3321 * Get the current interface media status on a 1000BASE-X device. 3322 */ 3323 static void 3324 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3325 { 3326 struct wm_softc *sc = ifp->if_softc; 3327 uint32_t ctrl; 3328 3329 ifmr->ifm_status = IFM_AVALID; 3330 ifmr->ifm_active = IFM_ETHER; 3331 3332 if (sc->sc_tbi_linkup == 0) { 3333 ifmr->ifm_active |= IFM_NONE; 3334 return; 3335 } 3336 3337 ifmr->ifm_status |= IFM_ACTIVE; 3338 ifmr->ifm_active |= IFM_1000_SX; 3339 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3340 ifmr->ifm_active |= IFM_FDX; 3341 ctrl = CSR_READ(sc, WMREG_CTRL); 3342 if (ctrl & CTRL_RFCE) 3343 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3344 if (ctrl & CTRL_TFCE) 3345 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3346 } 3347 3348 /* 3349 * wm_tbi_mediachange: [ifmedia interface function] 3350 * 3351 * Set hardware to newly-selected media on a 1000BASE-X device. 3352 */ 3353 static int 3354 wm_tbi_mediachange(struct ifnet *ifp) 3355 { 3356 struct wm_softc *sc = ifp->if_softc; 3357 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3358 uint32_t status; 3359 int i; 3360 3361 sc->sc_txcw = ife->ifm_data; 3362 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3363 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3364 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3365 sc->sc_txcw |= TXCW_ANE; 3366 3367 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3368 delay(10000); 3369 3370 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3371 3372 sc->sc_tbi_anstate = 0; 3373 3374 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3375 /* Have signal; wait for the link to come up. */ 3376 for (i = 0; i < 50; i++) { 3377 delay(10000); 3378 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3379 break; 3380 } 3381 3382 status = CSR_READ(sc, WMREG_STATUS); 3383 if (status & STATUS_LU) { 3384 /* Link is up. */ 3385 DPRINTF(WM_DEBUG_LINK, 3386 ("%s: LINK: set media -> link up %s\n", 3387 sc->sc_dev.dv_xname, 3388 (status & STATUS_FD) ? "FDX" : "HDX")); 3389 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3390 sc->sc_fcrtl &= ~FCRTL_XONE; 3391 if (status & STATUS_FD) 3392 sc->sc_tctl |= 3393 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3394 else 3395 sc->sc_tctl |= 3396 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3397 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3398 sc->sc_fcrtl |= FCRTL_XONE; 3399 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3400 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3401 WMREG_OLD_FCRTL : WMREG_FCRTL, 3402 sc->sc_fcrtl); 3403 sc->sc_tbi_linkup = 1; 3404 } else { 3405 /* Link is down. */ 3406 DPRINTF(WM_DEBUG_LINK, 3407 ("%s: LINK: set media -> link down\n", 3408 sc->sc_dev.dv_xname)); 3409 sc->sc_tbi_linkup = 0; 3410 } 3411 } else { 3412 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3413 sc->sc_dev.dv_xname)); 3414 sc->sc_tbi_linkup = 0; 3415 } 3416 3417 wm_tbi_set_linkled(sc); 3418 3419 return (0); 3420 } 3421 3422 /* 3423 * wm_tbi_set_linkled: 3424 * 3425 * Update the link LED on 1000BASE-X devices. 3426 */ 3427 static void 3428 wm_tbi_set_linkled(struct wm_softc *sc) 3429 { 3430 3431 if (sc->sc_tbi_linkup) 3432 sc->sc_ctrl |= CTRL_SWDPIN(0); 3433 else 3434 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3435 3436 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3437 } 3438 3439 /* 3440 * wm_tbi_check_link: 3441 * 3442 * Check the link on 1000BASE-X devices. 3443 */ 3444 static void 3445 wm_tbi_check_link(struct wm_softc *sc) 3446 { 3447 uint32_t rxcw, ctrl, status; 3448 3449 if (sc->sc_tbi_anstate == 0) 3450 return; 3451 else if (sc->sc_tbi_anstate > 1) { 3452 DPRINTF(WM_DEBUG_LINK, 3453 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3454 sc->sc_tbi_anstate)); 3455 sc->sc_tbi_anstate--; 3456 return; 3457 } 3458 3459 sc->sc_tbi_anstate = 0; 3460 3461 rxcw = CSR_READ(sc, WMREG_RXCW); 3462 ctrl = CSR_READ(sc, WMREG_CTRL); 3463 status = CSR_READ(sc, WMREG_STATUS); 3464 3465 if ((status & STATUS_LU) == 0) { 3466 DPRINTF(WM_DEBUG_LINK, 3467 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3468 sc->sc_tbi_linkup = 0; 3469 } else { 3470 DPRINTF(WM_DEBUG_LINK, 3471 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3472 (status & STATUS_FD) ? "FDX" : "HDX")); 3473 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3474 sc->sc_fcrtl &= ~FCRTL_XONE; 3475 if (status & STATUS_FD) 3476 sc->sc_tctl |= 3477 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3478 else 3479 sc->sc_tctl |= 3480 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3481 if (ctrl & CTRL_TFCE) 3482 sc->sc_fcrtl |= FCRTL_XONE; 3483 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3484 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3485 WMREG_OLD_FCRTL : WMREG_FCRTL, 3486 sc->sc_fcrtl); 3487 sc->sc_tbi_linkup = 1; 3488 } 3489 3490 wm_tbi_set_linkled(sc); 3491 } 3492 3493 /* 3494 * wm_gmii_reset: 3495 * 3496 * Reset the PHY. 3497 */ 3498 static void 3499 wm_gmii_reset(struct wm_softc *sc) 3500 { 3501 uint32_t reg; 3502 3503 if (sc->sc_type >= WM_T_82544) { 3504 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3505 delay(20000); 3506 3507 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3508 delay(20000); 3509 } else { 3510 /* The PHY reset pin is active-low. */ 3511 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3512 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3513 CTRL_EXT_SWDPIN(4)); 3514 reg |= CTRL_EXT_SWDPIO(4); 3515 3516 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3517 delay(10); 3518 3519 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3520 delay(10); 3521 3522 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3523 delay(10); 3524 #if 0 3525 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3526 #endif 3527 } 3528 } 3529 3530 /* 3531 * wm_gmii_mediainit: 3532 * 3533 * Initialize media for use on 1000BASE-T devices. 3534 */ 3535 static void 3536 wm_gmii_mediainit(struct wm_softc *sc) 3537 { 3538 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3539 3540 /* We have MII. */ 3541 sc->sc_flags |= WM_F_HAS_MII; 3542 3543 sc->sc_tipg = TIPG_1000T_DFLT; 3544 3545 /* 3546 * Let the chip set speed/duplex on its own based on 3547 * signals from the PHY. 3548 */ 3549 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3550 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3551 3552 /* Initialize our media structures and probe the GMII. */ 3553 sc->sc_mii.mii_ifp = ifp; 3554 3555 if (sc->sc_type >= WM_T_82544) { 3556 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3557 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3558 } else { 3559 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3560 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3561 } 3562 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3563 3564 wm_gmii_reset(sc); 3565 3566 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3567 wm_gmii_mediastatus); 3568 3569 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3570 MII_OFFSET_ANY, MIIF_DOPAUSE); 3571 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3572 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3573 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3574 } else 3575 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3576 } 3577 3578 /* 3579 * wm_gmii_mediastatus: [ifmedia interface function] 3580 * 3581 * Get the current interface media status on a 1000BASE-T device. 3582 */ 3583 static void 3584 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3585 { 3586 struct wm_softc *sc = ifp->if_softc; 3587 3588 mii_pollstat(&sc->sc_mii); 3589 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3590 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3591 sc->sc_flowflags; 3592 } 3593 3594 /* 3595 * wm_gmii_mediachange: [ifmedia interface function] 3596 * 3597 * Set hardware to newly-selected media on a 1000BASE-T device. 3598 */ 3599 static int 3600 wm_gmii_mediachange(struct ifnet *ifp) 3601 { 3602 struct wm_softc *sc = ifp->if_softc; 3603 3604 if (ifp->if_flags & IFF_UP) 3605 mii_mediachg(&sc->sc_mii); 3606 return (0); 3607 } 3608 3609 #define MDI_IO CTRL_SWDPIN(2) 3610 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3611 #define MDI_CLK CTRL_SWDPIN(3) 3612 3613 static void 3614 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3615 { 3616 uint32_t i, v; 3617 3618 v = CSR_READ(sc, WMREG_CTRL); 3619 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3620 v |= MDI_DIR | CTRL_SWDPIO(3); 3621 3622 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3623 if (data & i) 3624 v |= MDI_IO; 3625 else 3626 v &= ~MDI_IO; 3627 CSR_WRITE(sc, WMREG_CTRL, v); 3628 delay(10); 3629 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3630 delay(10); 3631 CSR_WRITE(sc, WMREG_CTRL, v); 3632 delay(10); 3633 } 3634 } 3635 3636 static uint32_t 3637 i82543_mii_recvbits(struct wm_softc *sc) 3638 { 3639 uint32_t v, i, data = 0; 3640 3641 v = CSR_READ(sc, WMREG_CTRL); 3642 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3643 v |= CTRL_SWDPIO(3); 3644 3645 CSR_WRITE(sc, WMREG_CTRL, v); 3646 delay(10); 3647 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3648 delay(10); 3649 CSR_WRITE(sc, WMREG_CTRL, v); 3650 delay(10); 3651 3652 for (i = 0; i < 16; i++) { 3653 data <<= 1; 3654 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3655 delay(10); 3656 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3657 data |= 1; 3658 CSR_WRITE(sc, WMREG_CTRL, v); 3659 delay(10); 3660 } 3661 3662 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3663 delay(10); 3664 CSR_WRITE(sc, WMREG_CTRL, v); 3665 delay(10); 3666 3667 return (data); 3668 } 3669 3670 #undef MDI_IO 3671 #undef MDI_DIR 3672 #undef MDI_CLK 3673 3674 /* 3675 * wm_gmii_i82543_readreg: [mii interface function] 3676 * 3677 * Read a PHY register on the GMII (i82543 version). 3678 */ 3679 static int 3680 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3681 { 3682 struct wm_softc *sc = (void *) self; 3683 int rv; 3684 3685 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3686 i82543_mii_sendbits(sc, reg | (phy << 5) | 3687 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3688 rv = i82543_mii_recvbits(sc) & 0xffff; 3689 3690 DPRINTF(WM_DEBUG_GMII, 3691 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3692 sc->sc_dev.dv_xname, phy, reg, rv)); 3693 3694 return (rv); 3695 } 3696 3697 /* 3698 * wm_gmii_i82543_writereg: [mii interface function] 3699 * 3700 * Write a PHY register on the GMII (i82543 version). 3701 */ 3702 static void 3703 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3704 { 3705 struct wm_softc *sc = (void *) self; 3706 3707 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3708 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3709 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3710 (MII_COMMAND_START << 30), 32); 3711 } 3712 3713 /* 3714 * wm_gmii_i82544_readreg: [mii interface function] 3715 * 3716 * Read a PHY register on the GMII. 3717 */ 3718 static int 3719 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3720 { 3721 struct wm_softc *sc = (void *) self; 3722 uint32_t mdic = 0; 3723 int i, rv; 3724 3725 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3726 MDIC_REGADD(reg)); 3727 3728 for (i = 0; i < 100; i++) { 3729 mdic = CSR_READ(sc, WMREG_MDIC); 3730 if (mdic & MDIC_READY) 3731 break; 3732 delay(10); 3733 } 3734 3735 if ((mdic & MDIC_READY) == 0) { 3736 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3737 sc->sc_dev.dv_xname, phy, reg); 3738 rv = 0; 3739 } else if (mdic & MDIC_E) { 3740 #if 0 /* This is normal if no PHY is present. */ 3741 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3742 sc->sc_dev.dv_xname, phy, reg); 3743 #endif 3744 rv = 0; 3745 } else { 3746 rv = MDIC_DATA(mdic); 3747 if (rv == 0xffff) 3748 rv = 0; 3749 } 3750 3751 return (rv); 3752 } 3753 3754 /* 3755 * wm_gmii_i82544_writereg: [mii interface function] 3756 * 3757 * Write a PHY register on the GMII. 3758 */ 3759 static void 3760 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3761 { 3762 struct wm_softc *sc = (void *) self; 3763 uint32_t mdic = 0; 3764 int i; 3765 3766 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3767 MDIC_REGADD(reg) | MDIC_DATA(val)); 3768 3769 for (i = 0; i < 100; i++) { 3770 mdic = CSR_READ(sc, WMREG_MDIC); 3771 if (mdic & MDIC_READY) 3772 break; 3773 delay(10); 3774 } 3775 3776 if ((mdic & MDIC_READY) == 0) 3777 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3778 sc->sc_dev.dv_xname, phy, reg); 3779 else if (mdic & MDIC_E) 3780 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3781 sc->sc_dev.dv_xname, phy, reg); 3782 } 3783 3784 /* 3785 * wm_gmii_statchg: [mii interface function] 3786 * 3787 * Callback from MII layer when media changes. 3788 */ 3789 static void 3790 wm_gmii_statchg(struct device *self) 3791 { 3792 struct wm_softc *sc = (void *) self; 3793 struct mii_data *mii = &sc->sc_mii; 3794 3795 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3796 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3797 sc->sc_fcrtl &= ~FCRTL_XONE; 3798 3799 /* 3800 * Get flow control negotiation result. 3801 */ 3802 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3803 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3804 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3805 mii->mii_media_active &= ~IFM_ETH_FMASK; 3806 } 3807 3808 if (sc->sc_flowflags & IFM_FLOW) { 3809 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3810 sc->sc_ctrl |= CTRL_TFCE; 3811 sc->sc_fcrtl |= FCRTL_XONE; 3812 } 3813 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3814 sc->sc_ctrl |= CTRL_RFCE; 3815 } 3816 3817 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3818 DPRINTF(WM_DEBUG_LINK, 3819 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3820 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3821 } else { 3822 DPRINTF(WM_DEBUG_LINK, 3823 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3824 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3825 } 3826 3827 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3828 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3829 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3830 : WMREG_FCRTL, sc->sc_fcrtl); 3831 } 3832
Indexes created Tue Sep 23 20:09:58 GMT 2025