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if_wmreg.h revision 1.14.4.3
      1  1.14.4.3      riz /*	$NetBSD: if_wmreg.h,v 1.14.4.3 2007/10/14 05:07:51 riz Exp $	*/
      2       1.1  thorpej 
      3       1.1  thorpej /*
      4       1.1  thorpej  * Copyright (c) 2001 Wasabi Systems, Inc.
      5       1.1  thorpej  * All rights reserved.
      6       1.1  thorpej  *
      7       1.1  thorpej  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8       1.1  thorpej  *
      9       1.1  thorpej  * Redistribution and use in source and binary forms, with or without
     10       1.1  thorpej  * modification, are permitted provided that the following conditions
     11       1.1  thorpej  * are met:
     12       1.1  thorpej  * 1. Redistributions of source code must retain the above copyright
     13       1.1  thorpej  *    notice, this list of conditions and the following disclaimer.
     14       1.1  thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     15       1.1  thorpej  *    notice, this list of conditions and the following disclaimer in the
     16       1.1  thorpej  *    documentation and/or other materials provided with the distribution.
     17       1.1  thorpej  * 3. All advertising materials mentioning features or use of this software
     18       1.1  thorpej  *    must display the following acknowledgement:
     19       1.1  thorpej  *	This product includes software developed for the NetBSD Project by
     20       1.1  thorpej  *	Wasabi Systems, Inc.
     21       1.1  thorpej  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22       1.1  thorpej  *    or promote products derived from this software without specific prior
     23       1.1  thorpej  *    written permission.
     24       1.1  thorpej  *
     25       1.1  thorpej  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26       1.1  thorpej  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27       1.1  thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28       1.1  thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29       1.1  thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30       1.1  thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31       1.1  thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32       1.1  thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33       1.1  thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34       1.1  thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35       1.1  thorpej  * POSSIBILITY OF SUCH DAMAGE.
     36       1.1  thorpej  */
     37       1.1  thorpej 
     38       1.1  thorpej /*
     39       1.4     yamt  * Register description for the Intel i82542 (``Wiseman''),
     40       1.1  thorpej  * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit
     41       1.1  thorpej  * Ethernet chips.
     42       1.1  thorpej  */
     43       1.1  thorpej 
     44       1.1  thorpej /*
     45       1.1  thorpej  * The wiseman supports 64-bit PCI addressing.  This structure
     46       1.1  thorpej  * describes the address in descriptors.
     47       1.1  thorpej  */
     48       1.1  thorpej typedef struct wiseman_addr {
     49       1.1  thorpej 	uint32_t	wa_low;		/* low-order 32 bits */
     50       1.1  thorpej 	uint32_t	wa_high;	/* high-order 32 bits */
     51       1.1  thorpej } __attribute__((__packed__)) wiseman_addr_t;
     52       1.1  thorpej 
     53       1.1  thorpej /*
     54       1.1  thorpej  * The Wiseman receive descriptor.
     55       1.1  thorpej  *
     56       1.1  thorpej  * The receive descriptor ring must be aligned to a 4K boundary,
     57       1.1  thorpej  * and there must be an even multiple of 8 descriptors in the ring.
     58       1.1  thorpej  */
     59       1.1  thorpej typedef struct wiseman_rxdesc {
     60       1.1  thorpej 	wiseman_addr_t	wrx_addr;	/* buffer address */
     61       1.1  thorpej 
     62       1.1  thorpej 	uint16_t	wrx_len;	/* buffer length */
     63       1.1  thorpej 	uint16_t	wrx_cksum;	/* checksum (starting at PCSS) */
     64       1.1  thorpej 
     65       1.1  thorpej 	uint8_t		wrx_status;	/* Rx status */
     66       1.1  thorpej 	uint8_t		wrx_errors;	/* Rx errors */
     67       1.1  thorpej 	uint16_t	wrx_special;	/* special field (VLAN, etc.) */
     68       1.1  thorpej } __attribute__((__packed__)) wiseman_rxdesc_t;
     69       1.1  thorpej 
     70       1.1  thorpej /* wrx_status bits */
     71       1.1  thorpej #define	WRX_ST_DD	(1U << 0)	/* descriptor done */
     72       1.1  thorpej #define	WRX_ST_EOP	(1U << 1)	/* end of packet */
     73  1.14.4.1     tron #define	WRX_ST_IXSM	(1U << 2)	/* ignore checksum indication */
     74       1.1  thorpej #define	WRX_ST_VP	(1U << 3)	/* VLAN packet */
     75       1.1  thorpej #define	WRX_ST_BPDU	(1U << 4)	/* ??? */
     76       1.1  thorpej #define	WRX_ST_TCPCS	(1U << 5)	/* TCP checksum performed */
     77       1.1  thorpej #define	WRX_ST_IPCS	(1U << 6)	/* IP checksum performed */
     78       1.1  thorpej #define	WRX_ST_PIF	(1U << 7)	/* passed in-exact filter */
     79       1.1  thorpej 
     80       1.1  thorpej /* wrx_error bits */
     81       1.1  thorpej #define	WRX_ER_CE	(1U << 0)	/* CRC error */
     82       1.1  thorpej #define	WRX_ER_SE	(1U << 1)	/* symbol error */
     83       1.1  thorpej #define	WRX_ER_SEQ	(1U << 2)	/* sequence error */
     84       1.1  thorpej #define	WRX_ER_ICE	(1U << 3)	/* ??? */
     85       1.1  thorpej #define	WRX_ER_CXE	(1U << 4)	/* carrier extension error */
     86       1.1  thorpej #define	WRX_ER_TCPE	(1U << 5)	/* TCP checksum error */
     87       1.1  thorpej #define	WRX_ER_IPE	(1U << 6)	/* IP checksum error */
     88       1.1  thorpej #define	WRX_ER_RXE	(1U << 7)	/* Rx data error */
     89       1.1  thorpej 
     90       1.1  thorpej /* wrx_special field for VLAN packets */
     91       1.1  thorpej #define	WRX_VLAN_ID(x)	((x) & 0x0fff)	/* VLAN identifier */
     92       1.1  thorpej #define	WRX_VLAN_CFI	(1U << 12)	/* Canonical Form Indicator */
     93       1.1  thorpej #define	WRX_VLAN_PRI(x)	(((x) >> 13) & 7)/* VLAN priority field */
     94       1.1  thorpej 
     95       1.1  thorpej /*
     96       1.1  thorpej  * The Wiseman transmit descriptor.
     97       1.1  thorpej  *
     98       1.1  thorpej  * The transmit descriptor ring must be aligned to a 4K boundary,
     99       1.1  thorpej  * and there must be an even multiple of 8 descriptors in the ring.
    100       1.1  thorpej  */
    101       1.9  tsutsui typedef struct wiseman_tx_fields {
    102       1.9  tsutsui 	uint8_t wtxu_status;		/* Tx status */
    103       1.9  tsutsui 	uint8_t wtxu_options;		/* options */
    104       1.9  tsutsui 	uint16_t wtxu_vlan;		/* VLAN info */
    105       1.1  thorpej } __attribute__((__packed__)) wiseman_txfields_t;
    106       1.1  thorpej typedef struct wiseman_txdesc {
    107       1.1  thorpej 	wiseman_addr_t	wtx_addr;	/* buffer address */
    108       1.1  thorpej 	uint32_t	wtx_cmdlen;	/* command and length */
    109       1.1  thorpej 	wiseman_txfields_t wtx_fields;	/* fields; see below */
    110       1.1  thorpej } __attribute__((__packed__)) wiseman_txdesc_t;
    111       1.1  thorpej 
    112       1.9  tsutsui /* Commands for wtx_cmdlen */
    113       1.1  thorpej #define	WTX_CMD_EOP	(1U << 24)	/* end of packet */
    114       1.1  thorpej #define	WTX_CMD_IFCS	(1U << 25)	/* insert FCS */
    115       1.1  thorpej #define	WTX_CMD_RS	(1U << 27)	/* report status */
    116       1.1  thorpej #define	WTX_CMD_RPS	(1U << 28)	/* report packet sent */
    117       1.1  thorpej #define	WTX_CMD_DEXT	(1U << 29)	/* descriptor extension */
    118       1.1  thorpej #define	WTX_CMD_VLE	(1U << 30)	/* VLAN enable */
    119       1.1  thorpej #define	WTX_CMD_IDE	(1U << 31)	/* interrupt delay enable */
    120       1.1  thorpej 
    121       1.1  thorpej /* Descriptor types (if DEXT is set) */
    122       1.9  tsutsui #define	WTX_DTYP_C	(0U << 20)	/* context */
    123      1.10  thorpej #define	WTX_DTYP_D	(1U << 20)	/* data */
    124       1.1  thorpej 
    125       1.1  thorpej /* wtx_fields status bits */
    126       1.1  thorpej #define	WTX_ST_DD	(1U << 0)	/* descriptor done */
    127       1.1  thorpej #define	WTX_ST_EC	(1U << 1)	/* excessive collisions */
    128       1.1  thorpej #define	WTX_ST_LC	(1U << 2)	/* late collision */
    129       1.1  thorpej #define	WTX_ST_TU	(1U << 3)	/* transmit underrun */
    130       1.1  thorpej 
    131       1.9  tsutsui /* wtx_fields option bits for IP/TCP/UDP checksum offload */
    132       1.9  tsutsui #define	WTX_IXSM	(1U << 0)	/* IP checksum offload */
    133       1.9  tsutsui #define	WTX_TXSM	(1U << 1)	/* TCP/UDP checksum offload */
    134       1.1  thorpej 
    135      1.13  thorpej /* Maximum payload per Tx descriptor */
    136      1.13  thorpej #define	WTX_MAX_LEN	4096
    137      1.13  thorpej 
    138       1.1  thorpej /*
    139       1.1  thorpej  * The Livengood TCP/IP context descriptor.
    140       1.1  thorpej  */
    141       1.1  thorpej struct livengood_tcpip_ctxdesc {
    142       1.1  thorpej 	uint32_t	tcpip_ipcs;	/* IP checksum context */
    143       1.1  thorpej 	uint32_t	tcpip_tucs;	/* TCP/UDP checksum context */
    144       1.1  thorpej 	uint32_t	tcpip_cmdlen;
    145       1.1  thorpej 	uint32_t	tcpip_seg;	/* TCP segmentation context */
    146       1.1  thorpej };
    147       1.1  thorpej 
    148       1.1  thorpej /* commands for context descriptors */
    149       1.2  thorpej #define	WTX_TCPIP_CMD_TCP	(1U << 24)	/* 1 = TCP, 0 = UDP */
    150       1.2  thorpej #define	WTX_TCPIP_CMD_IP	(1U << 25)	/* 1 = IPv4, 0 = IPv6 */
    151       1.1  thorpej #define	WTX_TCPIP_CMD_TSE	(1U << 26)	/* segmentation context valid */
    152       1.1  thorpej 
    153       1.1  thorpej #define	WTX_TCPIP_IPCSS(x)	((x) << 0)	/* checksum start */
    154       1.1  thorpej #define	WTX_TCPIP_IPCSO(x)	((x) << 8)	/* checksum value offset */
    155       1.1  thorpej #define	WTX_TCPIP_IPCSE(x)	((x) << 16)	/* checksum end */
    156       1.1  thorpej 
    157       1.1  thorpej #define	WTX_TCPIP_TUCSS(x)	((x) << 0)	/* checksum start */
    158       1.1  thorpej #define	WTX_TCPIP_TUCSO(x)	((x) << 8)	/* checksum value offset */
    159       1.1  thorpej #define	WTX_TCPIP_TUCSE(x)	((x) << 16)	/* checksum end */
    160       1.1  thorpej 
    161       1.1  thorpej #define	WTX_TCPIP_SEG_STATUS(x)	((x) << 0)
    162       1.1  thorpej #define	WTX_TCPIP_SEG_HDRLEN(x)	((x) << 8)
    163       1.1  thorpej #define	WTX_TCPIP_SEG_MSS(x)	((x) << 16)
    164       1.1  thorpej 
    165       1.1  thorpej /*
    166       1.1  thorpej  * PCI config registers used by the Wiseman.
    167       1.1  thorpej  */
    168       1.1  thorpej #define	WM_PCI_MMBA	PCI_MAPREG_START
    169  1.14.4.3      riz /* registers for FLASH access on ICH8 */
    170  1.14.4.3      riz #define WM_ICH8_FLASH	0x0014
    171       1.1  thorpej 
    172       1.1  thorpej /*
    173       1.1  thorpej  * Wiseman Control/Status Registers.
    174       1.1  thorpej  */
    175       1.1  thorpej #define	WMREG_CTRL	0x0000	/* Device Control Register */
    176       1.1  thorpej #define	CTRL_FD		(1U << 0)	/* full duplex */
    177       1.1  thorpej #define	CTRL_BEM	(1U << 1)	/* big-endian mode */
    178       1.1  thorpej #define	CTRL_PRIOR	(1U << 2)	/* 0 = receive, 1 = fair */
    179       1.1  thorpej #define	CTRL_LRST	(1U << 3)	/* link reset */
    180       1.1  thorpej #define	CTRL_ASDE	(1U << 5)	/* auto speed detect enable */
    181       1.1  thorpej #define	CTRL_SLU	(1U << 6)	/* set link up */
    182       1.1  thorpej #define	CTRL_ILOS	(1U << 7)	/* invert loss of signal */
    183       1.1  thorpej #define	CTRL_SPEED(x)	((x) << 8)	/* speed (Livengood) */
    184       1.1  thorpej #define	CTRL_SPEED_10	CTRL_SPEED(0)
    185       1.1  thorpej #define	CTRL_SPEED_100	CTRL_SPEED(1)
    186       1.1  thorpej #define	CTRL_SPEED_1000	CTRL_SPEED(2)
    187       1.1  thorpej #define	CTRL_SPEED_MASK	CTRL_SPEED(3)
    188       1.1  thorpej #define	CTRL_FRCSPD	(1U << 11)	/* force speed (Livengood) */
    189       1.1  thorpej #define	CTRL_FRCFDX	(1U << 12)	/* force full-duplex (Livengood) */
    190  1.14.4.2   bouyer #define CTRL_D_UD_EN	(1U << 13)	/* Dock/Undock enable */
    191  1.14.4.2   bouyer #define CTRL_D_UD_POL	(1U << 14)	/* Defined polarity of Dock/Undock indication in SDP[0] */
    192  1.14.4.2   bouyer #define CTRL_F_PHY_R 	(1U << 15)	/* Reset both PHY ports, through PHYRST_N pin */
    193  1.14.4.2   bouyer #define CTRL_EXT_LINK_EN (1U << 16)	/* enable link status from external LINK_0 and LINK_1 pins */
    194       1.1  thorpej #define	CTRL_SWDPINS_SHIFT	18
    195       1.1  thorpej #define	CTRL_SWDPINS_MASK	0x0f
    196       1.1  thorpej #define	CTRL_SWDPIN(x)		(1U << (CTRL_SWDPINS_SHIFT + (x)))
    197       1.1  thorpej #define	CTRL_SWDPIO_SHIFT	22
    198       1.1  thorpej #define	CTRL_SWDPIO_MASK	0x0f
    199       1.1  thorpej #define	CTRL_SWDPIO(x)		(1U << (CTRL_SWDPIO_SHIFT + (x)))
    200       1.1  thorpej #define	CTRL_RST	(1U << 26)	/* device reset */
    201       1.1  thorpej #define	CTRL_RFCE	(1U << 27)	/* Rx flow control enable */
    202       1.1  thorpej #define	CTRL_TFCE	(1U << 28)	/* Tx flow control enable */
    203       1.1  thorpej #define	CTRL_VME	(1U << 30)	/* VLAN Mode Enable */
    204       1.1  thorpej #define	CTRL_PHY_RESET	(1U << 31)	/* PHY reset (Cordova) */
    205       1.1  thorpej 
    206       1.7  thorpej #define	WMREG_CTRL_SHADOW 0x0004	/* Device Control Register (shadow) */
    207       1.6  thorpej 
    208       1.1  thorpej #define	WMREG_STATUS	0x0008	/* Device Status Register */
    209       1.1  thorpej #define	STATUS_FD	(1U << 0)	/* full duplex */
    210       1.1  thorpej #define	STATUS_LU	(1U << 1)	/* link up */
    211       1.1  thorpej #define	STATUS_TCKOK	(1U << 2)	/* Tx clock running */
    212       1.1  thorpej #define	STATUS_RBCOK	(1U << 3)	/* Rx clock running */
    213       1.3  thorpej #define	STATUS_FUNCID_SHIFT 2		/* 82546 function ID */
    214       1.3  thorpej #define	STATUS_FUNCID_MASK  3		/* ... */
    215       1.1  thorpej #define	STATUS_TXOFF	(1U << 4)	/* Tx paused */
    216       1.1  thorpej #define	STATUS_TBIMODE	(1U << 5)	/* fiber mode (Livengood) */
    217       1.1  thorpej #define	STATUS_SPEED(x)	((x) << 6)	/* speed indication */
    218       1.1  thorpej #define	STATUS_SPEED_10	  STATUS_SPEED(0)
    219       1.1  thorpej #define	STATUS_SPEED_100  STATUS_SPEED(1)
    220       1.1  thorpej #define	STATUS_SPEED_1000 STATUS_SPEED(2)
    221       1.1  thorpej #define	STATUS_ASDV(x)	((x) << 8)	/* auto speed det. val. (Livengood) */
    222       1.1  thorpej #define	STATUS_MTXCKOK	(1U << 10)	/* MTXD clock running */
    223       1.1  thorpej #define	STATUS_PCI66	(1U << 11)	/* 66MHz bus (Livengood) */
    224       1.1  thorpej #define	STATUS_BUS64	(1U << 12)	/* 64-bit bus (Livengood) */
    225       1.1  thorpej #define	STATUS_PCIX_MODE (1U << 13)	/* PCIX mode (Cordova) */
    226       1.1  thorpej #define	STATUS_PCIXSPD(x) ((x) << 14)	/* PCIX speed indication (Cordova) */
    227       1.1  thorpej #define	STATUS_PCIXSPD_50_66   STATUS_PCIXSPD(0)
    228       1.1  thorpej #define	STATUS_PCIXSPD_66_100  STATUS_PCIXSPD(1)
    229       1.1  thorpej #define	STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2)
    230       1.8  thorpej #define	STATUS_PCIXSPD_MASK    STATUS_PCIXSPD(3)
    231       1.1  thorpej 
    232       1.1  thorpej #define	WMREG_EECD	0x0010	/* EEPROM Control Register */
    233       1.1  thorpej #define	EECD_SK		(1U << 0)	/* clock */
    234       1.1  thorpej #define	EECD_CS		(1U << 1)	/* chip select */
    235       1.1  thorpej #define	EECD_DI		(1U << 2)	/* data in */
    236       1.1  thorpej #define	EECD_DO		(1U << 3)	/* data out */
    237       1.1  thorpej #define	EECD_FWE(x)	((x) << 4)	/* flash write enable control */
    238       1.1  thorpej #define	EECD_FWE_DISABLED EECD_FWE(1)
    239       1.1  thorpej #define	EECD_FWE_ENABLED  EECD_FWE(2)
    240       1.3  thorpej #define	EECD_EE_REQ	(1U << 6)	/* (shared) EEPROM request */
    241       1.3  thorpej #define	EECD_EE_GNT	(1U << 7)	/* (shared) EEPROM grant */
    242       1.3  thorpej #define	EECD_EE_PRES	(1U << 8)	/* EEPROM present */
    243       1.3  thorpej #define	EECD_EE_SIZE	(1U << 9)	/* EEPROM size
    244       1.3  thorpej 					   (0 = 64 word, 1 = 256 word) */
    245  1.14.4.2   bouyer #define	EECD_EE_AUTORD	(1U << 9)	/* auto read done */
    246       1.6  thorpej #define	EECD_EE_ABITS	(1U << 10)	/* EEPROM address bits
    247       1.6  thorpej 					   (based on type) */
    248       1.6  thorpej #define	EECD_EE_TYPE	(1U << 13)	/* EEPROM type
    249       1.6  thorpej 					   (0 = Microwire, 1 = SPI) */
    250  1.14.4.3      riz #define EECD_SEC1VAL	(1U << 22)	/* Sector One Valid */
    251       1.1  thorpej 
    252       1.1  thorpej #define	UWIRE_OPC_ERASE	0x04		/* MicroWire "erase" opcode */
    253       1.1  thorpej #define	UWIRE_OPC_WRITE	0x05		/* MicroWire "write" opcode */
    254       1.1  thorpej #define	UWIRE_OPC_READ	0x06		/* MicroWire "read" opcode */
    255       1.6  thorpej 
    256       1.6  thorpej #define	SPI_OPC_WRITE	0x02		/* SPI "write" opcode */
    257       1.6  thorpej #define	SPI_OPC_READ	0x03		/* SPI "read" opcode */
    258       1.6  thorpej #define	SPI_OPC_A8	0x08		/* opcode bit 3 == address bit 8 */
    259       1.6  thorpej #define	SPI_OPC_WREN	0x06		/* SPI "set write enable" opcode */
    260       1.6  thorpej #define	SPI_OPC_WRDI	0x04		/* SPI "clear write enable" opcode */
    261       1.6  thorpej #define	SPI_OPC_RDSR	0x05		/* SPI "read status" opcode */
    262       1.6  thorpej #define	SPI_OPC_WRSR	0x01		/* SPI "write status" opcode */
    263       1.6  thorpej #define	SPI_MAX_RETRIES	5000		/* max wait of 5ms for RDY signal */
    264       1.6  thorpej 
    265       1.6  thorpej #define	SPI_SR_RDY	0x01
    266       1.6  thorpej #define	SPI_SR_WEN	0x02
    267       1.6  thorpej #define	SPI_SR_BP0	0x04
    268       1.6  thorpej #define	SPI_SR_BP1	0x08
    269       1.6  thorpej #define	SPI_SR_WPEN	0x80
    270       1.1  thorpej 
    271       1.1  thorpej #define	EEPROM_OFF_MACADDR	0x00	/* MAC address offset */
    272       1.1  thorpej #define	EEPROM_OFF_CFG1		0x0a	/* config word 1 */
    273       1.1  thorpej #define	EEPROM_OFF_CFG2		0x0f	/* config word 2 */
    274       1.1  thorpej #define	EEPROM_OFF_SWDPIN	0x20	/* SWD Pins (Cordova) */
    275       1.1  thorpej 
    276       1.1  thorpej #define	EEPROM_CFG1_LVDID	(1U << 0)
    277       1.1  thorpej #define	EEPROM_CFG1_LSSID	(1U << 1)
    278       1.1  thorpej #define	EEPROM_CFG1_PME_CLOCK	(1U << 2)
    279       1.1  thorpej #define	EEPROM_CFG1_PM		(1U << 3)
    280       1.1  thorpej #define	EEPROM_CFG1_ILOS	(1U << 4)
    281       1.1  thorpej #define	EEPROM_CFG1_SWDPIO_SHIFT 5
    282       1.1  thorpej #define	EEPROM_CFG1_SWDPIO_MASK	(0xf << EEPROM_CFG1_SWDPIO_SHIFT)
    283       1.1  thorpej #define	EEPROM_CFG1_IPS1	(1U << 8)
    284       1.1  thorpej #define	EEPROM_CFG1_LRST	(1U << 9)
    285       1.1  thorpej #define	EEPROM_CFG1_FD		(1U << 10)
    286       1.1  thorpej #define	EEPROM_CFG1_FRCSPD	(1U << 11)
    287       1.1  thorpej #define	EEPROM_CFG1_IPS0	(1U << 12)
    288       1.1  thorpej #define	EEPROM_CFG1_64_32_BAR	(1U << 13)
    289       1.1  thorpej 
    290       1.1  thorpej #define	EEPROM_CFG2_CSR_RD_SPLIT (1U << 1)
    291       1.1  thorpej #define	EEPROM_CFG2_APM_EN	(1U << 2)
    292       1.1  thorpej #define	EEPROM_CFG2_64_BIT	(1U << 3)
    293       1.1  thorpej #define	EEPROM_CFG2_MAX_READ	(1U << 4)
    294       1.1  thorpej #define	EEPROM_CFG2_DMCR_MAP	(1U << 5)
    295       1.1  thorpej #define	EEPROM_CFG2_133_CAP	(1U << 6)
    296       1.1  thorpej #define	EEPROM_CFG2_MSI_DIS	(1U << 7)
    297       1.1  thorpej #define	EEPROM_CFG2_FLASH_DIS	(1U << 8)
    298       1.1  thorpej #define	EEPROM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9)
    299       1.1  thorpej #define	EEPROM_CFG2_ANE		(1U << 11)
    300       1.1  thorpej #define	EEPROM_CFG2_PAUSE(x)	(((x) & 3) >> 12)
    301       1.1  thorpej #define	EEPROM_CFG2_ASDE	(1U << 14)
    302       1.1  thorpej #define	EEPROM_CFG2_APM_PME	(1U << 15)
    303       1.1  thorpej #define	EEPROM_CFG2_SWDPIO_SHIFT 4
    304       1.1  thorpej #define	EEPROM_CFG2_SWDPIO_MASK	(0xf << EEPROM_CFG2_SWDPIO_SHIFT)
    305       1.1  thorpej 
    306       1.1  thorpej #define	EEPROM_SWDPIN_MASK	0xdf
    307       1.1  thorpej #define	EEPROM_SWDPIN_SWDPIN_SHIFT 0
    308       1.1  thorpej #define	EEPROM_SWDPIN_SWDPIO_SHIFT 8
    309       1.1  thorpej 
    310  1.14.4.2   bouyer #define	WMREG_EERD	0x0014	/* EEPROM read */
    311  1.14.4.2   bouyer #define	EERD_DONE	0x02    /* done bit */
    312  1.14.4.2   bouyer #define	EERD_START	0x01	/* First bit for telling part to start operation */
    313  1.14.4.2   bouyer #define	EERD_ADDR_SHIFT	2	/* Shift to the address bits */
    314  1.14.4.2   bouyer #define	EERD_DATA_SHIFT	16	/* Offset to data in EEPROM read/write registers */
    315  1.14.4.2   bouyer 
    316       1.1  thorpej #define	WMREG_CTRL_EXT	0x0018	/* Extended Device Control Register */
    317       1.1  thorpej #define	CTRL_EXT_GPI_EN(x)	(1U << (x)) /* gpin interrupt enable */
    318       1.1  thorpej #define	CTRL_EXT_SWDPINS_SHIFT	4
    319       1.1  thorpej #define	CTRL_EXT_SWDPINS_MASK	0x0d
    320       1.5     matt #define	CTRL_EXT_SWDPIN(x)	(1U << (CTRL_EXT_SWDPINS_SHIFT + (x) - 4))
    321       1.1  thorpej #define	CTRL_EXT_SWDPIO_SHIFT	8
    322       1.1  thorpej #define	CTRL_EXT_SWDPIO_MASK	0x0d
    323       1.5     matt #define	CTRL_EXT_SWDPIO(x)	(1U << (CTRL_EXT_SWDPIO_SHIFT + (x) - 4))
    324       1.1  thorpej #define	CTRL_EXT_ASDCHK		(1U << 12) /* ASD check */
    325       1.1  thorpej #define	CTRL_EXT_EE_RST		(1U << 13) /* EEPROM reset */
    326       1.1  thorpej #define	CTRL_EXT_IPS		(1U << 14) /* invert power state bit 0 */
    327       1.1  thorpej #define	CTRL_EXT_SPD_BYPS	(1U << 15) /* speed select bypass */
    328       1.1  thorpej #define	CTRL_EXT_IPS1		(1U << 16) /* invert power state bit 1 */
    329       1.1  thorpej #define	CTRL_EXT_RO_DIS		(1U << 17) /* relaxed ordering disabled */
    330  1.14.4.2   bouyer #define	CTRL_EXT_LINK_MODE_MASK	0x00C00000
    331  1.14.4.2   bouyer #define	CTRL_EXT_LINK_MODE_GMII	0x00000000
    332  1.14.4.2   bouyer #define	CTRL_EXT_LINK_MODE_TBI	0x00C00000
    333  1.14.4.2   bouyer #define	CTRL_EXT_LINK_MODE_KMRN	0x00000000
    334  1.14.4.2   bouyer #define	CTRL_EXT_LINK_MODE_SERDES 0x00C00000
    335  1.14.4.2   bouyer 
    336       1.1  thorpej 
    337       1.1  thorpej #define	WMREG_MDIC	0x0020	/* MDI Control Register */
    338       1.1  thorpej #define	MDIC_DATA(x)	((x) & 0xffff)
    339       1.1  thorpej #define	MDIC_REGADD(x)	((x) << 16)
    340       1.1  thorpej #define	MDIC_PHYADD(x)	((x) << 21)
    341       1.1  thorpej #define	MDIC_OP_WRITE	(1U << 26)
    342       1.1  thorpej #define	MDIC_OP_READ	(2U << 26)
    343       1.1  thorpej #define	MDIC_READY	(1U << 28)
    344       1.1  thorpej #define	MDIC_I		(1U << 29)	/* interrupt on MDI complete */
    345       1.1  thorpej #define	MDIC_E		(1U << 30)	/* MDI error */
    346       1.1  thorpej 
    347       1.1  thorpej #define	WMREG_FCAL	0x0028	/* Flow Control Address Low */
    348       1.1  thorpej #define	FCAL_CONST	0x00c28001	/* Flow Control MAC addr low */
    349       1.1  thorpej 
    350       1.1  thorpej #define	WMREG_FCAH	0x002c	/* Flow Control Address High */
    351       1.1  thorpej #define	FCAH_CONST	0x00000100	/* Flow Control MAC addr high */
    352       1.1  thorpej 
    353       1.1  thorpej #define	WMREG_FCT	0x0030	/* Flow Control Type */
    354       1.1  thorpej 
    355       1.1  thorpej #define	WMREG_VET	0x0038	/* VLAN Ethertype */
    356       1.1  thorpej 
    357       1.1  thorpej #define	WMREG_RAL_BASE	0x0040	/* Receive Address List */
    358       1.1  thorpej #define	WMREG_CORDOVA_RAL_BASE 0x5400
    359       1.1  thorpej #define	WMREG_RAL_LO(b, x) ((b) + ((x) << 3))
    360       1.1  thorpej #define	WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4)
    361       1.1  thorpej 	/*
    362       1.1  thorpej 	 * Receive Address List: The LO part is the low-order 32-bits
    363       1.1  thorpej 	 * of the MAC address.  The HI part is the high-order 16-bits
    364       1.1  thorpej 	 * along with a few control bits.
    365       1.1  thorpej 	 */
    366       1.1  thorpej #define	RAL_AS(x)	((x) << 16)	/* address select */
    367       1.1  thorpej #define	RAL_AS_DEST	RAL_AS(0)	/* (cordova?) */
    368       1.1  thorpej #define	RAL_AS_SOURCE	RAL_AS(1)	/* (cordova?) */
    369       1.1  thorpej #define	RAL_RDR1	(1U << 30)	/* put packet in alt. rx ring */
    370       1.1  thorpej #define	RAL_AV		(1U << 31)	/* entry is valid */
    371       1.1  thorpej 
    372       1.1  thorpej #define	WM_RAL_TABSIZE	16
    373  1.14.4.3      riz #define	WM_ICH8_RAL_TABSIZE 7
    374       1.1  thorpej 
    375       1.1  thorpej #define	WMREG_ICR	0x00c0	/* Interrupt Cause Register */
    376       1.1  thorpej #define	ICR_TXDW	(1U << 0)	/* Tx desc written back */
    377       1.1  thorpej #define	ICR_TXQE	(1U << 1)	/* Tx queue empty */
    378       1.1  thorpej #define	ICR_LSC		(1U << 2)	/* link status change */
    379       1.1  thorpej #define	ICR_RXSEQ	(1U << 3)	/* receive sequence error */
    380       1.1  thorpej #define	ICR_RXDMT0	(1U << 4)	/* Rx ring 0 nearly empty */
    381       1.1  thorpej #define	ICR_RXO		(1U << 6)	/* Rx overrun */
    382       1.1  thorpej #define	ICR_RXT0	(1U << 7)	/* Rx ring 0 timer */
    383       1.1  thorpej #define	ICR_MDAC	(1U << 9)	/* MDIO access complete */
    384       1.1  thorpej #define	ICR_RXCFG	(1U << 10)	/* Receiving /C/ */
    385       1.1  thorpej #define	ICR_GPI(x)	(1U << (x))	/* general purpose interrupts */
    386  1.14.4.2   bouyer #define	ICR_INT		(1U << 31)	/* device generated an interrupt */
    387       1.1  thorpej 
    388      1.14   briggs #define WMREG_ITR	0x00c4	/* Interrupt Throttling Register */
    389      1.14   briggs #define ITR_IVAL_MASK	0xffff		/* Interval mask */
    390      1.14   briggs #define ITR_IVAL_SHIFT	0		/* Interval shift */
    391      1.14   briggs 
    392       1.1  thorpej #define	WMREG_ICS	0x00c8	/* Interrupt Cause Set Register */
    393       1.1  thorpej 	/* See ICR bits. */
    394       1.1  thorpej 
    395       1.1  thorpej #define	WMREG_IMS	0x00d0	/* Interrupt Mask Set Register */
    396       1.1  thorpej 	/* See ICR bits. */
    397       1.1  thorpej 
    398       1.1  thorpej #define	WMREG_IMC	0x00d8	/* Interrupt Mask Clear Register */
    399       1.1  thorpej 	/* See ICR bits. */
    400       1.1  thorpej 
    401       1.1  thorpej #define	WMREG_RCTL	0x0100	/* Receive Control */
    402       1.1  thorpej #define	RCTL_EN		(1U << 1)	/* receiver enable */
    403       1.1  thorpej #define	RCTL_SBP	(1U << 2)	/* store bad packets */
    404       1.1  thorpej #define	RCTL_UPE	(1U << 3)	/* unicast promisc. enable */
    405       1.1  thorpej #define	RCTL_MPE	(1U << 4)	/* multicast promisc. enable */
    406       1.1  thorpej #define	RCTL_LPE	(1U << 5)	/* large packet enable */
    407       1.1  thorpej #define	RCTL_LBM(x)	((x) << 6)	/* loopback mode */
    408       1.1  thorpej #define	RCTL_LBM_NONE	RCTL_LBM(0)
    409       1.1  thorpej #define	RCTL_LBM_PHY	RCTL_LBM(3)
    410       1.1  thorpej #define	RCTL_RDMTS(x)	((x) << 8)	/* receive desc. min thresh size */
    411       1.1  thorpej #define	RCTL_RDMTS_1_2	RCTL_RDMTS(0)
    412       1.1  thorpej #define	RCTL_RDMTS_1_4	RCTL_RDMTS(1)
    413       1.1  thorpej #define	RCTL_RDMTS_1_8	RCTL_RDMTS(2)
    414       1.1  thorpej #define	RCTL_RDMTS_MASK	RCTL_RDMTS(3)
    415       1.1  thorpej #define	RCTL_MO(x)	((x) << 12)	/* multicast offset */
    416       1.1  thorpej #define	RCTL_BAM	(1U << 15)	/* broadcast accept mode */
    417       1.1  thorpej #define	RCTL_2k		(0 << 16)	/* 2k Rx buffers */
    418       1.1  thorpej #define	RCTL_1k		(1 << 16)	/* 1k Rx buffers */
    419       1.1  thorpej #define	RCTL_512	(2 << 16)	/* 512 byte Rx buffers */
    420       1.1  thorpej #define	RCTL_256	(3 << 16)	/* 256 byte Rx buffers */
    421       1.1  thorpej #define	RCTL_BSEX_16k	(1 << 16)	/* 16k Rx buffers (BSEX) */
    422       1.1  thorpej #define	RCTL_BSEX_8k	(2 << 16)	/* 8k Rx buffers (BSEX) */
    423       1.1  thorpej #define	RCTL_BSEX_4k	(3 << 16)	/* 4k Rx buffers (BSEX) */
    424       1.1  thorpej #define	RCTL_DPF	(1U << 22)	/* discard pause frames */
    425       1.1  thorpej #define	RCTL_PMCF	(1U << 23)	/* pass MAC control frames */
    426       1.1  thorpej #define	RCTL_BSEX	(1U << 25)	/* buffer size extension (Livengood) */
    427       1.1  thorpej #define	RCTL_SECRC	(1U << 26)	/* strip Ethernet CRC */
    428       1.1  thorpej 
    429       1.1  thorpej #define	WMREG_OLD_RDTR0	0x0108	/* Receive Delay Timer (ring 0) */
    430       1.1  thorpej #define	WMREG_RDTR	0x2820
    431       1.1  thorpej #define	RDTR_FPD	(1U << 31)	/* flush partial descriptor */
    432       1.1  thorpej 
    433      1.14   briggs #define	WMREG_RADV	0x282c	/* Receive Interrupt Absolute Delay Timer */
    434      1.14   briggs 
    435       1.1  thorpej #define	WMREG_OLD_RDBAL0 0x0110	/* Receive Descriptor Base Low (ring 0) */
    436       1.1  thorpej #define	WMREG_RDBAL	0x2800
    437       1.1  thorpej 
    438       1.1  thorpej #define	WMREG_OLD_RDBAH0 0x0114	/* Receive Descriptor Base High (ring 0) */
    439       1.1  thorpej #define	WMREG_RDBAH	0x2804
    440       1.1  thorpej 
    441       1.1  thorpej #define	WMREG_OLD_RDLEN0 0x0118	/* Receive Descriptor Length (ring 0) */
    442       1.1  thorpej #define	WMREG_RDLEN	0x2808
    443       1.1  thorpej 
    444       1.1  thorpej #define	WMREG_OLD_RDH0	0x0120	/* Receive Descriptor Head (ring 0) */
    445       1.1  thorpej #define	WMREG_RDH	0x2810
    446       1.1  thorpej 
    447       1.1  thorpej #define	WMREG_OLD_RDT0	0x0128	/* Receive Descriptor Tail (ring 0) */
    448       1.1  thorpej #define	WMREG_RDT	0x2818
    449       1.1  thorpej 
    450       1.1  thorpej #define	WMREG_RXDCTL	0x2828	/* Receive Descriptor Control */
    451       1.1  thorpej #define	RXDCTL_PTHRESH(x) ((x) << 0)	/* prefetch threshold */
    452       1.1  thorpej #define	RXDCTL_HTHRESH(x) ((x) << 8)	/* host threshold */
    453       1.1  thorpej #define	RXDCTL_WTHRESH(x) ((x) << 16)	/* write back threshold */
    454       1.1  thorpej #define	RXDCTL_GRAN	(1U << 24)	/* 0 = cacheline, 1 = descriptor */
    455       1.1  thorpej 
    456       1.1  thorpej #define	WMREG_OLD_RDTR1	0x0130	/* Receive Delay Timer (ring 1) */
    457       1.1  thorpej 
    458       1.1  thorpej #define	WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */
    459       1.1  thorpej 
    460       1.1  thorpej #define	WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */
    461       1.1  thorpej 
    462       1.1  thorpej #define	WMREG_OLD_RDLEN1 0x0140	/* Receive Drscriptor Length (ring 1) */
    463       1.1  thorpej 
    464       1.1  thorpej #define	WMREG_OLD_RDH1	0x0148
    465       1.1  thorpej 
    466       1.1  thorpej #define	WMREG_OLD_RDT1	0x0150
    467       1.1  thorpej 
    468       1.1  thorpej #define	WMREG_OLD_FCRTH 0x0160	/* Flow Control Rx Threshold Hi (OLD) */
    469       1.1  thorpej #define	WMREG_FCRTL	0x2160	/* Flow Control Rx Threshold Lo */
    470       1.1  thorpej #define	FCRTH_DFLT	0x00008000
    471       1.1  thorpej 
    472       1.1  thorpej #define	WMREG_OLD_FCRTL 0x0168	/* Flow Control Rx Threshold Lo (OLD) */
    473       1.1  thorpej #define	WMREG_FCRTH	0x2168	/* Flow Control Rx Threhsold Hi */
    474       1.1  thorpej #define	FCRTL_DFLT	0x00004000
    475      1.11  thorpej #define	FCRTL_XONE	0x80000000	/* Enable XON frame transmission */
    476       1.1  thorpej 
    477       1.1  thorpej #define	WMREG_FCTTV	0x0170	/* Flow Control Transmit Timer Value */
    478      1.11  thorpej #define	FCTTV_DFLT	0x00000600
    479       1.1  thorpej 
    480       1.1  thorpej #define	WMREG_TXCW	0x0178	/* Transmit Configuration Word (TBI mode) */
    481       1.1  thorpej 	/* See MII ANAR_X bits. */
    482       1.1  thorpej #define	TXCW_TxConfig	(1U << 30)	/* Tx Config */
    483       1.1  thorpej #define	TXCW_ANE	(1U << 31)	/* Autonegotiate */
    484       1.1  thorpej 
    485       1.1  thorpej #define	WMREG_RXCW	0x0180	/* Receive Configuration Word (TBI mode) */
    486       1.1  thorpej 	/* See MII ANLPAR_X bits. */
    487       1.1  thorpej #define	RXCW_NC		(1U << 26)	/* no carrier */
    488       1.1  thorpej #define	RXCW_IV		(1U << 27)	/* config invalid */
    489       1.1  thorpej #define	RXCW_CC		(1U << 28)	/* config change */
    490       1.1  thorpej #define	RXCW_C		(1U << 29)	/* /C/ reception */
    491       1.1  thorpej #define	RXCW_SYNCH	(1U << 30)	/* synchronized */
    492       1.1  thorpej #define	RXCW_ANC	(1U << 31)	/* autonegotiation complete */
    493       1.1  thorpej 
    494       1.1  thorpej #define	WMREG_MTA	0x0200	/* Multicast Table Array */
    495       1.1  thorpej #define	WMREG_CORDOVA_MTA 0x5200
    496       1.1  thorpej 
    497       1.1  thorpej #define	WMREG_TCTL	0x0400	/* Transmit Control Register */
    498       1.1  thorpej #define	TCTL_EN		(1U << 1)	/* transmitter enable */
    499       1.1  thorpej #define	TCTL_PSP	(1U << 3)	/* pad short packets */
    500       1.1  thorpej #define	TCTL_CT(x)	(((x) & 0xff) << 4)   /* 4:11 - collision threshold */
    501       1.1  thorpej #define	TCTL_COLD(x)	(((x) & 0x3ff) << 12) /* 12:21 - collision distance */
    502       1.1  thorpej #define	TCTL_SWXOFF	(1U << 22)	/* software XOFF */
    503       1.1  thorpej #define	TCTL_RTLC	(1U << 24)	/* retransmit on late collision */
    504       1.1  thorpej #define	TCTL_NRTU	(1U << 25)	/* no retransmit on underrun */
    505  1.14.4.2   bouyer #define	TCTL_MULR	(1U << 28)	/* multiple request */
    506       1.1  thorpej 
    507       1.1  thorpej #define	TX_COLLISION_THRESHOLD		15
    508  1.14.4.2   bouyer #define	TX_COLLISION_DISTANCE_HDX	512
    509  1.14.4.2   bouyer #define	TX_COLLISION_DISTANCE_FDX	64
    510  1.14.4.2   bouyer 
    511  1.14.4.2   bouyer #define	WMREG_TCTL_EXT	0x0404	/* Transmit Control Register */
    512  1.14.4.2   bouyer #define	TCTL_EXT_BST_MASK	0x000003FF /* Backoff Slot Time */
    513  1.14.4.2   bouyer #define	TCTL_EXT_GCEX_MASK	0x000FFC00 /* Gigabit Carry Extend Padding */
    514  1.14.4.2   bouyer 
    515  1.14.4.2   bouyer #define	DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
    516       1.1  thorpej 
    517       1.1  thorpej #define	WMREG_TQSA_LO	0x0408
    518       1.1  thorpej 
    519       1.1  thorpej #define	WMREG_TQSA_HI	0x040c
    520       1.1  thorpej 
    521       1.1  thorpej #define	WMREG_TIPG	0x0410	/* Transmit IPG Register */
    522       1.1  thorpej #define	TIPG_IPGT(x)	(x)		/* IPG transmit time */
    523       1.1  thorpej #define	TIPG_IPGR1(x)	((x) << 10)	/* IPG receive time 1 */
    524       1.1  thorpej #define	TIPG_IPGR2(x)	((x) << 20)	/* IPG receive time 2 */
    525       1.1  thorpej 
    526       1.1  thorpej #define	TIPG_WM_DFLT	(TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a))
    527       1.1  thorpej #define	TIPG_LG_DFLT	(TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06))
    528       1.1  thorpej #define	TIPG_1000T_DFLT	(TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06))
    529  1.14.4.2   bouyer #define	TIPG_1000T_80003_DFLT \
    530  1.14.4.2   bouyer     (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07))
    531  1.14.4.2   bouyer #define	TIPG_10_100_80003_DFLT \
    532  1.14.4.2   bouyer     (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07))
    533       1.1  thorpej 
    534       1.1  thorpej #define	WMREG_TQC	0x0418
    535       1.1  thorpej 
    536  1.14.4.2   bouyer #define	WMREG_EEWR	0x102c	/* EEPROM write */
    537  1.14.4.2   bouyer 
    538      1.12  thorpej #define	WMREG_RDFH	0x2410	/* Receive Data FIFO Head */
    539      1.12  thorpej 
    540      1.12  thorpej #define	WMREG_RDFT	0x2418	/* Receive Data FIFO Tail */
    541      1.12  thorpej 
    542      1.12  thorpej #define	WMREG_RDFHS	0x2420	/* Receive Data FIFO Head Saved */
    543      1.12  thorpej 
    544      1.12  thorpej #define	WMREG_RDFTS	0x2428	/* Receive Data FIFO Tail Saved */
    545      1.12  thorpej 
    546      1.12  thorpej #define	WMREG_TDFH	0x3410	/* Transmit Data FIFO Head */
    547      1.12  thorpej 
    548      1.12  thorpej #define	WMREG_TDFT	0x3418	/* Transmit Data FIFO Tail */
    549      1.12  thorpej 
    550      1.12  thorpej #define	WMREG_TDFHS	0x3420	/* Transmit Data FIFO Head Saved */
    551      1.12  thorpej 
    552      1.12  thorpej #define	WMREG_TDFTS	0x3428	/* Transmit Data FIFO Tail Saved */
    553      1.12  thorpej 
    554      1.12  thorpej #define	WMREG_TDFPC	0x3430	/* Transmit Data FIFO Packet Count */
    555      1.12  thorpej 
    556       1.1  thorpej #define	WMREG_OLD_TBDAL	0x0420	/* Transmit Descriptor Base Lo */
    557       1.1  thorpej #define	WMREG_TBDAL	0x3800
    558       1.1  thorpej 
    559       1.1  thorpej #define	WMREG_OLD_TBDAH	0x0424	/* Transmit Descriptor Base Hi */
    560       1.1  thorpej #define	WMREG_TBDAH	0x3804
    561       1.1  thorpej 
    562       1.1  thorpej #define	WMREG_OLD_TDLEN	0x0428	/* Transmit Descriptor Length */
    563       1.1  thorpej #define	WMREG_TDLEN	0x3808
    564       1.1  thorpej 
    565       1.1  thorpej #define	WMREG_OLD_TDH	0x0430	/* Transmit Descriptor Head */
    566       1.1  thorpej #define	WMREG_TDH	0x3810
    567       1.1  thorpej 
    568       1.1  thorpej #define	WMREG_OLD_TDT	0x0438	/* Transmit Descriptor Tail */
    569       1.1  thorpej #define	WMREG_TDT	0x3818
    570       1.1  thorpej 
    571       1.1  thorpej #define	WMREG_OLD_TIDV	0x0440	/* Transmit Delay Interrupt Value */
    572       1.1  thorpej #define	WMREG_TIDV	0x3820
    573       1.1  thorpej 
    574       1.1  thorpej #define	WMREG_TXDCTL	0x3828	/* Trandmit Descriptor Control */
    575       1.1  thorpej #define	TXDCTL_PTHRESH(x) ((x) << 0)	/* prefetch threshold */
    576       1.1  thorpej #define	TXDCTL_HTHRESH(x) ((x) << 8)	/* host threshold */
    577       1.1  thorpej #define	TXDCTL_WTHRESH(x) ((x) << 16)	/* write back threshold */
    578       1.1  thorpej 
    579      1.14   briggs #define	WMREG_TADV	0x382c	/* Transmit Absolute Interrupt Delay Timer */
    580      1.14   briggs 
    581       1.1  thorpej #define	WMREG_AIT	0x0458	/* Adaptive IFS Throttle */
    582       1.1  thorpej 
    583       1.1  thorpej #define	WMREG_VFTA	0x0600
    584       1.1  thorpej 
    585       1.1  thorpej #define	WM_MC_TABSIZE	128
    586  1.14.4.3      riz #define	WM_ICH8_MC_TABSIZE 32
    587       1.1  thorpej #define	WM_VLAN_TABSIZE	128
    588       1.1  thorpej 
    589       1.1  thorpej #define	WMREG_PBA	0x1000	/* Packet Buffer Allocation */
    590      1.12  thorpej #define	PBA_BYTE_SHIFT	10		/* KB -> bytes */
    591      1.12  thorpej #define	PBA_ADDR_SHIFT	7		/* KB -> quadwords */
    592  1.14.4.3      riz #define	PBA_8K		0x0008
    593  1.14.4.2   bouyer #define	PBA_12K		0x000c
    594      1.12  thorpej #define	PBA_16K		0x0010		/* 16K, default Tx allocation */
    595      1.12  thorpej #define	PBA_22K		0x0016
    596      1.12  thorpej #define	PBA_24K		0x0018
    597      1.12  thorpej #define	PBA_30K		0x001e
    598  1.14.4.2   bouyer #define	PBA_32K		0x0020
    599      1.12  thorpej #define	PBA_40K		0x0028
    600      1.12  thorpej #define	PBA_48K		0x0030		/* 48K, default Rx allocation */
    601       1.1  thorpej 
    602  1.14.4.3      riz #define	WMREG_PBS	0x1000	/* Packet Buffer Size (ICH8 only ?) */
    603  1.14.4.3      riz 
    604       1.1  thorpej #define	WMREG_TXDMAC	0x3000	/* Transfer DMA Control */
    605       1.1  thorpej #define	TXDMAC_DPP	(1U << 0)	/* disable packet prefetch */
    606       1.1  thorpej 
    607       1.1  thorpej #define	WMREG_TSPMT	0x3830	/* TCP Segmentation Pad and Minimum
    608       1.1  thorpej 				   Threshold (Cordova) */
    609       1.1  thorpej #define	TSPMT_TSMT(x)	(x)		/* TCP seg min transfer */
    610       1.1  thorpej #define	TSPMT_TSPBP(x)	((x) << 16)	/* TCP seg pkt buf padding */
    611       1.1  thorpej 
    612       1.1  thorpej #define	WMREG_RXCSUM	0x5000	/* Receive Checksum register */
    613       1.1  thorpej #define	RXCSUM_PCSS	0x000000ff	/* Packet Checksum Start */
    614       1.1  thorpej #define	RXCSUM_IPOFL	(1U << 8)	/* IP checksum offload */
    615       1.1  thorpej #define	RXCSUM_TUOFL	(1U << 9)	/* TCP/UDP checksum offload */
    616      1.11  thorpej 
    617  1.14.4.2   bouyer #define	WMREG_RXERRC	0x400C	/* receive error Count - R/clr */
    618  1.14.4.2   bouyer #define	WMREG_COLC	0x4028	/* collision Count - R/clr */
    619      1.11  thorpej #define	WMREG_XONRXC	0x4048	/* XON Rx Count - R/clr */
    620      1.11  thorpej #define	WMREG_XONTXC	0x404c	/* XON Tx Count - R/clr */
    621      1.11  thorpej #define	WMREG_XOFFRXC	0x4050	/* XOFF Rx Count - R/clr */
    622      1.11  thorpej #define	WMREG_XOFFTXC	0x4054	/* XOFF Tx Count - R/clr */
    623      1.11  thorpej #define	WMREG_FCRUC	0x4058	/* Flow Control Rx Unsupported Count - R/clr */
    624  1.14.4.2   bouyer 
    625  1.14.4.2   bouyer #define	WMREG_KUMCTRLSTA 0x0034	/* MAC-PHY interface - RW */
    626  1.14.4.2   bouyer #define	KUMCTRLSTA_MASK			0x0000FFFF
    627  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET		0x001F0000
    628  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET_SHIFT		16
    629  1.14.4.2   bouyer #define	KUMCTRLSTA_REN			0x00200000
    630  1.14.4.2   bouyer 
    631  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET_FIFO_CTRL	0x00000000
    632  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET_CTRL		0x00000001
    633  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET_INB_CTRL	0x00000002
    634  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET_DIAG		0x00000003
    635  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET_TIMEOUTS	0x00000004
    636  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET_INB_PARAM	0x00000009
    637  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET_HD_CTRL	0x00000010
    638  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET_M2P_SERDES	0x0000001E
    639  1.14.4.2   bouyer #define	KUMCTRLSTA_OFFSET_M2P_MODES	0x0000001F
    640  1.14.4.2   bouyer 
    641  1.14.4.2   bouyer /* FIFO Control */
    642  1.14.4.2   bouyer #define	KUMCTRLSTA_FIFO_CTRL_RX_BYPASS	0x00000008
    643  1.14.4.2   bouyer #define	KUMCTRLSTA_FIFO_CTRL_TX_BYPASS	0x00000800
    644  1.14.4.2   bouyer 
    645  1.14.4.2   bouyer /* In-Band Control */
    646  1.14.4.2   bouyer #define	KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500
    647  1.14.4.2   bouyer #define	KUMCTRLSTA_INB_CTRL_DIS_PADDING	0x00000010
    648  1.14.4.2   bouyer 
    649  1.14.4.2   bouyer /* Half-Duplex Control */
    650  1.14.4.2   bouyer #define	KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
    651  1.14.4.2   bouyer #define	KUMCTRLSTA_HD_CTRL_1000_DEFAULT	0x00000000
    652  1.14.4.2   bouyer 
    653  1.14.4.2   bouyer #define	WMREG_MDPHYA	0x003C	/* PHY address - RW */
    654  1.14.4.2   bouyer 
    655  1.14.4.2   bouyer #define	WMREG_MANC2H	0x5860	/* Managment Control To Host - RW */
    656  1.14.4.2   bouyer 
    657  1.14.4.2   bouyer #define	WMREG_SWSM	0x5b50	/* SW Semaphore */
    658  1.14.4.2   bouyer #define	SWSM_SMBI	0x00000001	/* Driver Semaphore bit */
    659  1.14.4.2   bouyer #define	SWSM_SWESMBI	0x00000002	/* FW Semaphore bit */
    660  1.14.4.2   bouyer #define	SWSM_WMNG	0x00000004	/* Wake MNG Clock */
    661  1.14.4.2   bouyer #define	SWSM_DRV_LOAD	0x00000008	/* Driver Loaded Bit */
    662  1.14.4.2   bouyer 
    663  1.14.4.2   bouyer #define	WMREG_SW_FW_SYNC 0x5b5c	/* software-firmware semaphore */
    664  1.14.4.2   bouyer #define	SWFW_EEP_SM		0x0001 /* eeprom access */
    665  1.14.4.2   bouyer #define	SWFW_PHY0_SM		0x0002 /* first ctrl phy access */
    666  1.14.4.2   bouyer #define	SWFW_PHY1_SM		0x0004 /* second ctrl phy access */
    667  1.14.4.2   bouyer #define	SWFW_MAC_CSR_SM		0x0008
    668  1.14.4.2   bouyer #define	SWFW_SOFT_SHIFT		0	/* software semaphores */
    669  1.14.4.2   bouyer #define	SWFW_FIRM_SHIFT		16	/* firmware semaphores */
    670  1.14.4.3      riz 
    671  1.14.4.3      riz #define WMREG_EXTCNFCTR		0x0f00  /* Extended Configuration Control */
    672  1.14.4.3      riz #define EXTCNFCTR_PCIE_WRITE_ENABLE	0x00000001
    673  1.14.4.3      riz #define EXTCNFCTR_PHY_WRITE_ENABLE	0x00000002
    674  1.14.4.3      riz #define EXTCNFCTR_D_UD_ENABLE		0x00000004
    675  1.14.4.3      riz #define EXTCNFCTR_D_UD_LATENCY		0x00000008
    676  1.14.4.3      riz #define EXTCNFCTR_D_UD_OWNER		0x00000010
    677  1.14.4.3      riz #define EXTCNFCTR_MDIO_SW_OWNERSHIP	0x00000020
    678  1.14.4.3      riz #define EXTCNFCTR_MDIO_HW_OWNERSHIP	0x00000040
    679  1.14.4.3      riz #define EXTCNFCTR_EXT_CNF_POINTER	0x0FFF0000
    680  1.14.4.3      riz #define E1000_EXTCNF_CTRL_SWFLAG	EXTCNFCTR_MDIO_SW_OWNERSHIP
    681  1.14.4.3      riz 
    682  1.14.4.3      riz /* ich8 flash control */
    683  1.14.4.3      riz #define ICH_FLASH_COMMAND_TIMEOUT            5000    /* 5000 uSecs - adjusted */
    684  1.14.4.3      riz #define ICH_FLASH_ERASE_TIMEOUT              3000000 /* Up to 3 seconds - worst case */
    685  1.14.4.3      riz #define ICH_FLASH_CYCLE_REPEAT_COUNT         10      /* 10 cycles */
    686  1.14.4.3      riz #define ICH_FLASH_SEG_SIZE_256               256
    687  1.14.4.3      riz #define ICH_FLASH_SEG_SIZE_4K                4096
    688  1.14.4.3      riz #define ICH_FLASH_SEG_SIZE_64K               65536
    689  1.14.4.3      riz 
    690  1.14.4.3      riz #define ICH_CYCLE_READ                       0x0
    691  1.14.4.3      riz #define ICH_CYCLE_RESERVED                   0x1
    692  1.14.4.3      riz #define ICH_CYCLE_WRITE                      0x2
    693  1.14.4.3      riz #define ICH_CYCLE_ERASE                      0x3
    694  1.14.4.3      riz 
    695  1.14.4.3      riz #define ICH_FLASH_GFPREG   0x0000
    696  1.14.4.3      riz #define ICH_FLASH_HSFSTS   0x0004 /* Flash Status Register */
    697  1.14.4.3      riz #define HSFSTS_DONE		0x0001 /* Flash Cycle Done */
    698  1.14.4.3      riz #define HSFSTS_ERR		0x0002 /* Flash Cycle Error */
    699  1.14.4.3      riz #define HSFSTS_DAEL		0x0004 /* Direct Access error Log */
    700  1.14.4.3      riz #define HSFSTS_ERSZ_MASK	0x0018 /* Block/Sector Erase Size */
    701  1.14.4.3      riz #define HSFSTS_ERSZ_SHIFT	3
    702  1.14.4.3      riz #define HSFSTS_FLINPRO		0x0020 /* flash SPI cycle in Progress */
    703  1.14.4.3      riz #define HSFSTS_FLDVAL		0x4000 /* Flash Descriptor Valid */
    704  1.14.4.3      riz #define HSFSTS_FLLK		0x8000 /* Flash Configuration Lock-Down */
    705  1.14.4.3      riz #define ICH_FLASH_HSFCTL   0x0006 /* Flash control Register */
    706  1.14.4.3      riz #define HSFCTL_GO		0x0001 /* Flash Cycle Go */
    707  1.14.4.3      riz #define HSFCTL_CYCLE_MASK	0x0006 /* Flash Cycle */
    708  1.14.4.3      riz #define HSFCTL_CYCLE_SHIFT	1
    709  1.14.4.3      riz #define HSFCTL_BCOUNT_MASK	0x0300 /* Data Byte Count */
    710  1.14.4.3      riz #define HSFCTL_BCOUNT_SHIFT	8
    711  1.14.4.3      riz #define ICH_FLASH_FADDR    0x0008
    712  1.14.4.3      riz #define ICH_FLASH_FDATA0   0x0010
    713  1.14.4.3      riz #define ICH_FLASH_FRACC    0x0050
    714  1.14.4.3      riz #define ICH_FLASH_FREG0    0x0054
    715  1.14.4.3      riz #define ICH_FLASH_FREG1    0x0058
    716  1.14.4.3      riz #define ICH_FLASH_FREG2    0x005C
    717  1.14.4.3      riz #define ICH_FLASH_FREG3    0x0060
    718  1.14.4.3      riz #define ICH_FLASH_FPR0     0x0074
    719  1.14.4.3      riz #define ICH_FLASH_FPR1     0x0078
    720  1.14.4.3      riz #define ICH_FLASH_SSFSTS   0x0090
    721  1.14.4.3      riz #define ICH_FLASH_SSFCTL   0x0092
    722  1.14.4.3      riz #define ICH_FLASH_PREOP    0x0094
    723  1.14.4.3      riz #define ICH_FLASH_OPTYPE   0x0096
    724  1.14.4.3      riz #define ICH_FLASH_OPMENU   0x0098
    725  1.14.4.3      riz 
    726  1.14.4.3      riz #define ICH_FLASH_REG_MAPSIZE      0x00A0
    727  1.14.4.3      riz #define ICH_FLASH_SECTOR_SIZE      4096
    728  1.14.4.3      riz #define ICH_GFPREG_BASE_MASK       0x1FFF
    729  1.14.4.3      riz #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
    730