if_wmreg.h revision 1.5
1 /* $NetBSD: if_wmreg.h,v 1.5 2003/05/30 02:08:55 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Register description for the Intel i82542 (``Wiseman''), 40 * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit 41 * Ethernet chips. 42 */ 43 44 /* 45 * The wiseman supports 64-bit PCI addressing. This structure 46 * describes the address in descriptors. 47 */ 48 typedef struct wiseman_addr { 49 uint32_t wa_low; /* low-order 32 bits */ 50 uint32_t wa_high; /* high-order 32 bits */ 51 } __attribute__((__packed__)) wiseman_addr_t; 52 53 /* 54 * The Wiseman receive descriptor. 55 * 56 * The receive descriptor ring must be aligned to a 4K boundary, 57 * and there must be an even multiple of 8 descriptors in the ring. 58 */ 59 typedef struct wiseman_rxdesc { 60 wiseman_addr_t wrx_addr; /* buffer address */ 61 62 uint16_t wrx_len; /* buffer length */ 63 uint16_t wrx_cksum; /* checksum (starting at PCSS) */ 64 65 uint8_t wrx_status; /* Rx status */ 66 uint8_t wrx_errors; /* Rx errors */ 67 uint16_t wrx_special; /* special field (VLAN, etc.) */ 68 } __attribute__((__packed__)) wiseman_rxdesc_t; 69 70 /* wrx_status bits */ 71 #define WRX_ST_DD (1U << 0) /* descriptor done */ 72 #define WRX_ST_EOP (1U << 1) /* end of packet */ 73 #define WRX_ST_ISXM (1U << 2) /* ignore checksum indication */ 74 #define WRX_ST_VP (1U << 3) /* VLAN packet */ 75 #define WRX_ST_BPDU (1U << 4) /* ??? */ 76 #define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */ 77 #define WRX_ST_IPCS (1U << 6) /* IP checksum performed */ 78 #define WRX_ST_PIF (1U << 7) /* passed in-exact filter */ 79 80 /* wrx_error bits */ 81 #define WRX_ER_CE (1U << 0) /* CRC error */ 82 #define WRX_ER_SE (1U << 1) /* symbol error */ 83 #define WRX_ER_SEQ (1U << 2) /* sequence error */ 84 #define WRX_ER_ICE (1U << 3) /* ??? */ 85 #define WRX_ER_CXE (1U << 4) /* carrier extension error */ 86 #define WRX_ER_TCPE (1U << 5) /* TCP checksum error */ 87 #define WRX_ER_IPE (1U << 6) /* IP checksum error */ 88 #define WRX_ER_RXE (1U << 7) /* Rx data error */ 89 90 /* wrx_special field for VLAN packets */ 91 #define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */ 92 #define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */ 93 #define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */ 94 95 /* 96 * The Wiseman transmit descriptor. 97 * 98 * The transmit descriptor ring must be aligned to a 4K boundary, 99 * and there must be an even multiple of 8 descriptors in the ring. 100 */ 101 typedef union wiseman_tx_fields { 102 uint32_t wtxu_bits; /* bits; see below; */ 103 struct { 104 uint8_t wtxu_status; /* Tx status */ 105 uint8_t wtxu_options; /* options */ 106 uint16_t wtxu_vlan; /* VLAN info */ 107 } __attribute__((__packed__)) wtxu_fields; 108 } __attribute__((__packed__)) wiseman_txfields_t; 109 typedef struct wiseman_txdesc { 110 wiseman_addr_t wtx_addr; /* buffer address */ 111 uint32_t wtx_cmdlen; /* command and length */ 112 wiseman_txfields_t wtx_fields; /* fields; see below */ 113 } __attribute__((__packed__)) wiseman_txdesc_t; 114 115 #define WTX_CMD_EOP (1U << 24) /* end of packet */ 116 #define WTX_CMD_IFCS (1U << 25) /* insert FCS */ 117 #define WTX_CMD_RS (1U << 27) /* report status */ 118 #define WTX_CMD_RPS (1U << 28) /* report packet sent */ 119 #define WTX_CMD_DEXT (1U << 29) /* descriptor extension */ 120 #define WTX_CMD_VLE (1U << 30) /* VLAN enable */ 121 #define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */ 122 123 /* Descriptor types (if DEXT is set) */ 124 #define WTX_DTYP_C (0 << 20) /* context */ 125 #define WTC_DTYP_D (1U << 20) /* data */ 126 127 /* wtx_fields status bits */ 128 #define WTX_ST_DD (1U << 0) /* descriptor done */ 129 #define WTX_ST_EC (1U << 1) /* excessive collisions */ 130 #define WTX_ST_LC (1U << 2) /* late collision */ 131 #define WTX_ST_TU (1U << 3) /* transmit underrun */ 132 133 /* wtx_fields bits for IP/TCP/UDP checksum offload */ 134 #define WTX_IXSM (1U << 8) /* IP checksum offload */ 135 #define WTX_TXSM (1U << 9) /* TCP/UDP checksum offload */ 136 137 /* 138 * The Livengood TCP/IP context descriptor. 139 */ 140 struct livengood_tcpip_ctxdesc { 141 uint32_t tcpip_ipcs; /* IP checksum context */ 142 uint32_t tcpip_tucs; /* TCP/UDP checksum context */ 143 uint32_t tcpip_cmdlen; 144 uint32_t tcpip_seg; /* TCP segmentation context */ 145 }; 146 147 /* commands for context descriptors */ 148 #define WTX_TCPIP_CMD_TCP (1U << 24) /* 1 = TCP, 0 = UDP */ 149 #define WTX_TCPIP_CMD_IP (1U << 25) /* 1 = IPv4, 0 = IPv6 */ 150 #define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */ 151 152 #define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */ 153 #define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */ 154 #define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */ 155 156 #define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */ 157 #define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */ 158 #define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */ 159 160 #define WTX_TCPIP_SEG_STATUS(x) ((x) << 0) 161 #define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8) 162 #define WTX_TCPIP_SEG_MSS(x) ((x) << 16) 163 164 /* 165 * PCI config registers used by the Wiseman. 166 */ 167 #define WM_PCI_MMBA PCI_MAPREG_START 168 169 /* 170 * Wiseman Control/Status Registers. 171 */ 172 #define WMREG_CTRL 0x0000 /* Device Control Register */ 173 #define CTRL_FD (1U << 0) /* full duplex */ 174 #define CTRL_BEM (1U << 1) /* big-endian mode */ 175 #define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */ 176 #define CTRL_LRST (1U << 3) /* link reset */ 177 #define CTRL_ASDE (1U << 5) /* auto speed detect enable */ 178 #define CTRL_SLU (1U << 6) /* set link up */ 179 #define CTRL_ILOS (1U << 7) /* invert loss of signal */ 180 #define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */ 181 #define CTRL_SPEED_10 CTRL_SPEED(0) 182 #define CTRL_SPEED_100 CTRL_SPEED(1) 183 #define CTRL_SPEED_1000 CTRL_SPEED(2) 184 #define CTRL_SPEED_MASK CTRL_SPEED(3) 185 #define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */ 186 #define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */ 187 #define CTRL_SWDPINS_SHIFT 18 188 #define CTRL_SWDPINS_MASK 0x0f 189 #define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x))) 190 #define CTRL_SWDPIO_SHIFT 22 191 #define CTRL_SWDPIO_MASK 0x0f 192 #define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x))) 193 #define CTRL_RST (1U << 26) /* device reset */ 194 #define CTRL_RFCE (1U << 27) /* Rx flow control enable */ 195 #define CTRL_TFCE (1U << 28) /* Tx flow control enable */ 196 #define CTRL_VME (1U << 30) /* VLAN Mode Enable */ 197 #define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */ 198 199 #define WMREG_STATUS 0x0008 /* Device Status Register */ 200 #define STATUS_FD (1U << 0) /* full duplex */ 201 #define STATUS_LU (1U << 1) /* link up */ 202 #define STATUS_TCKOK (1U << 2) /* Tx clock running */ 203 #define STATUS_RBCOK (1U << 3) /* Rx clock running */ 204 #define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */ 205 #define STATUS_FUNCID_MASK 3 /* ... */ 206 #define STATUS_TXOFF (1U << 4) /* Tx paused */ 207 #define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */ 208 #define STATUS_SPEED(x) ((x) << 6) /* speed indication */ 209 #define STATUS_SPEED_10 STATUS_SPEED(0) 210 #define STATUS_SPEED_100 STATUS_SPEED(1) 211 #define STATUS_SPEED_1000 STATUS_SPEED(2) 212 #define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */ 213 #define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */ 214 #define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */ 215 #define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */ 216 #define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */ 217 #define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */ 218 #define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0) 219 #define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1) 220 #define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2) 221 222 #define WMREG_EECD 0x0010 /* EEPROM Control Register */ 223 #define EECD_SK (1U << 0) /* clock */ 224 #define EECD_CS (1U << 1) /* chip select */ 225 #define EECD_DI (1U << 2) /* data in */ 226 #define EECD_DO (1U << 3) /* data out */ 227 #define EECD_FWE(x) ((x) << 4) /* flash write enable control */ 228 #define EECD_FWE_DISABLED EECD_FWE(1) 229 #define EECD_FWE_ENABLED EECD_FWE(2) 230 #define EECD_EE_REQ (1U << 6) /* (shared) EEPROM request */ 231 #define EECD_EE_GNT (1U << 7) /* (shared) EEPROM grant */ 232 #define EECD_EE_PRES (1U << 8) /* EEPROM present */ 233 #define EECD_EE_SIZE (1U << 9) /* EEPROM size 234 (0 = 64 word, 1 = 256 word) */ 235 236 #define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */ 237 #define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */ 238 #define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */ 239 240 #define EEPROM_OFF_MACADDR 0x00 /* MAC address offset */ 241 #define EEPROM_OFF_CFG1 0x0a /* config word 1 */ 242 #define EEPROM_OFF_CFG2 0x0f /* config word 2 */ 243 #define EEPROM_OFF_SWDPIN 0x20 /* SWD Pins (Cordova) */ 244 245 #define EEPROM_CFG1_LVDID (1U << 0) 246 #define EEPROM_CFG1_LSSID (1U << 1) 247 #define EEPROM_CFG1_PME_CLOCK (1U << 2) 248 #define EEPROM_CFG1_PM (1U << 3) 249 #define EEPROM_CFG1_ILOS (1U << 4) 250 #define EEPROM_CFG1_SWDPIO_SHIFT 5 251 #define EEPROM_CFG1_SWDPIO_MASK (0xf << EEPROM_CFG1_SWDPIO_SHIFT) 252 #define EEPROM_CFG1_IPS1 (1U << 8) 253 #define EEPROM_CFG1_LRST (1U << 9) 254 #define EEPROM_CFG1_FD (1U << 10) 255 #define EEPROM_CFG1_FRCSPD (1U << 11) 256 #define EEPROM_CFG1_IPS0 (1U << 12) 257 #define EEPROM_CFG1_64_32_BAR (1U << 13) 258 259 #define EEPROM_CFG2_CSR_RD_SPLIT (1U << 1) 260 #define EEPROM_CFG2_APM_EN (1U << 2) 261 #define EEPROM_CFG2_64_BIT (1U << 3) 262 #define EEPROM_CFG2_MAX_READ (1U << 4) 263 #define EEPROM_CFG2_DMCR_MAP (1U << 5) 264 #define EEPROM_CFG2_133_CAP (1U << 6) 265 #define EEPROM_CFG2_MSI_DIS (1U << 7) 266 #define EEPROM_CFG2_FLASH_DIS (1U << 8) 267 #define EEPROM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9) 268 #define EEPROM_CFG2_ANE (1U << 11) 269 #define EEPROM_CFG2_PAUSE(x) (((x) & 3) >> 12) 270 #define EEPROM_CFG2_ASDE (1U << 14) 271 #define EEPROM_CFG2_APM_PME (1U << 15) 272 #define EEPROM_CFG2_SWDPIO_SHIFT 4 273 #define EEPROM_CFG2_SWDPIO_MASK (0xf << EEPROM_CFG2_SWDPIO_SHIFT) 274 275 #define EEPROM_SWDPIN_MASK 0xdf 276 #define EEPROM_SWDPIN_SWDPIN_SHIFT 0 277 #define EEPROM_SWDPIN_SWDPIO_SHIFT 8 278 279 #define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */ 280 #define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */ 281 #define CTRL_EXT_SWDPINS_SHIFT 4 282 #define CTRL_EXT_SWDPINS_MASK 0x0d 283 #define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT + (x) - 4)) 284 #define CTRL_EXT_SWDPIO_SHIFT 8 285 #define CTRL_EXT_SWDPIO_MASK 0x0d 286 #define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT + (x) - 4)) 287 #define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */ 288 #define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */ 289 #define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */ 290 #define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */ 291 #define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */ 292 #define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */ 293 294 #define WMREG_MDIC 0x0020 /* MDI Control Register */ 295 #define MDIC_DATA(x) ((x) & 0xffff) 296 #define MDIC_REGADD(x) ((x) << 16) 297 #define MDIC_PHYADD(x) ((x) << 21) 298 #define MDIC_OP_WRITE (1U << 26) 299 #define MDIC_OP_READ (2U << 26) 300 #define MDIC_READY (1U << 28) 301 #define MDIC_I (1U << 29) /* interrupt on MDI complete */ 302 #define MDIC_E (1U << 30) /* MDI error */ 303 304 #define WMREG_FCAL 0x0028 /* Flow Control Address Low */ 305 #define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */ 306 307 #define WMREG_FCAH 0x002c /* Flow Control Address High */ 308 #define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */ 309 310 #define WMREG_FCT 0x0030 /* Flow Control Type */ 311 312 #define WMREG_VET 0x0038 /* VLAN Ethertype */ 313 314 #define WMREG_RAL_BASE 0x0040 /* Receive Address List */ 315 #define WMREG_CORDOVA_RAL_BASE 0x5400 316 #define WMREG_RAL_LO(b, x) ((b) + ((x) << 3)) 317 #define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4) 318 /* 319 * Receive Address List: The LO part is the low-order 32-bits 320 * of the MAC address. The HI part is the high-order 16-bits 321 * along with a few control bits. 322 */ 323 #define RAL_AS(x) ((x) << 16) /* address select */ 324 #define RAL_AS_DEST RAL_AS(0) /* (cordova?) */ 325 #define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */ 326 #define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */ 327 #define RAL_AV (1U << 31) /* entry is valid */ 328 329 #define WM_RAL_TABSIZE 16 330 331 #define WMREG_ICR 0x00c0 /* Interrupt Cause Register */ 332 #define ICR_TXDW (1U << 0) /* Tx desc written back */ 333 #define ICR_TXQE (1U << 1) /* Tx queue empty */ 334 #define ICR_LSC (1U << 2) /* link status change */ 335 #define ICR_RXSEQ (1U << 3) /* receive sequence error */ 336 #define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */ 337 #define ICR_RXO (1U << 6) /* Rx overrun */ 338 #define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */ 339 #define ICR_MDAC (1U << 9) /* MDIO access complete */ 340 #define ICR_RXCFG (1U << 10) /* Receiving /C/ */ 341 #define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */ 342 343 #define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */ 344 /* See ICR bits. */ 345 346 #define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */ 347 /* See ICR bits. */ 348 349 #define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */ 350 /* See ICR bits. */ 351 352 #define WMREG_RCTL 0x0100 /* Receive Control */ 353 #define RCTL_EN (1U << 1) /* receiver enable */ 354 #define RCTL_SBP (1U << 2) /* store bad packets */ 355 #define RCTL_UPE (1U << 3) /* unicast promisc. enable */ 356 #define RCTL_MPE (1U << 4) /* multicast promisc. enable */ 357 #define RCTL_LPE (1U << 5) /* large packet enable */ 358 #define RCTL_LBM(x) ((x) << 6) /* loopback mode */ 359 #define RCTL_LBM_NONE RCTL_LBM(0) 360 #define RCTL_LBM_PHY RCTL_LBM(3) 361 #define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */ 362 #define RCTL_RDMTS_1_2 RCTL_RDMTS(0) 363 #define RCTL_RDMTS_1_4 RCTL_RDMTS(1) 364 #define RCTL_RDMTS_1_8 RCTL_RDMTS(2) 365 #define RCTL_RDMTS_MASK RCTL_RDMTS(3) 366 #define RCTL_MO(x) ((x) << 12) /* multicast offset */ 367 #define RCTL_BAM (1U << 15) /* broadcast accept mode */ 368 #define RCTL_2k (0 << 16) /* 2k Rx buffers */ 369 #define RCTL_1k (1 << 16) /* 1k Rx buffers */ 370 #define RCTL_512 (2 << 16) /* 512 byte Rx buffers */ 371 #define RCTL_256 (3 << 16) /* 256 byte Rx buffers */ 372 #define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */ 373 #define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */ 374 #define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */ 375 #define RCTL_DPF (1U << 22) /* discard pause frames */ 376 #define RCTL_PMCF (1U << 23) /* pass MAC control frames */ 377 #define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */ 378 #define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */ 379 380 #define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */ 381 #define WMREG_RDTR 0x2820 382 #define RDTR_FPD (1U << 31) /* flush partial descriptor */ 383 384 #define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */ 385 #define WMREG_RDBAL 0x2800 386 387 #define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */ 388 #define WMREG_RDBAH 0x2804 389 390 #define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */ 391 #define WMREG_RDLEN 0x2808 392 393 #define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */ 394 #define WMREG_RDH 0x2810 395 396 #define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */ 397 #define WMREG_RDT 0x2818 398 399 #define WMREG_RXDCTL 0x2828 /* Receive Descriptor Control */ 400 #define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 401 #define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 402 #define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 403 #define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */ 404 405 #define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */ 406 407 #define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */ 408 409 #define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */ 410 411 #define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */ 412 413 #define WMREG_OLD_RDH1 0x0148 414 415 #define WMREG_OLD_RDT1 0x0150 416 417 #define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */ 418 #define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */ 419 #define FCRTH_DFLT 0x00008000 420 421 #define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */ 422 #define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */ 423 #define FCRTL_DFLT 0x00004000 424 425 #define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */ 426 #define FCTTV_DFLT 0x00000100 427 428 #define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */ 429 /* See MII ANAR_X bits. */ 430 #define TXCW_TxConfig (1U << 30) /* Tx Config */ 431 #define TXCW_ANE (1U << 31) /* Autonegotiate */ 432 433 #define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */ 434 /* See MII ANLPAR_X bits. */ 435 #define RXCW_NC (1U << 26) /* no carrier */ 436 #define RXCW_IV (1U << 27) /* config invalid */ 437 #define RXCW_CC (1U << 28) /* config change */ 438 #define RXCW_C (1U << 29) /* /C/ reception */ 439 #define RXCW_SYNCH (1U << 30) /* synchronized */ 440 #define RXCW_ANC (1U << 31) /* autonegotiation complete */ 441 442 #define WMREG_MTA 0x0200 /* Multicast Table Array */ 443 #define WMREG_CORDOVA_MTA 0x5200 444 445 #define WMREG_TCTL 0x0400 /* Transmit Control Register */ 446 #define TCTL_EN (1U << 1) /* transmitter enable */ 447 #define TCTL_PSP (1U << 3) /* pad short packets */ 448 #define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */ 449 #define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */ 450 #define TCTL_SWXOFF (1U << 22) /* software XOFF */ 451 #define TCTL_RTLC (1U << 24) /* retransmit on late collision */ 452 #define TCTL_NRTU (1U << 25) /* no retransmit on underrun */ 453 454 #define TX_COLLISION_THRESHOLD 15 455 #define TX_COLLISION_DISTANCE_HDX 64 456 #define TX_COLLISION_DISTANCE_FDX 512 457 458 #define WMREG_TQSA_LO 0x0408 459 460 #define WMREG_TQSA_HI 0x040c 461 462 #define WMREG_TIPG 0x0410 /* Transmit IPG Register */ 463 #define TIPG_IPGT(x) (x) /* IPG transmit time */ 464 #define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */ 465 #define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */ 466 467 #define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a)) 468 #define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 469 #define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 470 471 #define WMREG_TQC 0x0418 472 473 #define WMREG_OLD_TBDAL 0x0420 /* Transmit Descriptor Base Lo */ 474 #define WMREG_TBDAL 0x3800 475 476 #define WMREG_OLD_TBDAH 0x0424 /* Transmit Descriptor Base Hi */ 477 #define WMREG_TBDAH 0x3804 478 479 #define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */ 480 #define WMREG_TDLEN 0x3808 481 482 #define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */ 483 #define WMREG_TDH 0x3810 484 485 #define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */ 486 #define WMREG_TDT 0x3818 487 488 #define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */ 489 #define WMREG_TIDV 0x3820 490 491 #define WMREG_TXDCTL 0x3828 /* Trandmit Descriptor Control */ 492 #define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 493 #define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 494 #define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 495 496 #define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */ 497 498 #define WMREG_VFTA 0x0600 499 500 #define WM_MC_TABSIZE 128 501 #define WM_VLAN_TABSIZE 128 502 503 #define WMREG_PBA 0x1000 /* Packet Buffer Allocation */ 504 505 #define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */ 506 #define TXDMAC_DPP (1U << 0) /* disable packet prefetch */ 507 508 #define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum 509 Threshold (Cordova) */ 510 #define TSPMT_TSMT(x) (x) /* TCP seg min transfer */ 511 #define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */ 512 513 #define WMREG_RXCSUM 0x5000 /* Receive Checksum register */ 514 #define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */ 515 #define RXCSUM_IPOFL (1U << 8) /* IP checksum offload */ 516 #define RXCSUM_TUOFL (1U << 9) /* TCP/UDP checksum offload */ 517
Indexes created Sun Oct 19 21:10:07 GMT 2025