if_wmreg.h revision 1.52
1 /* $NetBSD: if_wmreg.h,v 1.52 2013/04/21 19:59:41 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Register description for the Intel i82542 (``Wiseman''), 40 * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit 41 * Ethernet chips. 42 */ 43 44 /* 45 * The wiseman supports 64-bit PCI addressing. This structure 46 * describes the address in descriptors. 47 */ 48 typedef struct wiseman_addr { 49 uint32_t wa_low; /* low-order 32 bits */ 50 uint32_t wa_high; /* high-order 32 bits */ 51 } __packed wiseman_addr_t; 52 53 /* 54 * The Wiseman receive descriptor. 55 * 56 * The receive descriptor ring must be aligned to a 4K boundary, 57 * and there must be an even multiple of 8 descriptors in the ring. 58 */ 59 typedef struct wiseman_rxdesc { 60 volatile wiseman_addr_t wrx_addr; /* buffer address */ 61 62 volatile uint16_t wrx_len; /* buffer length */ 63 volatile uint16_t wrx_cksum; /* checksum (starting at PCSS)*/ 64 65 volatile uint8_t wrx_status; /* Rx status */ 66 volatile uint8_t wrx_errors; /* Rx errors */ 67 volatile uint16_t wrx_special; /* special field (VLAN, etc.) */ 68 } __packed wiseman_rxdesc_t; 69 70 /* wrx_status bits */ 71 #define WRX_ST_DD (1U << 0) /* descriptor done */ 72 #define WRX_ST_EOP (1U << 1) /* end of packet */ 73 #define WRX_ST_IXSM (1U << 2) /* ignore checksum indication */ 74 #define WRX_ST_VP (1U << 3) /* VLAN packet */ 75 #define WRX_ST_BPDU (1U << 4) /* ??? */ 76 #define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */ 77 #define WRX_ST_IPCS (1U << 6) /* IP checksum performed */ 78 #define WRX_ST_PIF (1U << 7) /* passed in-exact filter */ 79 80 /* wrx_error bits */ 81 #define WRX_ER_CE (1U << 0) /* CRC error */ 82 #define WRX_ER_SE (1U << 1) /* symbol error */ 83 #define WRX_ER_SEQ (1U << 2) /* sequence error */ 84 #define WRX_ER_ICE (1U << 3) /* ??? */ 85 #define WRX_ER_CXE (1U << 4) /* carrier extension error */ 86 #define WRX_ER_TCPE (1U << 5) /* TCP checksum error */ 87 #define WRX_ER_IPE (1U << 6) /* IP checksum error */ 88 #define WRX_ER_RXE (1U << 7) /* Rx data error */ 89 90 /* wrx_special field for VLAN packets */ 91 #define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */ 92 #define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */ 93 #define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */ 94 95 /* 96 * The Wiseman transmit descriptor. 97 * 98 * The transmit descriptor ring must be aligned to a 4K boundary, 99 * and there must be an even multiple of 8 descriptors in the ring. 100 */ 101 typedef struct wiseman_tx_fields { 102 uint8_t wtxu_status; /* Tx status */ 103 uint8_t wtxu_options; /* options */ 104 uint16_t wtxu_vlan; /* VLAN info */ 105 } __packed wiseman_txfields_t; 106 typedef struct wiseman_txdesc { 107 wiseman_addr_t wtx_addr; /* buffer address */ 108 uint32_t wtx_cmdlen; /* command and length */ 109 wiseman_txfields_t wtx_fields; /* fields; see below */ 110 } __packed wiseman_txdesc_t; 111 112 /* Commands for wtx_cmdlen */ 113 #define WTX_CMD_EOP (1U << 24) /* end of packet */ 114 #define WTX_CMD_IFCS (1U << 25) /* insert FCS */ 115 #define WTX_CMD_RS (1U << 27) /* report status */ 116 #define WTX_CMD_RPS (1U << 28) /* report packet sent */ 117 #define WTX_CMD_DEXT (1U << 29) /* descriptor extension */ 118 #define WTX_CMD_VLE (1U << 30) /* VLAN enable */ 119 #define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */ 120 121 /* Descriptor types (if DEXT is set) */ 122 #define WTX_DTYP_C (0U << 20) /* context */ 123 #define WTX_DTYP_D (1U << 20) /* data */ 124 125 /* wtx_fields status bits */ 126 #define WTX_ST_DD (1U << 0) /* descriptor done */ 127 #define WTX_ST_EC (1U << 1) /* excessive collisions */ 128 #define WTX_ST_LC (1U << 2) /* late collision */ 129 #define WTX_ST_TU (1U << 3) /* transmit underrun */ 130 131 /* wtx_fields option bits for IP/TCP/UDP checksum offload */ 132 #define WTX_IXSM (1U << 0) /* IP checksum offload */ 133 #define WTX_TXSM (1U << 1) /* TCP/UDP checksum offload */ 134 135 /* Maximum payload per Tx descriptor */ 136 #define WTX_MAX_LEN 4096 137 138 /* 139 * The Livengood TCP/IP context descriptor. 140 */ 141 struct livengood_tcpip_ctxdesc { 142 uint32_t tcpip_ipcs; /* IP checksum context */ 143 uint32_t tcpip_tucs; /* TCP/UDP checksum context */ 144 uint32_t tcpip_cmdlen; 145 uint32_t tcpip_seg; /* TCP segmentation context */ 146 }; 147 148 /* commands for context descriptors */ 149 #define WTX_TCPIP_CMD_TCP (1U << 24) /* 1 = TCP, 0 = UDP */ 150 #define WTX_TCPIP_CMD_IP (1U << 25) /* 1 = IPv4, 0 = IPv6 */ 151 #define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */ 152 153 #define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */ 154 #define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */ 155 #define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */ 156 157 #define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */ 158 #define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */ 159 #define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */ 160 161 #define WTX_TCPIP_SEG_STATUS(x) ((x) << 0) 162 #define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8) 163 #define WTX_TCPIP_SEG_MSS(x) ((x) << 16) 164 165 /* 166 * PCI config registers used by the Wiseman. 167 */ 168 #define WM_PCI_MMBA PCI_MAPREG_START 169 /* registers for FLASH access on ICH8 */ 170 #define WM_ICH8_FLASH 0x0014 171 172 /* 173 * Wiseman Control/Status Registers. 174 */ 175 #define WMREG_CTRL 0x0000 /* Device Control Register */ 176 #define CTRL_FD (1U << 0) /* full duplex */ 177 #define CTRL_BEM (1U << 1) /* big-endian mode */ 178 #define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */ 179 #define CTRL_LRST (1U << 3) /* link reset */ 180 #define CTRL_GIO_M_DIS (1U << 3) /* disabl PCI master access */ 181 #define CTRL_ASDE (1U << 5) /* auto speed detect enable */ 182 #define CTRL_SLU (1U << 6) /* set link up */ 183 #define CTRL_ILOS (1U << 7) /* invert loss of signal */ 184 #define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */ 185 #define CTRL_SPEED_10 CTRL_SPEED(0) 186 #define CTRL_SPEED_100 CTRL_SPEED(1) 187 #define CTRL_SPEED_1000 CTRL_SPEED(2) 188 #define CTRL_SPEED_MASK CTRL_SPEED(3) 189 #define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */ 190 #define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */ 191 #define CTRL_D_UD_EN (1U << 13) /* Dock/Undock enable */ 192 #define CTRL_D_UD_POL (1U << 14) /* Defined polarity of Dock/Undock indication in SDP[0] */ 193 #define CTRL_F_PHY_R (1U << 15) /* Reset both PHY ports, through PHYRST_N pin */ 194 #define CTRL_EXT_LINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */ 195 #define CTRL_LANPHYPC_OVERRIDE (1U << 16) /* SW control of LANPHYPC */ 196 #define CTRL_LANPHYPC_VALUE (1U << 17) /* SW value of LANPHYPC */ 197 #define CTRL_SWDPINS_SHIFT 18 198 #define CTRL_SWDPINS_MASK 0x0f 199 #define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x))) 200 #define CTRL_SWDPIO_SHIFT 22 201 #define CTRL_SWDPIO_MASK 0x0f 202 #define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x))) 203 #define CTRL_RST (1U << 26) /* device reset */ 204 #define CTRL_RFCE (1U << 27) /* Rx flow control enable */ 205 #define CTRL_TFCE (1U << 28) /* Tx flow control enable */ 206 #define CTRL_VME (1U << 30) /* VLAN Mode Enable */ 207 #define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */ 208 209 #define WMREG_CTRL_SHADOW 0x0004 /* Device Control Register (shadow) */ 210 211 #define WMREG_STATUS 0x0008 /* Device Status Register */ 212 #define STATUS_FD (1U << 0) /* full duplex */ 213 #define STATUS_LU (1U << 1) /* link up */ 214 #define STATUS_TCKOK (1U << 2) /* Tx clock running */ 215 #define STATUS_RBCOK (1U << 3) /* Rx clock running */ 216 #define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */ 217 #define STATUS_FUNCID_MASK 3 /* ... */ 218 #define STATUS_TXOFF (1U << 4) /* Tx paused */ 219 #define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */ 220 #define STATUS_SPEED(x) ((x) << 6) /* speed indication */ 221 #define STATUS_SPEED_10 STATUS_SPEED(0) 222 #define STATUS_SPEED_100 STATUS_SPEED(1) 223 #define STATUS_SPEED_1000 STATUS_SPEED(2) 224 #define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */ 225 #define STATUS_LAN_INIT_DONE (1U << 9) /* Lan Init Completion by NVM */ 226 #define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */ 227 #define STATUS_PHYRA (1U << 10) /* PHY Reset Asserted (PCH) */ 228 #define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */ 229 #define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */ 230 #define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */ 231 #define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */ 232 #define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0) 233 #define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1) 234 #define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2) 235 #define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3) 236 #define STATUS_GIO_M_ENA (1U << 19) /* GIO master enable */ 237 #define STATUS_DEV_RST_SET (1U << 20) /* Device Reset Set */ 238 239 #define WMREG_EECD 0x0010 /* EEPROM Control Register */ 240 #define EECD_SK (1U << 0) /* clock */ 241 #define EECD_CS (1U << 1) /* chip select */ 242 #define EECD_DI (1U << 2) /* data in */ 243 #define EECD_DO (1U << 3) /* data out */ 244 #define EECD_FWE(x) ((x) << 4) /* flash write enable control */ 245 #define EECD_FWE_DISABLED EECD_FWE(1) 246 #define EECD_FWE_ENABLED EECD_FWE(2) 247 #define EECD_EE_REQ (1U << 6) /* (shared) EEPROM request */ 248 #define EECD_EE_GNT (1U << 7) /* (shared) EEPROM grant */ 249 #define EECD_EE_PRES (1U << 8) /* EEPROM present */ 250 #define EECD_EE_SIZE (1U << 9) /* EEPROM size 251 (0 = 64 word, 1 = 256 word) */ 252 #define EECD_EE_AUTORD (1U << 9) /* auto read done */ 253 #define EECD_EE_ABITS (1U << 10) /* EEPROM address bits 254 (based on type) */ 255 #define EECD_EE_TYPE (1U << 13) /* EEPROM type 256 (0 = Microwire, 1 = SPI) */ 257 #define EECD_SEC1VAL (1U << 22) /* Sector One Valid */ 258 #define EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */ 259 260 #define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */ 261 #define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */ 262 #define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */ 263 264 #define SPI_OPC_WRITE 0x02 /* SPI "write" opcode */ 265 #define SPI_OPC_READ 0x03 /* SPI "read" opcode */ 266 #define SPI_OPC_A8 0x08 /* opcode bit 3 == address bit 8 */ 267 #define SPI_OPC_WREN 0x06 /* SPI "set write enable" opcode */ 268 #define SPI_OPC_WRDI 0x04 /* SPI "clear write enable" opcode */ 269 #define SPI_OPC_RDSR 0x05 /* SPI "read status" opcode */ 270 #define SPI_OPC_WRSR 0x01 /* SPI "write status" opcode */ 271 #define SPI_MAX_RETRIES 5000 /* max wait of 5ms for RDY signal */ 272 273 #define SPI_SR_RDY 0x01 274 #define SPI_SR_WEN 0x02 275 #define SPI_SR_BP0 0x04 276 #define SPI_SR_BP1 0x08 277 #define SPI_SR_WPEN 0x80 278 279 #define EEPROM_OFF_MACADDR 0x00 /* MAC address offset */ 280 #define EEPROM_OFF_CFG1 0x0a /* config word 1 */ 281 #define EEPROM_OFF_CFG2 0x0f /* config word 2 */ 282 #define EEPROM_OFF_CFG3_PORTB 0x14 /* config word 3 */ 283 #define EEPROM_INIT_3GIO_3 0x1a /* PCIe Initial Configuration Word 3 */ 284 #define EEPROM_OFF_K1_CONFIG 0x1b /* NVM K1 Config */ 285 #define EEPROM_OFF_SWDPIN 0x20 /* SWD Pins (Cordova) */ 286 #define EEPROM_OFF_CFG3_PORTA 0x24 /* config word 3 */ 287 #define EEPROM_ALT_MAC_ADDR_PTR 0x37 /* to the alternative MAC addresses */ 288 289 #define EEPROM_CFG1_LVDID (1U << 0) 290 #define EEPROM_CFG1_LSSID (1U << 1) 291 #define EEPROM_CFG1_PME_CLOCK (1U << 2) 292 #define EEPROM_CFG1_PM (1U << 3) 293 #define EEPROM_CFG1_ILOS (1U << 4) 294 #define EEPROM_CFG1_SWDPIO_SHIFT 5 295 #define EEPROM_CFG1_SWDPIO_MASK (0xf << EEPROM_CFG1_SWDPIO_SHIFT) 296 #define EEPROM_CFG1_IPS1 (1U << 8) 297 #define EEPROM_CFG1_LRST (1U << 9) 298 #define EEPROM_CFG1_FD (1U << 10) 299 #define EEPROM_CFG1_FRCSPD (1U << 11) 300 #define EEPROM_CFG1_IPS0 (1U << 12) 301 #define EEPROM_CFG1_64_32_BAR (1U << 13) 302 303 #define EEPROM_CFG2_CSR_RD_SPLIT (1U << 1) 304 #define EEPROM_CFG2_82544_APM_EN (1U << 2) 305 #define EEPROM_CFG2_64_BIT (1U << 3) 306 #define EEPROM_CFG2_MAX_READ (1U << 4) 307 #define EEPROM_CFG2_DMCR_MAP (1U << 5) 308 #define EEPROM_CFG2_133_CAP (1U << 6) 309 #define EEPROM_CFG2_MSI_DIS (1U << 7) 310 #define EEPROM_CFG2_FLASH_DIS (1U << 8) 311 #define EEPROM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9) 312 #define EEPROM_CFG2_APM_EN (1U << 10) 313 #define EEPROM_CFG2_ANE (1U << 11) 314 #define EEPROM_CFG2_PAUSE(x) (((x) & 3) >> 12) 315 #define EEPROM_CFG2_ASDE (1U << 14) 316 #define EEPROM_CFG2_APM_PME (1U << 15) 317 #define EEPROM_CFG2_SWDPIO_SHIFT 4 318 #define EEPROM_CFG2_SWDPIO_MASK (0xf << EEPROM_CFG2_SWDPIO_SHIFT) 319 #define EEPROM_CFG2_MNGM_MASK (3U << 13) /* Manageability Operation mode */ 320 321 #define EEPROM_K1_CONFIG_ENABLE 0x01 322 323 #define EEPROM_SWDPIN_MASK 0xdf 324 #define EEPROM_SWDPIN_SWDPIN_SHIFT 0 325 #define EEPROM_SWDPIN_SWDPIO_SHIFT 8 326 327 #define EEPROM_3GIO_3_ASPM_MASK (0x3 << 2) /* Active State PM Support */ 328 329 #define EEPROM_CFG3_APME (1U << 10) 330 331 #define EEPROM_OFF_MACADDR_LAN1 3 /* macaddr offset from PTR (port 1) */ 332 #define EEPROM_OFF_MACADDR_LAN2 6 /* macaddr offset from PTR (port 2) */ 333 #define EEPROM_OFF_MACADDR_LAN3 9 /* macaddr offset from PTR (port 3) */ 334 335 /* 336 * EEPROM Partitioning. See Table 6-1, "EEPROM Top Level Partitioning" 337 * in 82580's datasheet. 338 */ 339 #define EEPROM_OFF_LAN1 0x0080 /* Offset for LAN1 (82580)*/ 340 #define EEPROM_OFF_LAN2 0x00c0 /* Offset for LAN2 (82580)*/ 341 #define EEPROM_OFF_LAN3 0x0100 /* Offset for LAN3 (82580)*/ 342 343 #define WMREG_EERD 0x0014 /* EEPROM read */ 344 #define EERD_DONE 0x02 /* done bit */ 345 #define EERD_START 0x01 /* First bit for telling part to start operation */ 346 #define EERD_ADDR_SHIFT 2 /* Shift to the address bits */ 347 #define EERD_DATA_SHIFT 16 /* Offset to data in EEPROM read/write registers */ 348 349 #define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */ 350 #define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */ 351 #define CTRL_EXT_SWDPINS_SHIFT 4 352 #define CTRL_EXT_SWDPINS_MASK 0x0d 353 /* The bit order of the SW Definable pin is not 6543 but 3654! */ 354 #define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT \ 355 + ((x) == 3 ? 3 : ((x) - 4)))) 356 #define CTRL_EXT_SWDPIO_SHIFT 8 357 #define CTRL_EXT_SWDPIO_MASK 0x0d 358 #define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT \ 359 + ((x) == 3 ? 3 : ((x) - 4)))) 360 #define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */ 361 #define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */ 362 #define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */ 363 #define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */ 364 #define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */ 365 #define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */ 366 #define CTRL_EXT_LINK_MODE_MASK 0x00C00000 367 #define CTRL_EXT_LINK_MODE_GMII 0x00000000 368 #define CTRL_EXT_LINK_MODE_KMRN 0x00000000 369 #define CTRL_EXT_LINK_MODE_1000KX 0x00400000 370 #define CTRL_EXT_LINK_MODE_SGMII 0x00800000 371 #define CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 372 #define CTRL_EXT_LINK_MODE_TBI 0x00C00000 373 #define CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 374 #define CTRL_EXT_PHYPDEN 0x00100000 375 #define CTRL_EXT_I2C_ENA 0x02000000 /* I2C enable */ 376 #define CTRL_EXT_DRV_LOAD 0x10000000 377 378 379 #define WMREG_MDIC 0x0020 /* MDI Control Register */ 380 #define MDIC_DATA(x) ((x) & 0xffff) 381 #define MDIC_REGADD(x) ((x) << 16) 382 #define MDIC_PHYADD(x) ((x) << 21) 383 #define MDIC_OP_WRITE (1U << 26) 384 #define MDIC_OP_READ (2U << 26) 385 #define MDIC_READY (1U << 28) 386 #define MDIC_I (1U << 29) /* interrupt on MDI complete */ 387 #define MDIC_E (1U << 30) /* MDI error */ 388 389 #define WMREG_SCTL 0x0024 /* SerDes Control - RW */ 390 /* 391 * These 4 macros are also used for other 8bit control registers on the 392 * 82575 393 */ 394 #define SCTL_CTL_READY (1U << 31) 395 #define SCTL_CTL_DATA_MASK 0x000000ff 396 #define SCTL_CTL_ADDR_SHIFT 8 397 #define SCTL_CTL_POLL_TIMEOUT 640 398 399 #define WMREG_FCAL 0x0028 /* Flow Control Address Low */ 400 #define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */ 401 402 #define WMREG_FCAH 0x002c /* Flow Control Address High */ 403 #define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */ 404 405 #define WMREG_FCT 0x0030 /* Flow Control Type */ 406 407 #define WMREG_VET 0x0038 /* VLAN Ethertype */ 408 409 #define WMREG_RAL_BASE 0x0040 /* Receive Address List */ 410 #define WMREG_CORDOVA_RAL_BASE 0x5400 411 #define WMREG_RAL_LO(b, x) ((b) + ((x) << 3)) 412 #define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4) 413 /* 414 * Receive Address List: The LO part is the low-order 32-bits 415 * of the MAC address. The HI part is the high-order 16-bits 416 * along with a few control bits. 417 */ 418 #define RAL_AS(x) ((x) << 16) /* address select */ 419 #define RAL_AS_DEST RAL_AS(0) /* (cordova?) */ 420 #define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */ 421 #define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */ 422 #define RAL_AV (1U << 31) /* entry is valid */ 423 424 #define WM_RAL_TABSIZE 15 /* RAL size for old devices */ 425 #define WM_RAL_TABSIZE_ICH8 7 /* RAL size for ICH* and PCH* */ 426 #define WM_RAL_TABSIZE_82575 16 /* RAL size for 82575 */ 427 #define WM_RAL_TABSIZE_82576 24 /* RAL size for 82576 and 82580 */ 428 #define WM_RAL_TABSIZE_I350 32 /* RAL size for I350 */ 429 430 #define WMREG_ICR 0x00c0 /* Interrupt Cause Register */ 431 #define ICR_TXDW (1U << 0) /* Tx desc written back */ 432 #define ICR_TXQE (1U << 1) /* Tx queue empty */ 433 #define ICR_LSC (1U << 2) /* link status change */ 434 #define ICR_RXSEQ (1U << 3) /* receive sequence error */ 435 #define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */ 436 #define ICR_RXO (1U << 6) /* Rx overrun */ 437 #define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */ 438 #define ICR_MDAC (1U << 9) /* MDIO access complete */ 439 #define ICR_RXCFG (1U << 10) /* Receiving /C/ */ 440 #define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */ 441 #define ICR_INT (1U << 31) /* device generated an interrupt */ 442 443 #define WMREG_ITR 0x00c4 /* Interrupt Throttling Register */ 444 #define ITR_IVAL_MASK 0xffff /* Interval mask */ 445 #define ITR_IVAL_SHIFT 0 /* Interval shift */ 446 447 #define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */ 448 /* See ICR bits. */ 449 450 #define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */ 451 /* See ICR bits. */ 452 453 #define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */ 454 /* See ICR bits. */ 455 456 #define WMREG_RCTL 0x0100 /* Receive Control */ 457 #define RCTL_EN (1U << 1) /* receiver enable */ 458 #define RCTL_SBP (1U << 2) /* store bad packets */ 459 #define RCTL_UPE (1U << 3) /* unicast promisc. enable */ 460 #define RCTL_MPE (1U << 4) /* multicast promisc. enable */ 461 #define RCTL_LPE (1U << 5) /* large packet enable */ 462 #define RCTL_LBM(x) ((x) << 6) /* loopback mode */ 463 #define RCTL_LBM_NONE RCTL_LBM(0) 464 #define RCTL_LBM_PHY RCTL_LBM(3) 465 #define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */ 466 #define RCTL_RDMTS_1_2 RCTL_RDMTS(0) 467 #define RCTL_RDMTS_1_4 RCTL_RDMTS(1) 468 #define RCTL_RDMTS_1_8 RCTL_RDMTS(2) 469 #define RCTL_RDMTS_MASK RCTL_RDMTS(3) 470 #define RCTL_MO(x) ((x) << 12) /* multicast offset */ 471 #define RCTL_BAM (1U << 15) /* broadcast accept mode */ 472 #define RCTL_2k (0 << 16) /* 2k Rx buffers */ 473 #define RCTL_1k (1 << 16) /* 1k Rx buffers */ 474 #define RCTL_512 (2 << 16) /* 512 byte Rx buffers */ 475 #define RCTL_256 (3 << 16) /* 256 byte Rx buffers */ 476 #define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */ 477 #define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */ 478 #define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */ 479 #define RCTL_DPF (1U << 22) /* discard pause frames */ 480 #define RCTL_PMCF (1U << 23) /* pass MAC control frames */ 481 #define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */ 482 #define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */ 483 484 #define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */ 485 #define WMREG_RDTR 0x2820 486 #define RDTR_FPD (1U << 31) /* flush partial descriptor */ 487 488 #define WMREG_RADV 0x282c /* Receive Interrupt Absolute Delay Timer */ 489 490 #define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */ 491 #define WMREG_RDBAL 0x2800 492 #define WMREG_RDBAL_2 0x0c00 /* for 82576 ... */ 493 494 #define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */ 495 #define WMREG_RDBAH 0x2804 496 #define WMREG_RDBAH_2 0x0c04 /* for 82576 ... */ 497 498 #define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */ 499 #define WMREG_RDLEN 0x2808 500 #define WMREG_RDLEN_2 0x0c08 /* for 82576 ... */ 501 502 #define WMREG_SRRCTL 0x280c /* additional recieve control used in 82575 ... */ 503 #define WMREG_SRRCTL_2 0x0c0c /* for 82576 ... */ 504 #define SRRCTL_BSIZEPKT_MASK 0x0000007f 505 #define SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 506 #define SRRCTL_BSIZEHDRSIZE_MASK 0x00000f00 507 #define SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 508 #define SRRCTL_DESCTYPE_LEGACY 0x00000000 509 #define SRRCTL_DESCTYPE_ADV_ONEBUF (1U << 25) 510 #define SRRCTL_DESCTYPE_HDR_SPLIT (2U << 25) 511 #define SRRCTL_DESCTYPE_HDR_REPLICATION (3U << 25) 512 #define SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT (4U << 25) 513 #define SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS (5U << 25) /* 82575 only */ 514 #define SRRCTL_DESCTYPE_MASK (7U << 25) 515 #define SRRCTL_DROP_EN 0x80000000 516 517 #define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */ 518 #define WMREG_RDH 0x2810 519 #define WMREG_RDH_2 0x0c10 /* for 82576 ... */ 520 521 #define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */ 522 #define WMREG_RDT 0x2818 523 #define WMREG_RDT_2 0x0c18 /* for 82576 ... */ 524 525 #define WMREG_RXDCTL 0x2828 /* Receive Descriptor Control */ 526 #define WMREG_RXDCTL_2 0x0c28 /* for 82576 ... */ 527 #define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 528 #define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 529 #define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 530 #define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */ 531 /* flags used starting with 82575 ... */ 532 #define RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 533 #define RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ 534 535 #define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */ 536 537 #define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */ 538 539 #define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */ 540 541 #define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */ 542 543 #define WMREG_OLD_RDH1 0x0148 544 545 #define WMREG_OLD_RDT1 0x0150 546 547 #define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */ 548 #define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */ 549 #define FCRTH_DFLT 0x00008000 550 551 #define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */ 552 #define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */ 553 #define FCRTL_DFLT 0x00004000 554 #define FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 555 556 #define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */ 557 #define FCTTV_DFLT 0x00000600 558 559 #define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */ 560 /* See MII ANAR_X bits. */ 561 #define TXCW_SYM_PAUSE (1U << 7) /* sym pause request */ 562 #define TXCW_ASYM_PAUSE (1U << 8) /* asym pause request */ 563 #define TXCW_TxConfig (1U << 30) /* Tx Config */ 564 #define TXCW_ANE (1U << 31) /* Autonegotiate */ 565 566 #define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */ 567 /* See MII ANLPAR_X bits. */ 568 #define RXCW_NC (1U << 26) /* no carrier */ 569 #define RXCW_IV (1U << 27) /* config invalid */ 570 #define RXCW_CC (1U << 28) /* config change */ 571 #define RXCW_C (1U << 29) /* /C/ reception */ 572 #define RXCW_SYNCH (1U << 30) /* synchronized */ 573 #define RXCW_ANC (1U << 31) /* autonegotiation complete */ 574 575 #define WMREG_MTA 0x0200 /* Multicast Table Array */ 576 #define WMREG_CORDOVA_MTA 0x5200 577 578 #define WMREG_TCTL 0x0400 /* Transmit Control Register */ 579 #define TCTL_EN (1U << 1) /* transmitter enable */ 580 #define TCTL_PSP (1U << 3) /* pad short packets */ 581 #define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */ 582 #define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */ 583 #define TCTL_SWXOFF (1U << 22) /* software XOFF */ 584 #define TCTL_RTLC (1U << 24) /* retransmit on late collision */ 585 #define TCTL_NRTU (1U << 25) /* no retransmit on underrun */ 586 #define TCTL_MULR (1U << 28) /* multiple request */ 587 588 #define TX_COLLISION_THRESHOLD 15 589 #define TX_COLLISION_DISTANCE_HDX 512 590 #define TX_COLLISION_DISTANCE_FDX 64 591 592 #define WMREG_TCTL_EXT 0x0404 /* Transmit Control Register */ 593 #define TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 594 #define TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 595 596 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 597 598 #define WMREG_TQSA_LO 0x0408 599 600 #define WMREG_TQSA_HI 0x040c 601 602 #define WMREG_TIPG 0x0410 /* Transmit IPG Register */ 603 #define TIPG_IPGT(x) (x) /* IPG transmit time */ 604 #define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */ 605 #define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */ 606 607 #define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a)) 608 #define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 609 #define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 610 #define TIPG_1000T_80003_DFLT \ 611 (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) 612 #define TIPG_10_100_80003_DFLT \ 613 (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) 614 615 #define WMREG_TQC 0x0418 616 617 #define WMREG_EEWR 0x102c /* EEPROM write */ 618 619 #define WMREG_RDFH 0x2410 /* Receive Data FIFO Head */ 620 621 #define WMREG_RDFT 0x2418 /* Receive Data FIFO Tail */ 622 623 #define WMREG_RDFHS 0x2420 /* Receive Data FIFO Head Saved */ 624 625 #define WMREG_RDFTS 0x2428 /* Receive Data FIFO Tail Saved */ 626 627 #define WMREG_TDFH 0x3410 /* Transmit Data FIFO Head */ 628 629 #define WMREG_TDFT 0x3418 /* Transmit Data FIFO Tail */ 630 631 #define WMREG_TDFHS 0x3420 /* Transmit Data FIFO Head Saved */ 632 633 #define WMREG_TDFTS 0x3428 /* Transmit Data FIFO Tail Saved */ 634 635 #define WMREG_TDFPC 0x3430 /* Transmit Data FIFO Packet Count */ 636 637 #define WMREG_OLD_TDBAL 0x0420 /* Transmit Descriptor Base Lo */ 638 #define WMREG_TDBAL 0x3800 639 640 #define WMREG_OLD_TDBAH 0x0424 /* Transmit Descriptor Base Hi */ 641 #define WMREG_TDBAH 0x3804 642 643 #define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */ 644 #define WMREG_TDLEN 0x3808 645 646 #define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */ 647 #define WMREG_TDH 0x3810 648 649 #define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */ 650 #define WMREG_TDT 0x3818 651 652 #define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */ 653 #define WMREG_TIDV 0x3820 654 655 #define WMREG_TXDCTL 0x3828 /* Trandmit Descriptor Control */ 656 #define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 657 #define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 658 #define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 659 /* flags used starting with 82575 ... */ 660 #define TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 661 #define TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 662 #define TXDCTL_PRIORITY 0x08000000 663 664 #define WMREG_TADV 0x382c /* Transmit Absolute Interrupt Delay Timer */ 665 666 #define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */ 667 668 #define WMREG_VFTA 0x0600 669 670 #define WM_MC_TABSIZE 128 671 #define WM_ICH8_MC_TABSIZE 32 672 #define WM_VLAN_TABSIZE 128 673 674 #define WMREG_PBA 0x1000 /* Packet Buffer Allocation */ 675 #define PBA_BYTE_SHIFT 10 /* KB -> bytes */ 676 #define PBA_ADDR_SHIFT 7 /* KB -> quadwords */ 677 #define PBA_8K 0x0008 678 #define PBA_10K 0x000a 679 #define PBA_12K 0x000c 680 #define PBA_16K 0x0010 /* 16K, default Tx allocation */ 681 #define PBA_20K 0x0014 682 #define PBA_22K 0x0016 683 #define PBA_24K 0x0018 684 #define PBA_26K 0x001a 685 #define PBA_30K 0x001e 686 #define PBA_32K 0x0020 687 #define PBA_34K 0x0022 688 #define PBA_35K 0x0023 689 #define PBA_40K 0x0028 690 #define PBA_48K 0x0030 /* 48K, default Rx allocation */ 691 #define PBA_64K 0x0040 692 693 #define WMREG_PBS 0x1008 /* Packet Buffer Size (ICH) */ 694 695 #define WMREG_EEMNGCTL 0x1010 /* MNG EEprom Control */ 696 #define EEMNGCTL_CFGDONE_0 0x040000 /* MNG config cycle done */ 697 #define EEMNGCTL_CFGDONE_1 0x080000 /* 2nd port */ 698 699 #define WMREG_I2CCMD 0x1028 /* SFPI2C Command Register - RW */ 700 #define I2CCMD_REG_ADDR_SHIFT 16 701 #define I2CCMD_REG_ADDR 0x00ff0000 702 #define I2CCMD_PHY_ADDR_SHIFT 24 703 #define I2CCMD_PHY_ADDR 0x07000000 704 #define I2CCMD_OPCODE_READ 0x08000000 705 #define I2CCMD_OPCODE_WRITE 0x00000000 706 #define I2CCMD_RESET 0x10000000 707 #define I2CCMD_READY 0x20000000 708 #define I2CCMD_INTERRUPT_ENA 0x40000000 709 #define I2CCMD_ERROR 0x80000000 710 #define MAX_SGMII_PHY_REG_ADDR 255 711 #define I2CCMD_PHY_TIMEOUT 200 712 713 #define WMREG_EICS 0x01520 /* Ext. Interrupt Cause Set - WO */ 714 #define WMREG_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 715 #define WMREG_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 716 #define WMREG_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 717 #define WMREG_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 718 719 #define WMREG_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 720 721 #define EITR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 722 #define EITR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 723 #define EITR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 724 #define EITR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 725 #define EITR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 726 #define EITR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 727 #define EITR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 728 #define EITR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 729 #define EITR_TCP_TIMER 0x40000000 /* TCP Timer */ 730 #define EITR_OTHER 0x80000000 /* Interrupt Cause Active */ 731 732 #define WMREG_EITR(x) (0x01680 + (0x4 * (x))) 733 #define EITR_ITR_INT_MASK 0x0000ffff 734 735 #define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */ 736 #define TXDMAC_DPP (1U << 0) /* disable packet prefetch */ 737 738 #define WMREG_KABGTXD 0x3004 /* AFE and Gap Transmit Ref Data */ 739 #define KABGTXD_BGSQLBIAS 0x00050000 740 741 #define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum 742 Threshold (Cordova) */ 743 744 #define WMREG_TARC0 0x3840 /* Tx arbitration count */ 745 746 #define TSPMT_TSMT(x) (x) /* TCP seg min transfer */ 747 #define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */ 748 749 #define WMREG_CRCERRS 0x4000 /* CRC Error Count */ 750 #define WMREG_ALGNERRC 0x4004 /* Alignment Error Count */ 751 #define WMREG_SYMERRC 0x4008 /* Symbol Error Count */ 752 #define WMREG_RXERRC 0x400c /* receive error Count - R/clr */ 753 #define WMREG_MPC 0x4010 /* Missed Packets Count - R/clr */ 754 #define WMREG_COLC 0x4028 /* collision Count - R/clr */ 755 #define WMREG_SEC 0x4038 /* Sequence Error Count */ 756 #define WMREG_CEXTERR 0x403c /* Carrier Extension Error Count */ 757 #define WMREG_RLEC 0x4040 /* Receive Length Error Count */ 758 #define WMREG_XONRXC 0x4048 /* XON Rx Count - R/clr */ 759 #define WMREG_XONTXC 0x404c /* XON Tx Count - R/clr */ 760 #define WMREG_XOFFRXC 0x4050 /* XOFF Rx Count - R/clr */ 761 #define WMREG_XOFFTXC 0x4054 /* XOFF Tx Count - R/clr */ 762 #define WMREG_FCRUC 0x4058 /* Flow Control Rx Unsupported Count - R/clr */ 763 #define WMREG_RNBC 0x40a0 /* Receive No Buffers Count */ 764 765 #define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */ 766 #define KUMCTRLSTA_MASK 0x0000FFFF 767 #define KUMCTRLSTA_OFFSET 0x001F0000 768 #define KUMCTRLSTA_OFFSET_SHIFT 16 769 #define KUMCTRLSTA_REN 0x00200000 770 771 #define KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 772 #define KUMCTRLSTA_OFFSET_CTRL 0x00000001 773 #define KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 774 #define KUMCTRLSTA_OFFSET_DIAG 0x00000003 775 #define KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 776 #define KUMCTRLSTA_OFFSET_K1_CONFIG 0x00000007 777 #define KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 778 #define KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 779 #define KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E 780 #define KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F 781 782 /* FIFO Control */ 783 #define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 784 #define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 785 786 /* In-Band Control */ 787 #define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500 788 #define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 789 790 /* Diag */ 791 #define KUMCTRLSTA_DIAG_NELPBK 0x1000 792 793 /* K1 Config */ 794 #define KUMCTRLSTA_K1_ENABLE 0x0002 795 796 /* Half-Duplex Control */ 797 #define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 798 #define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 799 800 #define WMREG_MDPHYA 0x003C /* PHY address - RW */ 801 802 #define WMREG_RXCSUM 0x5000 /* Receive Checksum register */ 803 #define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */ 804 #define RXCSUM_IPOFL (1U << 8) /* IP checksum offload */ 805 #define RXCSUM_TUOFL (1U << 9) /* TCP/UDP checksum offload */ 806 #define RXCSUM_IPV6OFL (1U << 10) /* IPv6 checksum offload */ 807 808 #define WMREG_RLPML 0x5004 /* Rx Long Packet Max Length */ 809 810 #define WMREG_WUC 0x5800 /* Wakeup Control */ 811 #define WUC_APME 0x00000001 /* APM Enable */ 812 #define WUC_PME_EN 0x00000002 /* PME Enable */ 813 814 #define WMREG_WUFC 0x5808 /* Wakeup Filter COntrol */ 815 #define WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 816 #define WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 817 #define WUFC_MC 0x00000008 /* Directed Multicast Wakeup En */ 818 #define WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 819 #define WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup En */ 820 #define WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup En */ 821 #define WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup En */ 822 823 #define WMREG_MANC 0x5820 /* Management Control */ 824 #define MANC_SMBUS_EN 0x00000001 825 #define MANC_ASF_EN 0x00000002 826 #define MANC_ARP_EN 0x00002000 827 #define MANC_RECV_TCO_EN 0x00020000 828 #define MANC_BLK_PHY_RST_ON_IDE 0x00040000 829 #define MANC_EN_MAC_ADDR_FILTER 0x00100000 830 #define MANC_EN_MNG2HOST 0x00200000 831 832 #define WMREG_MANC2H 0x5860 /* Manaegment Control To Host - RW */ 833 #define MANC2H_PORT_623 (1 << 5) 834 #define MANC2H_PORT_624 (1 << 6) 835 836 #define WMREG_GCR 0x5b00 /* PCIe Control */ 837 #define GCR_RXD_NO_SNOOP 0x00000001 838 #define GCR_RXDSCW_NO_SNOOP 0x00000002 839 #define GCR_RXDSCR_NO_SNOOP 0x00000004 840 #define GCR_TXD_NO_SNOOP 0x00000008 841 #define GCR_TXDSCW_NO_SNOOP 0x00000010 842 #define GCR_TXDSCR_NO_SNOOP 0x00000020 843 #define GCR_CMPL_TMOUT_MASK 0x0000f000 844 #define GCR_CMPL_TMOUT_10MS 0x00001000 845 #define GCR_CMPL_TMOUT_RESEND 0x00010000 846 #define GCR_CAP_VER2 0x00040000 847 848 #define WMREG_FACTPS 0x5b30 /* Function Active and Power State to MNG */ 849 #define FACTPS_MNGCG 0x20000000 850 #define FACTPS_LFS 0x40000000 /* LAN Function Select */ 851 852 #define WMREG_GIOCTL 0x5b44 /* GIO Analog Control Register */ 853 #define WMREG_CCMCTL 0x5b48 /* CCM Control Register */ 854 #define WMREG_SCCTL 0x5b4c /* PCIc PLL Configuration Register */ 855 856 #define WMREG_SWSM 0x5b50 /* SW Semaphore */ 857 #define SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 858 #define SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 859 #define SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 860 #define SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 861 862 #define WMREG_FWSM 0x5b54 /* FW Semaphore */ 863 #define FWSM_MODE_MASK 0xe 864 #define FWSM_MODE_SHIFT 0x1 865 #define MNG_ICH_IAMT_MODE 0x2 /* PT mode? */ 866 #define MNG_IAMT_MODE 0x3 867 #define FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ 868 #define FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 869 870 #define WMREG_SW_FW_SYNC 0x5b5c /* software-firmware semaphore */ 871 #define SWFW_EEP_SM 0x0001 /* eeprom access */ 872 #define SWFW_PHY0_SM 0x0002 /* first ctrl phy access */ 873 #define SWFW_PHY1_SM 0x0004 /* second ctrl phy access */ 874 #define SWFW_MAC_CSR_SM 0x0008 875 #define SWFW_PHY2_SM 0x0020 /* first ctrl phy access */ 876 #define SWFW_PHY3_SM 0x0040 /* first ctrl phy access */ 877 #define SWFW_SOFT_SHIFT 0 /* software semaphores */ 878 #define SWFW_FIRM_SHIFT 16 /* firmware semaphores */ 879 880 #define WMREG_CRC_OFFSET 0x5f50 881 882 #define WMREG_EXTCNFCTR 0x0f00 /* Extended Configuration Control */ 883 #define EXTCNFCTR_PCIE_WRITE_ENABLE 0x00000001 884 #define EXTCNFCTR_PHY_WRITE_ENABLE 0x00000002 885 #define EXTCNFCTR_D_UD_ENABLE 0x00000004 886 #define EXTCNFCTR_D_UD_LATENCY 0x00000008 887 #define EXTCNFCTR_D_UD_OWNER 0x00000010 888 #define EXTCNFCTR_MDIO_SW_OWNERSHIP 0x00000020 889 #define EXTCNFCTR_MDIO_HW_OWNERSHIP 0x00000040 890 #define EXTCNFCTR_GATE_PHY_CFG 0x00000080 891 #define EXTCNFCTR_EXT_CNF_POINTER 0x0FFF0000 892 #define E1000_EXTCNF_CTRL_SWFLAG EXTCNFCTR_MDIO_SW_OWNERSHIP 893 894 #define WMREG_PHY_CTRL 0x0f10 /* PHY control */ 895 #define PHY_CTRL_SPD_EN (1 << 0) 896 #define PHY_CTRL_D0A_LPLU (1 << 1) 897 #define PHY_CTRL_NOND0A_LPLU (1 << 2) 898 #define PHY_CTRL_NOND0A_GBE_DIS (1 << 3) 899 #define PHY_CTRL_GBE_DIS (1 << 4) 900 901 /* Energy Efficient Ethernet "EEE" registers */ 902 #define WMREG_LTRC 0x01a0 /* Latency Tolerance Reportiong Control */ 903 #define WMREG_EEER 0x0e30 /* Energy Efficiency Ethernet "EEE" */ 904 #define EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 905 #define EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 906 #define EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 907 #define EEER_EEER_NEG 0x20000000 /* EEER capability nego */ 908 #define EEER_EEER_RX_LPI_STATUS 0x40000000 /* EEER Rx in LPI state */ 909 #define EEER_EEER_TX_LPI_STATUS 0x80000000 /* EEER Tx in LPI state */ 910 #define WMREG_EEE_SU 0x0e34 /* EEE Setup */ 911 #define WMREG_IPCNFG 0x0e38 /* Internal PHY Configuration */ 912 #define IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 913 #define IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 914 #define WMREG_TLPIC 0x4148 /* EEE Tx LPI Count */ 915 #define WMREG_RLPIC 0x414c /* EEE Rx LPI Count */ 916 917 /* ich8 flash control */ 918 #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 919 #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 920 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 921 #define ICH_FLASH_SEG_SIZE_256 256 922 #define ICH_FLASH_SEG_SIZE_4K 4096 923 #define ICH_FLASH_SEG_SIZE_64K 65536 924 925 #define ICH_CYCLE_READ 0x0 926 #define ICH_CYCLE_RESERVED 0x1 927 #define ICH_CYCLE_WRITE 0x2 928 #define ICH_CYCLE_ERASE 0x3 929 930 #define ICH_FLASH_GFPREG 0x0000 931 #define ICH_FLASH_HSFSTS 0x0004 /* Flash Status Register */ 932 #define HSFSTS_DONE 0x0001 /* Flash Cycle Done */ 933 #define HSFSTS_ERR 0x0002 /* Flash Cycle Error */ 934 #define HSFSTS_DAEL 0x0004 /* Direct Access error Log */ 935 #define HSFSTS_ERSZ_MASK 0x0018 /* Block/Sector Erase Size */ 936 #define HSFSTS_ERSZ_SHIFT 3 937 #define HSFSTS_FLINPRO 0x0020 /* flash SPI cycle in Progress */ 938 #define HSFSTS_FLDVAL 0x4000 /* Flash Descriptor Valid */ 939 #define HSFSTS_FLLK 0x8000 /* Flash Configuration Lock-Down */ 940 #define ICH_FLASH_HSFCTL 0x0006 /* Flash control Register */ 941 #define HSFCTL_GO 0x0001 /* Flash Cycle Go */ 942 #define HSFCTL_CYCLE_MASK 0x0006 /* Flash Cycle */ 943 #define HSFCTL_CYCLE_SHIFT 1 944 #define HSFCTL_BCOUNT_MASK 0x0300 /* Data Byte Count */ 945 #define HSFCTL_BCOUNT_SHIFT 8 946 #define ICH_FLASH_FADDR 0x0008 947 #define ICH_FLASH_FDATA0 0x0010 948 #define ICH_FLASH_FRACC 0x0050 949 #define ICH_FLASH_FREG0 0x0054 950 #define ICH_FLASH_FREG1 0x0058 951 #define ICH_FLASH_FREG2 0x005C 952 #define ICH_FLASH_FREG3 0x0060 953 #define ICH_FLASH_FPR0 0x0074 954 #define ICH_FLASH_FPR1 0x0078 955 #define ICH_FLASH_SSFSTS 0x0090 956 #define ICH_FLASH_SSFCTL 0x0092 957 #define ICH_FLASH_PREOP 0x0094 958 #define ICH_FLASH_OPTYPE 0x0096 959 #define ICH_FLASH_OPMENU 0x0098 960 961 #define ICH_FLASH_REG_MAPSIZE 0x00A0 962 #define ICH_FLASH_SECTOR_SIZE 4096 963 #define ICH_GFPREG_BASE_MASK 0x1FFF 964 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 965 966 #define ICH_NVM_SIG_WORD 0x13 967 #define ICH_NVM_SIG_MASK 0xc000 968 #define ICH_NVM_VALID_SIG_MASK 0xc0 969 #define ICH_NVM_SIG_VALUE 0x80 970 971 /* for PCI express Capability registers */ 972 #define WM_PCIE_DCSR2_16MS 0x00000005 973 974 /* advanced TX descriptor for 82575 and newer */ 975 typedef union nq_txdesc { 976 struct { 977 uint64_t nqtxd_addr; 978 uint32_t nqtxd_cmdlen; 979 uint32_t nqtxd_fields; 980 } nqtx_data; 981 struct { 982 uint32_t nqtxc_vl_len; 983 uint32_t nqtxc_sn; 984 uint32_t nqtxc_cmd; 985 uint32_t nqtxc_mssidx; 986 } nqrx_ctx; 987 } __packed nq_txdesc_t; 988 989 990 /* Commands for nqtxd_cmdlen and nqtxc_cmd */ 991 #define NQTX_CMD_EOP (1U << 24) /* end of packet */ 992 #define NQTX_CMD_IFCS (1U << 25) /* insert FCS */ 993 #define NQTX_CMD_RS (1U << 27) /* report status */ 994 #define NQTX_CMD_DEXT (1U << 29) /* descriptor extension */ 995 #define NQTX_CMD_VLE (1U << 30) /* VLAN enable */ 996 #define NQTX_CMD_TSE (1U << 31) /* TCP segmentation enable */ 997 998 /* Descriptor types (if DEXT is set) */ 999 #define NQTX_DTYP_C (2U << 20) /* context */ 1000 #define NQTX_DTYP_D (3U << 20) /* data */ 1001 1002 #define NQTXD_FIELDS_IDX_SHIFT 4 /* context index shift */ 1003 #define NQTXD_FIELDS_IDX_MASK 0xf 1004 #define NQTXD_FIELDS_PAYLEN_SHIFT 14 /* payload len shift */ 1005 #define NQTXD_FIELDS_PAYLEN_MASK 0x3ffff 1006 1007 #define NQTXD_FIELDS_IXSM (1U << 8) /* do IP checksum */ 1008 #define NQTXD_FIELDS_TUXSM (1U << 9) /* do TCP/UDP checksum */ 1009 1010 #define NQTXC_VLLEN_IPLEN_SHIFT 0 /* IP header len */ 1011 #define NQTXC_VLLEN_IPLEN_MASK 0x1ff 1012 #define NQTXC_VLLEN_MACLEN_SHIFT 9 /* MAC header len */ 1013 #define NQTXC_VLLEN_MACLEN_MASK 0x7f 1014 #define NQTXC_VLLEN_VLAN_SHIFT 16 /* vlan number */ 1015 #define NQTXC_VLLEN_VLAN_MASK 0xffff 1016 1017 #define NQTXC_CMD_MKRLOC_SHIFT 0 /* IP checksum offset */ 1018 #define NQTXC_CMD_MKRLOC_MASK 0x1ff 1019 #define NQTXC_CMD_SNAP (1U << 9) 1020 #define NQTXC_CMD_IP4 (1U << 10) 1021 #define NQTXC_CMD_IP6 (0U << 10) 1022 #define NQTXC_CMD_TCP (1U << 11) 1023 #define NQTXC_CMD_UDP (0U << 11) 1024 #define NQTXC_MSSIDX_IDX_SHIFT 4 /* context index shift */ 1025 #define NQTXC_MSSIDX_IDX_MASK 0xf 1026 #define NQTXC_MSSIDX_L4LEN_SHIFT 8 /* L4 header len shift */ 1027 #define NQTXC_MSSIDX_L4LEN_MASK 0xff 1028 #define NQTXC_MSSIDX_MSS_SHIFT 16 /* MSS */ 1029 #define NQTXC_MSSIDX_MSS_MASK 0xffff 1030
Indexes created Mon Oct 20 01:09:56 GMT 2025