if_wmreg.h revision 1.65.2.3
1 /* $NetBSD: if_wmreg.h,v 1.65.2.3 2015/09/22 12:05:59 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /****************************************************************************** 39 40 Copyright (c) 2001-2012, Intel Corporation 41 All rights reserved. 42 43 Redistribution and use in source and binary forms, with or without 44 modification, are permitted provided that the following conditions are met: 45 46 1. Redistributions of source code must retain the above copyright notice, 47 this list of conditions and the following disclaimer. 48 49 2. Redistributions in binary form must reproduce the above copyright 50 notice, this list of conditions and the following disclaimer in the 51 documentation and/or other materials provided with the distribution. 52 53 3. Neither the name of the Intel Corporation nor the names of its 54 contributors may be used to endorse or promote products derived from 55 this software without specific prior written permission. 56 57 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 58 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 61 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 POSSIBILITY OF SUCH DAMAGE. 68 69 ******************************************************************************/ 70 71 /* 72 * Register description for the Intel i82542 (``Wiseman''), 73 * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit 74 * Ethernet chips. 75 */ 76 77 /* 78 * The wiseman supports 64-bit PCI addressing. This structure 79 * describes the address in descriptors. 80 */ 81 typedef struct wiseman_addr { 82 uint32_t wa_low; /* low-order 32 bits */ 83 uint32_t wa_high; /* high-order 32 bits */ 84 } __packed wiseman_addr_t; 85 86 /* 87 * The Wiseman receive descriptor. 88 * 89 * The receive descriptor ring must be aligned to a 4K boundary, 90 * and there must be an even multiple of 8 descriptors in the ring. 91 */ 92 typedef struct wiseman_rxdesc { 93 volatile wiseman_addr_t wrx_addr; /* buffer address */ 94 95 volatile uint16_t wrx_len; /* buffer length */ 96 volatile uint16_t wrx_cksum; /* checksum (starting at PCSS)*/ 97 98 volatile uint8_t wrx_status; /* Rx status */ 99 volatile uint8_t wrx_errors; /* Rx errors */ 100 volatile uint16_t wrx_special; /* special field (VLAN, etc.) */ 101 } __packed wiseman_rxdesc_t; 102 103 /* wrx_status bits */ 104 #define WRX_ST_DD (1U << 0) /* descriptor done */ 105 #define WRX_ST_EOP (1U << 1) /* end of packet */ 106 #define WRX_ST_IXSM (1U << 2) /* ignore checksum indication */ 107 #define WRX_ST_VP (1U << 3) /* VLAN packet */ 108 #define WRX_ST_BPDU (1U << 4) /* ??? */ 109 #define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */ 110 #define WRX_ST_IPCS (1U << 6) /* IP checksum performed */ 111 #define WRX_ST_PIF (1U << 7) /* passed in-exact filter */ 112 113 /* wrx_error bits */ 114 #define WRX_ER_CE (1U << 0) /* CRC error */ 115 #define WRX_ER_SE (1U << 1) /* symbol error */ 116 #define WRX_ER_SEQ (1U << 2) /* sequence error */ 117 #define WRX_ER_ICE (1U << 3) /* ??? */ 118 #define WRX_ER_CXE (1U << 4) /* carrier extension error */ 119 #define WRX_ER_TCPE (1U << 5) /* TCP checksum error */ 120 #define WRX_ER_IPE (1U << 6) /* IP checksum error */ 121 #define WRX_ER_RXE (1U << 7) /* Rx data error */ 122 123 /* wrx_special field for VLAN packets */ 124 #define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */ 125 #define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */ 126 #define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */ 127 128 /* 129 * The Wiseman transmit descriptor. 130 * 131 * The transmit descriptor ring must be aligned to a 4K boundary, 132 * and there must be an even multiple of 8 descriptors in the ring. 133 */ 134 typedef struct wiseman_tx_fields { 135 uint8_t wtxu_status; /* Tx status */ 136 uint8_t wtxu_options; /* options */ 137 uint16_t wtxu_vlan; /* VLAN info */ 138 } __packed wiseman_txfields_t; 139 typedef struct wiseman_txdesc { 140 wiseman_addr_t wtx_addr; /* buffer address */ 141 uint32_t wtx_cmdlen; /* command and length */ 142 wiseman_txfields_t wtx_fields; /* fields; see below */ 143 } __packed wiseman_txdesc_t; 144 145 /* Commands for wtx_cmdlen */ 146 #define WTX_CMD_EOP (1U << 24) /* end of packet */ 147 #define WTX_CMD_IFCS (1U << 25) /* insert FCS */ 148 #define WTX_CMD_RS (1U << 27) /* report status */ 149 #define WTX_CMD_RPS (1U << 28) /* report packet sent */ 150 #define WTX_CMD_DEXT (1U << 29) /* descriptor extension */ 151 #define WTX_CMD_VLE (1U << 30) /* VLAN enable */ 152 #define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */ 153 154 /* Descriptor types (if DEXT is set) */ 155 #define WTX_DTYP_C (0U << 20) /* context */ 156 #define WTX_DTYP_D (1U << 20) /* data */ 157 158 /* wtx_fields status bits */ 159 #define WTX_ST_DD (1U << 0) /* descriptor done */ 160 #define WTX_ST_EC (1U << 1) /* excessive collisions */ 161 #define WTX_ST_LC (1U << 2) /* late collision */ 162 #define WTX_ST_TU (1U << 3) /* transmit underrun */ 163 164 /* wtx_fields option bits for IP/TCP/UDP checksum offload */ 165 #define WTX_IXSM (1U << 0) /* IP checksum offload */ 166 #define WTX_TXSM (1U << 1) /* TCP/UDP checksum offload */ 167 168 /* Maximum payload per Tx descriptor */ 169 #define WTX_MAX_LEN 4096 170 171 /* 172 * The Livengood TCP/IP context descriptor. 173 */ 174 struct livengood_tcpip_ctxdesc { 175 uint32_t tcpip_ipcs; /* IP checksum context */ 176 uint32_t tcpip_tucs; /* TCP/UDP checksum context */ 177 uint32_t tcpip_cmdlen; 178 uint32_t tcpip_seg; /* TCP segmentation context */ 179 }; 180 181 /* commands for context descriptors */ 182 #define WTX_TCPIP_CMD_TCP (1U << 24) /* 1 = TCP, 0 = UDP */ 183 #define WTX_TCPIP_CMD_IP (1U << 25) /* 1 = IPv4, 0 = IPv6 */ 184 #define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */ 185 186 #define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */ 187 #define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */ 188 #define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */ 189 190 #define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */ 191 #define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */ 192 #define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */ 193 194 #define WTX_TCPIP_SEG_STATUS(x) ((x) << 0) 195 #define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8) 196 #define WTX_TCPIP_SEG_MSS(x) ((x) << 16) 197 198 /* 199 * PCI config registers used by the Wiseman. 200 */ 201 #define WM_PCI_MMBA PCI_MAPREG_START 202 /* registers for FLASH access on ICH8 */ 203 #define WM_ICH8_FLASH 0x0014 204 205 /* 206 * Wiseman Control/Status Registers. 207 */ 208 #define WMREG_CTRL 0x0000 /* Device Control Register */ 209 #define CTRL_FD (1U << 0) /* full duplex */ 210 #define CTRL_BEM (1U << 1) /* big-endian mode */ 211 #define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */ 212 #define CTRL_GIO_M_DIS (1U << 2) /* disabl PCI master access */ 213 #define CTRL_LRST (1U << 3) /* link reset */ 214 #define CTRL_ASDE (1U << 5) /* auto speed detect enable */ 215 #define CTRL_SLU (1U << 6) /* set link up */ 216 #define CTRL_ILOS (1U << 7) /* invert loss of signal */ 217 #define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */ 218 #define CTRL_SPEED_10 CTRL_SPEED(0) 219 #define CTRL_SPEED_100 CTRL_SPEED(1) 220 #define CTRL_SPEED_1000 CTRL_SPEED(2) 221 #define CTRL_SPEED_MASK CTRL_SPEED(3) 222 #define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */ 223 #define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */ 224 #define CTRL_D_UD_EN (1U << 13) /* Dock/Undock enable */ 225 #define CTRL_D_UD_POL (1U << 14) /* Defined polarity of Dock/Undock indication in SDP[0] */ 226 #define CTRL_F_PHY_R (1U << 15) /* Reset both PHY ports, through PHYRST_N pin */ 227 #define CTRL_EXT_LINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */ 228 #define CTRL_LANPHYPC_OVERRIDE (1U << 16) /* SW control of LANPHYPC */ 229 #define CTRL_LANPHYPC_VALUE (1U << 17) /* SW value of LANPHYPC */ 230 #define CTRL_SWDPINS_SHIFT 18 231 #define CTRL_SWDPINS_MASK 0x0f 232 #define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x))) 233 #define CTRL_SWDPIO_SHIFT 22 234 #define CTRL_SWDPIO_MASK 0x0f 235 #define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x))) 236 #define CTRL_MEHE (1U << 17) /* Memory Error Handling Enable(I217)*/ 237 #define CTRL_RST (1U << 26) /* device reset */ 238 #define CTRL_RFCE (1U << 27) /* Rx flow control enable */ 239 #define CTRL_TFCE (1U << 28) /* Tx flow control enable */ 240 #define CTRL_VME (1U << 30) /* VLAN Mode Enable */ 241 #define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */ 242 243 #define WMREG_CTRL_SHADOW 0x0004 /* Device Control Register (shadow) */ 244 245 #define WMREG_STATUS 0x0008 /* Device Status Register */ 246 #define STATUS_FD (1U << 0) /* full duplex */ 247 #define STATUS_LU (1U << 1) /* link up */ 248 #define STATUS_TCKOK (1U << 2) /* Tx clock running */ 249 #define STATUS_RBCOK (1U << 3) /* Rx clock running */ 250 #define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */ 251 #define STATUS_FUNCID_MASK 3 /* ... */ 252 #define STATUS_TXOFF (1U << 4) /* Tx paused */ 253 #define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */ 254 #define STATUS_SPEED(x) ((x) << 6) /* speed indication */ 255 #define STATUS_SPEED_10 STATUS_SPEED(0) 256 #define STATUS_SPEED_100 STATUS_SPEED(1) 257 #define STATUS_SPEED_1000 STATUS_SPEED(2) 258 #define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */ 259 #define STATUS_LAN_INIT_DONE (1U << 9) /* Lan Init Completion by NVM */ 260 #define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */ 261 #define STATUS_PHYRA (1U << 10) /* PHY Reset Asserted (PCH) */ 262 #define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */ 263 #define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */ 264 #define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */ 265 #define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */ 266 #define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0) 267 #define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1) 268 #define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2) 269 #define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3) 270 #define STATUS_GIO_M_ENA (1U << 19) /* GIO master enable */ 271 #define STATUS_DEV_RST_SET (1U << 20) /* Device Reset Set */ 272 273 #define WMREG_EECD 0x0010 /* EEPROM Control Register */ 274 #define EECD_SK (1U << 0) /* clock */ 275 #define EECD_CS (1U << 1) /* chip select */ 276 #define EECD_DI (1U << 2) /* data in */ 277 #define EECD_DO (1U << 3) /* data out */ 278 #define EECD_FWE(x) ((x) << 4) /* flash write enable control */ 279 #define EECD_FWE_DISABLED EECD_FWE(1) 280 #define EECD_FWE_ENABLED EECD_FWE(2) 281 #define EECD_EE_REQ (1U << 6) /* (shared) EEPROM request */ 282 #define EECD_EE_GNT (1U << 7) /* (shared) EEPROM grant */ 283 #define EECD_EE_PRES (1U << 8) /* EEPROM present */ 284 #define EECD_EE_SIZE (1U << 9) /* EEPROM size 285 (0 = 64 word, 1 = 256 word) */ 286 #define EECD_EE_AUTORD (1U << 9) /* auto read done */ 287 #define EECD_EE_ABITS (1U << 10) /* EEPROM address bits 288 (based on type) */ 289 #define EECD_EE_SIZE_EX_MASK __BITS(14,11) /* EEPROM size for new devices */ 290 #define EECD_EE_TYPE (1U << 13) /* EEPROM type 291 (0 = Microwire, 1 = SPI) */ 292 #define EECD_SEC1VAL (1U << 22) /* Sector One Valid */ 293 #define EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */ 294 295 #define WMREG_EERD 0x0014 /* EEPROM read */ 296 #define EERD_DONE 0x02 /* done bit */ 297 #define EERD_START 0x01 /* First bit for telling part to start operation */ 298 #define EERD_ADDR_SHIFT 2 /* Shift to the address bits */ 299 #define EERD_DATA_SHIFT 16 /* Offset to data in EEPROM read/write registers */ 300 301 #define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */ 302 #define CTRL_EXT_NSICR __BIT(0) /* Non Interrupt clear on read */ 303 #define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */ 304 #define CTRL_EXT_SWDPINS_SHIFT 4 305 #define CTRL_EXT_SWDPINS_MASK 0x0d 306 /* The bit order of the SW Definable pin is not 6543 but 3654! */ 307 #define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT \ 308 + ((x) == 3 ? 3 : ((x) - 4)))) 309 #define CTRL_EXT_SWDPIO_SHIFT 8 310 #define CTRL_EXT_SWDPIO_MASK 0x0d 311 #define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT \ 312 + ((x) == 3 ? 3 : ((x) - 4)))) 313 #define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */ 314 #define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */ 315 #define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */ 316 #define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */ 317 #define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */ 318 #define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */ 319 #define CTRL_EXT_SDLPE (1U << 18) /* SerDes Low Power Enable */ 320 #define CTRL_EXT_DMA_DYN_CLK (1U << 19) /* DMA Dynamic Gating Enable */ 321 #define CTRL_EXT_LINK_MODE_MASK 0x00C00000 322 #define CTRL_EXT_LINK_MODE_GMII 0x00000000 323 #define CTRL_EXT_LINK_MODE_KMRN 0x00000000 324 #define CTRL_EXT_LINK_MODE_1000KX 0x00400000 325 #define CTRL_EXT_LINK_MODE_SGMII 0x00800000 326 #define CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 327 #define CTRL_EXT_LINK_MODE_TBI 0x00C00000 328 #define CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 329 #define CTRL_EXT_PHYPDEN 0x00100000 330 #define CTRL_EXT_EIAME __BIT(24) /* Extended Interrupt Auto Mask En */ 331 #define CTRL_EXT_I2C_ENA 0x02000000 /* I2C enable */ 332 #define CTRL_EXT_DRV_LOAD 0x10000000 333 #define CTRL_EXT_PBA __BIT(31) /* PBA Support */ 334 335 #define WMREG_MDIC 0x0020 /* MDI Control Register */ 336 #define MDIC_DATA(x) ((x) & 0xffff) 337 #define MDIC_REGADD(x) ((x) << 16) 338 #define MDIC_PHY_SHIFT 21 339 #define MDIC_PHY_MASK __BITS(25, 21) 340 #define MDIC_PHYADD(x) ((x) << 21) 341 #define MDIC_OP_WRITE (1U << 26) 342 #define MDIC_OP_READ (2U << 26) 343 #define MDIC_READY (1U << 28) 344 #define MDIC_I (1U << 29) /* interrupt on MDI complete */ 345 #define MDIC_E (1U << 30) /* MDI error */ 346 #define MDIC_DEST (1U << 31) /* Destination */ 347 348 #define WMREG_SCTL 0x0024 /* SerDes Control - RW */ 349 /* 350 * These 4 macros are also used for other 8bit control registers on the 351 * 82575 352 */ 353 #define SCTL_CTL_READY (1U << 31) 354 #define SCTL_CTL_DATA_MASK 0x000000ff 355 #define SCTL_CTL_ADDR_SHIFT 8 356 #define SCTL_CTL_POLL_TIMEOUT 640 357 #define SCTL_DISABLE_SERDES_LOOPBACK 0x0400 358 359 #define WMREG_FCAL 0x0028 /* Flow Control Address Low */ 360 #define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */ 361 362 #define WMREG_FCAH 0x002c /* Flow Control Address High */ 363 #define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */ 364 365 #define WMREG_FCT 0x0030 /* Flow Control Type */ 366 367 #define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */ 368 #define KUMCTRLSTA_MASK 0x0000FFFF 369 #define KUMCTRLSTA_OFFSET 0x001F0000 370 #define KUMCTRLSTA_OFFSET_SHIFT 16 371 #define KUMCTRLSTA_REN 0x00200000 372 373 #define KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 374 #define KUMCTRLSTA_OFFSET_CTRL 0x00000001 375 #define KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 376 #define KUMCTRLSTA_OFFSET_DIAG 0x00000003 377 #define KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 378 #define KUMCTRLSTA_OFFSET_K1_CONFIG 0x00000007 379 #define KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 380 #define KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 381 #define KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E 382 #define KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F 383 384 /* FIFO Control */ 385 #define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 386 #define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 387 388 /* In-Band Control */ 389 #define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500 390 #define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 391 392 /* Diag */ 393 #define KUMCTRLSTA_DIAG_NELPBK 0x1000 394 395 /* K1 Config */ 396 #define KUMCTRLSTA_K1_ENABLE 0x0002 397 398 /* Half-Duplex Control */ 399 #define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 400 #define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 401 402 #define WMREG_VET 0x0038 /* VLAN Ethertype */ 403 #define WMREG_MDPHYA 0x003C /* PHY address - RW */ 404 #define WMREG_RAL_BASE 0x0040 /* Receive Address List */ 405 #define WMREG_CORDOVA_RAL_BASE 0x5400 406 #define WMREG_RAL_LO(b, x) ((b) + ((x) << 3)) 407 #define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4) 408 /* 409 * Receive Address List: The LO part is the low-order 32-bits 410 * of the MAC address. The HI part is the high-order 16-bits 411 * along with a few control bits. 412 */ 413 #define RAL_AS(x) ((x) << 16) /* address select */ 414 #define RAL_AS_DEST RAL_AS(0) /* (cordova?) */ 415 #define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */ 416 #define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */ 417 #define RAL_AV (1U << 31) /* entry is valid */ 418 419 #define WM_RAL_TABSIZE 15 /* RAL size for old devices */ 420 #define WM_RAL_TABSIZE_ICH8 7 /* RAL size for ICH* and PCH* */ 421 #define WM_RAL_TABSIZE_82575 16 /* RAL size for 82575 */ 422 #define WM_RAL_TABSIZE_82576 24 /* RAL size for 82576 and 82580 */ 423 #define WM_RAL_TABSIZE_I350 32 /* RAL size for I350 */ 424 425 #define WMREG_ICR 0x00c0 /* Interrupt Cause Register */ 426 #define ICR_TXDW (1U << 0) /* Tx desc written back */ 427 #define ICR_TXQE (1U << 1) /* Tx queue empty */ 428 #define ICR_LSC (1U << 2) /* link status change */ 429 #define ICR_RXSEQ (1U << 3) /* receive sequence error */ 430 #define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */ 431 #define ICR_RXO (1U << 6) /* Rx overrun */ 432 #define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */ 433 #define ICR_MDAC (1U << 9) /* MDIO access complete */ 434 #define ICR_RXCFG (1U << 10) /* Receiving /C/ */ 435 #define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */ 436 #define ICR_RXQ0 __BIT(20) /* 82574: Rx queue 0 interrupt */ 437 #define ICR_RXQ1 __BIT(21) /* 82574: Rx queue 1 interrupt */ 438 #define ICR_TXQ0 __BIT(22) /* 82574: Tx queue 0 interrupt */ 439 #define ICR_TXQ1 __BIT(23) /* 82574: Tx queue 1 interrupt */ 440 #define ICR_OTHER __BIT(24) /* 82574: Other interrupt */ 441 #define ICR_INT (1U << 31) /* device generated an interrupt */ 442 443 #define WMREG_ITR 0x00c4 /* Interrupt Throttling Register */ 444 #define ITR_IVAL_MASK 0xffff /* Interval mask */ 445 #define ITR_IVAL_SHIFT 0 /* Interval shift */ 446 447 #define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */ 448 /* See ICR bits. */ 449 450 #define WMREG_IVAR 0x00e4 /* Interrupt Vector Allocation Register */ 451 #define WMREG_IVAR0 0x01700 /* Interrupt Vector Allocation */ 452 #define IVAR_ALLOC_MASK __BITS(0, 6) /* Bit 5 and 6 are reserved */ 453 #define IVAR_VALID __BIT(7) 454 /* IVAR definitions for 82580 and newer */ 455 #define WMREG_IVAR_Q(x) (WMREG_IVAR0 + ((x) % 2) * 4) 456 #define IVAR_TX_MASK_Q(x) (0x000000ff << (((x) % 2) == 0 ? 8 : 24)) 457 #define IVAR_RX_MASK_Q(x) (0x000000ff << (((x) % 2) == 0 ? 0 : 16)) 458 /* IVAR definitions for 82576 */ 459 #define WMREG_IVAR_Q_82576(x) (WMREG_IVAR0 + ((x) & 0x7) * 4) 460 #define IVAR_TX_MASK_Q_82576(x) (0x000000ff << (((x) / 8) == 0 ? 8 : 24)) 461 #define IVAR_RX_MASK_Q_82576(x) (0x000000ff << (((x) / 8) == 0 ? 0 : 16)) 462 /* IVAR definitions for 82574 */ 463 #define IVAR_ALLOC_MASK_82574 __BITS(0, 2) 464 #define IVAR_VALID_82574 __BIT(3) 465 #define IVAR_TX_MASK_Q_82574(x) (0x0000000f << ((x) == 0 ? 8 : 12)) 466 #define IVAR_RX_MASK_Q_82574(x) (0x0000000f << ((x) == 0 ? 0 : 4)) 467 #define IVAR_OTHER_MASK __BITS(16, 19) 468 #define IVAR_INT_ON_ALL_WB __BIT(31) 469 470 #define WMREG_IVAR_MISC 0x01740 /* IVAR for other causes */ 471 #define IVAR_MISC_TCPTIMER __BITS(0, 7) 472 #define IVAR_MISC_OTHER __BITS(8, 15) 473 474 #define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */ 475 /* See ICR bits. */ 476 477 #define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */ 478 /* See ICR bits. */ 479 480 #define WMREG_EIAC_82574 0x00dc /* Interrupt Auto Clear Register */ 481 #define WMREG_EIAC_82574_MSIX_MASK (ICR_RXQ0 | ICR_RXQ1 \ 482 | ICR_TXQ0 | ICR_TXQ1 | ICR_OTHER) 483 484 #define WMREG_RCTL 0x0100 /* Receive Control */ 485 #define RCTL_EN (1U << 1) /* receiver enable */ 486 #define RCTL_SBP (1U << 2) /* store bad packets */ 487 #define RCTL_UPE (1U << 3) /* unicast promisc. enable */ 488 #define RCTL_MPE (1U << 4) /* multicast promisc. enable */ 489 #define RCTL_LPE (1U << 5) /* large packet enable */ 490 #define RCTL_LBM(x) ((x) << 6) /* loopback mode */ 491 #define RCTL_LBM_NONE RCTL_LBM(0) 492 #define RCTL_LBM_PHY RCTL_LBM(3) 493 #define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */ 494 #define RCTL_RDMTS_1_2 RCTL_RDMTS(0) 495 #define RCTL_RDMTS_1_4 RCTL_RDMTS(1) 496 #define RCTL_RDMTS_1_8 RCTL_RDMTS(2) 497 #define RCTL_RDMTS_MASK RCTL_RDMTS(3) 498 #define RCTL_MO(x) ((x) << 12) /* multicast offset */ 499 #define RCTL_BAM (1U << 15) /* broadcast accept mode */ 500 #define RCTL_2k (0 << 16) /* 2k Rx buffers */ 501 #define RCTL_1k (1 << 16) /* 1k Rx buffers */ 502 #define RCTL_512 (2 << 16) /* 512 byte Rx buffers */ 503 #define RCTL_256 (3 << 16) /* 256 byte Rx buffers */ 504 #define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */ 505 #define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */ 506 #define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */ 507 #define RCTL_DPF (1U << 22) /* discard pause frames */ 508 #define RCTL_PMCF (1U << 23) /* pass MAC control frames */ 509 #define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */ 510 #define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */ 511 512 #define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */ 513 #define WMREG_RDTR 0x2820 514 #define RDTR_FPD (1U << 31) /* flush partial descriptor */ 515 516 #define WMREG_LTRC 0x01a0 /* Latency Tolerance Reportiong Control */ 517 518 #define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */ 519 #define WMREG_RDBAL 0x2800 520 #define WMREG_RDBAL_2 0x0c00 /* for 82576 ... */ 521 522 #define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */ 523 #define WMREG_RDBAH 0x2804 524 #define WMREG_RDBAH_2 0x0c04 /* for 82576 ... */ 525 526 #define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */ 527 #define WMREG_RDLEN 0x2808 528 #define WMREG_RDLEN_2 0x0c08 /* for 82576 ... */ 529 530 #define WMREG_SRRCTL 0x280c /* additional recv control used in 82575 ... */ 531 #define WMREG_SRRCTL_2 0x0c0c /* for 82576 ... */ 532 #define SRRCTL_BSIZEPKT_MASK 0x0000007f 533 #define SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 534 #define SRRCTL_BSIZEHDRSIZE_MASK 0x00000f00 535 #define SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 536 #define SRRCTL_DESCTYPE_LEGACY 0x00000000 537 #define SRRCTL_DESCTYPE_ADV_ONEBUF (1U << 25) 538 #define SRRCTL_DESCTYPE_HDR_SPLIT (2U << 25) 539 #define SRRCTL_DESCTYPE_HDR_REPLICATION (3U << 25) 540 #define SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT (4U << 25) 541 #define SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS (5U << 25) /* 82575 only */ 542 #define SRRCTL_DESCTYPE_MASK (7U << 25) 543 #define SRRCTL_DROP_EN 0x80000000 544 545 #define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */ 546 #define WMREG_RDH 0x2810 547 #define WMREG_RDH_2 0x0c10 /* for 82576 ... */ 548 549 #define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */ 550 #define WMREG_RDT 0x2818 551 #define WMREG_RDT_2 0x0c18 /* for 82576 ... */ 552 553 #define WMREG_RXDCTL 0x2828 /* Receive Descriptor Control */ 554 #define WMREG_RXDCTL_2 0x0c28 /* for 82576 ... */ 555 #define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 556 #define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 557 #define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 558 #define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */ 559 /* flags used starting with 82575 ... */ 560 #define RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 561 #define RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ 562 563 #define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */ 564 #define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */ 565 #define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */ 566 #define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */ 567 #define WMREG_OLD_RDH1 0x0148 568 #define WMREG_OLD_RDT1 0x0150 569 #define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */ 570 #define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */ 571 #define FCRTH_DFLT 0x00008000 572 573 #define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */ 574 #define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */ 575 #define FCRTL_DFLT 0x00004000 576 #define FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 577 578 #define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */ 579 #define FCTTV_DFLT 0x00000600 580 581 #define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */ 582 /* See MII ANAR_X bits. */ 583 #define TXCW_FD (1U << 5) /* Full Duplex */ 584 #define TXCW_HD (1U << 6) /* Half Duplex */ 585 #define TXCW_SYM_PAUSE (1U << 7) /* sym pause request */ 586 #define TXCW_ASYM_PAUSE (1U << 8) /* asym pause request */ 587 #define TXCW_TxConfig (1U << 30) /* Tx Config */ 588 #define TXCW_ANE (1U << 31) /* Autonegotiate */ 589 590 #define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */ 591 /* See MII ANLPAR_X bits. */ 592 #define RXCW_NC (1U << 26) /* no carrier */ 593 #define RXCW_IV (1U << 27) /* config invalid */ 594 #define RXCW_CC (1U << 28) /* config change */ 595 #define RXCW_C (1U << 29) /* /C/ reception */ 596 #define RXCW_SYNCH (1U << 30) /* synchronized */ 597 #define RXCW_ANC (1U << 31) /* autonegotiation complete */ 598 599 #define WMREG_MTA 0x0200 /* Multicast Table Array */ 600 #define WMREG_CORDOVA_MTA 0x5200 601 602 #define WMREG_TCTL 0x0400 /* Transmit Control Register */ 603 #define TCTL_EN (1U << 1) /* transmitter enable */ 604 #define TCTL_PSP (1U << 3) /* pad short packets */ 605 #define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */ 606 #define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */ 607 #define TCTL_SWXOFF (1U << 22) /* software XOFF */ 608 #define TCTL_RTLC (1U << 24) /* retransmit on late collision */ 609 #define TCTL_NRTU (1U << 25) /* no retransmit on underrun */ 610 #define TCTL_MULR (1U << 28) /* multiple request */ 611 612 #define TX_COLLISION_THRESHOLD 15 613 #define TX_COLLISION_DISTANCE_HDX 512 614 #define TX_COLLISION_DISTANCE_FDX 64 615 616 #define WMREG_TCTL_EXT 0x0404 /* Transmit Control Register */ 617 #define TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 618 #define TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 619 620 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 621 622 #define WMREG_TIPG 0x0410 /* Transmit IPG Register */ 623 #define TIPG_IPGT(x) (x) /* IPG transmit time */ 624 #define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */ 625 #define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */ 626 #define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a)) 627 #define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 628 #define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 629 #define TIPG_1000T_80003_DFLT \ 630 (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) 631 #define TIPG_10_100_80003_DFLT \ 632 (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) 633 634 #define WMREG_TQC 0x0418 635 636 #define WMREG_OLD_TDBAL 0x0420 /* Transmit Descriptor Base Lo */ 637 #define WMREG_TDBAL 0x3800 638 639 #define WMREG_OLD_TDBAH 0x0424 /* Transmit Descriptor Base Hi */ 640 #define WMREG_TDBAH 0x3804 641 642 #define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */ 643 #define WMREG_TDLEN 0x3808 644 645 #define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */ 646 #define WMREG_TDH 0x3810 647 648 #define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */ 649 #define WMREG_TDT 0x3818 650 651 #define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */ 652 #define WMREG_TIDV 0x3820 653 654 #define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */ 655 #define WMREG_VFTA 0x0600 656 657 #define WMREG_MDICNFG 0x0e04 /* MDC/MDIO Configuration Register */ 658 #define MDICNFG_PHY_SHIFT 21 659 #define MDICNFG_PHY_MASK __BITS(25, 21) 660 #define MDICNFG_COM_MDIO __BIT(30) 661 #define MDICNFG_DEST __BIT(31) 662 663 #define WM_MC_TABSIZE 128 664 #define WM_ICH8_MC_TABSIZE 32 665 #define WM_VLAN_TABSIZE 128 666 667 #define WMREG_PHPM 0x0e14 /* PHY Power Management */ 668 #define PHPM_GO_LINK_D __BIT(5) /* Go Link Disconnect */ 669 670 #define WMREG_EEER 0x0e30 /* Energy Efficiency Ethernet "EEE" */ 671 #define EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 672 #define EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 673 #define EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 674 #define EEER_EEER_NEG 0x20000000 /* EEER capability nego */ 675 #define EEER_EEER_RX_LPI_STATUS 0x40000000 /* EEER Rx in LPI state */ 676 #define EEER_EEER_TX_LPI_STATUS 0x80000000 /* EEER Tx in LPI state */ 677 #define WMREG_EEE_SU 0x0e34 /* EEE Setup */ 678 #define WMREG_IPCNFG 0x0e38 /* Internal PHY Configuration */ 679 #define IPCNFG_10BASE_TE 0x00000002 /* IPCNFG 10BASE-Te low power op. */ 680 #define IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 681 #define IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 682 683 #define WMREG_EXTCNFCTR 0x0f00 /* Extended Configuration Control */ 684 #define EXTCNFCTR_PCIE_WRITE_ENABLE 0x00000001 685 #define EXTCNFCTR_PHY_WRITE_ENABLE 0x00000002 686 #define EXTCNFCTR_D_UD_ENABLE 0x00000004 687 #define EXTCNFCTR_D_UD_LATENCY 0x00000008 688 #define EXTCNFCTR_D_UD_OWNER 0x00000010 689 #define EXTCNFCTR_MDIO_SW_OWNERSHIP 0x00000020 690 #define EXTCNFCTR_MDIO_HW_OWNERSHIP 0x00000040 691 #define EXTCNFCTR_GATE_PHY_CFG 0x00000080 692 #define EXTCNFCTR_EXT_CNF_POINTER 0x0FFF0000 693 694 #define WMREG_PHY_CTRL 0x0f10 /* PHY control */ 695 #define PHY_CTRL_SPD_EN (1 << 0) 696 #define PHY_CTRL_D0A_LPLU (1 << 1) 697 #define PHY_CTRL_NOND0A_LPLU (1 << 2) 698 #define PHY_CTRL_NOND0A_GBE_DIS (1 << 3) 699 #define PHY_CTRL_GBE_DIS (1 << 4) 700 701 #define WMREG_PBA 0x1000 /* Packet Buffer Allocation */ 702 #define PBA_BYTE_SHIFT 10 /* KB -> bytes */ 703 #define PBA_ADDR_SHIFT 7 /* KB -> quadwords */ 704 #define PBA_8K 0x0008 705 #define PBA_10K 0x000a 706 #define PBA_12K 0x000c 707 #define PBA_14K 0x000e 708 #define PBA_16K 0x0010 /* 16K, default Tx allocation */ 709 #define PBA_20K 0x0014 710 #define PBA_22K 0x0016 711 #define PBA_24K 0x0018 712 #define PBA_26K 0x001a 713 #define PBA_30K 0x001e 714 #define PBA_32K 0x0020 715 #define PBA_34K 0x0022 716 #define PBA_35K 0x0023 717 #define PBA_40K 0x0028 718 #define PBA_48K 0x0030 /* 48K, default Rx allocation */ 719 #define PBA_64K 0x0040 720 721 #define WMREG_PBS 0x1008 /* Packet Buffer Size (ICH) */ 722 723 #define WMREG_PBECCSTS 0x100c /* Packet Buffer ECC Status (PCH_LPT) */ 724 #define PBECCSTS_CORR_ERR_CNT_MASK 0x000000ff 725 #define PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000ff00 726 #define PBECCSTS_UNCORR_ECC_ENABLE 0x00010000 727 728 #define WMREG_EEMNGCTL 0x1010 /* MNG EEprom Control */ 729 #define EEMNGCTL_CFGDONE_0 0x040000 /* MNG config cycle done */ 730 #define EEMNGCTL_CFGDONE_1 0x080000 /* 2nd port */ 731 732 #define WMREG_I2CCMD 0x1028 /* SFPI2C Command Register - RW */ 733 #define I2CCMD_REG_ADDR_SHIFT 16 734 #define I2CCMD_REG_ADDR 0x00ff0000 735 #define I2CCMD_PHY_ADDR_SHIFT 24 736 #define I2CCMD_PHY_ADDR 0x07000000 737 #define I2CCMD_OPCODE_READ 0x08000000 738 #define I2CCMD_OPCODE_WRITE 0x00000000 739 #define I2CCMD_RESET 0x10000000 740 #define I2CCMD_READY 0x20000000 741 #define I2CCMD_INTERRUPT_ENA 0x40000000 742 #define I2CCMD_ERROR 0x80000000 743 #define MAX_SGMII_PHY_REG_ADDR 255 744 #define I2CCMD_PHY_TIMEOUT 200 745 746 #define WMREG_EEWR 0x102c /* EEPROM write */ 747 748 #define WMREG_PBA_ECC 0x01100 /* PBA ECC */ 749 #define PBA_ECC_COUNTER_MASK 0xfff00000 /* ECC counter mask */ 750 #define PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 751 #define PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 752 #define PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 753 #define PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 754 755 #define WMREG_GPIE 0x01514 /* General Purpose Interrupt Enable */ 756 #define GPIE_NSICR __BIT(0) /* Non Selective Interrupt Clear */ 757 #define GPIE_MULTI_MSIX __BIT(4) /* Multiple MSIX */ 758 #define GPIE_EIAME __BIT(30) /* Extended Interrupt Auto Mask Ena. */ 759 #define GPIE_PBA __BIT(31) /* PBA support */ 760 761 #define WMREG_EICS 0x01520 /* Ext. Interrupt Cause Set - WO */ 762 #define WMREG_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 763 #define WMREG_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 764 #define WMREG_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 765 #define WMREG_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 766 767 #define WMREG_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 768 769 #define WMREG_MSIXBM(x) (0x1600 + (x) * 4) /* MSI-X Allocation */ 770 771 #define EITR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 772 #define EITR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 773 #define EITR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 774 #define EITR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 775 #define EITR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 776 #define EITR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 777 #define EITR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 778 #define EITR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 779 #define EITR_TCP_TIMER 0x40000000 /* TCP Timer */ 780 #define EITR_OTHER 0x80000000 /* Interrupt Cause Active */ 781 782 #define WMREG_EITR(x) (0x01680 + (0x4 * (x))) 783 #define EITR_ITR_INT_MASK 0x0000ffff 784 785 #define WMREG_RXPBS 0x2404 /* Rx Packet Buffer Size */ 786 #define RXPBS_SIZE_MASK_82576 0x0000007F 787 788 #define WMREG_RDFH 0x2410 /* Receive Data FIFO Head */ 789 #define WMREG_RDFT 0x2418 /* Receive Data FIFO Tail */ 790 #define WMREG_RDFHS 0x2420 /* Receive Data FIFO Head Saved */ 791 #define WMREG_RDFTS 0x2428 /* Receive Data FIFO Tail Saved */ 792 #define WMREG_RADV 0x282c /* Receive Interrupt Absolute Delay Timer */ 793 794 #define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */ 795 #define TXDMAC_DPP (1U << 0) /* disable packet prefetch */ 796 797 #define WMREG_KABGTXD 0x3004 /* AFE and Gap Transmit Ref Data */ 798 #define KABGTXD_BGSQLBIAS 0x00050000 799 800 #define WMREG_TDFH 0x3410 /* Transmit Data FIFO Head */ 801 #define WMREG_TDFT 0x3418 /* Transmit Data FIFO Tail */ 802 #define WMREG_TDFHS 0x3420 /* Transmit Data FIFO Head Saved */ 803 #define WMREG_TDFTS 0x3428 /* Transmit Data FIFO Tail Saved */ 804 #define WMREG_TDFPC 0x3430 /* Transmit Data FIFO Packet Count */ 805 806 #define WMREG_TXDCTL(n) /* Trandmit Descriptor Control */ \ 807 (((n) < 4) ? (0x3828 + ((n) * 0x100)) : (0xe028 + ((n) * 0x40))) 808 #define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 809 #define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 810 #define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 811 /* flags used starting with 82575 ... */ 812 #define TXDCTL_COUNT_DESC __BIT(22) /* Enable the counting of desc. 813 still to be processed. */ 814 #define TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 815 #define TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 816 #define TXDCTL_PRIORITY 0x08000000 817 818 #define WMREG_TADV 0x382c /* Transmit Absolute Interrupt Delay Timer */ 819 #define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum 820 Threshold (Cordova) */ 821 #define TSPMT_TSMT(x) (x) /* TCP seg min transfer */ 822 #define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */ 823 824 #define WMREG_TARC0 0x3840 /* Tx arbitration count (0) */ 825 #define WMREG_TARC1 0x3940 /* Tx arbitration count (1) */ 826 827 #define WMREG_CRCERRS 0x4000 /* CRC Error Count */ 828 #define WMREG_ALGNERRC 0x4004 /* Alignment Error Count */ 829 #define WMREG_SYMERRC 0x4008 /* Symbol Error Count */ 830 #define WMREG_RXERRC 0x400c /* receive error Count - R/clr */ 831 #define WMREG_MPC 0x4010 /* Missed Packets Count - R/clr */ 832 #define WMREG_COLC 0x4028 /* collision Count - R/clr */ 833 #define WMREG_SEC 0x4038 /* Sequence Error Count */ 834 #define WMREG_CEXTERR 0x403c /* Carrier Extension Error Count */ 835 #define WMREG_RLEC 0x4040 /* Receive Length Error Count */ 836 #define WMREG_XONRXC 0x4048 /* XON Rx Count - R/clr */ 837 #define WMREG_XONTXC 0x404c /* XON Tx Count - R/clr */ 838 #define WMREG_XOFFRXC 0x4050 /* XOFF Rx Count - R/clr */ 839 #define WMREG_XOFFTXC 0x4054 /* XOFF Tx Count - R/clr */ 840 #define WMREG_FCRUC 0x4058 /* Flow Control Rx Unsupported Count - R/clr */ 841 #define WMREG_RNBC 0x40a0 /* Receive No Buffers Count */ 842 #define WMREG_TLPIC 0x4148 /* EEE Tx LPI Count */ 843 #define WMREG_RLPIC 0x414c /* EEE Rx LPI Count */ 844 845 #define WMREG_PCS_CFG 0x4200 /* PCS Configuration */ 846 #define PCS_CFG_PCS_EN __BIT(3) 847 848 #define WMREG_PCS_LCTL 0x4208 /* PCS Link Control */ 849 #define PCS_LCTL_FSV_1000 __BIT(2) /* AN Timeout Enable */ 850 #define PCS_LCTL_FDV_FULL __BIT(3) /* AN Timeout Enable */ 851 #define PCS_LCTL_FSD __BIT(4) /* AN Timeout Enable */ 852 #define PCS_LCTL_FORCE_FC __BIT(7) /* AN Timeout Enable */ 853 #define PCS_LCTL_AN_ENABLE __BIT(16) /* AN Timeout Enable */ 854 #define PCS_LCTL_AN_RESTART __BIT(17) /* AN Timeout Enable */ 855 #define PCS_LCTL_AN_TIMEOUT __BIT(18) /* AN Timeout Enable */ 856 857 #define WMREG_PCS_LSTS 0x420c /* PCS Link Status */ 858 #define PCS_LSTS_LINKOK __BIT(0) 859 #define PCS_LSTS_SPEED_100 __BIT(1) 860 #define PCS_LSTS_SPEED_1000 __BIT(2) 861 #define PCS_LSTS_FDX __BIT(3) 862 #define PCS_LSTS_AN_COMP __BIT(16) 863 864 #define WMREG_PCS_ANADV 0x4218 /* AN Advertsement */ 865 #define WMREG_PCS_LPAB 0x421c /* Link Partnet Ability */ 866 867 #define WMREG_RXCSUM 0x5000 /* Receive Checksum register */ 868 #define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */ 869 #define RXCSUM_IPOFL (1U << 8) /* IP checksum offload */ 870 #define RXCSUM_TUOFL (1U << 9) /* TCP/UDP checksum offload */ 871 #define RXCSUM_IPV6OFL (1U << 10) /* IPv6 checksum offload */ 872 873 #define WMREG_RLPML 0x5004 /* Rx Long Packet Max Length */ 874 875 #define WMREG_RFCTL 0x5008 /* Receive Filter Control */ 876 #define WMREG_RFCTL_NFSWDIS __BIT(6) /* NFS Write Disable */ 877 #define WMREG_RFCTL_NFSRDIS __BIT(7) /* NFS Read Disable */ 878 #define WMREG_RFCTL_ACKDIS __BIT(13) /* ACK Accelerate Disable */ 879 #define WMREG_RFCTL_IPV6EXDIS __BIT(16) /* IPv6 Extension Header Disable */ 880 #define WMREG_RFCTL_NEWIPV6EXDIS __BIT(17) /* New IPv6 Extension Header */ 881 882 #define WMREG_WUC 0x5800 /* Wakeup Control */ 883 #define WUC_APME 0x00000001 /* APM Enable */ 884 #define WUC_PME_EN 0x00000002 /* PME Enable */ 885 886 #define WMREG_WUFC 0x5808 /* Wakeup Filter COntrol */ 887 #define WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 888 #define WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 889 #define WUFC_MC 0x00000008 /* Directed Multicast Wakeup En */ 890 #define WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 891 #define WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup En */ 892 #define WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup En */ 893 #define WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup En */ 894 895 #define WMREG_MANC 0x5820 /* Management Control */ 896 #define MANC_SMBUS_EN 0x00000001 897 #define MANC_ASF_EN 0x00000002 898 #define MANC_ARP_EN 0x00002000 899 #define MANC_RECV_TCO_RESET 0x00010000 900 #define MANC_RECV_TCO_EN 0x00020000 901 #define MANC_BLK_PHY_RST_ON_IDE 0x00040000 902 #define MANC_RECV_ALL 0x00080000 903 #define MANC_EN_MAC_ADDR_FILTER 0x00100000 904 #define MANC_EN_MNG2HOST 0x00200000 905 906 #define WMREG_MANC2H 0x5860 /* Manaegment Control To Host - RW */ 907 #define MANC2H_PORT_623 (1 << 5) 908 #define MANC2H_PORT_624 (1 << 6) 909 910 #define WMREG_GCR 0x5b00 /* PCIe Control */ 911 #define GCR_RXD_NO_SNOOP 0x00000001 912 #define GCR_RXDSCW_NO_SNOOP 0x00000002 913 #define GCR_RXDSCR_NO_SNOOP 0x00000004 914 #define GCR_TXD_NO_SNOOP 0x00000008 915 #define GCR_TXDSCW_NO_SNOOP 0x00000010 916 #define GCR_TXDSCR_NO_SNOOP 0x00000020 917 #define GCR_CMPL_TMOUT_MASK 0x0000f000 918 #define GCR_CMPL_TMOUT_10MS 0x00001000 919 #define GCR_CMPL_TMOUT_RESEND 0x00010000 920 #define GCR_CAP_VER2 0x00040000 921 922 #define WMREG_FACTPS 0x5b30 /* Function Active and Power State to MNG */ 923 #define FACTPS_MNGCG 0x20000000 924 #define FACTPS_LFS 0x40000000 /* LAN Function Select */ 925 926 #define WMREG_GIOCTL 0x5b44 /* GIO Analog Control Register */ 927 #define WMREG_CCMCTL 0x5b48 /* CCM Control Register */ 928 #define WMREG_SCCTL 0x5b4c /* PCIc PLL Configuration Register */ 929 930 #define WMREG_SWSM 0x5b50 /* SW Semaphore */ 931 #define SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 932 #define SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 933 #define SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 934 #define SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 935 936 #define WMREG_FWSM 0x5b54 /* FW Semaphore */ 937 #define FWSM_MODE_MASK 0xe 938 #define FWSM_MODE_SHIFT 0x1 939 #define MNG_ICH_IAMT_MODE 0x2 /* PT mode? */ 940 #define MNG_IAMT_MODE 0x3 941 #define FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ 942 #define FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 943 944 #define WMREG_SWSM2 0x5b58 /* SW Semaphore 2 */ 945 #define SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 946 947 #define WMREG_SW_FW_SYNC 0x5b5c /* software-firmware semaphore */ 948 #define SWFW_EEP_SM 0x0001 /* eeprom access */ 949 #define SWFW_PHY0_SM 0x0002 /* first ctrl phy access */ 950 #define SWFW_PHY1_SM 0x0004 /* second ctrl phy access */ 951 #define SWFW_MAC_CSR_SM 0x0008 952 #define SWFW_PHY2_SM 0x0020 /* first ctrl phy access */ 953 #define SWFW_PHY3_SM 0x0040 /* first ctrl phy access */ 954 #define SWFW_SOFT_SHIFT 0 /* software semaphores */ 955 #define SWFW_FIRM_SHIFT 16 /* firmware semaphores */ 956 957 #define WMREG_GCR2 0x5b64 /* 3GPIO Control Register 2 */ 958 959 #define WMREG_CRC_OFFSET 0x5f50 960 961 #define WMREG_EEC 0x12010 962 #define EEC_FLASH_DETECTED (1U << 19) /* FLASH */ 963 #define EEC_FLUPD (1U << 23) /* Update FLASH */ 964 965 #define WMREG_EEARBC_I210 0x12024 966 967 /* 968 * NVM related values. 969 * Microwire, SPI, and flash 970 */ 971 #define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */ 972 #define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */ 973 #define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */ 974 975 #define SPI_OPC_WRITE 0x02 /* SPI "write" opcode */ 976 #define SPI_OPC_READ 0x03 /* SPI "read" opcode */ 977 #define SPI_OPC_A8 0x08 /* opcode bit 3 == address bit 8 */ 978 #define SPI_OPC_WREN 0x06 /* SPI "set write enable" opcode */ 979 #define SPI_OPC_WRDI 0x04 /* SPI "clear write enable" opcode */ 980 #define SPI_OPC_RDSR 0x05 /* SPI "read status" opcode */ 981 #define SPI_OPC_WRSR 0x01 /* SPI "write status" opcode */ 982 #define SPI_MAX_RETRIES 5000 /* max wait of 5ms for RDY signal */ 983 984 #define SPI_SR_RDY 0x01 985 #define SPI_SR_WEN 0x02 986 #define SPI_SR_BP0 0x04 987 #define SPI_SR_BP1 0x08 988 #define SPI_SR_WPEN 0x80 989 990 #define NVM_CHECKSUM 0xBABA 991 #define NVM_SIZE 0x0040 992 #define NVM_WORD_SIZE_BASE_SHIFT 6 993 994 #define NVM_OFF_MACADDR 0x0000 /* MAC address offset 0 */ 995 #define NVM_OFF_MACADDR1 0x0001 /* MAC address offset 1 */ 996 #define NVM_OFF_MACADDR2 0x0002 /* MAC address offset 2 */ 997 #define NVM_OFF_COMPAT 0x0003 998 #define NVM_OFF_ID_LED_SETTINGS 0x0004 999 #define NVM_OFF_VERSION 0x0005 1000 #define NVM_OFF_CFG1 0x000a /* config word 1 */ 1001 #define NVM_OFF_CFG2 0x000f /* config word 2 */ 1002 #define NVM_OFF_EEPROM_SIZE 0x0012 /* NVM SIZE */ 1003 #define NVM_OFF_CFG4 0x0013 /* config word 4 */ 1004 #define NVM_OFF_CFG3_PORTB 0x0014 /* config word 3 */ 1005 #define NVM_OFF_FUTURE_INIT_WORD1 0x0019 1006 #define NVM_OFF_INIT_3GIO_3 0x001a /* PCIe Initial Configuration Word 3 */ 1007 #define NVM_OFF_K1_CONFIG 0x001b /* NVM K1 Config */ 1008 #define NVM_OFF_LED_1_CFG 0x001c 1009 #define NVM_OFF_LED_0_2_CFG 0x001f 1010 #define NVM_OFF_SWDPIN 0x0020 /* SWD Pins (Cordova) */ 1011 #define NVM_OFF_CFG3_PORTA 0x0024 /* config word 3 */ 1012 #define NVM_OFF_ALT_MAC_ADDR_PTR 0x0037 /* to the alternative MAC addresses */ 1013 #define NVM_OFF_COMB_VER_PTR 0x003d 1014 #define NVM_OFF_IMAGE_UID0 0x0042 1015 #define NVM_OFF_IMAGE_UID1 0x0043 1016 1017 #define NVM_COMPAT_VALID_CHECKSUM 0x0001 1018 1019 #define NVM_CFG1_LVDID (1U << 0) 1020 #define NVM_CFG1_LSSID (1U << 1) 1021 #define NVM_CFG1_PME_CLOCK (1U << 2) 1022 #define NVM_CFG1_PM (1U << 3) 1023 #define NVM_CFG1_ILOS (1U << 4) 1024 #define NVM_CFG1_SWDPIO_SHIFT 5 1025 #define NVM_CFG1_SWDPIO_MASK (0xf << NVM_CFG1_SWDPIO_SHIFT) 1026 #define NVM_CFG1_IPS1 (1U << 8) 1027 #define NVM_CFG1_LRST (1U << 9) 1028 #define NVM_CFG1_FD (1U << 10) 1029 #define NVM_CFG1_FRCSPD (1U << 11) 1030 #define NVM_CFG1_IPS0 (1U << 12) 1031 #define NVM_CFG1_64_32_BAR (1U << 13) 1032 1033 #define NVM_CFG2_CSR_RD_SPLIT (1U << 1) 1034 #define NVM_CFG2_82544_APM_EN (1U << 2) 1035 #define NVM_CFG2_64_BIT (1U << 3) 1036 #define NVM_CFG2_MAX_READ (1U << 4) 1037 #define NVM_CFG2_DMCR_MAP (1U << 5) 1038 #define NVM_CFG2_133_CAP (1U << 6) 1039 #define NVM_CFG2_MSI_DIS (1U << 7) 1040 #define NVM_CFG2_FLASH_DIS (1U << 8) 1041 #define NVM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9) 1042 #define NVM_CFG2_APM_EN (1U << 10) 1043 #define NVM_CFG2_ANE (1U << 11) 1044 #define NVM_CFG2_PAUSE(x) (((x) & 3) >> 12) 1045 #define NVM_CFG2_ASDE (1U << 14) 1046 #define NVM_CFG2_APM_PME (1U << 15) 1047 #define NVM_CFG2_SWDPIO_SHIFT 4 1048 #define NVM_CFG2_SWDPIO_MASK (0xf << NVM_CFG2_SWDPIO_SHIFT) 1049 #define NVM_CFG2_MNGM_SHIFT 13 /* Manageability Operation mode */ 1050 #define NVM_CFG2_MNGM_MASK (3U << NVM_CFG2_MNGM_SHIFT) 1051 #define NVM_CFG2_MNGM_DIS 0 1052 #define NVM_CFG2_MNGM_NCSI 1 1053 #define NVM_CFG2_MNGM_PT 2 1054 1055 #define NVM_COMPAT_SERDES_FORCE_MODE __BIT(14) /* Don't use autonego */ 1056 1057 #define NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM 0x0040 1058 1059 #define NVM_K1_CONFIG_ENABLE 0x01 1060 1061 #define NVM_SWDPIN_MASK 0xdf 1062 #define NVM_SWDPIN_SWDPIN_SHIFT 0 1063 #define NVM_SWDPIN_SWDPIO_SHIFT 8 1064 1065 #define NVM_3GIO_3_ASPM_MASK (0x3 << 2) /* Active State PM Support */ 1066 1067 #define NVM_CFG3_APME (1U << 10) 1068 #define NVM_CFG3_PORTA_EXT_MDIO (1U << 2) /* External MDIO Interface */ 1069 #define NVM_CFG3_PORTA_COM_MDIO (1U << 3) /* MDIO Interface is shared */ 1070 1071 #define NVM_OFF_MACADDR_82571(x) (3 * (x)) 1072 1073 /* 1074 * EEPROM Partitioning. See Table 6-1, "EEPROM Top Level Partitioning" 1075 * in 82580's datasheet. 1076 */ 1077 #define NVM_OFF_LAN_FUNC_82580(x) ((x) ? (0x40 + (0x40 * (x))) : 0) 1078 1079 #define NVM_COMBO_VER_OFF 0x0083 1080 1081 #define NVM_MAJOR_MASK 0xf000 1082 #define NVM_MAJOR_SHIFT 12 1083 #define NVM_MINOR_MASK 0x0ff0 1084 #define NVM_MINOR_SHIFT 4 1085 #define NVM_BUILD_MASK 0x000f 1086 #define NVM_UID_VALID 0x8000 1087 1088 /* iNVM Registers for i21[01] */ 1089 #define WM_INVM_DATA_REG(reg) (0x12120 + 4*(reg)) 1090 #define INVM_SIZE 64 /* Number of INVM Data Registers */ 1091 1092 /* iNVM default vaule */ 1093 #define NVM_INIT_CTRL_2_DEFAULT_I211 0x7243 1094 #define NVM_INIT_CTRL_4_DEFAULT_I211 0x00c1 1095 #define NVM_LED_1_CFG_DEFAULT_I211 0x0184 1096 #define NVM_LED_0_2_CFG_DEFAULT_I211 0x200c 1097 #define NVM_RESERVED_WORD 0xffff 1098 1099 #define INVM_DWORD_TO_RECORD_TYPE(dword) ((dword) & 0x7) 1100 #define INVM_DWORD_TO_WORD_ADDRESS(dword) (((dword) & 0x0000FE00) >> 9) 1101 #define INVM_DWORD_TO_WORD_DATA(dword) (((dword) & 0xFFFF0000) >> 16) 1102 1103 #define INVM_UNINITIALIZED_STRUCTURE 0x0 1104 #define INVM_WORD_AUTOLOAD_STRUCTURE 0x1 1105 #define INVM_CSR_AUTOLOAD_STRUCTURE 0x2 1106 #define INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE 0x3 1107 #define INVM_RSA_KEY_SHA256_STRUCTURE 0x4 1108 #define INVM_INVALIDATED_STRUCTURE 0xf 1109 1110 #define INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 1111 #define INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 1112 1113 #define INVM_DEFAULT_AL 0x202f 1114 #define INVM_AUTOLOAD 0x0a 1115 #define INVM_PLL_WO_VAL 0x0010 1116 1117 /* Version and Image Type field */ 1118 #define INVM_VER_1 __BITS(12,3) 1119 #define INVM_VER_2 __BITS(22,13) 1120 #define INVM_IMGTYPE __BITS(28,23) 1121 #define INVM_MINOR __BITS(3,0) 1122 #define INVM_MAJOR __BITS(9,4) 1123 1124 /* Word definitions for ID LED Settings */ 1125 #define ID_LED_RESERVED_FFFF 0xFFFF 1126 1127 /* ich8 flash control */ 1128 #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 1129 #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 1130 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 1131 #define ICH_FLASH_SEG_SIZE_256 256 1132 #define ICH_FLASH_SEG_SIZE_4K 4096 1133 #define ICH_FLASH_SEG_SIZE_64K 65536 1134 1135 #define ICH_CYCLE_READ 0x0 1136 #define ICH_CYCLE_RESERVED 0x1 1137 #define ICH_CYCLE_WRITE 0x2 1138 #define ICH_CYCLE_ERASE 0x3 1139 1140 #define ICH_FLASH_GFPREG 0x0000 1141 #define ICH_FLASH_HSFSTS 0x0004 /* Flash Status Register */ 1142 #define HSFSTS_DONE 0x0001 /* Flash Cycle Done */ 1143 #define HSFSTS_ERR 0x0002 /* Flash Cycle Error */ 1144 #define HSFSTS_DAEL 0x0004 /* Direct Access error Log */ 1145 #define HSFSTS_ERSZ_MASK 0x0018 /* Block/Sector Erase Size */ 1146 #define HSFSTS_ERSZ_SHIFT 3 1147 #define HSFSTS_FLINPRO 0x0020 /* flash SPI cycle in Progress */ 1148 #define HSFSTS_FLDVAL 0x4000 /* Flash Descriptor Valid */ 1149 #define HSFSTS_FLLK 0x8000 /* Flash Configuration Lock-Down */ 1150 #define ICH_FLASH_HSFCTL 0x0006 /* Flash control Register */ 1151 #define HSFCTL_GO 0x0001 /* Flash Cycle Go */ 1152 #define HSFCTL_CYCLE_MASK 0x0006 /* Flash Cycle */ 1153 #define HSFCTL_CYCLE_SHIFT 1 1154 #define HSFCTL_BCOUNT_MASK 0x0300 /* Data Byte Count */ 1155 #define HSFCTL_BCOUNT_SHIFT 8 1156 #define ICH_FLASH_FADDR 0x0008 1157 #define ICH_FLASH_FDATA0 0x0010 1158 #define ICH_FLASH_FRACC 0x0050 1159 #define ICH_FLASH_FREG0 0x0054 1160 #define ICH_FLASH_FREG1 0x0058 1161 #define ICH_FLASH_FREG2 0x005C 1162 #define ICH_FLASH_FREG3 0x0060 1163 #define ICH_FLASH_FPR0 0x0074 1164 #define ICH_FLASH_FPR1 0x0078 1165 #define ICH_FLASH_SSFSTS 0x0090 1166 #define ICH_FLASH_SSFCTL 0x0092 1167 #define ICH_FLASH_PREOP 0x0094 1168 #define ICH_FLASH_OPTYPE 0x0096 1169 #define ICH_FLASH_OPMENU 0x0098 1170 1171 #define ICH_FLASH_REG_MAPSIZE 0x00A0 1172 #define ICH_FLASH_SECTOR_SIZE 4096 1173 #define ICH_GFPREG_BASE_MASK 0x1FFF 1174 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 1175 1176 #define ICH_NVM_SIG_WORD 0x13 1177 #define ICH_NVM_SIG_MASK 0xc000 1178 #define ICH_NVM_VALID_SIG_MASK 0xc0 1179 #define ICH_NVM_SIG_VALUE 0x80 1180 1181 /* for PCI express Capability registers */ 1182 #define WM_PCIE_DCSR2_16MS 0x00000005 1183 1184 /* SFF SFP ROM data */ 1185 #define SFF_SFP_ID_OFF 0x00 1186 #define SFF_SFP_ID_UNKNOWN 0x00 /* Unknown */ 1187 #define SFF_SFP_ID_SFF 0x02 /* Module soldered to motherboard */ 1188 #define SFF_SFP_ID_SFP 0x03 /* SFP transceiver */ 1189 1190 #define SFF_SFP_ETH_FLAGS_OFF 0x06 1191 #define SFF_SFP_ETH_FLAGS_1000SX 0x01 1192 #define SFF_SFP_ETH_FLAGS_1000LX 0x02 1193 #define SFF_SFP_ETH_FLAGS_1000CX 0x04 1194 #define SFF_SFP_ETH_FLAGS_1000T 0x08 1195 #define SFF_SFP_ETH_FLAGS_100FX 0x10 1196 1197 /* I21[01] PHY related definitions */ 1198 #define GS40G_PAGE_SELECT 0x16 1199 #define GS40G_PAGE_SHIFT 16 1200 #define GS40G_OFFSET_MASK 0xffff 1201 #define GS40G_PHY_PLL_FREQ_PAGE 0xfc0000 1202 #define GS40G_PHY_PLL_FREQ_REG 0x000e 1203 #define GS40G_PHY_PLL_UNCONF 0xff 1204 1205 /* advanced TX descriptor for 82575 and newer */ 1206 typedef union nq_txdesc { 1207 struct { 1208 uint64_t nqtxd_addr; 1209 uint32_t nqtxd_cmdlen; 1210 uint32_t nqtxd_fields; 1211 } nqtx_data; 1212 struct { 1213 uint32_t nqtxc_vl_len; 1214 uint32_t nqtxc_sn; 1215 uint32_t nqtxc_cmd; 1216 uint32_t nqtxc_mssidx; 1217 } nqrx_ctx; 1218 } __packed nq_txdesc_t; 1219 1220 1221 /* Commands for nqtxd_cmdlen and nqtxc_cmd */ 1222 #define NQTX_CMD_EOP (1U << 24) /* end of packet */ 1223 #define NQTX_CMD_IFCS (1U << 25) /* insert FCS */ 1224 #define NQTX_CMD_RS (1U << 27) /* report status */ 1225 #define NQTX_CMD_DEXT (1U << 29) /* descriptor extension */ 1226 #define NQTX_CMD_VLE (1U << 30) /* VLAN enable */ 1227 #define NQTX_CMD_TSE (1U << 31) /* TCP segmentation enable */ 1228 1229 /* Descriptor types (if DEXT is set) */ 1230 #define NQTX_DTYP_C (2U << 20) /* context */ 1231 #define NQTX_DTYP_D (3U << 20) /* data */ 1232 1233 #define NQTXD_FIELDS_IDX_SHIFT 4 /* context index shift */ 1234 #define NQTXD_FIELDS_IDX_MASK 0xf 1235 #define NQTXD_FIELDS_PAYLEN_SHIFT 14 /* payload len shift */ 1236 #define NQTXD_FIELDS_PAYLEN_MASK 0x3ffff 1237 1238 #define NQTXD_FIELDS_IXSM (1U << 8) /* do IP checksum */ 1239 #define NQTXD_FIELDS_TUXSM (1U << 9) /* do TCP/UDP checksum */ 1240 1241 #define NQTXC_VLLEN_IPLEN_SHIFT 0 /* IP header len */ 1242 #define NQTXC_VLLEN_IPLEN_MASK 0x1ff 1243 #define NQTXC_VLLEN_MACLEN_SHIFT 9 /* MAC header len */ 1244 #define NQTXC_VLLEN_MACLEN_MASK 0x7f 1245 #define NQTXC_VLLEN_VLAN_SHIFT 16 /* vlan number */ 1246 #define NQTXC_VLLEN_VLAN_MASK 0xffff 1247 1248 #define NQTXC_CMD_MKRLOC_SHIFT 0 /* IP checksum offset */ 1249 #define NQTXC_CMD_MKRLOC_MASK 0x1ff 1250 #define NQTXC_CMD_SNAP (1U << 9) 1251 #define NQTXC_CMD_IP4 (1U << 10) 1252 #define NQTXC_CMD_IP6 (0U << 10) 1253 #define NQTXC_CMD_TCP (1U << 11) 1254 #define NQTXC_CMD_UDP (0U << 11) 1255 #define NQTXC_MSSIDX_IDX_SHIFT 4 /* context index shift */ 1256 #define NQTXC_MSSIDX_IDX_MASK 0xf 1257 #define NQTXC_MSSIDX_L4LEN_SHIFT 8 /* L4 header len shift */ 1258 #define NQTXC_MSSIDX_L4LEN_MASK 0xff 1259 #define NQTXC_MSSIDX_MSS_SHIFT 16 /* MSS */ 1260 #define NQTXC_MSSIDX_MSS_MASK 0xffff 1261
Indexes created Sun Oct 19 16:10:00 GMT 2025