if_wmreg.h revision 1.99
1 /* $NetBSD: if_wmreg.h,v 1.99 2017/06/26 04:09:02 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /****************************************************************************** 39 40 Copyright (c) 2001-2012, Intel Corporation 41 All rights reserved. 42 43 Redistribution and use in source and binary forms, with or without 44 modification, are permitted provided that the following conditions are met: 45 46 1. Redistributions of source code must retain the above copyright notice, 47 this list of conditions and the following disclaimer. 48 49 2. Redistributions in binary form must reproduce the above copyright 50 notice, this list of conditions and the following disclaimer in the 51 documentation and/or other materials provided with the distribution. 52 53 3. Neither the name of the Intel Corporation nor the names of its 54 contributors may be used to endorse or promote products derived from 55 this software without specific prior written permission. 56 57 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 58 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 61 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 POSSIBILITY OF SUCH DAMAGE. 68 69 ******************************************************************************/ 70 71 /* 72 * Register description for the Intel i82542 (``Wiseman''), 73 * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit 74 * Ethernet chips. 75 */ 76 77 /* 78 * The wiseman supports 64-bit PCI addressing. This structure 79 * describes the address in descriptors. 80 */ 81 typedef struct wiseman_addr { 82 uint32_t wa_low; /* low-order 32 bits */ 83 uint32_t wa_high; /* high-order 32 bits */ 84 } __packed wiseman_addr_t; 85 86 /* 87 * The Wiseman receive descriptor. 88 * 89 * The receive descriptor ring must be aligned to a 4K boundary, 90 * and there must be an even multiple of 8 descriptors in the ring. 91 */ 92 typedef struct wiseman_rxdesc { 93 volatile wiseman_addr_t wrx_addr; /* buffer address */ 94 95 volatile uint16_t wrx_len; /* buffer length */ 96 volatile uint16_t wrx_cksum; /* checksum (starting at PCSS)*/ 97 98 volatile uint8_t wrx_status; /* Rx status */ 99 volatile uint8_t wrx_errors; /* Rx errors */ 100 volatile uint16_t wrx_special; /* special field (VLAN, etc.) */ 101 } __packed wiseman_rxdesc_t; 102 103 /* wrx_status bits */ 104 #define WRX_ST_DD (1U << 0) /* descriptor done */ 105 #define WRX_ST_EOP (1U << 1) /* end of packet */ 106 #define WRX_ST_IXSM (1U << 2) /* ignore checksum indication */ 107 #define WRX_ST_VP (1U << 3) /* VLAN packet */ 108 #define WRX_ST_BPDU (1U << 4) /* ??? */ 109 #define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */ 110 #define WRX_ST_IPCS (1U << 6) /* IP checksum performed */ 111 #define WRX_ST_PIF (1U << 7) /* passed in-exact filter */ 112 113 /* wrx_error bits */ 114 #define WRX_ER_CE (1U << 0) /* CRC error */ 115 #define WRX_ER_SE (1U << 1) /* symbol error */ 116 #define WRX_ER_SEQ (1U << 2) /* sequence error */ 117 #define WRX_ER_ICE (1U << 3) /* ??? */ 118 #define WRX_ER_CXE (1U << 4) /* carrier extension error */ 119 #define WRX_ER_TCPE (1U << 5) /* TCP checksum error */ 120 #define WRX_ER_IPE (1U << 6) /* IP checksum error */ 121 #define WRX_ER_RXE (1U << 7) /* Rx data error */ 122 123 /* wrx_special field for VLAN packets */ 124 #define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */ 125 #define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */ 126 #define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */ 127 128 /* extended RX descriptor for 82574 */ 129 typedef union ext_rxdesc { 130 struct { 131 uint64_t erxd_addr; /* Packet Buffer Address */ 132 uint64_t erxd_dd; /* 63:1 reserved, 0 DD */ 133 } erx_data; 134 struct { 135 uint32_t erxc_mrq; /* 136 * 31:13 reserved 137 * 12:8 Rx queue associated with the packet 138 * 7:4 reserved 3:0 RSS Type 139 */ 140 uint32_t erxc_rsshash; /* RSS Hash or {Fragment Checksum, IP identification } */ 141 uint32_t erxc_err_stat; /* 31:20 Extended Error, 19:0 Extened Status */ 142 uint16_t erxc_pktlen; /* PKT_LEN */ 143 uint16_t erxc_vlan; /* VLAN Tag */ 144 } erx_ctx; 145 } __packed ext_rxdesc_t; 146 147 #define EXTRXD_DD_MASK __BIT(0) 148 149 /* 150 * erxc_rsshash is used for below 2 patterns 151 * (1) Fragment Checksum and IP identification 152 * - Fragment Checksum is valid 153 * when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set 154 * - IP identification is valid 155 * when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set 156 * (2) RSS Hash 157 * when RXCSUM.PCSD bit is set 158 */ 159 #define EXTRXC_IP_ID_MASK __BITS(15,0) 160 #define EXTRXC_FRAG_CSUM_MASK __BITS(31,16) 161 #define EXTRXC_IP_ID(rsshash) __SHIFTOUT(rsshash,ERXC_IP_ID_MASK) 162 #define EXTRXC_FRAG_CSUM(rsshash) __SHIFTOUT(rsshash,ERXC_FRAG_CSUM_MASK) 163 164 /* macros for nrxc_mrq */ 165 #define EXTRXC_RSS_TYPE_MASK __BITS(3,0) 166 /* __BITS(7,4) is reserved */ 167 #define EXTRXC_QUEUE_MASK __BITS(12,8) 168 /* __BITS(31,13) is reserved */ 169 #define EXTRXC_RSS_TYPE(mrq) __SHIFTOUT(mrq,EXTRXC_RSS_TYPE_MASK) 170 #define EXTRXC_QUEUE(mrq) __SHIFTOUT(mrq,EXTRXC_QUEUE_MASK) 171 172 #define EXTRXC_RSS_TYPE_NONE 0x0 /* No hash computation done. */ 173 #define EXTRXC_RSS_TYPE_TCP_IPV4 0x1 174 #define EXTRXC_RSS_TYPE_IPV4 0x2 175 #define EXTRXC_RSS_TYPE_TCP_IPV6 0x3 176 #define EXTRXC_RSS_TYPE_IPV6_EX 0x4 177 #define EXTRXC_RSS_TYPE_IPV6 0x5 178 /*0x6:0xF is reserved. */ 179 180 #define EXTRXC_STATUS_MASK __BITS(19,0) 181 #define EXTRXC_ERROR_MASK __BITS(31,20) 182 #define EXTRXC_STATUS(err_stat) __SHIFTOUT(err_stat,EXTRXC_STATUS_MASK) 183 #define EXTRXC_ERROR(err_stat) __SHIFTOUT(err_stat,EXTRXC_ERROR_MASK) 184 185 /* 3:0 is reserved. */ 186 #define EXTRXC_ERROR_CE __BIT(4) /* The same as WRX_ER_CE. */ 187 #define EXTRXC_ERROR_SE __BIT(5) /* The same as WRX_ER_SE. */ 188 #define EXTRXC_ERROR_SEQ __BIT(6) /* The same as WRX_ER_SEQ. */ 189 /* 7 is reserved. */ 190 #define EXTRXC_ERROR_CXE __BIT(8) /* The same as WRX_ER_CXE. */ 191 #define EXTRXC_ERROR_TCPE __BIT(9) /* The same as WRX_ER_TCPE. */ 192 #define EXTRXC_ERROR_IPE __BIT(10) /* The same as WRX_ER_IPE. */ 193 #define EXTRXC_ERROR_RXE __BIT(11) /* The same as WRX_ER_RXE. */ 194 195 #define EXTRXC_STATUS_DD __BIT(0) /* The same as WRX_ST_DD. */ 196 #define EXTRXC_STATUS_EOP __BIT(1) /* The same as WRX_ST_EOP. */ 197 /* 2 is reserved. */ 198 #define EXTRXC_STATUS_VP __BIT(3) /* The same as WRX_ST_VP. */ 199 #define EXTRXC_STATUS_UDPCS __BIT(4) /* UDP checksum calculated on packet. */ 200 #define EXTRXC_STATUS_TCPCS __BIT(5) /* The same as WRX_ST_TCPCS. */ 201 #define EXTRXC_STATUS_IPCS __BIT(6) /* The same as WRX_ST_IPCS. */ 202 /* 7 is reserved. */ 203 #define EXTRXC_STATUS_TST __BIT(8) /* Time stamp taken. */ 204 #define EXTRXC_STATUS_IPIDV __BIT(9) /* IP identification valid. */ 205 #define EXTRXC_STATUS_UDPV __BIT(10) /* Valid UDP XSUM. */ 206 /* 14:11 is reserved. */ 207 #define EXTRXC_STATUS_ACK __BIT(15) /* ACK packet indication. */ 208 #define EXTRXC_STATUS_PKTTYPE_MASK __BITS(19,16) 209 #define EXTRXC_STATUS_PKTTYPE(status) __SHIFTOUT(status,EXTRXC_STATUS_PKTTYPE_MASK) 210 211 /* advanced RX descriptor for 82575 and newer */ 212 typedef union nq_rxdesc { 213 struct { 214 uint64_t nrxd_paddr; /* 63:1 Packet Buffer Address, 0 A0/NSE */ 215 uint64_t nrxd_haddr; /* 63:1 HEader Buffer Address, 0 DD */ 216 } nqrx_data; 217 struct { 218 uint32_t nrxc_misc; /* 219 * 31: SPH, 30:21 HDR_LEN[9:0], 220 * 20:19 HDR_LEN[11:10], 18:17 RSV, 221 * 16:4 Packet Type 3:0 RSS Type 222 */ 223 uint32_t nrxc_rsshash; /* RSS Hash or {Fragment Checksum, IP identification } */ 224 uint32_t nrxc_err_stat; /* 31:20 Extended Error, 19:0 Extened Status */ 225 uint16_t nrxc_pktlen; /* PKT_LEN */ 226 uint16_t nrxc_vlan; /* VLAN Tag */ 227 } nqrx_ctx; 228 } __packed nq_rxdesc_t; 229 230 /* for nrxd_paddr macros */ 231 #define NQRXD_A0_MASK __BIT(0) 232 #define NQRXD_NSE_MASK __BIT(0) 233 #define NQRXD_ADDR_MASK __BITS(63,1) 234 /* for nrxd_haddr macros */ 235 #define NQRXD_DD_MASK __BIT(0) 236 237 /* 238 * nrxc_rsshash is used for below 2 patterns 239 * (1) Fragment Checksum and IP identification 240 * - Fragment Checksum is valid 241 * when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set 242 * - IP identification is valid 243 * when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set 244 * (2) RSS Hash 245 * when RXCSUM.PCSD bit is set 246 */ 247 #define NQRXC_IP_ID_MASK __BITS(15,0) 248 #define NQRXC_FRAG_CSUM_MASK __BITS(31,16) 249 #define NQRXC_IP_ID(rsshash) __SHIFTOUT(rsshash,NRXC_IP_ID_MASK) 250 #define NQRXC_FRAG_CSUM(rsshash) __SHIFTOUT(rsshash,NRXC_FRAG_CSUM_MASK) 251 252 /* macros for nrxc_misc */ 253 #define NQRXC_RSS_TYPE_MASK __BITS(3,0) 254 #define NQRXC_PKT_TYPE_ID_MASK __BITS(11,4) 255 #define NQRXC_PKT_TYPE_ETQF_INDEX_MASK __BITS(11,4) 256 #define NQRXC_PKT_TYPE_ETQF_VALID_MASK __BIT(15) 257 #define NQRXC_PKT_TYPE_VLAN_MASK __BIT(16) 258 #define NQRXC_PKT_TYPE_MASK __BITS(16,4) 259 /* __BITS(18,17) is reserved */ 260 #define NQRXC_HDRLEN_HIGH_MASK __BITS(20,19) 261 #define NQRXC_HDRLEN_LOW_MASK __BITS(30,21) 262 #define NQRXC_SPH_MASK __BIT(31) 263 264 #define NQRXC_RSS_TYPE(misc) __SHIFTOUT(misc,NQRXC_RSS_TYPE_MASK) 265 #define NQRXC_PKT_TYPE_ID(pkttype) \ 266 __SHIFTOUT(pkttype,NQRXC_PKT_TYPE_ID_MASK) 267 #define NQRXC_PKT_TYPE(misc) __SHIFTOUT(misc,NQRXC_PKT_TYPE_MASK) 268 #define NQRXC_PKT_TYPE_ETQF_INDEX(pkttype) \ 269 __SHIFTOUT(pkttype,NQRXC_PKT_TYPE_ETQF_INDEX_MASK) 270 #define NQRXC_PKT_TYPE_ETQF_VALID NQRXC_PKT_TYPE_ETQF_VALID_MASK 271 #define NQRXC_PKT_TYPE_VLAN NQRXC_PKT_TYPE_VLAN_MASK 272 #define NQRXC_HEADER_LEN(misc) (__SHIFTOUT(misc,NQRXC_HDRLEN_LOW_MASK) \ 273 | __SHIFTOUT(misc,NQRXC_HDRLEN_HIGH_MASK) << 10) 274 #define NQRXC_SPH NQRXC_SPH_MASK 275 276 #define NQRXC_RSS_TYPE_NONE 0x0 /* No hash computation done. */ 277 #define NQRXC_RSS_TYPE_TCP_IPV4 0x1 278 #define NQRXC_RSS_TYPE_IPV4 0x2 279 #define NQRXC_RSS_TYPE_TCP_IPV6 0x3 280 #define NQRXC_RSS_TYPE_IPV6_EX 0x4 281 #define NQRXC_RSS_TYPE_IPV6 0x5 282 #define NQRXC_RSS_TYPE_TCP_IPV6_EX 0x6 283 #define NQRXC_RSS_TYPE_UDP_IPV4 0x7 284 #define NQRXC_RSS_TYPE_UDP_IPV6 0x8 285 #define NQRXC_RSS_TYPE_UDP_IPV6_EX 0x9 286 /*0xA:0xF is reserved. */ 287 288 #define NQRXC_PKT_TYPE_IPV4 __BIT(0) 289 #define NQRXC_PKT_TYPE_IPV4E __BIT(1) 290 #define NQRXC_PKT_TYPE_IPV6 __BIT(2) 291 #define NQRXC_PKT_TYPE_IPV6E __BIT(3) 292 #define NQRXC_PKT_TYPE_TCP __BIT(4) 293 #define NQRXC_PKT_TYPE_UDP __BIT(5) 294 #define NQRXC_PKT_TYPE_SCTP __BIT(6) 295 #define NQRXC_PKT_TYPE_NFS __BIT(7) 296 297 #define NQRXC_STATUS_MASK __BITS(19,0) 298 #define NQRXC_ERROR_MASK __BITS(31,20) 299 #define NQRXC_STATUS(err_stat) __SHIFTOUT(err_stat,NQRXC_STATUS_MASK) 300 #define NQRXC_ERROR(err_stat) __SHIFTOUT(err_stat,NQRXC_ERROR_MASK) 301 302 /* 2:0 is reserved. */ 303 #define NQRXC_ERROR_HB0 __BIT(3) /* Header Buffer Overflow. */ 304 /* 6:4 is reserved. */ 305 /* 8:7 is reserved. */ 306 #define NQRXC_ERROR_L4E __BIT(9) /* L4 error indication. */ 307 #define NQRXC_ERROR_IPE __BIT(10) /* The same as WRX_ER_IPE. */ 308 #define NQRXC_ERROR_RXE __BIT(11) /* The same as WRX_ER_RXE. */ 309 /* XXX Where is WRX_ER_CE, WRX_ER_SE, WRX_ER_SEQ, WRX_ER_CXE error? */ 310 311 #define NQRXC_STATUS_DD __BIT(0) /* The same as WRX_ST_DD. */ 312 #define NQRXC_STATUS_EOP __BIT(1) /* The same as WRX_ST_EOP. */ 313 /* 2 is reserved */ 314 #define NQRXC_STATUS_VP __BIT(3) /* The same as WRX_ST_VP. */ 315 #define NQRXC_STATUS_UDPCS __BIT(4) /* UDP checksum or IP payload checksum. */ 316 /* XXX in I210 spec, this bit is the same as WRX_ST_BPDU(is "???" comment) */ 317 #define NQRXC_STATUS_L4I __BIT(5) /* L4 integrity check was done. */ 318 #define NQRXC_STATUS_IPCS __BIT(6) /* The same as WRX_ST_IPCS. */ 319 #define NQRXC_STATUS_PIF __BIT(7) /* The same as WRX_ST_PIF. */ 320 /* 8 is reserved */ 321 #define NQRXC_STATUS_VEXT __BIT(9) /* First VLAN is found on a bouble VLAN packet. */ 322 #define NQRXC_STATUS_UDPV __BIT(10) /* The packet contains a valid checksum field in a first fragment UDP IPv4 packet. */ 323 #define NQRXC_STATUS_LLINT __BIT(11) /* The packet caused an immediate interrupt. */ 324 #define NQRXC_STATUS_STRIPCRC __BIT(12) /* Ethernet CRC is stripped. */ 325 /* 14:13 is reserved */ 326 #define NQRXC_STATUS_TSIP __BIT(15) /* Timestamp in packet. */ 327 #define NQRXC_STATUS_TS __BIT(16) /* Time stamped packet. */ 328 /* 17 is reserved */ 329 #define NQRXC_STATUS_LB __BIT(18) /* Sent by a local virtual machine (VM to VM switch indication). */ 330 #define NQRXC_STATUS_MC __BIT(19) /* Packet received from Manageability Controller */ 331 /* "MBC" in i350 spec */ 332 333 /* 334 * The Wiseman transmit descriptor. 335 * 336 * The transmit descriptor ring must be aligned to a 4K boundary, 337 * and there must be an even multiple of 8 descriptors in the ring. 338 */ 339 typedef struct wiseman_tx_fields { 340 uint8_t wtxu_status; /* Tx status */ 341 uint8_t wtxu_options; /* options */ 342 uint16_t wtxu_vlan; /* VLAN info */ 343 } __packed wiseman_txfields_t; 344 typedef struct wiseman_txdesc { 345 wiseman_addr_t wtx_addr; /* buffer address */ 346 uint32_t wtx_cmdlen; /* command and length */ 347 wiseman_txfields_t wtx_fields; /* fields; see below */ 348 } __packed wiseman_txdesc_t; 349 350 /* Commands for wtx_cmdlen */ 351 #define WTX_CMD_EOP (1U << 24) /* end of packet */ 352 #define WTX_CMD_IFCS (1U << 25) /* insert FCS */ 353 #define WTX_CMD_RS (1U << 27) /* report status */ 354 #define WTX_CMD_RPS (1U << 28) /* report packet sent */ 355 #define WTX_CMD_DEXT (1U << 29) /* descriptor extension */ 356 #define WTX_CMD_VLE (1U << 30) /* VLAN enable */ 357 #define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */ 358 359 /* Descriptor types (if DEXT is set) */ 360 #define WTX_DTYP_C (0U << 20) /* context */ 361 #define WTX_DTYP_D (1U << 20) /* data */ 362 363 /* wtx_fields status bits */ 364 #define WTX_ST_DD (1U << 0) /* descriptor done */ 365 #define WTX_ST_EC (1U << 1) /* excessive collisions */ 366 #define WTX_ST_LC (1U << 2) /* late collision */ 367 #define WTX_ST_TU (1U << 3) /* transmit underrun */ 368 369 /* wtx_fields option bits for IP/TCP/UDP checksum offload */ 370 #define WTX_IXSM (1U << 0) /* IP checksum offload */ 371 #define WTX_TXSM (1U << 1) /* TCP/UDP checksum offload */ 372 373 /* Maximum payload per Tx descriptor */ 374 #define WTX_MAX_LEN 4096 375 376 /* 377 * The Livengood TCP/IP context descriptor. 378 */ 379 struct livengood_tcpip_ctxdesc { 380 uint32_t tcpip_ipcs; /* IP checksum context */ 381 uint32_t tcpip_tucs; /* TCP/UDP checksum context */ 382 uint32_t tcpip_cmdlen; 383 uint32_t tcpip_seg; /* TCP segmentation context */ 384 }; 385 386 /* commands for context descriptors */ 387 #define WTX_TCPIP_CMD_TCP (1U << 24) /* 1 = TCP, 0 = UDP */ 388 #define WTX_TCPIP_CMD_IP (1U << 25) /* 1 = IPv4, 0 = IPv6 */ 389 #define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */ 390 391 #define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */ 392 #define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */ 393 #define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */ 394 395 #define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */ 396 #define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */ 397 #define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */ 398 399 #define WTX_TCPIP_SEG_STATUS(x) ((x) << 0) 400 #define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8) 401 #define WTX_TCPIP_SEG_MSS(x) ((x) << 16) 402 403 /* 404 * PCI config registers used by the Wiseman. 405 */ 406 #define WM_PCI_MMBA PCI_MAPREG_START 407 /* registers for FLASH access on ICH8 */ 408 #define WM_ICH8_FLASH 0x0014 409 410 #define WM_PCI_LTR_CAP_LPT 0xa8 411 412 /* XXX Only for PCH_SPT? */ 413 #define WM_PCI_DESCRING_STATUS 0xe4 414 #define DESCRING_STATUS_FLUSH_REQ __BIT(8) 415 416 /* 417 * Wiseman Control/Status Registers. 418 */ 419 #define WMREG_CTRL 0x0000 /* Device Control Register */ 420 #define CTRL_FD (1U << 0) /* full duplex */ 421 #define CTRL_BEM (1U << 1) /* big-endian mode */ 422 #define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */ 423 #define CTRL_GIO_M_DIS (1U << 2) /* disabl PCI master access */ 424 #define CTRL_LRST (1U << 3) /* link reset */ 425 #define CTRL_ASDE (1U << 5) /* auto speed detect enable */ 426 #define CTRL_SLU (1U << 6) /* set link up */ 427 #define CTRL_ILOS (1U << 7) /* invert loss of signal */ 428 #define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */ 429 #define CTRL_SPEED_10 CTRL_SPEED(0) 430 #define CTRL_SPEED_100 CTRL_SPEED(1) 431 #define CTRL_SPEED_1000 CTRL_SPEED(2) 432 #define CTRL_SPEED_MASK CTRL_SPEED(3) 433 #define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */ 434 #define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */ 435 #define CTRL_D_UD_EN (1U << 13) /* Dock/Undock enable */ 436 #define CTRL_D_UD_POL (1U << 14) /* Defined polarity of Dock/Undock indication in SDP[0] */ 437 #define CTRL_F_PHY_R (1U << 15) /* Reset both PHY ports, through PHYRST_N pin */ 438 #define CTRL_EXT_LINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */ 439 #define CTRL_LANPHYPC_OVERRIDE (1U << 16) /* SW control of LANPHYPC */ 440 #define CTRL_LANPHYPC_VALUE (1U << 17) /* SW value of LANPHYPC */ 441 #define CTRL_SWDPINS_SHIFT 18 442 #define CTRL_SWDPINS_MASK 0x0f 443 #define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x))) 444 #define CTRL_SWDPIO_SHIFT 22 445 #define CTRL_SWDPIO_MASK 0x0f 446 #define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x))) 447 #define CTRL_MEHE (1U << 19) /* Memory Error Handling Enable(I217)*/ 448 #define CTRL_RST (1U << 26) /* device reset */ 449 #define CTRL_RFCE (1U << 27) /* Rx flow control enable */ 450 #define CTRL_TFCE (1U << 28) /* Tx flow control enable */ 451 #define CTRL_VME (1U << 30) /* VLAN Mode Enable */ 452 #define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */ 453 454 #define WMREG_CTRL_SHADOW 0x0004 /* Device Control Register (shadow) */ 455 456 #define WMREG_STATUS 0x0008 /* Device Status Register */ 457 #define STATUS_FD (1U << 0) /* full duplex */ 458 #define STATUS_LU (1U << 1) /* link up */ 459 #define STATUS_TCKOK (1U << 2) /* Tx clock running */ 460 #define STATUS_RBCOK (1U << 3) /* Rx clock running */ 461 #define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */ 462 #define STATUS_FUNCID_MASK 3 /* ... */ 463 #define STATUS_TXOFF (1U << 4) /* Tx paused */ 464 #define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */ 465 #define STATUS_SPEED __BITS(7, 6) /* speed indication */ 466 #define STATUS_SPEED_10 0 467 #define STATUS_SPEED_100 1 468 #define STATUS_SPEED_1000 2 469 #define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */ 470 #define STATUS_LAN_INIT_DONE (1U << 9) /* Lan Init Completion by NVM */ 471 #define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */ 472 #define STATUS_PHYRA (1U << 10) /* PHY Reset Asserted (PCH) */ 473 #define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */ 474 #define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */ 475 #define STATUS_2P5_SKU __BIT(12) /* Value of the 2.5GBE SKU strap */ 476 #define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */ 477 #define STATUS_2P5_SKU_OVER __BIT(13) /* Value of the 2.5GBE SKU override */ 478 #define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */ 479 #define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0) 480 #define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1) 481 #define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2) 482 #define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3) 483 #define STATUS_GIO_M_ENA (1U << 19) /* GIO master enable */ 484 #define STATUS_DEV_RST_SET (1U << 20) /* Device Reset Set */ 485 486 /* Strapping Option Register (PCH_SPT and newer) */ 487 #define WMREG_STRAP 0x000c 488 #define STRAP_NVMSIZE __BITS(1, 6) 489 #define STRAP_FREQ __BITS(12, 13) 490 #define STRAP_SMBUSADDR __BITS(17, 23) 491 492 #define WMREG_EECD 0x0010 /* EEPROM Control Register */ 493 #define EECD_SK (1U << 0) /* clock */ 494 #define EECD_CS (1U << 1) /* chip select */ 495 #define EECD_DI (1U << 2) /* data in */ 496 #define EECD_DO (1U << 3) /* data out */ 497 #define EECD_FWE(x) ((x) << 4) /* flash write enable control */ 498 #define EECD_FWE_DISABLED EECD_FWE(1) 499 #define EECD_FWE_ENABLED EECD_FWE(2) 500 #define EECD_EE_REQ (1U << 6) /* (shared) EEPROM request */ 501 #define EECD_EE_GNT (1U << 7) /* (shared) EEPROM grant */ 502 #define EECD_EE_PRES (1U << 8) /* EEPROM present */ 503 #define EECD_EE_SIZE (1U << 9) /* EEPROM size 504 (0 = 64 word, 1 = 256 word) */ 505 #define EECD_EE_AUTORD (1U << 9) /* auto read done */ 506 #define EECD_EE_ABITS (1U << 10) /* EEPROM address bits 507 (based on type) */ 508 #define EECD_EE_SIZE_EX_MASK __BITS(14,11) /* EEPROM size for new devices */ 509 #define EECD_EE_TYPE (1U << 13) /* EEPROM type 510 (0 = Microwire, 1 = SPI) */ 511 #define EECD_SEC1VAL (1U << 22) /* Sector One Valid */ 512 #define EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */ 513 514 #define WMREG_EERD 0x0014 /* EEPROM read */ 515 #define EERD_DONE 0x02 /* done bit */ 516 #define EERD_START 0x01 /* First bit for telling part to start operation */ 517 #define EERD_ADDR_SHIFT 2 /* Shift to the address bits */ 518 #define EERD_DATA_SHIFT 16 /* Offset to data in EEPROM read/write registers */ 519 520 #define WMREG_FEXTNVM6 0x0010 /* Future Extended NVM 6 */ 521 #define FEXTNVM6_K1_OFF_ENABLE __BIT(31) 522 523 #define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */ 524 #define CTRL_EXT_NSICR __BIT(0) /* Non Interrupt clear on read */ 525 #define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */ 526 #define CTRL_EXT_NVMVS __BITS(0, 1) /* NVM valid sector */ 527 #define CTRL_EXT_LPCD __BIT(2) /* LCD Power Cycle Done */ 528 #define CTRL_EXT_SWDPINS_SHIFT 4 529 #define CTRL_EXT_SWDPINS_MASK 0x0d 530 /* The bit order of the SW Definable pin is not 6543 but 3654! */ 531 #define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT \ 532 + ((x) == 3 ? 3 : ((x) - 4)))) 533 #define CTRL_EXT_SWDPIO_SHIFT 8 534 #define CTRL_EXT_SWDPIO_MASK 0x0d 535 #define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT \ 536 + ((x) == 3 ? 3 : ((x) - 4)))) 537 #define CTRL_EXT_FORCE_SMBUS __BIT(11) /* Force SMBus mode */ 538 #define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */ 539 #define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */ 540 #define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */ 541 #define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */ 542 #define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */ 543 #define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */ 544 #define CTRL_EXT_SDLPE (1U << 18) /* SerDes Low Power Enable */ 545 #define CTRL_EXT_DMA_DYN_CLK (1U << 19) /* DMA Dynamic Gating Enable */ 546 #define CTRL_EXT_PHYPDEN __BIT(20) 547 #define CTRL_EXT_LINK_MODE_MASK 0x00C00000 548 #define CTRL_EXT_LINK_MODE_GMII 0x00000000 549 #define CTRL_EXT_LINK_MODE_KMRN 0x00000000 550 #define CTRL_EXT_LINK_MODE_1000KX 0x00400000 551 #define CTRL_EXT_LINK_MODE_SGMII 0x00800000 552 #define CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 553 #define CTRL_EXT_LINK_MODE_TBI 0x00C00000 554 #define CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 555 #define CTRL_EXT_EIAME __BIT(24) /* Extended Interrupt Auto Mask En */ 556 #define CTRL_EXT_I2C_ENA 0x02000000 /* I2C enable */ 557 #define CTRL_EXT_DRV_LOAD 0x10000000 558 #define CTRL_EXT_PBA __BIT(31) /* PBA Support */ 559 560 #define WMREG_MDIC 0x0020 /* MDI Control Register */ 561 #define MDIC_DATA(x) ((x) & 0xffff) 562 #define MDIC_REGADD(x) ((x) << 16) 563 #define MDIC_PHY_SHIFT 21 564 #define MDIC_PHY_MASK __BITS(25, 21) 565 #define MDIC_PHYADD(x) ((x) << 21) 566 #define MDIC_OP_WRITE (1U << 26) 567 #define MDIC_OP_READ (2U << 26) 568 #define MDIC_READY (1U << 28) 569 #define MDIC_I (1U << 29) /* interrupt on MDI complete */ 570 #define MDIC_E (1U << 30) /* MDI error */ 571 #define MDIC_DEST (1U << 31) /* Destination */ 572 573 #define WMREG_SCTL 0x0024 /* SerDes Control - RW */ 574 /* 575 * These 4 macros are also used for other 8bit control registers on the 576 * 82575 577 */ 578 #define SCTL_CTL_READY (1U << 31) 579 #define SCTL_CTL_DATA_MASK 0x000000ff 580 #define SCTL_CTL_ADDR_SHIFT 8 581 #define SCTL_CTL_POLL_TIMEOUT 640 582 #define SCTL_DISABLE_SERDES_LOOPBACK 0x0400 583 584 #define WMREG_FEXTNVM4 0x0024 /* Future Extended NVM 4 - RW */ 585 #define FEXTNVM4_BEACON_DURATION __BITS(2, 0) 586 #define FEXTNVM4_BEACON_DURATION_8US 0x7 587 #define FEXTNVM4_BEACON_DURATION_16US 0x3 588 589 #define WMREG_FCAL 0x0028 /* Flow Control Address Low */ 590 #define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */ 591 592 #define WMREG_FCAH 0x002c /* Flow Control Address High */ 593 #define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */ 594 595 #define WMREG_FCT 0x0030 /* Flow Control Type */ 596 597 #define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */ 598 #define KUMCTRLSTA_MASK 0x0000FFFF 599 #define KUMCTRLSTA_OFFSET 0x001F0000 600 #define KUMCTRLSTA_OFFSET_SHIFT 16 601 #define KUMCTRLSTA_REN 0x00200000 602 603 #define KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 604 #define KUMCTRLSTA_OFFSET_CTRL 0x00000001 605 #define KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 606 #define KUMCTRLSTA_OFFSET_DIAG 0x00000003 607 #define KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 608 #define KUMCTRLSTA_OFFSET_K1_CONFIG 0x00000007 609 #define KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 610 #define KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 611 #define KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E 612 #define KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F 613 614 /* FIFO Control */ 615 #define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 616 #define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 617 618 /* In-Band Control */ 619 #define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500 620 #define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 621 622 /* Diag */ 623 #define KUMCTRLSTA_DIAG_NELPBK 0x1000 624 625 /* K1 Config */ 626 #define KUMCTRLSTA_K1_ENABLE 0x0002 627 628 /* Half-Duplex Control */ 629 #define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 630 #define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 631 632 #define WMREG_VET 0x0038 /* VLAN Ethertype */ 633 #define WMREG_MDPHYA 0x003C /* PHY address - RW */ 634 635 #define WMREG_FEXTNVM3 0x003c /* Future Extended NVM 3 */ 636 #define FEXTNVM3_PHY_CFG_COUNTER_MASK __BITS(27, 26) 637 #define FEXTNVM3_PHY_CFG_COUNTER_50MS __BIT(27) 638 639 #define WMREG_RAL(x) (0x0040 + ((x) * 8)) /* Receive Address List */ 640 #define WMREG_RAH(x) (WMREG_RAL(x) + 4) 641 #define WMREG_CORDOVA_RAL(x) (((x) <= 15) ? (0x5400 + ((x) * 8)) : \ 642 (0x54e0 + (((x) - 16) * 8))) 643 #define WMREG_CORDOVA_RAH(x) (WMREG_CORDOVA_RAL(x) + 4) 644 #define WMREG_SHRAL(x) (0x5438 + ((x) * 8)) 645 #define WMREG_SHRAH(x) (WMREG_PCH_LPT_SHRAL(x) + 4) 646 #define WMREG_PCH_LPT_SHRAL(x) (0x5408 + ((x) * 8)) 647 #define WMREG_PCH_LPT_SHRAH(x) (WMREG_PCH_LPT_SHRAL(x) + 4) 648 #define WMREG_RAL_LO(b, x) ((b) + ((x) << 3)) 649 #define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4) 650 /* 651 * Receive Address List: The LO part is the low-order 32-bits 652 * of the MAC address. The HI part is the high-order 16-bits 653 * along with a few control bits. 654 */ 655 #define RAL_AS(x) ((x) << 16) /* address select */ 656 #define RAL_AS_DEST RAL_AS(0) /* (cordova?) */ 657 #define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */ 658 #define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */ 659 #define RAL_AV (1U << 31) /* entry is valid */ 660 661 #define WM_RAL_TABSIZE 15 /* RAL size for old devices */ 662 #define WM_RAL_TABSIZE_ICH8 7 /* RAL size for ICH* and PCH* */ 663 #define WM_RAL_TABSIZE_PCH2 5 /* RAL size for PCH2 */ 664 #define WM_RAL_TABSIZE_PCH_LPT 12 /* RAL size for PCH_LPT */ 665 #define WM_RAL_TABSIZE_82575 16 /* RAL size for 82575 */ 666 #define WM_RAL_TABSIZE_82576 24 /* RAL size for 82576 and 82580 */ 667 #define WM_RAL_TABSIZE_I350 32 /* RAL size for I350 */ 668 669 #define WMREG_ICR 0x00c0 /* Interrupt Cause Register */ 670 #define ICR_TXDW (1U << 0) /* Tx desc written back */ 671 #define ICR_TXQE (1U << 1) /* Tx queue empty */ 672 #define ICR_LSC (1U << 2) /* link status change */ 673 #define ICR_RXSEQ (1U << 3) /* receive sequence error */ 674 #define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */ 675 #define ICR_RXO (1U << 6) /* Rx overrun */ 676 #define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */ 677 #define ICR_MDAC (1U << 9) /* MDIO access complete */ 678 #define ICR_RXCFG (1U << 10) /* Receiving /C/ */ 679 #define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */ 680 #define ICR_RXQ(x) __BIT(20+(x)) /* 82574: Rx queue x interrupt x=0,1 */ 681 #define ICR_TXQ(x) __BIT(22+(x)) /* 82574: Tx queue x interrupt x=0,1 */ 682 #define ICR_OTHER __BIT(24) /* 82574: Other interrupt */ 683 #define ICR_INT (1U << 31) /* device generated an interrupt */ 684 685 #define WMREG_ITR 0x00c4 /* Interrupt Throttling Register */ 686 #define ITR_IVAL_MASK 0xffff /* Interval mask */ 687 #define ITR_IVAL_SHIFT 0 /* Interval shift */ 688 689 #define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */ 690 /* See ICR bits. */ 691 692 #define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */ 693 /* See ICR bits. */ 694 695 #define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */ 696 /* See ICR bits. */ 697 698 #define WMREG_EIAC_82574 0x00dc /* Interrupt Auto Clear Register */ 699 #define WMREG_EIAC_82574_MSIX_MASK (ICR_RXQ(0) | ICR_RXQ(1) \ 700 | ICR_TXQ(0) | ICR_TXQ(1) | ICR_OTHER) 701 702 #define WMREG_FEXTNVM7 0x00e4 /* Future Extended NVM 7 */ 703 #define FEXTNVM7_SIDE_CLK_UNGATE __BIT(2) 704 #define FEXTNVM7_DIS_SMB_PERST __BIT(5) 705 #define FEXTNVM7_DIS_PB_READ __BIT(18) 706 707 #define WMREG_IVAR 0x00e4 /* Interrupt Vector Allocation Register */ 708 #define WMREG_IVAR0 0x01700 /* Interrupt Vector Allocation */ 709 #define IVAR_ALLOC_MASK __BITS(0, 6) /* Bit 5 and 6 are reserved */ 710 #define IVAR_VALID __BIT(7) 711 /* IVAR definitions for 82580 and newer */ 712 #define WMREG_IVAR_Q(x) (WMREG_IVAR0 + ((x) / 2) * 4) 713 #define IVAR_TX_MASK_Q(x) (0x000000ff << (((x) % 2) == 0 ? 8 : 24)) 714 #define IVAR_RX_MASK_Q(x) (0x000000ff << (((x) % 2) == 0 ? 0 : 16)) 715 /* IVAR definitions for 82576 */ 716 #define WMREG_IVAR_Q_82576(x) (WMREG_IVAR0 + ((x) & 0x7) * 4) 717 #define IVAR_TX_MASK_Q_82576(x) (0x000000ff << (((x) / 8) == 0 ? 8 : 24)) 718 #define IVAR_RX_MASK_Q_82576(x) (0x000000ff << (((x) / 8) == 0 ? 0 : 16)) 719 /* IVAR definitions for 82574 */ 720 #define IVAR_ALLOC_MASK_82574 __BITS(0, 2) 721 #define IVAR_VALID_82574 __BIT(3) 722 #define IVAR_TX_MASK_Q_82574(x) (0x0000000f << ((x) == 0 ? 8 : 12)) 723 #define IVAR_RX_MASK_Q_82574(x) (0x0000000f << ((x) == 0 ? 0 : 4)) 724 #define IVAR_OTHER_MASK __BITS(16, 19) 725 #define IVAR_INT_ON_ALL_WB __BIT(31) 726 727 #define WMREG_IVAR_MISC 0x01740 /* IVAR for other causes */ 728 #define IVAR_MISC_TCPTIMER __BITS(0, 7) 729 #define IVAR_MISC_OTHER __BITS(8, 15) 730 731 #define WMREG_LTRV 0x00f8 /* Latency Tolerance Reporting */ 732 #define LTRV_VALUE __BITS(9, 0) 733 #define LTRV_SCALE __BITS(12, 10) 734 #define LTRV_SCALE_MAX 5 735 #define LTRV_SNOOP_REQ __BIT(15) 736 #define LTRV_SEND __BIT(30) 737 #define LTRV_NONSNOOP __BITS(31, 16) 738 #define LTRV_NONSNOOP_REQ __BIT(31) 739 740 #define WMREG_RCTL 0x0100 /* Receive Control */ 741 #define RCTL_EN (1U << 1) /* receiver enable */ 742 #define RCTL_SBP (1U << 2) /* store bad packets */ 743 #define RCTL_UPE (1U << 3) /* unicast promisc. enable */ 744 #define RCTL_MPE (1U << 4) /* multicast promisc. enable */ 745 #define RCTL_LPE (1U << 5) /* large packet enable */ 746 #define RCTL_LBM(x) ((x) << 6) /* loopback mode */ 747 #define RCTL_LBM_NONE RCTL_LBM(0) 748 #define RCTL_LBM_PHY RCTL_LBM(3) 749 #define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */ 750 #define RCTL_RDMTS_1_2 RCTL_RDMTS(0) 751 #define RCTL_RDMTS_1_4 RCTL_RDMTS(1) 752 #define RCTL_RDMTS_1_8 RCTL_RDMTS(2) 753 #define RCTL_RDMTS_MASK RCTL_RDMTS(3) 754 #define RCTL_DTYP_MASK __BITS(11,10) /* descriptor type. 82574 only */ 755 #define RCTL_DTYP(x) __SHIFTIN(x,RCTL_DTYP_MASK) 756 #define RCTL_DTYP_ONEBUF RCTL_DTYP(0) /* use one buffer(not split header). */ 757 #define RCTL_DTYP_SPH RCTL_DTYP(1) /* split header buffer. */ 758 /* RCTL_DTYP(2) and RCTL_DTYP(3) are reserved. */ 759 #define RCTL_MO(x) ((x) << 12) /* multicast offset */ 760 #define RCTL_BAM (1U << 15) /* broadcast accept mode */ 761 #define RCTL_RDMTS_HEX __BIT(16) 762 #define RCTL_2k (0 << 16) /* 2k Rx buffers */ 763 #define RCTL_1k (1 << 16) /* 1k Rx buffers */ 764 #define RCTL_512 (2 << 16) /* 512 byte Rx buffers */ 765 #define RCTL_256 (3 << 16) /* 256 byte Rx buffers */ 766 #define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */ 767 #define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */ 768 #define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */ 769 #define RCTL_DPF (1U << 22) /* discard pause frames */ 770 #define RCTL_PMCF (1U << 23) /* pass MAC control frames */ 771 #define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */ 772 #define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */ 773 774 #define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */ 775 #define WMREG_RDTR 0x2820 776 #define RDTR_FPD (1U << 31) /* flush partial descriptor */ 777 778 #define WMREG_LTRC 0x01a0 /* Latency Tolerance Reportiong Control */ 779 780 #define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */ 781 #define WMREG_RDBAL(x) \ 782 ((x) < 4 ? (0x02800 + ((x) * 0x100)) : \ 783 (0x0C000 + ((x) * 0x40))) 784 785 #define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */ 786 #define WMREG_RDBAH(x) \ 787 ((x) < 4 ? (0x02804 + ((x) * 0x100)) : \ 788 (0x0c004 + ((x) * 0x40))) 789 790 #define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */ 791 #define WMREG_RDLEN(x) \ 792 ((x) < 4 ? (0x02808 + ((x) * 0x100)) : \ 793 (0x0c008 + ((x) * 0x40))) 794 795 #define WMREG_SRRCTL(x) \ 796 ((x) < 4 ? (0x0280c + ((x) * 0x100)) : \ 797 (0x0c00c + ((x) * 0x40))) /* additional recv control used in 82575 ... */ 798 #define SRRCTL_BSIZEPKT_MASK 0x0000007f 799 #define SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 800 #define SRRCTL_BSIZEHDRSIZE_MASK 0x00000f00 801 #define SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 802 #define SRRCTL_DESCTYPE_LEGACY 0x00000000 803 #define SRRCTL_DESCTYPE_ADV_ONEBUF (1U << 25) 804 #define SRRCTL_DESCTYPE_HDR_SPLIT (2U << 25) 805 #define SRRCTL_DESCTYPE_HDR_REPLICATION (3U << 25) 806 #define SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT (4U << 25) 807 #define SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS (5U << 25) /* 82575 only */ 808 #define SRRCTL_DESCTYPE_MASK (7U << 25) 809 #define SRRCTL_DROP_EN 0x80000000 810 811 #define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */ 812 #define WMREG_RDH(x) \ 813 ((x) < 4 ? (0x02810 + ((x) * 0x100)) : \ 814 (0x0C010 + ((x) * 0x40))) 815 816 #define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */ 817 #define WMREG_RDT(x) \ 818 ((x) < 4 ? (0x02818 + ((x) * 0x100)) : \ 819 (0x0C018 + ((x) * 0x40))) 820 821 #define WMREG_RXDCTL(x) \ 822 ((x) < 4 ? (0x02828 + ((x) * 0x100)) : \ 823 (0x0c028 + ((x) * 0x40))) /* Receive Descriptor Control */ 824 #define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 825 #define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 826 #define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 827 #define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */ 828 /* flags used starting with 82575 ... */ 829 #define RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 830 #define RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ 831 832 #define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */ 833 #define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */ 834 #define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */ 835 #define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */ 836 #define WMREG_OLD_RDH1 0x0148 837 #define WMREG_OLD_RDT1 0x0150 838 #define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */ 839 #define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */ 840 #define FCRTH_DFLT 0x00008000 841 842 #define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */ 843 #define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */ 844 #define FCRTL_DFLT 0x00004000 845 #define FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 846 847 #define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */ 848 #define FCTTV_DFLT 0x00000600 849 850 #define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */ 851 /* See MII ANAR_X bits. */ 852 #define TXCW_FD (1U << 5) /* Full Duplex */ 853 #define TXCW_HD (1U << 6) /* Half Duplex */ 854 #define TXCW_SYM_PAUSE (1U << 7) /* sym pause request */ 855 #define TXCW_ASYM_PAUSE (1U << 8) /* asym pause request */ 856 #define TXCW_TxConfig (1U << 30) /* Tx Config */ 857 #define TXCW_ANE (1U << 31) /* Autonegotiate */ 858 859 #define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */ 860 /* See MII ANLPAR_X bits. */ 861 #define RXCW_NC (1U << 26) /* no carrier */ 862 #define RXCW_IV (1U << 27) /* config invalid */ 863 #define RXCW_CC (1U << 28) /* config change */ 864 #define RXCW_C (1U << 29) /* /C/ reception */ 865 #define RXCW_SYNCH (1U << 30) /* synchronized */ 866 #define RXCW_ANC (1U << 31) /* autonegotiation complete */ 867 868 #define WMREG_MTA 0x0200 /* Multicast Table Array */ 869 #define WMREG_CORDOVA_MTA 0x5200 870 871 #define WMREG_TCTL 0x0400 /* Transmit Control Register */ 872 #define TCTL_EN (1U << 1) /* transmitter enable */ 873 #define TCTL_PSP (1U << 3) /* pad short packets */ 874 #define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */ 875 #define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */ 876 #define TCTL_SWXOFF (1U << 22) /* software XOFF */ 877 #define TCTL_RTLC (1U << 24) /* retransmit on late collision */ 878 #define TCTL_NRTU (1U << 25) /* no retransmit on underrun */ 879 #define TCTL_MULR (1U << 28) /* multiple request */ 880 881 #define TX_COLLISION_THRESHOLD 15 882 #define TX_COLLISION_DISTANCE_HDX 512 883 #define TX_COLLISION_DISTANCE_FDX 64 884 885 #define WMREG_TCTL_EXT 0x0404 /* Transmit Control Register */ 886 #define TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 887 #define TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 888 889 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 890 891 #define WMREG_TIPG 0x0410 /* Transmit IPG Register */ 892 #define TIPG_IPGT(x) (x) /* IPG transmit time */ 893 #define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */ 894 #define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */ 895 #define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a)) 896 #define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 897 #define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 898 #define TIPG_1000T_80003_DFLT \ 899 (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) 900 #define TIPG_10_100_80003_DFLT \ 901 (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) 902 903 #define WMREG_TQC 0x0418 904 905 #define WMREG_OLD_TDBAL 0x0420 /* Transmit Descriptor Base Lo */ 906 #define WMREG_TDBAL(x) \ 907 ((x) < 4 ? (0x03800 + ((x) * 0x100)) : \ 908 (0x0E000 + ((x) * 0x40))) 909 910 #define WMREG_OLD_TDBAH 0x0424 /* Transmit Descriptor Base Hi */ 911 #define WMREG_TDBAH(x)\ 912 ((x) < 4 ? (0x03804 + ((x) * 0x100)) : \ 913 (0x0E004 + ((x) * 0x40))) 914 915 #define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */ 916 #define WMREG_TDLEN(x) \ 917 ((x) < 4 ? (0x03808 + ((x) * 0x100)) : \ 918 (0x0E008 + ((x) * 0x40))) 919 920 #define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */ 921 #define WMREG_TDH(x) \ 922 ((x) < 4 ? (0x03810 + ((x) * 0x100)) : \ 923 (0x0E010 + ((x) * 0x40))) 924 925 #define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */ 926 #define WMREG_TDT(x) \ 927 ((x) < 4 ? (0x03818 + ((x) * 0x100)) : \ 928 (0x0E018 + ((x) * 0x40))) 929 930 #define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */ 931 #define WMREG_TIDV 0x3820 932 933 #define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */ 934 #define WMREG_VFTA 0x0600 935 936 #define WMREG_MDICNFG 0x0e04 /* MDC/MDIO Configuration Register */ 937 #define MDICNFG_PHY_SHIFT 21 938 #define MDICNFG_PHY_MASK __BITS(25, 21) 939 #define MDICNFG_COM_MDIO __BIT(30) 940 #define MDICNFG_DEST __BIT(31) 941 942 #define WM_MC_TABSIZE 128 943 #define WM_ICH8_MC_TABSIZE 32 944 #define WM_VLAN_TABSIZE 128 945 946 #define WMREG_PHPM 0x0e14 /* PHY Power Management */ 947 #define PHPM_GO_LINK_D __BIT(5) /* Go Link Disconnect */ 948 949 #define WMREG_EEER 0x0e30 /* Energy Efficiency Ethernet "EEE" */ 950 #define EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 951 #define EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 952 #define EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 953 #define EEER_EEER_NEG 0x20000000 /* EEER capability nego */ 954 #define EEER_EEER_RX_LPI_STATUS 0x40000000 /* EEER Rx in LPI state */ 955 #define EEER_EEER_TX_LPI_STATUS 0x80000000 /* EEER Tx in LPI state */ 956 #define WMREG_EEE_SU 0x0e34 /* EEE Setup */ 957 #define WMREG_IPCNFG 0x0e38 /* Internal PHY Configuration */ 958 #define IPCNFG_10BASE_TE 0x00000002 /* IPCNFG 10BASE-Te low power op. */ 959 #define IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 960 #define IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 961 962 #define WMREG_EXTCNFCTR 0x0f00 /* Extended Configuration Control */ 963 #define EXTCNFCTR_PCIE_WRITE_ENABLE 0x00000001 964 #define EXTCNFCTR_PHY_WRITE_ENABLE 0x00000002 965 #define EXTCNFCTR_D_UD_ENABLE 0x00000004 966 #define EXTCNFCTR_D_UD_LATENCY 0x00000008 967 #define EXTCNFCTR_D_UD_OWNER 0x00000010 968 #define EXTCNFCTR_MDIO_SW_OWNERSHIP 0x00000020 969 #define EXTCNFCTR_MDIO_HW_OWNERSHIP 0x00000040 970 #define EXTCNFCTR_GATE_PHY_CFG 0x00000080 971 #define EXTCNFCTR_EXT_CNF_POINTER 0x0FFF0000 972 973 #define WMREG_PHY_CTRL 0x0f10 /* PHY control */ 974 #define PHY_CTRL_SPD_EN (1 << 0) 975 #define PHY_CTRL_D0A_LPLU (1 << 1) 976 #define PHY_CTRL_NOND0A_LPLU (1 << 2) 977 #define PHY_CTRL_NOND0A_GBE_DIS (1 << 3) 978 #define PHY_CTRL_GBE_DIS (1 << 6) 979 980 #define WMREG_PCIEANACFG 0x0f18 /* PCIE Analog Config */ 981 982 #define WMREG_IOSFPC 0x0f28 /* Tx corrupted data */ 983 984 #define WMREG_PBA 0x1000 /* Packet Buffer Allocation */ 985 #define PBA_BYTE_SHIFT 10 /* KB -> bytes */ 986 #define PBA_ADDR_SHIFT 7 /* KB -> quadwords */ 987 #define PBA_8K 0x0008 988 #define PBA_10K 0x000a 989 #define PBA_12K 0x000c 990 #define PBA_14K 0x000e 991 #define PBA_16K 0x0010 /* 16K, default Tx allocation */ 992 #define PBA_20K 0x0014 993 #define PBA_22K 0x0016 994 #define PBA_24K 0x0018 995 #define PBA_26K 0x001a 996 #define PBA_30K 0x001e 997 #define PBA_32K 0x0020 998 #define PBA_34K 0x0022 999 #define PBA_35K 0x0023 1000 #define PBA_40K 0x0028 1001 #define PBA_48K 0x0030 /* 48K, default Rx allocation */ 1002 #define PBA_64K 0x0040 1003 #define PBA_RXA_MASK __BITS(15, 0) 1004 1005 #define WMREG_PBS 0x1008 /* Packet Buffer Size (ICH) */ 1006 1007 #define WMREG_PBECCSTS 0x100c /* Packet Buffer ECC Status (PCH_LPT) */ 1008 #define PBECCSTS_CORR_ERR_CNT_MASK 0x000000ff 1009 #define PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000ff00 1010 #define PBECCSTS_UNCORR_ECC_ENABLE 0x00010000 1011 1012 #define WMREG_EEMNGCTL 0x1010 /* MNG EEprom Control */ 1013 #define EEMNGCTL_CFGDONE_0 0x040000 /* MNG config cycle done */ 1014 #define EEMNGCTL_CFGDONE_1 0x080000 /* 2nd port */ 1015 1016 #define WMREG_I2CCMD 0x1028 /* SFPI2C Command Register - RW */ 1017 #define I2CCMD_REG_ADDR_SHIFT 16 1018 #define I2CCMD_REG_ADDR 0x00ff0000 1019 #define I2CCMD_PHY_ADDR_SHIFT 24 1020 #define I2CCMD_PHY_ADDR 0x07000000 1021 #define I2CCMD_OPCODE_READ 0x08000000 1022 #define I2CCMD_OPCODE_WRITE 0x00000000 1023 #define I2CCMD_RESET 0x10000000 1024 #define I2CCMD_READY 0x20000000 1025 #define I2CCMD_INTERRUPT_ENA 0x40000000 1026 #define I2CCMD_ERROR 0x80000000 1027 #define MAX_SGMII_PHY_REG_ADDR 255 1028 #define I2CCMD_PHY_TIMEOUT 200 1029 1030 #define WMREG_EEWR 0x102c /* EEPROM write */ 1031 1032 #define WMREG_PBA_ECC 0x01100 /* PBA ECC */ 1033 #define PBA_ECC_COUNTER_MASK 0xfff00000 /* ECC counter mask */ 1034 #define PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 1035 #define PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 1036 #define PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 1037 #define PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 1038 1039 #define WMREG_GPIE 0x01514 /* General Purpose Interrupt Enable */ 1040 #define GPIE_NSICR __BIT(0) /* Non Selective Interrupt Clear */ 1041 #define GPIE_MULTI_MSIX __BIT(4) /* Multiple MSIX */ 1042 #define GPIE_EIAME __BIT(30) /* Extended Interrupt Auto Mask Ena. */ 1043 #define GPIE_PBA __BIT(31) /* PBA support */ 1044 1045 #define WMREG_EICS 0x01520 /* Ext. Interrupt Cause Set - WO */ 1046 #define WMREG_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 1047 #define WMREG_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 1048 #define WMREG_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 1049 #define WMREG_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 1050 1051 #define WMREG_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 1052 1053 #define WMREG_MSIXBM(x) (0x1600 + (x) * 4) /* MSI-X Allocation */ 1054 1055 #define EITR_RX_QUEUE(x) __BIT(0+(x)) /* Rx Queue x Interrupt x=[0-3] */ 1056 #define EITR_TX_QUEUE(x) __BIT(8+(x)) /* Tx Queue x Interrupt x=[0-3] */ 1057 #define EITR_TCP_TIMER 0x40000000 /* TCP Timer */ 1058 #define EITR_OTHER 0x80000000 /* Interrupt Cause Active */ 1059 1060 #define WMREG_EITR(x) (0x01680 + (0x4 * (x))) 1061 #define EITR_ITR_INT_MASK __BITS(14,2) 1062 #define EITR_COUNTER_MASK_82575 __BITS(31,16) 1063 #define EITR_CNT_INGR __BIT(31) /* does not overwrite counter */ 1064 1065 #define WMREG_EITR_82574(x) (0x000E8 + (0x4 * (x))) 1066 #define EITR_ITR_INT_MASK_82574 __BITS(15, 0) 1067 1068 #define WMREG_RXPBS 0x2404 /* Rx Packet Buffer Size */ 1069 #define RXPBS_SIZE_MASK_82576 0x0000007F 1070 1071 #define WMREG_RDFH 0x2410 /* Receive Data FIFO Head */ 1072 #define WMREG_RDFT 0x2418 /* Receive Data FIFO Tail */ 1073 #define WMREG_RDFHS 0x2420 /* Receive Data FIFO Head Saved */ 1074 #define WMREG_RDFTS 0x2428 /* Receive Data FIFO Tail Saved */ 1075 #define WMREG_RADV 0x282c /* Receive Interrupt Absolute Delay Timer */ 1076 1077 #define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */ 1078 #define TXDMAC_DPP (1U << 0) /* disable packet prefetch */ 1079 1080 #define WMREG_KABGTXD 0x3004 /* AFE and Gap Transmit Ref Data */ 1081 #define KABGTXD_BGSQLBIAS 0x00050000 1082 1083 #define WMREG_TDFH 0x3410 /* Transmit Data FIFO Head */ 1084 #define WMREG_TDFT 0x3418 /* Transmit Data FIFO Tail */ 1085 #define WMREG_TDFHS 0x3420 /* Transmit Data FIFO Head Saved */ 1086 #define WMREG_TDFTS 0x3428 /* Transmit Data FIFO Tail Saved */ 1087 #define WMREG_TDFPC 0x3430 /* Transmit Data FIFO Packet Count */ 1088 1089 #define WMREG_TXDCTL(n) /* Trandmit Descriptor Control */ \ 1090 (((n) < 4) ? (0x3828 + ((n) * 0x100)) : (0xe028 + ((n) * 0x40))) 1091 #define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 1092 #define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 1093 #define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 1094 /* flags used starting with 82575 ... */ 1095 #define TXDCTL_COUNT_DESC __BIT(22) /* Enable the counting of desc. 1096 still to be processed. */ 1097 #define TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 1098 #define TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 1099 #define TXDCTL_PRIORITY 0x08000000 1100 1101 #define WMREG_TADV 0x382c /* Transmit Absolute Interrupt Delay Timer */ 1102 #define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum 1103 Threshold (Cordova) */ 1104 #define TSPMT_TSMT(x) (x) /* TCP seg min transfer */ 1105 #define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */ 1106 1107 #define WMREG_TARC0 0x3840 /* Tx arbitration count (0) */ 1108 #define WMREG_TARC1 0x3940 /* Tx arbitration count (1) */ 1109 1110 #define WMREG_CRCERRS 0x4000 /* CRC Error Count */ 1111 #define WMREG_ALGNERRC 0x4004 /* Alignment Error Count */ 1112 #define WMREG_SYMERRC 0x4008 /* Symbol Error Count */ 1113 #define WMREG_RXERRC 0x400c /* receive error Count - R/clr */ 1114 #define WMREG_MPC 0x4010 /* Missed Packets Count - R/clr */ 1115 #define WMREG_COLC 0x4028 /* collision Count - R/clr */ 1116 #define WMREG_SEC 0x4038 /* Sequence Error Count */ 1117 #define WMREG_CEXTERR 0x403c /* Carrier Extension Error Count */ 1118 #define WMREG_RLEC 0x4040 /* Receive Length Error Count */ 1119 #define WMREG_XONRXC 0x4048 /* XON Rx Count - R/clr */ 1120 #define WMREG_XONTXC 0x404c /* XON Tx Count - R/clr */ 1121 #define WMREG_XOFFRXC 0x4050 /* XOFF Rx Count - R/clr */ 1122 #define WMREG_XOFFTXC 0x4054 /* XOFF Tx Count - R/clr */ 1123 #define WMREG_FCRUC 0x4058 /* Flow Control Rx Unsupported Count - R/clr */ 1124 #define WMREG_RNBC 0x40a0 /* Receive No Buffers Count */ 1125 #define WMREG_TLPIC 0x4148 /* EEE Tx LPI Count */ 1126 #define WMREG_RLPIC 0x414c /* EEE Rx LPI Count */ 1127 1128 #define WMREG_PCS_CFG 0x4200 /* PCS Configuration */ 1129 #define PCS_CFG_PCS_EN __BIT(3) 1130 1131 #define WMREG_PCS_LCTL 0x4208 /* PCS Link Control */ 1132 #define PCS_LCTL_FSV_1000 __BIT(2) /* AN Timeout Enable */ 1133 #define PCS_LCTL_FDV_FULL __BIT(3) /* AN Timeout Enable */ 1134 #define PCS_LCTL_FSD __BIT(4) /* AN Timeout Enable */ 1135 #define PCS_LCTL_FORCE_FC __BIT(7) /* AN Timeout Enable */ 1136 #define PCS_LCTL_AN_ENABLE __BIT(16) /* AN Timeout Enable */ 1137 #define PCS_LCTL_AN_RESTART __BIT(17) /* AN Timeout Enable */ 1138 #define PCS_LCTL_AN_TIMEOUT __BIT(18) /* AN Timeout Enable */ 1139 1140 #define WMREG_PCS_LSTS 0x420c /* PCS Link Status */ 1141 #define PCS_LSTS_LINKOK __BIT(0) 1142 #define PCS_LSTS_SPEED __BITS(2, 1) 1143 #define PCS_LSTS_SPEED_10 0 1144 #define PCS_LSTS_SPEED_100 1 1145 #define PCS_LSTS_SPEED_1000 2 1146 #define PCS_LSTS_FDX __BIT(3) 1147 #define PCS_LSTS_AN_COMP __BIT(16) 1148 1149 #define WMREG_PCS_ANADV 0x4218 /* AN Advertsement */ 1150 #define WMREG_PCS_LPAB 0x421c /* Link Partnet Ability */ 1151 1152 #define WMREG_RXCSUM 0x5000 /* Receive Checksum register */ 1153 #define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */ 1154 #define RXCSUM_IPOFL (1U << 8) /* IP checksum offload */ 1155 #define RXCSUM_TUOFL (1U << 9) /* TCP/UDP checksum offload */ 1156 #define RXCSUM_IPV6OFL (1U << 10) /* IPv6 checksum offload */ 1157 #define RXCSUM_CRCOFL (1U << 11) /* SCTP CRC32 checksum offload */ 1158 #define RXCSUM_IPPCSE (1U << 12) /* IP payload checksum enable */ 1159 #define RXCSUM_PCSD (1U << 13) /* packet checksum disabled */ 1160 1161 #define WMREG_RLPML 0x5004 /* Rx Long Packet Max Length */ 1162 1163 #define WMREG_RFCTL 0x5008 /* Receive Filter Control */ 1164 #define WMREG_RFCTL_NFSWDIS __BIT(6) /* NFS Write Disable */ 1165 #define WMREG_RFCTL_NFSRDIS __BIT(7) /* NFS Read Disable */ 1166 #define WMREG_RFCTL_ACKDIS __BIT(12) /* ACK Accelerate Disable */ 1167 #define WMREG_RFCTL_ACKD_DIS __BIT(13) /* ACK data Disable */ 1168 #define WMREG_RFCTL_EXSTEN __BIT(15) /* Extended status Enable. 82574 only. */ 1169 #define WMREG_RFCTL_IPV6EXDIS __BIT(16) /* IPv6 Extension Header Disable */ 1170 #define WMREG_RFCTL_NEWIPV6EXDIS __BIT(17) /* New IPv6 Extension Header */ 1171 1172 #define WMREG_WUC 0x5800 /* Wakeup Control */ 1173 #define WUC_APME 0x00000001 /* APM Enable */ 1174 #define WUC_PME_EN 0x00000002 /* PME Enable */ 1175 1176 #define WMREG_WUFC 0x5808 /* Wakeup Filter Control */ 1177 #define WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 1178 #define WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 1179 #define WUFC_MC 0x00000008 /* Directed Multicast Wakeup En */ 1180 #define WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 1181 #define WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup En */ 1182 #define WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup En */ 1183 #define WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup En */ 1184 1185 #define WMREG_MRQC 0x5818 /* Multiple Receive Queues Command */ 1186 #define MRQC_DISABLE_RSS 0x00000000 1187 #define MRQC_ENABLE_RSS_MQ_82574 __BIT(0) /* enable RSS for 82574 */ 1188 #define MRQC_ENABLE_RSS_MQ __BIT(1) /* enable hardware max RSS without VMDq */ 1189 #define MRQC_ENABLE_RSS_VMDQ __BITS(1, 0) /* enable RSS with VMDq */ 1190 #define MRQC_DEFQ_MASK __BITS(5, 3) 1191 /* 1192 * Defines the default queue in non VMDq 1193 * mode according to value of the Multiple Receive 1194 * Queues Enable field. 1195 */ 1196 #define MRQC_DEFQ_NOT_RSS_FLT __SHFTIN(__BIT(1), MRQC_DEFQ_MASK) 1197 /* 1198 * the destination of all packets 1199 * not forwarded by RSS or filters 1200 */ 1201 #define MRQC_DEFQ_NOT_MAC_ETH __SHFTIN(__BITS(1, 0), MRQC_DEFQ_MASK) 1202 /* 1203 * Def_Q field is ignored. Queueing 1204 * decision of all packets not forwarded 1205 * by MAC address and Ether-type filters 1206 * is according to VT_CTL.DEF_PL field. 1207 */ 1208 #define MRQC_DEFQ_IGNORED1 __SHFTIN(__BIT(2), MRQC_DEFQ_MASK) 1209 /* Def_Q field is ignored */ 1210 #define MRQC_DEFQ_IGNORED2 __SHFTIN(__BIT(2)|__BIT(0), MRQC_DEFQ_MASK) 1211 /* Def_Q field is ignored */ 1212 #define MRQC_DEFQ_VMDQ __SHFTIN(__BITS(2, 1), MRQC_DEFQ_MASK) 1213 /* for VMDq mode */ 1214 #define MRQC_RSS_FIELD_IPV4_TCP __BIT(16) 1215 #define MRQC_RSS_FIELD_IPV4 __BIT(17) 1216 #define MRQC_RSS_FIELD_IPV6_TCP_EX __BIT(18) 1217 #define MRQC_RSS_FIELD_IPV6_EX __BIT(19) 1218 #define MRQC_RSS_FIELD_IPV6 __BIT(20) 1219 #define MRQC_RSS_FIELD_IPV6_TCP __BIT(21) 1220 #define MRQC_RSS_FIELD_IPV4_UDP __BIT(22) 1221 #define MRQC_RSS_FIELD_IPV6_UDP __BIT(23) 1222 #define MRQC_RSS_FIELD_IPV6_UDP_EX __BIT(24) 1223 1224 #define WMREG_RETA_Q(x) (0x5c00 + ((x) >> 2) * 4) /* Redirection Table */ 1225 #define RETA_NUM_ENTRIES 128 1226 #define RETA_ENTRY_MASK_Q(x) (0x000000ff << (((x) % 4) * 8)) /* Redirection Table */ 1227 #define RETA_ENT_QINDEX_MASK __BITS(3,0) /*queue index for 82580 and newer */ 1228 #define RETA_ENT_QINDEX0_MASK_82575 __BITS(3,2) /*queue index for pool0 */ 1229 #define RETA_ENT_QINDEX1_MASK_82575 __BITS(7,6) /*queue index for pool1 and regular RSS */ 1230 #define RETA_ENT_QINDEX_MASK_82574 __BIT(7) /*queue index for 82574 */ 1231 1232 #define WMREG_RSSRK(x) (0x5c80 + (x) * 4) /* RSS Random Key Register */ 1233 #define RSSRK_NUM_REGS 10 1234 1235 #define WMREG_MANC 0x5820 /* Management Control */ 1236 #define MANC_SMBUS_EN 0x00000001 1237 #define MANC_ASF_EN 0x00000002 1238 #define MANC_ARP_EN 0x00002000 1239 #define MANC_RECV_TCO_RESET 0x00010000 1240 #define MANC_RECV_TCO_EN 0x00020000 1241 #define MANC_BLK_PHY_RST_ON_IDE 0x00040000 1242 #define MANC_RECV_ALL 0x00080000 1243 #define MANC_EN_MAC_ADDR_FILTER 0x00100000 1244 #define MANC_EN_MNG2HOST 0x00200000 1245 1246 #define WMREG_MANC2H 0x5860 /* Management Control To Host - RW */ 1247 #define MANC2H_PORT_623 (1 << 5) 1248 #define MANC2H_PORT_624 (1 << 6) 1249 1250 #define WMREG_GCR 0x5b00 /* PCIe Control */ 1251 #define GCR_RXD_NO_SNOOP 0x00000001 1252 #define GCR_RXDSCW_NO_SNOOP 0x00000002 1253 #define GCR_RXDSCR_NO_SNOOP 0x00000004 1254 #define GCR_TXD_NO_SNOOP 0x00000008 1255 #define GCR_TXDSCW_NO_SNOOP 0x00000010 1256 #define GCR_TXDSCR_NO_SNOOP 0x00000020 1257 #define GCR_CMPL_TMOUT_MASK 0x0000f000 1258 #define GCR_CMPL_TMOUT_10MS 0x00001000 1259 #define GCR_CMPL_TMOUT_RESEND 0x00010000 1260 #define GCR_CAP_VER2 0x00040000 1261 #define GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 1262 1263 #define WMREG_FACTPS 0x5b30 /* Function Active and Power State to MNG */ 1264 #define FACTPS_MNGCG 0x20000000 1265 #define FACTPS_LFS 0x40000000 /* LAN Function Select */ 1266 1267 #define WMREG_GIOCTL 0x5b44 /* GIO Analog Control Register */ 1268 #define WMREG_CCMCTL 0x5b48 /* CCM Control Register */ 1269 #define WMREG_SCCTL 0x5b4c /* PCIc PLL Configuration Register */ 1270 1271 #define WMREG_SWSM 0x5b50 /* SW Semaphore */ 1272 #define SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 1273 #define SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 1274 #define SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 1275 #define SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 1276 /* Intel driver defines H2ME register at 0x5b50 */ 1277 #define WMREG_H2ME 0x5b50 /* SW Semaphore */ 1278 #define H2ME_ULP __BIT(11) 1279 #define H2ME_ENFORCE_SETTINGS __BIT(12) 1280 1281 #define WMREG_FWSM 0x5b54 /* FW Semaphore */ 1282 #define FWSM_MODE __BITS(1, 3) 1283 #define MNG_ICH_IAMT_MODE 0x2 /* PT mode? */ 1284 #define MNG_IAMT_MODE 0x3 1285 #define FWSM_RSPCIPHY __BIT(6) /* Reset PHY on PCI reset */ 1286 #define FWSM_WLOCK_MAC __BITS(7, 9) 1287 #define FWSM_ULP_CFG_DONE __BIT(10) 1288 #define FWSM_FW_VALID __BIT(15) /* FW established a valid mode */ 1289 1290 #define WMREG_SWSM2 0x5b58 /* SW Semaphore 2 */ 1291 #define SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 1292 1293 #define WMREG_SW_FW_SYNC 0x5b5c /* software-firmware semaphore */ 1294 #define SWFW_EEP_SM 0x0001 /* eeprom access */ 1295 #define SWFW_PHY0_SM 0x0002 /* first ctrl phy access */ 1296 #define SWFW_PHY1_SM 0x0004 /* second ctrl phy access */ 1297 #define SWFW_MAC_CSR_SM 0x0008 1298 #define SWFW_PHY2_SM 0x0020 /* first ctrl phy access */ 1299 #define SWFW_PHY3_SM 0x0040 /* first ctrl phy access */ 1300 #define SWFW_SOFT_SHIFT 0 /* software semaphores */ 1301 #define SWFW_FIRM_SHIFT 16 /* firmware semaphores */ 1302 1303 #define WMREG_GCR2 0x5b64 /* 3GPIO Control Register 2 */ 1304 #define WMREG_FEXTNVM9 0x5bb4 /* Future Extended NVM 9 */ 1305 #define WMREG_FEXTNVM11 0x5bbc /* Future Extended NVM 11 */ 1306 #define FEXTNVM11_DIS_MULRFIX __BIT(13) /* Disable MULR fix */ 1307 1308 #define WMREG_CRC_OFFSET 0x5f50 1309 1310 #define WMREG_EEC 0x12010 1311 #define EEC_FLASH_DETECTED (1U << 19) /* FLASH */ 1312 #define EEC_FLUPD (1U << 23) /* Update FLASH */ 1313 1314 #define WMREG_EEARBC_I210 0x12024 1315 1316 /* 1317 * NVM related values. 1318 * Microwire, SPI, and flash 1319 */ 1320 #define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */ 1321 #define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */ 1322 #define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */ 1323 1324 #define SPI_OPC_WRITE 0x02 /* SPI "write" opcode */ 1325 #define SPI_OPC_READ 0x03 /* SPI "read" opcode */ 1326 #define SPI_OPC_A8 0x08 /* opcode bit 3 == address bit 8 */ 1327 #define SPI_OPC_WREN 0x06 /* SPI "set write enable" opcode */ 1328 #define SPI_OPC_WRDI 0x04 /* SPI "clear write enable" opcode */ 1329 #define SPI_OPC_RDSR 0x05 /* SPI "read status" opcode */ 1330 #define SPI_OPC_WRSR 0x01 /* SPI "write status" opcode */ 1331 #define SPI_MAX_RETRIES 5000 /* max wait of 5ms for RDY signal */ 1332 1333 #define SPI_SR_RDY 0x01 1334 #define SPI_SR_WEN 0x02 1335 #define SPI_SR_BP0 0x04 1336 #define SPI_SR_BP1 0x08 1337 #define SPI_SR_WPEN 0x80 1338 1339 #define NVM_CHECKSUM 0xBABA 1340 #define NVM_SIZE 0x0040 1341 #define NVM_WORD_SIZE_BASE_SHIFT 6 1342 1343 #define NVM_OFF_MACADDR 0x0000 /* MAC address offset 0 */ 1344 #define NVM_OFF_MACADDR1 0x0001 /* MAC address offset 1 */ 1345 #define NVM_OFF_MACADDR2 0x0002 /* MAC address offset 2 */ 1346 #define NVM_OFF_COMPAT 0x0003 1347 #define NVM_OFF_ID_LED_SETTINGS 0x0004 1348 #define NVM_OFF_VERSION 0x0005 1349 #define NVM_OFF_CFG1 0x000a /* config word 1 */ 1350 #define NVM_OFF_CFG2 0x000f /* config word 2 */ 1351 #define NVM_OFF_EEPROM_SIZE 0x0012 /* NVM SIZE */ 1352 #define NVM_OFF_CFG4 0x0013 /* config word 4 */ 1353 #define NVM_OFF_CFG3_PORTB 0x0014 /* config word 3 */ 1354 #define NVM_OFF_FUTURE_INIT_WORD1 0x0019 1355 #define NVM_OFF_INIT_3GIO_3 0x001a /* PCIe Initial Configuration Word 3 */ 1356 #define NVM_OFF_K1_CONFIG 0x001b /* NVM K1 Config */ 1357 #define NVM_OFF_LED_1_CFG 0x001c 1358 #define NVM_OFF_LED_0_2_CFG 0x001f 1359 #define NVM_OFF_SWDPIN 0x0020 /* SWD Pins (Cordova) */ 1360 #define NVM_OFF_CFG3_PORTA 0x0024 /* config word 3 */ 1361 #define NVM_OFF_ALT_MAC_ADDR_PTR 0x0037 /* to the alternative MAC addresses */ 1362 #define NVM_OFF_COMB_VER_PTR 0x003d 1363 #define NVM_OFF_IMAGE_UID0 0x0042 1364 #define NVM_OFF_IMAGE_UID1 0x0043 1365 1366 #define NVM_COMPAT_VALID_CHECKSUM 0x0001 1367 1368 #define NVM_CFG1_LVDID (1U << 0) 1369 #define NVM_CFG1_LSSID (1U << 1) 1370 #define NVM_CFG1_PME_CLOCK (1U << 2) 1371 #define NVM_CFG1_PM (1U << 3) 1372 #define NVM_CFG1_ILOS (1U << 4) 1373 #define NVM_CFG1_SWDPIO_SHIFT 5 1374 #define NVM_CFG1_SWDPIO_MASK (0xf << NVM_CFG1_SWDPIO_SHIFT) 1375 #define NVM_CFG1_IPS1 (1U << 8) 1376 #define NVM_CFG1_LRST (1U << 9) 1377 #define NVM_CFG1_FD (1U << 10) 1378 #define NVM_CFG1_FRCSPD (1U << 11) 1379 #define NVM_CFG1_IPS0 (1U << 12) 1380 #define NVM_CFG1_64_32_BAR (1U << 13) 1381 1382 #define NVM_CFG2_CSR_RD_SPLIT (1U << 1) 1383 #define NVM_CFG2_82544_APM_EN (1U << 2) 1384 #define NVM_CFG2_64_BIT (1U << 3) 1385 #define NVM_CFG2_MAX_READ (1U << 4) 1386 #define NVM_CFG2_DMCR_MAP (1U << 5) 1387 #define NVM_CFG2_133_CAP (1U << 6) 1388 #define NVM_CFG2_MSI_DIS (1U << 7) 1389 #define NVM_CFG2_FLASH_DIS (1U << 8) 1390 #define NVM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9) 1391 #define NVM_CFG2_APM_EN (1U << 10) 1392 #define NVM_CFG2_ANE (1U << 11) 1393 #define NVM_CFG2_PAUSE(x) (((x) & 3) >> 12) 1394 #define NVM_CFG2_ASDE (1U << 14) 1395 #define NVM_CFG2_APM_PME (1U << 15) 1396 #define NVM_CFG2_SWDPIO_SHIFT 4 1397 #define NVM_CFG2_SWDPIO_MASK (0xf << NVM_CFG2_SWDPIO_SHIFT) 1398 #define NVM_CFG2_MNGM_SHIFT 13 /* Manageability Operation mode */ 1399 #define NVM_CFG2_MNGM_MASK (3U << NVM_CFG2_MNGM_SHIFT) 1400 #define NVM_CFG2_MNGM_DIS 0 1401 #define NVM_CFG2_MNGM_NCSI 1 1402 #define NVM_CFG2_MNGM_PT 2 1403 1404 #define NVM_COMPAT_SERDES_FORCE_MODE __BIT(14) /* Don't use autonego */ 1405 1406 #define NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM 0x0040 1407 1408 #define NVM_K1_CONFIG_ENABLE 0x01 1409 1410 #define NVM_SWDPIN_MASK 0xdf 1411 #define NVM_SWDPIN_SWDPIN_SHIFT 0 1412 #define NVM_SWDPIN_SWDPIO_SHIFT 8 1413 1414 #define NVM_3GIO_3_ASPM_MASK (0x3 << 2) /* Active State PM Support */ 1415 1416 #define NVM_CFG3_APME (1U << 10) 1417 #define NVM_CFG3_PORTA_EXT_MDIO (1U << 2) /* External MDIO Interface */ 1418 #define NVM_CFG3_PORTA_COM_MDIO (1U << 3) /* MDIO Interface is shared */ 1419 1420 #define NVM_OFF_MACADDR_82571(x) (3 * (x)) 1421 1422 /* 1423 * EEPROM Partitioning. See Table 6-1, "EEPROM Top Level Partitioning" 1424 * in 82580's datasheet. 1425 */ 1426 #define NVM_OFF_LAN_FUNC_82580(x) ((x) ? (0x40 + (0x40 * (x))) : 0) 1427 1428 #define NVM_COMBO_VER_OFF 0x0083 1429 1430 #define NVM_MAJOR_MASK 0xf000 1431 #define NVM_MAJOR_SHIFT 12 1432 #define NVM_MINOR_MASK 0x0ff0 1433 #define NVM_MINOR_SHIFT 4 1434 #define NVM_BUILD_MASK 0x000f 1435 #define NVM_UID_VALID 0x8000 1436 1437 /* iNVM Registers for i21[01] */ 1438 #define WM_INVM_DATA_REG(reg) (0x12120 + 4*(reg)) 1439 #define INVM_SIZE 64 /* Number of INVM Data Registers */ 1440 1441 /* iNVM default vaule */ 1442 #define NVM_INIT_CTRL_2_DEFAULT_I211 0x7243 1443 #define NVM_INIT_CTRL_4_DEFAULT_I211 0x00c1 1444 #define NVM_LED_1_CFG_DEFAULT_I211 0x0184 1445 #define NVM_LED_0_2_CFG_DEFAULT_I211 0x200c 1446 #define NVM_RESERVED_WORD 0xffff 1447 1448 #define INVM_DWORD_TO_RECORD_TYPE(dword) ((dword) & 0x7) 1449 #define INVM_DWORD_TO_WORD_ADDRESS(dword) (((dword) & 0x0000FE00) >> 9) 1450 #define INVM_DWORD_TO_WORD_DATA(dword) (((dword) & 0xFFFF0000) >> 16) 1451 1452 #define INVM_UNINITIALIZED_STRUCTURE 0x0 1453 #define INVM_WORD_AUTOLOAD_STRUCTURE 0x1 1454 #define INVM_CSR_AUTOLOAD_STRUCTURE 0x2 1455 #define INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE 0x3 1456 #define INVM_RSA_KEY_SHA256_STRUCTURE 0x4 1457 #define INVM_INVALIDATED_STRUCTURE 0xf 1458 1459 #define INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 1460 #define INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 1461 1462 #define INVM_DEFAULT_AL 0x202f 1463 #define INVM_AUTOLOAD 0x0a 1464 #define INVM_PLL_WO_VAL 0x0010 1465 1466 /* Version and Image Type field */ 1467 #define INVM_VER_1 __BITS(12,3) 1468 #define INVM_VER_2 __BITS(22,13) 1469 #define INVM_IMGTYPE __BITS(28,23) 1470 #define INVM_MINOR __BITS(3,0) 1471 #define INVM_MAJOR __BITS(9,4) 1472 1473 /* Word definitions for ID LED Settings */ 1474 #define ID_LED_RESERVED_FFFF 0xFFFF 1475 1476 /* ich8 flash control */ 1477 #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 1478 #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 1479 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 1480 #define ICH_FLASH_SEG_SIZE_256 256 1481 #define ICH_FLASH_SEG_SIZE_4K 4096 1482 #define ICH_FLASH_SEG_SIZE_64K 65536 1483 1484 #define ICH_CYCLE_READ 0x0 1485 #define ICH_CYCLE_RESERVED 0x1 1486 #define ICH_CYCLE_WRITE 0x2 1487 #define ICH_CYCLE_ERASE 0x3 1488 1489 #define ICH_FLASH_GFPREG 0x0000 1490 #define ICH_FLASH_HSFSTS 0x0004 /* Flash Status Register */ 1491 #define HSFSTS_DONE 0x0001 /* Flash Cycle Done */ 1492 #define HSFSTS_ERR 0x0002 /* Flash Cycle Error */ 1493 #define HSFSTS_DAEL 0x0004 /* Direct Access error Log */ 1494 #define HSFSTS_ERSZ_MASK 0x0018 /* Block/Sector Erase Size */ 1495 #define HSFSTS_ERSZ_SHIFT 3 1496 #define HSFSTS_FLINPRO 0x0020 /* flash SPI cycle in Progress */ 1497 #define HSFSTS_FLDVAL 0x4000 /* Flash Descriptor Valid */ 1498 #define HSFSTS_FLLK 0x8000 /* Flash Configuration Lock-Down */ 1499 #define ICH_FLASH_HSFCTL 0x0006 /* Flash control Register */ 1500 #define HSFCTL_GO 0x0001 /* Flash Cycle Go */ 1501 #define HSFCTL_CYCLE_MASK 0x0006 /* Flash Cycle */ 1502 #define HSFCTL_CYCLE_SHIFT 1 1503 #define HSFCTL_BCOUNT_MASK 0x0300 /* Data Byte Count */ 1504 #define HSFCTL_BCOUNT_SHIFT 8 1505 #define ICH_FLASH_FADDR 0x0008 1506 #define ICH_FLASH_FDATA0 0x0010 1507 #define ICH_FLASH_FRACC 0x0050 1508 #define ICH_FLASH_FREG0 0x0054 1509 #define ICH_FLASH_FREG1 0x0058 1510 #define ICH_FLASH_FREG2 0x005C 1511 #define ICH_FLASH_FREG3 0x0060 1512 #define ICH_FLASH_FPR0 0x0074 1513 #define ICH_FLASH_FPR1 0x0078 1514 #define ICH_FLASH_SSFSTS 0x0090 1515 #define ICH_FLASH_SSFCTL 0x0092 1516 #define ICH_FLASH_PREOP 0x0094 1517 #define ICH_FLASH_OPTYPE 0x0096 1518 #define ICH_FLASH_OPMENU 0x0098 1519 1520 #define ICH_FLASH_REG_MAPSIZE 0x00A0 1521 #define ICH_FLASH_SECTOR_SIZE 4096 1522 #define ICH_GFPREG_BASE_MASK 0x1FFF 1523 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 1524 1525 #define ICH_NVM_SIG_WORD 0x13 1526 #define ICH_NVM_SIG_MASK 0xc000 1527 #define ICH_NVM_VALID_SIG_MASK 0xc0 1528 #define ICH_NVM_SIG_VALUE 0x80 1529 1530 #define NVM_SIZE_MULTIPLIER 4096 /* multiplier for NVMS field */ 1531 #define WM_PCH_SPT_FLASHOFFSET 0xe000 /* offset of NVM access regs(PCH_SPT)*/ 1532 1533 /* for PCI express Capability registers */ 1534 #define WM_PCIE_DCSR2_16MS 0x00000005 1535 1536 /* SFF SFP ROM data */ 1537 #define SFF_SFP_ID_OFF 0x00 1538 #define SFF_SFP_ID_UNKNOWN 0x00 /* Unknown */ 1539 #define SFF_SFP_ID_SFF 0x02 /* Module soldered to motherboard */ 1540 #define SFF_SFP_ID_SFP 0x03 /* SFP transceiver */ 1541 1542 #define SFF_SFP_ETH_FLAGS_OFF 0x06 1543 #define SFF_SFP_ETH_FLAGS_1000SX 0x01 1544 #define SFF_SFP_ETH_FLAGS_1000LX 0x02 1545 #define SFF_SFP_ETH_FLAGS_1000CX 0x04 1546 #define SFF_SFP_ETH_FLAGS_1000T 0x08 1547 #define SFF_SFP_ETH_FLAGS_100FX 0x10 1548 1549 /* I21[01] PHY related definitions */ 1550 #define GS40G_PAGE_SELECT 0x16 1551 #define GS40G_PAGE_SHIFT 16 1552 #define GS40G_OFFSET_MASK 0xffff 1553 #define GS40G_PHY_PLL_FREQ_PAGE 0xfc0000 1554 #define GS40G_PHY_PLL_FREQ_REG 0x000e 1555 #define GS40G_PHY_PLL_UNCONF 0xff 1556 1557 /* advanced TX descriptor for 82575 and newer */ 1558 typedef union nq_txdesc { 1559 struct { 1560 uint64_t nqtxd_addr; 1561 uint32_t nqtxd_cmdlen; 1562 uint32_t nqtxd_fields; 1563 } nqtx_data; 1564 struct { 1565 uint32_t nqtxc_vl_len; 1566 uint32_t nqtxc_sn; 1567 uint32_t nqtxc_cmd; 1568 uint32_t nqtxc_mssidx; 1569 } nqrx_ctx; 1570 } __packed nq_txdesc_t; 1571 1572 1573 /* Commands for nqtxd_cmdlen and nqtxc_cmd */ 1574 #define NQTX_CMD_EOP (1U << 24) /* end of packet */ 1575 #define NQTX_CMD_IFCS (1U << 25) /* insert FCS */ 1576 #define NQTX_CMD_RS (1U << 27) /* report status */ 1577 #define NQTX_CMD_DEXT (1U << 29) /* descriptor extension */ 1578 #define NQTX_CMD_VLE (1U << 30) /* VLAN enable */ 1579 #define NQTX_CMD_TSE (1U << 31) /* TCP segmentation enable */ 1580 1581 /* Descriptor types (if DEXT is set) */ 1582 #define NQTX_DTYP_C (2U << 20) /* context */ 1583 #define NQTX_DTYP_D (3U << 20) /* data */ 1584 1585 #define NQTXD_FIELDS_IDX_SHIFT 4 /* context index shift */ 1586 #define NQTXD_FIELDS_IDX_MASK 0xf 1587 #define NQTXD_FIELDS_PAYLEN_SHIFT 14 /* payload len shift */ 1588 #define NQTXD_FIELDS_PAYLEN_MASK 0x3ffff 1589 1590 #define NQTXD_FIELDS_IXSM (1U << 8) /* do IP checksum */ 1591 #define NQTXD_FIELDS_TUXSM (1U << 9) /* do TCP/UDP checksum */ 1592 1593 #define NQTXC_VLLEN_IPLEN_SHIFT 0 /* IP header len */ 1594 #define NQTXC_VLLEN_IPLEN_MASK 0x1ff 1595 #define NQTXC_VLLEN_MACLEN_SHIFT 9 /* MAC header len */ 1596 #define NQTXC_VLLEN_MACLEN_MASK 0x7f 1597 #define NQTXC_VLLEN_VLAN_SHIFT 16 /* vlan number */ 1598 #define NQTXC_VLLEN_VLAN_MASK 0xffff 1599 1600 #define NQTXC_CMD_MKRLOC_SHIFT 0 /* IP checksum offset */ 1601 #define NQTXC_CMD_MKRLOC_MASK 0x1ff 1602 #define NQTXC_CMD_SNAP (1U << 9) 1603 #define NQTXC_CMD_IP4 (1U << 10) 1604 #define NQTXC_CMD_IP6 (0U << 10) 1605 #define NQTXC_CMD_TCP (1U << 11) 1606 #define NQTXC_CMD_UDP (0U << 11) 1607 #define NQTXC_MSSIDX_IDX_SHIFT 4 /* context index shift */ 1608 #define NQTXC_MSSIDX_IDX_MASK 0xf 1609 #define NQTXC_MSSIDX_L4LEN_SHIFT 8 /* L4 header len shift */ 1610 #define NQTXC_MSSIDX_L4LEN_MASK 0xff 1611 #define NQTXC_MSSIDX_MSS_SHIFT 16 /* MSS */ 1612 #define NQTXC_MSSIDX_MSS_MASK 0xffff 1613
Indexes created Sun Oct 19 02:09:48 GMT 2025