if_wpireg.h revision 1.4
1 /* $NetBSD: if_wpireg.h,v 1.4 2007/07/09 19:38:52 degroote Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define WPI_TX_RING_COUNT 256 21 #define WPI_SVC_RING_COUNT 256 22 #define WPI_CMD_RING_COUNT 256 23 #define WPI_RX_RING_COUNT 64 24 25 #define WPI_BUF_ALIGN 4096 26 27 /* 28 * Rings must be aligned on a four 4K-pages boundary. 29 * I had a hard time figuring this out. 30 */ 31 #define WPI_RING_DMA_ALIGN 0x4000 32 33 /* maximum scatter/gather */ 34 #define WPI_MAX_SCATTER 4 35 36 /* maximum Rx buffer size (larger than MCLBYTES) */ 37 #define WPI_RBUF_SIZE (3 * 1024) /* XXX 3000 but must be aligned! */ 38 39 /* 40 * Control and status registers. 41 */ 42 #define WPI_HWCONFIG 0x000 43 #define WPI_INTR 0x008 44 #define WPI_MASK 0x00c 45 #define WPI_INTR_STATUS 0x010 46 #define WPI_GPIO_STATUS 0x018 47 #define WPI_RESET 0x020 48 #define WPI_GPIO_CTL 0x024 49 #define WPI_EEPROM_CTL 0x02c 50 #define WPI_EEPROM_STATUS 0x030 51 #define WPI_UCODE_CLR 0x05c 52 #define WPI_TEMPERATURE 0x060 53 #define WPI_CHICKEN 0x100 54 #define WPI_PLL_CTL 0x20c 55 #define WPI_FW_TARGET 0x410 56 #define WPI_WRITE_MEM_ADDR 0x444 57 #define WPI_READ_MEM_ADDR 0x448 58 #define WPI_WRITE_MEM_DATA 0x44c 59 #define WPI_READ_MEM_DATA 0x450 60 #define WPI_TX_WIDX 0x460 61 #define WPI_TX_CTL(qid) (0x940 + (qid) * 8) 62 #define WPI_TX_BASE(qid) (0x944 + (qid) * 8) 63 #define WPI_TX_DESC(qid) (0x980 + (qid) * 80) 64 #define WPI_RX_CONFIG 0xc00 65 #define WPI_RX_BASE 0xc04 66 #define WPI_RX_WIDX 0xc20 67 #define WPI_RX_RIDX_PTR 0xc24 68 #define WPI_RX_CTL 0xcc0 69 #define WPI_RX_STATUS 0xcc4 70 #define WPI_TX_CONFIG(qid) (0xd00 + (qid) * 32) 71 #define WPI_TX_CREDIT(qid) (0xd04 + (qid) * 32) 72 #define WPI_TX_STATE(qid) (0xd08 + (qid) * 32) 73 #define WPI_TX_BASE_PTR 0xe80 74 #define WPI_MSG_CONFIG 0xe88 75 #define WPI_TX_STATUS 0xe90 76 77 78 /* 79 * NIC internal memory offsets. 80 */ 81 #define WPI_MEM_MODE 0x2e00 82 #define WPI_MEM_RA 0x2e04 83 #define WPI_MEM_TXCFG 0x2e10 84 #define WPI_MEM_MAGIC4 0x2e14 85 #define WPI_MEM_MAGIC5 0x2e20 86 #define WPI_MEM_BYPASS1 0x2e2c 87 #define WPI_MEM_BYPASS2 0x2e30 88 #define WPI_MEM_CLOCK1 0x3004 89 #define WPI_MEM_CLOCK2 0x3008 90 #define WPI_MEM_POWER 0x300c 91 #define WPI_MEM_PCIDEV 0x3010 92 #define WPI_MEM_UCODE_CTL 0x3400 93 #define WPI_MEM_UCODE_SRC 0x3404 94 #define WPI_MEM_UCODE_DST 0x3408 95 #define WPI_MEM_UCODE_SIZE 0x340c 96 #define WPI_MEM_UCODE_BASE 0x3800 97 98 99 #define WPI_MEM_MAIN_TEXT_BASE 0x3490 100 #define WPI_MEM_MAIN_TEXT_SIZE 0x3494 101 #define WPI_MEM_MAIN_DATA_BASE 0x3498 102 #define WPI_MEM_MAIN_DATA_SIZE 0x349c 103 104 /* possible flags for register WPI_HWCONFIG */ 105 #define WPI_HW_ALM_MB (1 << 8) 106 #define WPI_HW_ALM_MM (1 << 9) 107 #define WPI_HW_SKU_MRC (1 << 10) 108 #define WPI_HW_REV_D (1 << 11) 109 #define WPI_HW_TYPE_B (1 << 12) 110 111 /* possible flags for registers WPI_READ_MEM_ADDR/WPI_WRITE_MEM_ADDR */ 112 #define WPI_MEM_4 ((sizeof (uint32_t) - 1) << 24) 113 114 /* possible values for WPI_FW_TARGET */ 115 #define WPI_FW_TEXT 0x00000000 116 #define WPI_FW_DATA 0x00800000 117 118 /* possible flags for WPI_GPIO_STATUS */ 119 #define WPI_POWERED (1 << 9) 120 121 /* possible flags for register WPI_RESET */ 122 #define WPI_NEVO_RESET (1 << 0) 123 #define WPI_SW_RESET (1 << 7) 124 #define WPI_MASTER_DISABLED (1 << 8) 125 #define WPI_STOP_MASTER (1 << 9) 126 127 /* possible flags for register WPI_GPIO_CTL */ 128 #define WPI_GPIO_CLOCK (1 << 0) 129 #define WPI_GPIO_INIT (1 << 2) 130 #define WPI_GPIO_MAC (1 << 3) 131 #define WPI_GPIO_SLEEP (1 << 4) 132 #define WPI_GPIO_PWR_STATUS 0x07000000 133 #define WPI_GPIO_PWR_SLEEP (4 << 24) 134 135 /* possible flags for register WPI_CHICKEN */ 136 #define WPI_CHICKEN_RXNOLOS (1 << 23) 137 138 /* possible flags for register WPI_PLL_CTL */ 139 #define WPI_PLL_INIT (1 << 24) 140 141 /* possible flags for register WPI_UCODE_CLR */ 142 #define WPI_RADIO_OFF (1 << 1) 143 #define WPI_DISABLE_CMD (1 << 2) 144 145 /* possible flags for WPI_RX_STATUS */ 146 #define WPI_RX_IDLE (1 << 24) 147 148 /* possible flags for register WPI_UC_CTL */ 149 #define WPI_UC_RUN (1 << 30) 150 151 /* possible flags for register WPI_INTR_CSR */ 152 #define WPI_ALIVE_INTR (1 << 0) 153 #define WPI_WAKEUP_INTR (1 << 1) 154 #define WPI_SW_ERROR (1 << 25) 155 #define WPI_TX_INTR (1 << 27) 156 #define WPI_HW_ERROR (1 << 29) 157 #define WPI_RX_INTR (1 << 31) 158 159 #define WPI_INTR_MASK \ 160 (WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \ 161 WPI_ALIVE_INTR | WPI_WAKEUP_INTR) 162 163 /* possible flags for register WPI_TX_STATUS */ 164 #define WPI_TX_IDLE(qid) (1 << ((qid) + 24) | 1 << ((qid) + 16)) 165 166 /* possible flags for register WPI_EEPROM_CTL */ 167 #define WPI_EEPROM_READY (1 << 0) 168 169 /* possible flags for register WPI_EEPROM_STATUS */ 170 #define WPI_EEPROM_VERSION 0x00000007 171 #define WPI_EEPROM_LOCKED 0x00000180 172 173 174 struct wpi_shared { 175 uint32_t txbase[8]; 176 uint32_t next; 177 uint32_t reserved[2]; 178 } __attribute__((__packed__)); 179 180 #define WPI_MAX_SEG_LEN 65520 181 struct wpi_tx_desc { 182 uint32_t flags; 183 #define WPI_PAD32(x) ((((x) + 3) & ~3) - (x)) 184 185 struct { 186 uint32_t addr; 187 uint32_t len; 188 } __attribute__((__packed__)) segs[WPI_MAX_SCATTER]; 189 uint8_t reserved[28]; 190 } __attribute__((__packed__)); 191 192 struct wpi_tx_stat { 193 uint8_t nrts; 194 uint8_t ntries; 195 uint8_t nkill; 196 uint8_t rate; 197 uint32_t duration; 198 uint32_t status; 199 } __attribute__((__packed__)); 200 201 struct wpi_rx_desc { 202 uint32_t len; 203 uint8_t type; 204 #define WPI_UC_READY 1 205 #define WPI_RX_DONE 27 206 #define WPI_TX_DONE 28 207 #define WPI_START_SCAN 130 208 #define WPI_STOP_SCAN 132 209 #define WPI_STATE_CHANGED 161 210 211 uint8_t flags; 212 uint8_t idx; 213 uint8_t qid; 214 } __attribute__((__packed__)); 215 216 struct wpi_rx_stat { 217 uint8_t len; 218 #define WPI_STAT_MAXLEN 20 219 220 uint8_t id; 221 uint8_t rssi; /* received signal strength */ 222 #define WPI_RSSI_OFFSET 95 223 224 uint8_t agc; /* access gain control */ 225 uint16_t signal; 226 uint16_t noise; 227 } __attribute__((__packed__)); 228 229 struct wpi_rx_head { 230 uint16_t chan; 231 uint16_t flags; 232 uint8_t reserved; 233 uint8_t rate; 234 uint16_t len; 235 } __attribute__((__packed__)); 236 237 struct wpi_rx_tail { 238 uint32_t flags; 239 #define WPI_RX_NO_CRC_ERR (1 << 0) 240 #define WPI_RX_NO_OVFL_ERR (1 << 1) 241 /* shortcut for the above */ 242 #define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 243 244 uint64_t tstamp; 245 uint32_t tbeacon; 246 } __attribute__((__packed__)); 247 248 struct wpi_tx_cmd { 249 uint8_t code; 250 #define WPI_CMD_CONFIGURE 16 251 #define WPI_CMD_ASSOCIATE 17 252 #define WPI_CMD_SET_WME 19 253 #define WPI_CMD_TSF 20 254 #define WPI_CMD_ADD_NODE 24 255 #define WPI_CMD_TX_DATA 28 256 #define WPI_CMD_MRR_SETUP 71 257 #define WPI_CMD_SET_LED 72 258 #define WPI_CMD_SET_POWER_MODE 119 259 #define WPI_CMD_SCAN 128 260 #define WPI_CMD_SET_BEACON 145 261 #define WPI_CMD_TXPOWER 151 262 #define WPI_CMD_BLUETOOTH 155 263 264 uint8_t flags; 265 uint8_t idx; 266 uint8_t qid; 267 uint8_t data[124]; 268 } __attribute__((__packed__)); 269 270 /* structure for WPI_CMD_CONFIGURE */ 271 struct wpi_config { 272 uint8_t myaddr[IEEE80211_ADDR_LEN]; 273 uint16_t reserved1; 274 uint8_t bssid[IEEE80211_ADDR_LEN]; 275 uint16_t reserved2; 276 uint32_t reserved3[2]; 277 uint8_t mode; 278 #define WPI_MODE_HOSTAP 1 279 #define WPI_MODE_STA 3 280 #define WPI_MODE_IBSS 4 281 #define WPI_MODE_MONITOR 6 282 283 uint8_t reserved4[3]; 284 uint8_t ofdm_mask; 285 uint8_t cck_mask; 286 uint16_t associd; 287 288 uint32_t flags; 289 #define WPI_CONFIG_24GHZ (1 << 0) 290 #define WPI_CONFIG_CCK (1 << 1) 291 #define WPI_CONFIG_AUTO (1 << 2) 292 #define WPI_CONFIG_SHSLOT (1 << 4) 293 #define WPI_CONFIG_SHPREAMBLE (1 << 5) 294 #define WPI_CONFIG_NODIVERSITY (1 << 7) 295 #define WPI_CONFIG_ANTENNA_A (1 << 8) 296 #define WPI_CONFIG_ANTENNA_B (1 << 9) 297 #define WPI_CONFIG_TSF (1 << 15) 298 299 uint32_t filter; 300 #define WPI_FILTER_PROMISC (1 << 0) 301 #define WPI_FILTER_CTL (1 << 1) 302 #define WPI_FILTER_MULTICAST (1 << 2) 303 #define WPI_FILTER_NODECRYPT (1 << 3) 304 #define WPI_FILTER_BSS (1 << 5) 305 #define WPI_FILTER_BEACON (1 << 6) 306 307 uint8_t chan; 308 uint8_t reserved6[3]; 309 } __attribute__((__packed__)); 310 311 /* structure for command WPI_CMD_ASSOCIATE */ 312 struct wpi_assoc { 313 uint32_t flags; 314 uint32_t filter; 315 uint8_t ofdm_mask; 316 uint8_t cck_mask; 317 uint16_t reserved; 318 } __attribute__((__packed__)); 319 320 /* structure for command WPI_CMD_SET_WME */ 321 struct wpi_wme_setup { 322 uint32_t flags; 323 struct { 324 uint16_t cwmin; 325 uint16_t cwmax; 326 uint8_t aifsn; 327 uint8_t reserved; 328 uint16_t txop; 329 } __packed ac[WME_NUM_AC]; 330 } __attribute__((__packed__)); 331 332 /* structure for command WPI_CMD_TSF */ 333 struct wpi_cmd_tsf { 334 uint64_t tstamp; 335 uint16_t bintval; 336 uint16_t atim; 337 uint32_t binitval; 338 uint16_t lintval; 339 uint16_t reserved; 340 } __attribute__((__packed__)); 341 342 /* structure for WPI_CMD_ADD_NODE */ 343 struct wpi_node_info { 344 uint8_t control; 345 #define WPI_NODE_UPDATE (1 << 0) 346 347 uint8_t reserved1[3]; 348 uint8_t bssid[IEEE80211_ADDR_LEN]; 349 uint16_t reserved2; 350 uint8_t id; 351 #define WPI_ID_BSS 0 352 #define WPI_ID_BROADCAST 24 353 354 uint8_t flags; 355 uint16_t reserved3; 356 uint16_t key_flags; 357 uint8_t tkip; 358 uint8_t reserved4; 359 uint16_t ttak[5]; 360 uint16_t reserved5; 361 uint8_t key[IEEE80211_KEYBUF_SIZE]; 362 uint32_t action; 363 #define WPI_ACTION_SET_RATE 4 364 365 uint32_t mask; 366 uint16_t tid; 367 uint8_t rate; 368 uint8_t antenna; 369 #define WPI_ANTENNA_A (1 << 6) 370 #define WPI_ANTENNA_B (1 << 7) 371 #define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 372 373 uint8_t add_imm; 374 uint8_t del_imm; 375 uint16_t add_imm_start; 376 } __attribute__((__packed__)); 377 378 /* structure for command WPI_CMD_TX_DATA */ 379 struct wpi_cmd_data { 380 uint16_t len; 381 uint16_t lnext; 382 uint32_t flags; 383 #define WPI_TX_NEED_RTS (1 << 1) 384 #define WPI_TX_NEED_ACK (1 << 3) 385 #define WPI_TX_FULL_TXOP (1 << 7) 386 #define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 387 #define WPI_TX_AUTO_SEQ (1 << 13) 388 #define WPI_TX_INSERT_TSTAMP (1 << 16) 389 390 uint8_t rate; 391 uint8_t id; 392 uint8_t tid; 393 uint8_t security; 394 uint8_t key[IEEE80211_KEYBUF_SIZE]; 395 uint8_t tkip[IEEE80211_WEP_MICLEN]; 396 uint32_t fnext; 397 uint32_t lifetime; 398 #define WPI_LIFETIME_INFINITE 0xffffffff 399 400 uint8_t ofdm_mask; 401 uint8_t cck_mask; 402 uint8_t rts_ntries; 403 uint8_t data_ntries; 404 uint16_t timeout; 405 uint16_t txop; 406 struct ieee80211_frame wh; 407 } __attribute__((__packed__)); 408 409 /* structure for command WPI_CMD_SET_BEACON */ 410 struct wpi_cmd_beacon { 411 uint16_t len; 412 uint16_t reserved1; 413 uint32_t flags; /* same as wpi_cmd_data */ 414 uint8_t rate; 415 uint8_t id; 416 uint8_t reserved2[30]; 417 uint32_t lifetime; 418 uint8_t ofdm_mask; 419 uint8_t cck_mask; 420 uint16_t reserved3[3]; 421 uint16_t tim; 422 uint8_t timsz; 423 uint8_t reserved4; 424 struct ieee80211_frame wh; 425 } __attribute__((__packed__)); 426 427 /* structure for WPI_CMD_MRR_SETUP */ 428 struct wpi_mrr_setup { 429 uint32_t which; 430 #define WPI_MRR_CTL 0 431 #define WPI_MRR_DATA 1 432 433 struct { 434 uint8_t plcp; 435 uint8_t flags; 436 uint8_t ntries; 437 uint8_t next; 438 #define WPI_OFDM6 0 439 #define WPI_OFDM54 7 440 #define WPI_CCK1 8 441 #define WPI_CCK2 9 442 #define WPI_CCK11 11 443 444 } __attribute__((__packed__)) rates[WPI_CCK11 + 1]; 445 } __attribute__((__packed__)); 446 447 /* structure for WPI_CMD_SET_LED */ 448 struct wpi_cmd_led { 449 uint32_t unit; /* multiplier (in usecs) */ 450 uint8_t which; 451 #define WPI_LED_ACTIVITY 1 452 #define WPI_LED_LINK 2 453 454 uint8_t off; 455 uint8_t on; 456 uint8_t reserved; 457 } __attribute__((__packed__)); 458 459 /* structure for WPI_CMD_SET_POWER_MODE */ 460 struct wpi_power { 461 uint32_t flags; 462 #define WPI_POWER_CAM 0 /* constantly awake mode */ 463 464 uint32_t rx_timeout; 465 uint32_t tx_timeout; 466 uint32_t sleep[5]; 467 } __attribute__((__packed__)); 468 469 /* structure for command WPI_CMD_SCAN */ 470 471 struct wpi_scan_essid { 472 uint8_t id; 473 uint8_t len; 474 uint8_t data[IEEE80211_NWID_LEN]; 475 } __attribute__((__packed__)); 476 477 struct wpi_scan_hdr { 478 uint16_t len; 479 uint8_t reserved1; 480 uint8_t nchan; 481 uint16_t quiet; 482 uint16_t plcp_threshold; 483 uint16_t crc_threshold; 484 uint16_t reserved2; 485 uint32_t max_svc; /* background scans */ 486 uint32_t pause_svc; /* background scans */ 487 uint32_t flags; 488 uint32_t filter; 489 490 /* wpi_cmd_data structure */ 491 uint16_t paylen; 492 uint16_t lnext; 493 uint32_t txflags; 494 uint8_t rate; 495 uint8_t id; 496 uint8_t tid; 497 uint8_t security; 498 uint8_t key[IEEE80211_KEYBUF_SIZE]; 499 uint8_t tkip[IEEE80211_WEP_MICLEN]; 500 uint32_t fnext; 501 uint32_t lifetime; 502 uint8_t ofdm_mask; 503 uint8_t cck_mask; 504 uint8_t rts_ntries; 505 uint8_t data_ntries; 506 uint16_t timeout; 507 uint16_t txop; 508 509 struct wpi_scan_essid essid[4]; 510 511 /* followed by probe request body */ 512 /* followed by nchan x wpi_scan_chan */ 513 } __attribute__((__packed__)); 514 515 struct wpi_scan_chan { 516 uint8_t flags; 517 uint8_t chan; 518 #define WPI_CHAN_ACTIVE (1 << 0) 519 #define WPI_CHAN_DIRECT (1 << 1) 520 521 uint8_t rf_gain; 522 uint8_t dsp_gain; 523 uint16_t active; /* msecs */ 524 uint16_t passive; /* msecs */ 525 } __attribute__((__packed__)); 526 527 /* structure for WPI_CMD_TXPOWER */ 528 struct wpi_cmd_txpower { 529 uint8_t band; 530 #define WPI_BAND_5GHZ 0 531 #define WPI_BAND_2GHZ 1 532 533 uint8_t reserved; 534 uint16_t chan; 535 struct { 536 uint8_t plcp; 537 uint8_t rf_gain; 538 uint8_t dsp_gain; 539 uint8_t reserved; 540 } __attribute__((__packed__)) rates[WPI_CCK11 + 1]; 541 } __attribute__((__packed__)); 542 543 /* structure for WPI_CMD_BLUETOOTH */ 544 struct wpi_bluetooth { 545 uint8_t flags; 546 uint8_t lead; 547 uint8_t kill; 548 uint8_t reserved; 549 uint32_t ack; 550 uint32_t cts; 551 } __attribute__((__packed__)); 552 553 554 /* structure for WPI_UC_READY notification */ 555 struct wpi_ucode_info { 556 uint32_t version; 557 uint8_t revision[8]; 558 uint8_t type; 559 uint8_t subtype; 560 uint16_t reserved; 561 uint32_t logptr; 562 uint32_t errorptr; 563 uint32_t timestamp; 564 uint32_t valid; 565 } __attribute__((__packed__)); 566 567 /* structure for WPI_START_SCAN notification */ 568 struct wpi_start_scan { 569 uint64_t tstamp; 570 uint32_t tbeacon; 571 uint8_t chan; 572 uint8_t band; 573 uint16_t reserved; 574 uint32_t status; 575 } __attribute__((__packed__)); 576 577 /* structure for WPI_STOP_SCAN notification */ 578 struct wpi_stop_scan { 579 uint8_t nchan; 580 uint8_t status; 581 uint8_t reserved; 582 uint8_t chan; 583 uint64_t tsf; 584 } __attribute__((__packed__)); 585 586 /* firmware image header */ 587 struct wpi_firmware_hdr { 588 uint32_t version; 589 uint32_t main_textsz; 590 uint32_t main_datasz; 591 uint32_t boot_textsz; 592 uint32_t boot_datasz; 593 } __attribute__((__packed__)); 594 595 #define WPI_FW_MAIN_TEXT_MAXSZ (80 * 1024) 596 #define WPI_FW_MAIN_DATA_MAXSZ (32 * 1024) 597 #define WPI_FW_BOOT_TEXT_MAXSZ (80 * 1024) 598 #define WPI_FW_BOOT_DATA_MAXSZ (32 * 1024) 599 600 /* 601 + * Offsets into EEPROM. 602 + */ 603 604 #define WPI_EEPROM_MAC 0x015 605 #define WPI_EEPROM_REVISION 0x035 606 #define WPI_EEPROM_CAPABILITIES 0x045 607 #define WPI_EEPROM_TYPE 0x04a 608 #define WPI_EEPROM_DOMAIN 0x060 609 #define WPI_EEPROM_BAND1 0x063 610 #define WPI_EEPROM_BAND2 0x072 611 #define WPI_EEPROM_BAND3 0x080 612 #define WPI_EEPROM_BAND4 0x08d 613 #define WPI_EEPROM_BAND5 0x099 614 #define WPI_EEPROM_POWER_GRP 0x100 615 616 struct wpi_eeprom_chan { 617 uint8_t flags; 618 #define WPI_EEPROM_CHAN_VALID (1 << 0) 619 #define WPI_EEPROM_CHAN_IBSS (1 << 1) 620 #define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 621 #define WPI_EEPROM_CHAN_RADAR (1 << 4) 622 623 int8_t maxpwr; 624 } __attribute__((__packed__)); 625 626 struct wpi_eeprom_sample { 627 uint8_t index; 628 int8_t power; 629 uint16_t volt; 630 } __attribute__((__packed__)); 631 632 #define WPI_POWER_GROUPS_COUNT 5 633 struct wpi_eeprom_group { 634 struct wpi_eeprom_sample samples[5]; 635 int32_t coef[5]; 636 int32_t corr[5]; 637 int8_t maxpwr; 638 uint8_t chan; 639 int16_t temp; 640 } __attribute__((__packed__)); 641 642 #define WPI_CHAN_BANDS_COUNT 5 643 #define WPI_MAX_CHAN_PER_BAND 14 644 static const struct wpi_chan_band { 645 uint32_t addr; /* offset in EEPROM */ 646 uint8_t nchan; 647 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 648 } wpi_bands[5] = { 649 { WPI_EEPROM_BAND1, 14, 650 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 651 { WPI_EEPROM_BAND2, 13, 652 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 653 { WPI_EEPROM_BAND3, 12, 654 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 655 { WPI_EEPROM_BAND4, 11, 656 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 657 { WPI_EEPROM_BAND5, 6, 658 { 145, 149, 153, 157, 161, 165 } } 659 }; 660 661 /* convert rate index (device view) into rate in 500Kbps unit */ 662 static const uint8_t wpi_ridx_to_rate[] = { 663 12, 18, 24, 36, 48, 72, 96, 108, /* OFDM */ 664 2, 4, 11, 22 /* CCK */ 665 }; 666 667 /* convert rate index (device view) into PLCP code */ 668 static const uint8_t wpi_ridx_to_plcp[] = { 669 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, /* OFDM R1-R4 */ 670 10, 20, 55, 110 /* CCK */ 671 }; 672 673 #define WPI_MAX_PWR_INDEX 77 674 /* 675 * RF Tx gain values from highest to lowest power (values obtained from 676 * the reference driver.) 677 */ 678 static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 679 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 680 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 681 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 682 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 683 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 684 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 685 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 686 0x03 687 }; 688 689 static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 690 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 691 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 692 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 693 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 694 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 695 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 696 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 697 0x03 698 }; 699 700 /* 701 * DSP pre-DAC gain values from highest to lowest power (values obtained 702 * from the reference driver.) 703 */ 704 static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 705 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 706 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 707 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 708 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 709 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 710 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 711 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 712 0x5f 713 }; 714 715 static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 716 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 717 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 718 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 719 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 720 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 721 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 722 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 723 0x78 724 }; 725 726 #define WPI_READ(sc, reg) \ 727 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 728 729 #define WPI_WRITE(sc, reg, val) \ 730 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 731 732 #define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 733 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 734 (datap), (count)) 735
Indexes created Thu Sep 25 16:09:42 GMT 2025