if_xge.c revision 1.19.6.1
1 /* $NetBSD: if_xge.c,v 1.19.6.1 2015/06/06 14:40:09 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SUNET 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Device driver for the S2io Xframe Ten Gigabit Ethernet controller. 39 * 40 * TODO (in no specific order): 41 * HW VLAN support. 42 * IPv6 HW cksum. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_xge.c,v 1.19.6.1 2015/06/06 14:40:09 skrll Exp $"); 47 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/device.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #include <net/bpf.h> 63 64 #include <sys/bus.h> 65 #include <sys/intr.h> 66 #include <machine/endian.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcidevs.h> 74 75 #include <sys/proc.h> 76 77 #include <dev/pci/if_xgereg.h> 78 79 /* 80 * Some tunable constants, tune with care! 81 */ 82 #define RX_MODE RX_MODE_1 /* Receive mode (buffer usage, see below) */ 83 #define NRXDESCS 1016 /* # of receive descriptors (requested) */ 84 #define NTXDESCS 8192 /* Number of transmit descriptors */ 85 #define NTXFRAGS 100 /* Max fragments per packet */ 86 #define XGE_EVENT_COUNTERS /* Instrumentation */ 87 88 /* 89 * Receive buffer modes; 1, 3 or 5 buffers. 90 */ 91 #define RX_MODE_1 1 92 #define RX_MODE_3 3 93 #define RX_MODE_5 5 94 95 /* 96 * Use clever macros to avoid a bunch of #ifdef's. 97 */ 98 #define XCONCAT3(x,y,z) x ## y ## z 99 #define CONCAT3(x,y,z) XCONCAT3(x,y,z) 100 #define NDESC_BUFMODE CONCAT3(NDESC_,RX_MODE,BUFMODE) 101 #define rxd_4k CONCAT3(rxd,RX_MODE,_4k) 102 #define rxdesc ___CONCAT(rxd,RX_MODE) 103 104 #define NEXTTX(x) (((x)+1) % NTXDESCS) 105 #define NRXFRAGS RX_MODE /* hardware imposed frags */ 106 #define NRXPAGES ((NRXDESCS/NDESC_BUFMODE)+1) 107 #define NRXREAL (NRXPAGES*NDESC_BUFMODE) 108 #define RXMAPSZ (NRXPAGES*PAGE_SIZE) 109 110 #ifdef XGE_EVENT_COUNTERS 111 #define XGE_EVCNT_INCR(ev) (ev)->ev_count++ 112 #else 113 #define XGE_EVCNT_INCR(ev) /* nothing */ 114 #endif 115 116 /* 117 * Magics to fix a bug when the mac address can't be read correctly. 118 * Comes from the Linux driver. 119 */ 120 static uint64_t fix_mac[] = { 121 0x0060000000000000ULL, 0x0060600000000000ULL, 122 0x0040600000000000ULL, 0x0000600000000000ULL, 123 0x0020600000000000ULL, 0x0060600000000000ULL, 124 0x0020600000000000ULL, 0x0060600000000000ULL, 125 0x0020600000000000ULL, 0x0060600000000000ULL, 126 0x0020600000000000ULL, 0x0060600000000000ULL, 127 0x0020600000000000ULL, 0x0060600000000000ULL, 128 0x0020600000000000ULL, 0x0060600000000000ULL, 129 0x0020600000000000ULL, 0x0060600000000000ULL, 130 0x0020600000000000ULL, 0x0060600000000000ULL, 131 0x0020600000000000ULL, 0x0060600000000000ULL, 132 0x0020600000000000ULL, 0x0060600000000000ULL, 133 0x0020600000000000ULL, 0x0000600000000000ULL, 134 0x0040600000000000ULL, 0x0060600000000000ULL, 135 }; 136 137 138 struct xge_softc { 139 device_t sc_dev; 140 struct ethercom sc_ethercom; 141 #define sc_if sc_ethercom.ec_if 142 bus_dma_tag_t sc_dmat; 143 bus_space_tag_t sc_st; 144 bus_space_handle_t sc_sh; 145 bus_space_tag_t sc_txt; 146 bus_space_handle_t sc_txh; 147 void *sc_ih; 148 149 struct ifmedia xena_media; 150 pcireg_t sc_pciregs[16]; 151 152 /* Transmit structures */ 153 struct txd *sc_txd[NTXDESCS]; /* transmit frags array */ 154 bus_addr_t sc_txdp[NTXDESCS]; /* bus address of transmit frags */ 155 bus_dmamap_t sc_txm[NTXDESCS]; /* transmit frags map */ 156 struct mbuf *sc_txb[NTXDESCS]; /* transmit mbuf pointer */ 157 int sc_nexttx, sc_lasttx; 158 bus_dmamap_t sc_txmap; /* transmit descriptor map */ 159 160 /* Receive data */ 161 bus_dmamap_t sc_rxmap; /* receive descriptor map */ 162 struct rxd_4k *sc_rxd_4k[NRXPAGES]; /* receive desc pages */ 163 bus_dmamap_t sc_rxm[NRXREAL]; /* receive buffer map */ 164 struct mbuf *sc_rxb[NRXREAL]; /* mbufs on receive descriptors */ 165 int sc_nextrx; /* next descriptor to check */ 166 167 #ifdef XGE_EVENT_COUNTERS 168 struct evcnt sc_intr; /* # of interrupts */ 169 struct evcnt sc_txintr; /* # of transmit interrupts */ 170 struct evcnt sc_rxintr; /* # of receive interrupts */ 171 struct evcnt sc_txqe; /* # of xmit intrs when board queue empty */ 172 #endif 173 }; 174 175 static int xge_match(device_t parent, cfdata_t cf, void *aux); 176 static void xge_attach(device_t parent, device_t self, void *aux); 177 static int xge_alloc_txmem(struct xge_softc *); 178 static int xge_alloc_rxmem(struct xge_softc *); 179 static void xge_start(struct ifnet *); 180 static void xge_stop(struct ifnet *, int); 181 static int xge_add_rxbuf(struct xge_softc *, int); 182 static void xge_mcast_filter(struct xge_softc *sc); 183 static int xge_setup_xgxs(struct xge_softc *sc); 184 static int xge_ioctl(struct ifnet *ifp, u_long cmd, void *data); 185 static int xge_init(struct ifnet *ifp); 186 static void xge_ifmedia_status(struct ifnet *, struct ifmediareq *); 187 static int xge_xgmii_mediachange(struct ifnet *); 188 static int xge_intr(void *); 189 190 /* 191 * Helpers to address registers. 192 */ 193 #define PIF_WCSR(csr, val) pif_wcsr(sc, csr, val) 194 #define PIF_RCSR(csr) pif_rcsr(sc, csr) 195 #define TXP_WCSR(csr, val) txp_wcsr(sc, csr, val) 196 #define PIF_WKEY(csr, val) pif_wkey(sc, csr, val) 197 198 static inline void 199 pif_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val) 200 { 201 uint32_t lval, hval; 202 203 lval = val&0xffffffff; 204 hval = val>>32; 205 bus_space_write_4(sc->sc_st, sc->sc_sh, csr, lval); 206 bus_space_write_4(sc->sc_st, sc->sc_sh, csr+4, hval); 207 } 208 209 static inline uint64_t 210 pif_rcsr(struct xge_softc *sc, bus_size_t csr) 211 { 212 uint64_t val, val2; 213 val = bus_space_read_4(sc->sc_st, sc->sc_sh, csr); 214 val2 = bus_space_read_4(sc->sc_st, sc->sc_sh, csr+4); 215 val |= (val2 << 32); 216 return val; 217 } 218 219 static inline void 220 txp_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val) 221 { 222 uint32_t lval, hval; 223 224 lval = val&0xffffffff; 225 hval = val>>32; 226 bus_space_write_4(sc->sc_txt, sc->sc_txh, csr, lval); 227 bus_space_write_4(sc->sc_txt, sc->sc_txh, csr+4, hval); 228 } 229 230 231 static inline void 232 pif_wkey(struct xge_softc *sc, bus_size_t csr, uint64_t val) 233 { 234 uint32_t lval, hval; 235 236 lval = val&0xffffffff; 237 hval = val>>32; 238 PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); 239 bus_space_write_4(sc->sc_st, sc->sc_sh, csr, lval); 240 PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); 241 bus_space_write_4(sc->sc_st, sc->sc_sh, csr+4, hval); 242 } 243 244 245 CFATTACH_DECL_NEW(xge, sizeof(struct xge_softc), 246 xge_match, xge_attach, NULL, NULL); 247 248 #define XNAME device_xname(sc->sc_dev) 249 250 #define XGE_RXSYNC(desc, what) \ 251 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap, \ 252 (desc/NDESC_BUFMODE) * XGE_PAGE + sizeof(struct rxdesc) * \ 253 (desc%NDESC_BUFMODE), sizeof(struct rxdesc), what) 254 #define XGE_RXD(desc) &sc->sc_rxd_4k[desc/NDESC_BUFMODE]-> \ 255 r4_rxd[desc%NDESC_BUFMODE] 256 257 /* 258 * Non-tunable constants. 259 */ 260 #define XGE_MAX_MTU 9600 261 #define XGE_IP_MAXPACKET 65535 /* same as IP_MAXPACKET */ 262 263 static int 264 xge_match(device_t parent, cfdata_t cf, void *aux) 265 { 266 struct pci_attach_args *pa = aux; 267 268 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_S2IO && 269 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_S2IO_XFRAME) 270 return (1); 271 272 return (0); 273 } 274 275 void 276 xge_attach(device_t parent, device_t self, void *aux) 277 { 278 struct pci_attach_args *pa = aux; 279 struct xge_softc *sc; 280 struct ifnet *ifp; 281 pcireg_t memtype; 282 pci_intr_handle_t ih; 283 const char *intrstr = NULL; 284 pci_chipset_tag_t pc = pa->pa_pc; 285 uint8_t enaddr[ETHER_ADDR_LEN]; 286 uint64_t val; 287 int i; 288 char intrbuf[PCI_INTRSTR_LEN]; 289 290 sc = device_private(self); 291 sc->sc_dev = self; 292 sc->sc_dmat = pa->pa_dmat; 293 294 /* Get BAR0 address */ 295 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, XGE_PIF_BAR); 296 if (pci_mapreg_map(pa, XGE_PIF_BAR, memtype, 0, 297 &sc->sc_st, &sc->sc_sh, 0, 0)) { 298 aprint_error("%s: unable to map PIF BAR registers\n", XNAME); 299 return; 300 } 301 302 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, XGE_TXP_BAR); 303 if (pci_mapreg_map(pa, XGE_TXP_BAR, memtype, 0, 304 &sc->sc_txt, &sc->sc_txh, 0, 0)) { 305 aprint_error("%s: unable to map TXP BAR registers\n", XNAME); 306 return; 307 } 308 309 /* Save PCI config space */ 310 for (i = 0; i < 64; i += 4) 311 sc->sc_pciregs[i/4] = pci_conf_read(pa->pa_pc, pa->pa_tag, i); 312 313 #if BYTE_ORDER == LITTLE_ENDIAN 314 val = (uint64_t)0xFFFFFFFFFFFFFFFFULL; 315 val &= ~(TxF_R_SE|RxF_W_SE); 316 PIF_WCSR(SWAPPER_CTRL, val); 317 PIF_WCSR(SWAPPER_CTRL, val); 318 #elif BYTE_ORDER == BIG_ENDIAN 319 /* do nothing */ 320 #else 321 #error bad endianness! 322 #endif 323 324 if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) 325 return printf("%s: failed configuring endian, %llx != %llx!\n", 326 XNAME, (unsigned long long)val, SWAPPER_MAGIC); 327 328 /* 329 * The MAC addr may be all FF's, which is not good. 330 * Resolve it by writing some magics to GPIO_CONTROL and 331 * force a chip reset to read in the serial eeprom again. 332 */ 333 for (i = 0; i < sizeof(fix_mac)/sizeof(fix_mac[0]); i++) { 334 PIF_WCSR(GPIO_CONTROL, fix_mac[i]); 335 PIF_RCSR(GPIO_CONTROL); 336 } 337 338 /* 339 * Reset the chip and restore the PCI registers. 340 */ 341 PIF_WCSR(SW_RESET, 0xa5a5a50000000000ULL); 342 DELAY(500000); 343 for (i = 0; i < 64; i += 4) 344 pci_conf_write(pa->pa_pc, pa->pa_tag, i, sc->sc_pciregs[i/4]); 345 346 /* 347 * Restore the byte order registers. 348 */ 349 #if BYTE_ORDER == LITTLE_ENDIAN 350 val = (uint64_t)0xFFFFFFFFFFFFFFFFULL; 351 val &= ~(TxF_R_SE|RxF_W_SE); 352 PIF_WCSR(SWAPPER_CTRL, val); 353 PIF_WCSR(SWAPPER_CTRL, val); 354 #elif BYTE_ORDER == BIG_ENDIAN 355 /* do nothing */ 356 #else 357 #error bad endianness! 358 #endif 359 360 if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) 361 return printf("%s: failed configuring endian2, %llx != %llx!\n", 362 XNAME, (unsigned long long)val, SWAPPER_MAGIC); 363 364 /* 365 * XGXS initialization. 366 */ 367 /* 29, reset */ 368 PIF_WCSR(SW_RESET, 0); 369 DELAY(500000); 370 371 /* 30, configure XGXS transceiver */ 372 xge_setup_xgxs(sc); 373 374 /* 33, program MAC address (not needed here) */ 375 /* Get ethernet address */ 376 PIF_WCSR(RMAC_ADDR_CMD_MEM, 377 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(0)); 378 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 379 ; 380 val = PIF_RCSR(RMAC_ADDR_DATA0_MEM); 381 for (i = 0; i < ETHER_ADDR_LEN; i++) 382 enaddr[i] = (uint8_t)(val >> (56 - (8*i))); 383 384 /* 385 * Get memory for transmit descriptor lists. 386 */ 387 if (xge_alloc_txmem(sc)) 388 return printf("%s: failed allocating txmem.\n", XNAME); 389 390 /* 9 and 10 - set FIFO number/prio */ 391 PIF_WCSR(TX_FIFO_P0, TX_FIFO_LEN0(NTXDESCS)); 392 PIF_WCSR(TX_FIFO_P1, 0ULL); 393 PIF_WCSR(TX_FIFO_P2, 0ULL); 394 PIF_WCSR(TX_FIFO_P3, 0ULL); 395 396 /* 11, XXX set round-robin prio? */ 397 398 /* 12, enable transmit FIFO */ 399 val = PIF_RCSR(TX_FIFO_P0); 400 val |= TX_FIFO_ENABLE; 401 PIF_WCSR(TX_FIFO_P0, val); 402 403 /* 13, disable some error checks */ 404 PIF_WCSR(TX_PA_CFG, 405 TX_PA_CFG_IFR|TX_PA_CFG_ISO|TX_PA_CFG_ILC|TX_PA_CFG_ILE); 406 407 /* 408 * Create transmit DMA maps. 409 * Make them large for TSO. 410 */ 411 for (i = 0; i < NTXDESCS; i++) { 412 if (bus_dmamap_create(sc->sc_dmat, XGE_IP_MAXPACKET, 413 NTXFRAGS, MCLBYTES, 0, 0, &sc->sc_txm[i])) 414 return printf("%s: cannot create TX DMA maps\n", XNAME); 415 } 416 417 sc->sc_lasttx = NTXDESCS-1; 418 419 /* 420 * RxDMA initialization. 421 * Only use one out of 8 possible receive queues. 422 */ 423 if (xge_alloc_rxmem(sc)) /* allocate rx descriptor memory */ 424 return printf("%s: failed allocating rxmem\n", XNAME); 425 426 /* Create receive buffer DMA maps */ 427 for (i = 0; i < NRXREAL; i++) { 428 if (bus_dmamap_create(sc->sc_dmat, XGE_MAX_MTU, 429 NRXFRAGS, MCLBYTES, 0, 0, &sc->sc_rxm[i])) 430 return printf("%s: cannot create RX DMA maps\n", XNAME); 431 } 432 433 /* allocate mbufs to receive descriptors */ 434 for (i = 0; i < NRXREAL; i++) 435 if (xge_add_rxbuf(sc, i)) 436 panic("out of mbufs too early"); 437 438 /* 14, setup receive ring priority */ 439 PIF_WCSR(RX_QUEUE_PRIORITY, 0ULL); /* only use one ring */ 440 441 /* 15, setup receive ring round-robin calendar */ 442 PIF_WCSR(RX_W_ROUND_ROBIN_0, 0ULL); /* only use one ring */ 443 PIF_WCSR(RX_W_ROUND_ROBIN_1, 0ULL); 444 PIF_WCSR(RX_W_ROUND_ROBIN_2, 0ULL); 445 PIF_WCSR(RX_W_ROUND_ROBIN_3, 0ULL); 446 PIF_WCSR(RX_W_ROUND_ROBIN_4, 0ULL); 447 448 /* 16, write receive ring start address */ 449 PIF_WCSR(PRC_RXD0_0, (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr); 450 /* PRC_RXD0_[1-7] are not used */ 451 452 /* 17, Setup alarm registers */ 453 PIF_WCSR(PRC_ALARM_ACTION, 0ULL); /* Default everything to retry */ 454 455 /* 18, init receive ring controller */ 456 #if RX_MODE == RX_MODE_1 457 val = RING_MODE_1; 458 #elif RX_MODE == RX_MODE_3 459 val = RING_MODE_3; 460 #else /* RX_MODE == RX_MODE_5 */ 461 val = RING_MODE_5; 462 #endif 463 PIF_WCSR(PRC_CTRL_0, RC_IN_SVC|val); 464 /* leave 1-7 disabled */ 465 /* XXXX snoop configuration? */ 466 467 /* 19, set chip memory assigned to the queue */ 468 PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 64)); /* all 64M to queue 0 */ 469 470 /* 20, setup RLDRAM parameters */ 471 /* do not touch it for now */ 472 473 /* 21, setup pause frame thresholds */ 474 /* so not touch the defaults */ 475 /* XXX - must 0xff be written as stated in the manual? */ 476 477 /* 22, configure RED */ 478 /* we do not want to drop packets, so ignore */ 479 480 /* 23, initiate RLDRAM */ 481 val = PIF_RCSR(MC_RLDRAM_MRS); 482 val |= MC_QUEUE_SIZE_ENABLE|MC_RLDRAM_MRS_ENABLE; 483 PIF_WCSR(MC_RLDRAM_MRS, val); 484 DELAY(1000); 485 486 /* 487 * Setup interrupt policies. 488 */ 489 /* 40, Transmit interrupts */ 490 PIF_WCSR(TTI_DATA1_MEM, TX_TIMER_VAL(0x1ff) | TX_TIMER_AC | 491 TX_URNG_A(5) | TX_URNG_B(20) | TX_URNG_C(48)); 492 PIF_WCSR(TTI_DATA2_MEM, 493 TX_UFC_A(25) | TX_UFC_B(64) | TX_UFC_C(128) | TX_UFC_D(512)); 494 PIF_WCSR(TTI_COMMAND_MEM, TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE); 495 while (PIF_RCSR(TTI_COMMAND_MEM) & TTI_CMD_MEM_STROBE) 496 ; 497 498 /* 41, Receive interrupts */ 499 PIF_WCSR(RTI_DATA1_MEM, RX_TIMER_VAL(0x800) | RX_TIMER_AC | 500 RX_URNG_A(5) | RX_URNG_B(20) | RX_URNG_C(50)); 501 PIF_WCSR(RTI_DATA2_MEM, 502 RX_UFC_A(64) | RX_UFC_B(128) | RX_UFC_C(256) | RX_UFC_D(512)); 503 PIF_WCSR(RTI_COMMAND_MEM, RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE); 504 while (PIF_RCSR(RTI_COMMAND_MEM) & RTI_CMD_MEM_STROBE) 505 ; 506 507 /* 508 * Setup media stuff. 509 */ 510 ifmedia_init(&sc->xena_media, IFM_IMASK, xge_xgmii_mediachange, 511 xge_ifmedia_status); 512 ifmedia_add(&sc->xena_media, IFM_ETHER|IFM_10G_LR, 0, NULL); 513 ifmedia_set(&sc->xena_media, IFM_ETHER|IFM_10G_LR); 514 515 aprint_normal("%s: Ethernet address %s\n", XNAME, 516 ether_sprintf(enaddr)); 517 518 ifp = &sc->sc_ethercom.ec_if; 519 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 520 ifp->if_baudrate = 10000000000LL; 521 ifp->if_init = xge_init; 522 ifp->if_stop = xge_stop; 523 ifp->if_softc = sc; 524 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 525 ifp->if_ioctl = xge_ioctl; 526 ifp->if_start = xge_start; 527 IFQ_SET_MAXLEN(&ifp->if_snd, max(NTXDESCS - 1, IFQ_MAXLEN)); 528 IFQ_SET_READY(&ifp->if_snd); 529 530 /* 531 * Offloading capabilities. 532 */ 533 sc->sc_ethercom.ec_capabilities |= 534 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 535 ifp->if_capabilities |= 536 IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_IPv4_Tx | 537 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_TCPv4_Tx | 538 IFCAP_CSUM_UDPv4_Rx | IFCAP_CSUM_UDPv4_Tx | IFCAP_TSOv4; 539 540 /* 541 * Attach the interface. 542 */ 543 if_attach(ifp); 544 ether_ifattach(ifp, enaddr); 545 546 /* 547 * Setup interrupt vector before initializing. 548 */ 549 if (pci_intr_map(pa, &ih)) 550 return aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 551 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 552 if ((sc->sc_ih = 553 pci_intr_establish(pc, ih, IPL_NET, xge_intr, sc)) == NULL) 554 return aprint_error_dev(sc->sc_dev, "unable to establish interrupt at %s\n", 555 intrstr ? intrstr : "<unknown>"); 556 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 557 558 #ifdef XGE_EVENT_COUNTERS 559 evcnt_attach_dynamic(&sc->sc_intr, EVCNT_TYPE_MISC, 560 NULL, XNAME, "intr"); 561 evcnt_attach_dynamic(&sc->sc_txintr, EVCNT_TYPE_MISC, 562 NULL, XNAME, "txintr"); 563 evcnt_attach_dynamic(&sc->sc_rxintr, EVCNT_TYPE_MISC, 564 NULL, XNAME, "rxintr"); 565 evcnt_attach_dynamic(&sc->sc_txqe, EVCNT_TYPE_MISC, 566 NULL, XNAME, "txqe"); 567 #endif 568 } 569 570 void 571 xge_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 572 { 573 struct xge_softc *sc = ifp->if_softc; 574 uint64_t reg; 575 576 ifmr->ifm_status = IFM_AVALID; 577 ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; 578 579 reg = PIF_RCSR(ADAPTER_STATUS); 580 if ((reg & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0) 581 ifmr->ifm_status |= IFM_ACTIVE; 582 } 583 584 int 585 xge_xgmii_mediachange(struct ifnet *ifp) 586 { 587 return 0; 588 } 589 590 static void 591 xge_enable(struct xge_softc *sc) 592 { 593 uint64_t val; 594 595 /* 2, enable adapter */ 596 val = PIF_RCSR(ADAPTER_CONTROL); 597 val |= ADAPTER_EN; 598 PIF_WCSR(ADAPTER_CONTROL, val); 599 600 /* 3, light the card enable led */ 601 val = PIF_RCSR(ADAPTER_CONTROL); 602 val |= LED_ON; 603 PIF_WCSR(ADAPTER_CONTROL, val); 604 printf("%s: link up\n", XNAME); 605 606 } 607 608 int 609 xge_init(struct ifnet *ifp) 610 { 611 struct xge_softc *sc = ifp->if_softc; 612 uint64_t val; 613 614 if (ifp->if_flags & IFF_RUNNING) 615 return 0; 616 617 /* 31+32, setup MAC config */ 618 PIF_WKEY(MAC_CFG, TMAC_EN|RMAC_EN|TMAC_APPEND_PAD|RMAC_STRIP_FCS| 619 RMAC_BCAST_EN|RMAC_DISCARD_PFRM|RMAC_PROM_EN); 620 621 DELAY(1000); 622 623 /* 54, ensure that the adapter is 'quiescent' */ 624 val = PIF_RCSR(ADAPTER_STATUS); 625 if ((val & QUIESCENT) != QUIESCENT) { 626 char buf[200]; 627 printf("%s: adapter not quiescent, aborting\n", XNAME); 628 val = (val & QUIESCENT) ^ QUIESCENT; 629 snprintb(buf, sizeof buf, QUIESCENT_BMSK, val); 630 printf("%s: ADAPTER_STATUS missing bits %s\n", XNAME, buf); 631 return 1; 632 } 633 634 /* 56, enable the transmit laser */ 635 val = PIF_RCSR(ADAPTER_CONTROL); 636 val |= EOI_TX_ON; 637 PIF_WCSR(ADAPTER_CONTROL, val); 638 639 xge_enable(sc); 640 /* 641 * Enable all interrupts 642 */ 643 PIF_WCSR(TX_TRAFFIC_MASK, 0); 644 PIF_WCSR(RX_TRAFFIC_MASK, 0); 645 PIF_WCSR(GENERAL_INT_MASK, 0); 646 PIF_WCSR(TXPIC_INT_MASK, 0); 647 PIF_WCSR(RXPIC_INT_MASK, 0); 648 PIF_WCSR(MAC_INT_MASK, MAC_TMAC_INT); /* only from RMAC */ 649 PIF_WCSR(MAC_RMAC_ERR_MASK, ~RMAC_LINK_STATE_CHANGE_INT); 650 651 652 /* Done... */ 653 ifp->if_flags |= IFF_RUNNING; 654 ifp->if_flags &= ~IFF_OACTIVE; 655 656 return 0; 657 } 658 659 static void 660 xge_stop(struct ifnet *ifp, int disable) 661 { 662 struct xge_softc *sc = ifp->if_softc; 663 uint64_t val; 664 665 val = PIF_RCSR(ADAPTER_CONTROL); 666 val &= ~ADAPTER_EN; 667 PIF_WCSR(ADAPTER_CONTROL, val); 668 669 while ((PIF_RCSR(ADAPTER_STATUS) & QUIESCENT) != QUIESCENT) 670 ; 671 } 672 673 int 674 xge_intr(void *pv) 675 { 676 struct xge_softc *sc = pv; 677 struct txd *txd; 678 struct ifnet *ifp = &sc->sc_if; 679 bus_dmamap_t dmp; 680 uint64_t val; 681 int i, lasttx, plen; 682 683 val = PIF_RCSR(GENERAL_INT_STATUS); 684 if (val == 0) 685 return 0; /* no interrupt here */ 686 687 XGE_EVCNT_INCR(&sc->sc_intr); 688 689 PIF_WCSR(GENERAL_INT_STATUS, val); 690 691 if ((val = PIF_RCSR(MAC_RMAC_ERR_REG)) & RMAC_LINK_STATE_CHANGE_INT) { 692 /* Wait for quiescence */ 693 printf("%s: link down\n", XNAME); 694 while ((PIF_RCSR(ADAPTER_STATUS) & QUIESCENT) != QUIESCENT) 695 ; 696 PIF_WCSR(MAC_RMAC_ERR_REG, RMAC_LINK_STATE_CHANGE_INT); 697 698 val = PIF_RCSR(ADAPTER_STATUS); 699 if ((val & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0) 700 xge_enable(sc); /* Only if link restored */ 701 } 702 703 if ((val = PIF_RCSR(TX_TRAFFIC_INT))) { 704 XGE_EVCNT_INCR(&sc->sc_txintr); 705 PIF_WCSR(TX_TRAFFIC_INT, val); /* clear interrupt bits */ 706 } 707 /* 708 * Collect sent packets. 709 */ 710 lasttx = sc->sc_lasttx; 711 while ((i = NEXTTX(sc->sc_lasttx)) != sc->sc_nexttx) { 712 txd = sc->sc_txd[i]; 713 dmp = sc->sc_txm[i]; 714 715 bus_dmamap_sync(sc->sc_dmat, dmp, 0, 716 dmp->dm_mapsize, 717 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 718 719 if (txd->txd_control1 & TXD_CTL1_OWN) { 720 bus_dmamap_sync(sc->sc_dmat, dmp, 0, 721 dmp->dm_mapsize, BUS_DMASYNC_PREREAD); 722 break; 723 } 724 bus_dmamap_unload(sc->sc_dmat, dmp); 725 m_freem(sc->sc_txb[i]); 726 ifp->if_opackets++; 727 sc->sc_lasttx = i; 728 } 729 if (i == sc->sc_nexttx) { 730 XGE_EVCNT_INCR(&sc->sc_txqe); 731 } 732 733 if (sc->sc_lasttx != lasttx) 734 ifp->if_flags &= ~IFF_OACTIVE; 735 736 xge_start(ifp); /* Try to get more packets on the wire */ 737 738 if ((val = PIF_RCSR(RX_TRAFFIC_INT))) { 739 XGE_EVCNT_INCR(&sc->sc_rxintr); 740 PIF_WCSR(RX_TRAFFIC_INT, val); /* clear interrupt bits */ 741 } 742 743 for (;;) { 744 struct rxdesc *rxd; 745 struct mbuf *m; 746 747 XGE_RXSYNC(sc->sc_nextrx, 748 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 749 750 rxd = XGE_RXD(sc->sc_nextrx); 751 if (rxd->rxd_control1 & RXD_CTL1_OWN) { 752 XGE_RXSYNC(sc->sc_nextrx, BUS_DMASYNC_PREREAD); 753 break; 754 } 755 756 /* got a packet */ 757 m = sc->sc_rxb[sc->sc_nextrx]; 758 #if RX_MODE == RX_MODE_1 759 plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2); 760 #elif RX_MODE == RX_MODE_3 761 #error Fix rxmodes in xge_intr 762 #elif RX_MODE == RX_MODE_5 763 plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2); 764 plen += m->m_next->m_len = RXD_CTL2_BUF1SIZ(rxd->rxd_control2); 765 plen += m->m_next->m_next->m_len = 766 RXD_CTL2_BUF2SIZ(rxd->rxd_control2); 767 plen += m->m_next->m_next->m_next->m_len = 768 RXD_CTL3_BUF3SIZ(rxd->rxd_control3); 769 plen += m->m_next->m_next->m_next->m_next->m_len = 770 RXD_CTL3_BUF4SIZ(rxd->rxd_control3); 771 #endif 772 m->m_pkthdr.rcvif = ifp; 773 m->m_pkthdr.len = plen; 774 775 val = rxd->rxd_control1; 776 777 if (xge_add_rxbuf(sc, sc->sc_nextrx)) { 778 /* Failed, recycle this mbuf */ 779 #if RX_MODE == RX_MODE_1 780 rxd->rxd_control2 = RXD_MKCTL2(MCLBYTES, 0, 0); 781 rxd->rxd_control1 = RXD_CTL1_OWN; 782 #elif RX_MODE == RX_MODE_3 783 #elif RX_MODE == RX_MODE_5 784 #endif 785 XGE_RXSYNC(sc->sc_nextrx, 786 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 787 ifp->if_ierrors++; 788 break; 789 } 790 791 ifp->if_ipackets++; 792 793 if (RXD_CTL1_PROTOS(val) & (RXD_CTL1_P_IPv4|RXD_CTL1_P_IPv6)) { 794 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 795 if (RXD_CTL1_L3CSUM(val) != 0xffff) 796 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 797 } 798 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_TCP) { 799 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_TCPv6; 800 if (RXD_CTL1_L4CSUM(val) != 0xffff) 801 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 802 } 803 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_UDP) { 804 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4|M_CSUM_UDPv6; 805 if (RXD_CTL1_L4CSUM(val) != 0xffff) 806 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 807 } 808 809 bpf_mtap(ifp, m); 810 811 (*ifp->if_input)(ifp, m); 812 813 if (++sc->sc_nextrx == NRXREAL) 814 sc->sc_nextrx = 0; 815 816 } 817 818 return 0; 819 } 820 821 int 822 xge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 823 { 824 struct xge_softc *sc = ifp->if_softc; 825 struct ifreq *ifr = (struct ifreq *) data; 826 int s, error = 0; 827 828 s = splnet(); 829 830 switch (cmd) { 831 case SIOCSIFMTU: 832 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > XGE_MAX_MTU) 833 error = EINVAL; 834 else if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET){ 835 PIF_WCSR(RMAC_MAX_PYLD_LEN, 836 RMAC_PYLD_LEN(ifr->ifr_mtu)); 837 error = 0; 838 } 839 break; 840 841 case SIOCGIFMEDIA: 842 case SIOCSIFMEDIA: 843 error = ifmedia_ioctl(ifp, ifr, &sc->xena_media, cmd); 844 break; 845 846 default: 847 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 848 break; 849 850 error = 0; 851 852 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 853 ; 854 else if (ifp->if_flags & IFF_RUNNING) { 855 /* Change multicast list */ 856 xge_mcast_filter(sc); 857 } 858 break; 859 } 860 861 splx(s); 862 return(error); 863 } 864 865 void 866 xge_mcast_filter(struct xge_softc *sc) 867 { 868 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 869 struct ethercom *ec = &sc->sc_ethercom; 870 struct ether_multi *enm; 871 struct ether_multistep step; 872 int i, numaddr = 1; /* first slot used for card unicast address */ 873 uint64_t val; 874 875 ETHER_FIRST_MULTI(step, ec, enm); 876 while (enm != NULL) { 877 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 878 /* Skip ranges */ 879 goto allmulti; 880 } 881 if (numaddr == MAX_MCAST_ADDR) 882 goto allmulti; 883 for (val = 0, i = 0; i < ETHER_ADDR_LEN; i++) { 884 val <<= 8; 885 val |= enm->enm_addrlo[i]; 886 } 887 PIF_WCSR(RMAC_ADDR_DATA0_MEM, val << 16); 888 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL); 889 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 890 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(numaddr)); 891 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 892 ; 893 numaddr++; 894 ETHER_NEXT_MULTI(step, enm); 895 } 896 /* set the remaining entries to the broadcast address */ 897 for (i = numaddr; i < MAX_MCAST_ADDR; i++) { 898 PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0xffffffffffff0000ULL); 899 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL); 900 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 901 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(i)); 902 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 903 ; 904 } 905 ifp->if_flags &= ~IFF_ALLMULTI; 906 return; 907 908 allmulti: 909 /* Just receive everything with the multicast bit set */ 910 ifp->if_flags |= IFF_ALLMULTI; 911 PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0x8000000000000000ULL); 912 PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xF000000000000000ULL); 913 PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| 914 RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(1)); 915 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR) 916 ; 917 } 918 919 void 920 xge_start(struct ifnet *ifp) 921 { 922 struct xge_softc *sc = ifp->if_softc; 923 struct txd *txd = NULL; /* XXX - gcc */ 924 bus_dmamap_t dmp; 925 struct mbuf *m; 926 uint64_t par, lcr; 927 int nexttx = 0, ntxd, error, i; 928 929 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 930 return; 931 932 par = lcr = 0; 933 for (;;) { 934 IFQ_POLL(&ifp->if_snd, m); 935 if (m == NULL) 936 break; /* out of packets */ 937 938 if (sc->sc_nexttx == sc->sc_lasttx) 939 break; /* No more space */ 940 941 nexttx = sc->sc_nexttx; 942 dmp = sc->sc_txm[nexttx]; 943 944 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmp, m, 945 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0) { 946 printf("%s: bus_dmamap_load_mbuf error %d\n", 947 XNAME, error); 948 break; 949 } 950 IFQ_DEQUEUE(&ifp->if_snd, m); 951 952 bus_dmamap_sync(sc->sc_dmat, dmp, 0, dmp->dm_mapsize, 953 BUS_DMASYNC_PREWRITE); 954 955 txd = sc->sc_txd[nexttx]; 956 sc->sc_txb[nexttx] = m; 957 for (i = 0; i < dmp->dm_nsegs; i++) { 958 if (dmp->dm_segs[i].ds_len == 0) 959 continue; 960 txd->txd_control1 = dmp->dm_segs[i].ds_len; 961 txd->txd_control2 = 0; 962 txd->txd_bufaddr = dmp->dm_segs[i].ds_addr; 963 txd++; 964 } 965 ntxd = txd - sc->sc_txd[nexttx] - 1; 966 txd = sc->sc_txd[nexttx]; 967 txd->txd_control1 |= TXD_CTL1_OWN|TXD_CTL1_GCF; 968 txd->txd_control2 = TXD_CTL2_UTIL; 969 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 970 txd->txd_control1 |= TXD_CTL1_MSS(m->m_pkthdr.segsz); 971 txd->txd_control1 |= TXD_CTL1_LSO; 972 } 973 974 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 975 txd->txd_control2 |= TXD_CTL2_CIPv4; 976 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 977 txd->txd_control2 |= TXD_CTL2_CTCP; 978 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 979 txd->txd_control2 |= TXD_CTL2_CUDP; 980 txd[ntxd].txd_control1 |= TXD_CTL1_GCL; 981 982 bus_dmamap_sync(sc->sc_dmat, dmp, 0, dmp->dm_mapsize, 983 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 984 985 par = sc->sc_txdp[nexttx]; 986 lcr = TXDL_NUMTXD(ntxd) | TXDL_LGC_FIRST | TXDL_LGC_LAST; 987 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) 988 lcr |= TXDL_SFF; 989 TXP_WCSR(TXDL_PAR, par); 990 TXP_WCSR(TXDL_LCR, lcr); 991 992 bpf_mtap(ifp, m); 993 994 sc->sc_nexttx = NEXTTX(nexttx); 995 } 996 } 997 998 /* 999 * Allocate DMA memory for transmit descriptor fragments. 1000 * Only one map is used for all descriptors. 1001 */ 1002 int 1003 xge_alloc_txmem(struct xge_softc *sc) 1004 { 1005 struct txd *txp; 1006 bus_dma_segment_t seg; 1007 bus_addr_t txdp; 1008 void *kva; 1009 int i, rseg, state; 1010 1011 #define TXMAPSZ (NTXDESCS*NTXFRAGS*sizeof(struct txd)) 1012 state = 0; 1013 if (bus_dmamem_alloc(sc->sc_dmat, TXMAPSZ, PAGE_SIZE, 0, 1014 &seg, 1, &rseg, BUS_DMA_NOWAIT)) 1015 goto err; 1016 state++; 1017 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, TXMAPSZ, &kva, 1018 BUS_DMA_NOWAIT)) 1019 goto err; 1020 1021 state++; 1022 if (bus_dmamap_create(sc->sc_dmat, TXMAPSZ, 1, TXMAPSZ, 0, 1023 BUS_DMA_NOWAIT, &sc->sc_txmap)) 1024 goto err; 1025 state++; 1026 if (bus_dmamap_load(sc->sc_dmat, sc->sc_txmap, 1027 kva, TXMAPSZ, NULL, BUS_DMA_NOWAIT)) 1028 goto err; 1029 1030 /* setup transmit array pointers */ 1031 txp = (struct txd *)kva; 1032 txdp = seg.ds_addr; 1033 for (txp = (struct txd *)kva, i = 0; i < NTXDESCS; i++) { 1034 sc->sc_txd[i] = txp; 1035 sc->sc_txdp[i] = txdp; 1036 txp += NTXFRAGS; 1037 txdp += (NTXFRAGS * sizeof(struct txd)); 1038 } 1039 1040 return 0; 1041 1042 err: 1043 if (state > 2) 1044 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap); 1045 if (state > 1) 1046 bus_dmamem_unmap(sc->sc_dmat, kva, TXMAPSZ); 1047 if (state > 0) 1048 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1049 return ENOBUFS; 1050 } 1051 1052 /* 1053 * Allocate DMA memory for receive descriptor, 1054 * only one map is used for all descriptors. 1055 * link receive descriptor pages together. 1056 */ 1057 int 1058 xge_alloc_rxmem(struct xge_softc *sc) 1059 { 1060 struct rxd_4k *rxpp; 1061 bus_dma_segment_t seg; 1062 void *kva; 1063 int i, rseg, state; 1064 1065 /* sanity check */ 1066 if (sizeof(struct rxd_4k) != XGE_PAGE) { 1067 printf("bad compiler struct alignment, %d != %d\n", 1068 (int)sizeof(struct rxd_4k), XGE_PAGE); 1069 return EINVAL; 1070 } 1071 1072 state = 0; 1073 if (bus_dmamem_alloc(sc->sc_dmat, RXMAPSZ, PAGE_SIZE, 0, 1074 &seg, 1, &rseg, BUS_DMA_NOWAIT)) 1075 goto err; 1076 state++; 1077 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, RXMAPSZ, &kva, 1078 BUS_DMA_NOWAIT)) 1079 goto err; 1080 1081 state++; 1082 if (bus_dmamap_create(sc->sc_dmat, RXMAPSZ, 1, RXMAPSZ, 0, 1083 BUS_DMA_NOWAIT, &sc->sc_rxmap)) 1084 goto err; 1085 state++; 1086 if (bus_dmamap_load(sc->sc_dmat, sc->sc_rxmap, 1087 kva, RXMAPSZ, NULL, BUS_DMA_NOWAIT)) 1088 goto err; 1089 1090 /* setup receive page link pointers */ 1091 for (rxpp = (struct rxd_4k *)kva, i = 0; i < NRXPAGES; i++, rxpp++) { 1092 sc->sc_rxd_4k[i] = rxpp; 1093 rxpp->r4_next = (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr + 1094 (i*sizeof(struct rxd_4k)) + sizeof(struct rxd_4k); 1095 } 1096 sc->sc_rxd_4k[NRXPAGES-1]->r4_next = 1097 (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr; 1098 1099 return 0; 1100 1101 err: 1102 if (state > 2) 1103 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap); 1104 if (state > 1) 1105 bus_dmamem_unmap(sc->sc_dmat, kva, TXMAPSZ); 1106 if (state > 0) 1107 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1108 return ENOBUFS; 1109 } 1110 1111 1112 /* 1113 * Add a new mbuf chain to descriptor id. 1114 */ 1115 int 1116 xge_add_rxbuf(struct xge_softc *sc, int id) 1117 { 1118 struct rxdesc *rxd; 1119 struct mbuf *m[5]; 1120 int page, desc, error; 1121 #if RX_MODE == RX_MODE_5 1122 int i; 1123 #endif 1124 1125 page = id/NDESC_BUFMODE; 1126 desc = id%NDESC_BUFMODE; 1127 1128 rxd = &sc->sc_rxd_4k[page]->r4_rxd[desc]; 1129 1130 /* 1131 * Allocate mbufs. 1132 * Currently five mbufs and two clusters are used, 1133 * the hardware will put (ethernet, ip, tcp/udp) headers in 1134 * their own buffer and the clusters are only used for data. 1135 */ 1136 #if RX_MODE == RX_MODE_1 1137 MGETHDR(m[0], M_DONTWAIT, MT_DATA); 1138 if (m[0] == NULL) 1139 return ENOBUFS; 1140 MCLGET(m[0], M_DONTWAIT); 1141 if ((m[0]->m_flags & M_EXT) == 0) { 1142 m_freem(m[0]); 1143 return ENOBUFS; 1144 } 1145 m[0]->m_len = m[0]->m_pkthdr.len = m[0]->m_ext.ext_size; 1146 #elif RX_MODE == RX_MODE_3 1147 #error missing rxmode 3. 1148 #elif RX_MODE == RX_MODE_5 1149 MGETHDR(m[0], M_DONTWAIT, MT_DATA); 1150 for (i = 1; i < 5; i++) { 1151 MGET(m[i], M_DONTWAIT, MT_DATA); 1152 } 1153 if (m[3]) 1154 MCLGET(m[3], M_DONTWAIT); 1155 if (m[4]) 1156 MCLGET(m[4], M_DONTWAIT); 1157 if (!m[0] || !m[1] || !m[2] || !m[3] || !m[4] || 1158 ((m[3]->m_flags & M_EXT) == 0) || ((m[4]->m_flags & M_EXT) == 0)) { 1159 /* Out of something */ 1160 for (i = 0; i < 5; i++) 1161 if (m[i] != NULL) 1162 m_free(m[i]); 1163 return ENOBUFS; 1164 } 1165 /* Link'em together */ 1166 m[0]->m_next = m[1]; 1167 m[1]->m_next = m[2]; 1168 m[2]->m_next = m[3]; 1169 m[3]->m_next = m[4]; 1170 #else 1171 #error bad mode RX_MODE 1172 #endif 1173 1174 if (sc->sc_rxb[id]) 1175 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxm[id]); 1176 sc->sc_rxb[id] = m[0]; 1177 1178 error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rxm[id], m[0], 1179 BUS_DMA_READ|BUS_DMA_NOWAIT); 1180 if (error) 1181 return error; 1182 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxm[id], 0, 1183 sc->sc_rxm[id]->dm_mapsize, BUS_DMASYNC_PREREAD); 1184 1185 #if RX_MODE == RX_MODE_1 1186 rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, 0, 0); 1187 rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr; 1188 rxd->rxd_control1 = RXD_CTL1_OWN; 1189 #elif RX_MODE == RX_MODE_3 1190 #elif RX_MODE == RX_MODE_5 1191 rxd->rxd_control3 = RXD_MKCTL3(0, m[3]->m_len, m[4]->m_len); 1192 rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, m[1]->m_len, m[2]->m_len); 1193 rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr; 1194 rxd->rxd_buf1 = (uint64_t)sc->sc_rxm[id]->dm_segs[1].ds_addr; 1195 rxd->rxd_buf2 = (uint64_t)sc->sc_rxm[id]->dm_segs[2].ds_addr; 1196 rxd->rxd_buf3 = (uint64_t)sc->sc_rxm[id]->dm_segs[3].ds_addr; 1197 rxd->rxd_buf4 = (uint64_t)sc->sc_rxm[id]->dm_segs[4].ds_addr; 1198 rxd->rxd_control1 = RXD_CTL1_OWN; 1199 #endif 1200 1201 XGE_RXSYNC(id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1202 return 0; 1203 } 1204 1205 /* 1206 * These magics comes from the FreeBSD driver. 1207 */ 1208 int 1209 xge_setup_xgxs(struct xge_softc *sc) 1210 { 1211 /* The magic numbers are described in the users guide */ 1212 1213 /* Writing to MDIO 0x8000 (Global Config 0) */ 1214 PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50); 1215 PIF_WCSR(DTX_CONTROL, 0x80000515000000E0ULL); DELAY(50); 1216 PIF_WCSR(DTX_CONTROL, 0x80000515D93500E4ULL); DELAY(50); 1217 1218 /* Writing to MDIO 0x8000 (Global Config 1) */ 1219 PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50); 1220 PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50); 1221 PIF_WCSR(DTX_CONTROL, 0x80010515001e00e4ULL); DELAY(50); 1222 1223 /* Reset the Gigablaze */ 1224 PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50); 1225 PIF_WCSR(DTX_CONTROL, 0x80020515000000E0ULL); DELAY(50); 1226 PIF_WCSR(DTX_CONTROL, 0x80020515F21000E4ULL); DELAY(50); 1227 1228 /* read the pole settings */ 1229 PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50); 1230 PIF_WCSR(DTX_CONTROL, 0x80000515000000e0ULL); DELAY(50); 1231 PIF_WCSR(DTX_CONTROL, 0x80000515000000ecULL); DELAY(50); 1232 1233 PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50); 1234 PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50); 1235 PIF_WCSR(DTX_CONTROL, 0x80010515000000ecULL); DELAY(50); 1236 1237 PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50); 1238 PIF_WCSR(DTX_CONTROL, 0x80020515000000e0ULL); DELAY(50); 1239 PIF_WCSR(DTX_CONTROL, 0x80020515000000ecULL); DELAY(50); 1240 1241 /* Workaround for TX Lane XAUI initialization error. 1242 Read Xpak PHY register 24 for XAUI lane status */ 1243 PIF_WCSR(DTX_CONTROL, 0x0018040000000000ULL); DELAY(50); 1244 PIF_WCSR(DTX_CONTROL, 0x00180400000000e0ULL); DELAY(50); 1245 PIF_WCSR(DTX_CONTROL, 0x00180400000000ecULL); DELAY(50); 1246 1247 /* 1248 * Reading the MDIO control with value 0x1804001c0F001c 1249 * means the TxLanes were already in sync 1250 * Reading the MDIO control with value 0x1804000c0x001c 1251 * means some TxLanes are not in sync where x is a 4-bit 1252 * value representing each lanes 1253 */ 1254 #if 0 1255 val = PIF_RCSR(MDIO_CONTROL); 1256 if (val != 0x1804001c0F001cULL) { 1257 printf("%s: MDIO_CONTROL: %llx != %llx\n", 1258 XNAME, val, 0x1804001c0F001cULL); 1259 return 1; 1260 } 1261 #endif 1262 1263 /* Set and remove the DTE XS INTLoopBackN */ 1264 PIF_WCSR(DTX_CONTROL, 0x0000051500000000ULL); DELAY(50); 1265 PIF_WCSR(DTX_CONTROL, 0x00000515604000e0ULL); DELAY(50); 1266 PIF_WCSR(DTX_CONTROL, 0x00000515604000e4ULL); DELAY(50); 1267 PIF_WCSR(DTX_CONTROL, 0x00000515204000e4ULL); DELAY(50); 1268 PIF_WCSR(DTX_CONTROL, 0x00000515204000ecULL); DELAY(50); 1269 1270 #if 0 1271 /* Reading the DTX control register Should be 0x5152040001c */ 1272 val = PIF_RCSR(DTX_CONTROL); 1273 if (val != 0x5152040001cULL) { 1274 printf("%s: DTX_CONTROL: %llx != %llx\n", 1275 XNAME, val, 0x5152040001cULL); 1276 return 1; 1277 } 1278 #endif 1279 1280 PIF_WCSR(MDIO_CONTROL, 0x0018040000000000ULL); DELAY(50); 1281 PIF_WCSR(MDIO_CONTROL, 0x00180400000000e0ULL); DELAY(50); 1282 PIF_WCSR(MDIO_CONTROL, 0x00180400000000ecULL); DELAY(50); 1283 1284 #if 0 1285 /* Reading the MIOD control should be 0x1804001c0f001c */ 1286 val = PIF_RCSR(MDIO_CONTROL); 1287 if (val != 0x1804001c0f001cULL) { 1288 printf("%s: MDIO_CONTROL2: %llx != %llx\n", 1289 XNAME, val, 0x1804001c0f001cULL); 1290 return 1; 1291 } 1292 #endif 1293 return 0; 1294 } 1295
Indexes created Tue Oct 14 00:09:49 GMT 2025