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igc_base.c revision 1.1 
      1 /*	$OpenBSD: igc_base.c,v 1.1 2021/10/31 14:52:57 patrick Exp $	*/
      2 /*-
      3  * Copyright 2021 Intel Corp
      4  * Copyright 2021 Rubicon Communications, LLC (Netgate)
      5  * SPDX-License-Identifier: BSD-3-Clause
      6  */
      7 
      8 #include <dev/pci/igc_hw.h>
      9 #include <dev/pci/igc_i225.h>
     10 #include <dev/pci/if_igc.h>
     11 #include <dev/pci/igc_mac.h>
     12 #include <dev/pci/igc_base.h>
     13 
     14 /**
     15  *  igc_acquire_phy_base - Acquire rights to access PHY
     16  *  @hw: pointer to the HW structure
     17  *
     18  *  Acquire access rights to the correct PHY.
     19  **/
     20 int
     21 igc_acquire_phy_base(struct igc_hw *hw)
     22 {
     23 	uint16_t mask = IGC_SWFW_PHY0_SM;
     24 
     25 	DEBUGFUNC("igc_acquire_phy_base");
     26 
     27 	if (hw->bus.func == IGC_FUNC_1)
     28 		mask = IGC_SWFW_PHY1_SM;
     29 
     30 	return hw->mac.ops.acquire_swfw_sync(hw, mask);
     31 }
     32 
     33 /**
     34  *  igc_release_phy_base - Release rights to access PHY
     35  *  @hw: pointer to the HW structure
     36  *
     37  *  A wrapper to release access rights to the correct PHY.
     38  **/
     39 void
     40 igc_release_phy_base(struct igc_hw *hw)
     41 {
     42 	uint16_t mask = IGC_SWFW_PHY0_SM;
     43 
     44 	DEBUGFUNC("igc_release_phy_base");
     45 
     46 	if (hw->bus.func == IGC_FUNC_1)
     47 		mask = IGC_SWFW_PHY1_SM;
     48 
     49 	hw->mac.ops.release_swfw_sync(hw, mask);
     50 }
     51 
     52 /**
     53  *  igc_init_hw_base - Initialize hardware
     54  *  @hw: pointer to the HW structure
     55  *
     56  *  This inits the hardware readying it for operation.
     57  **/
     58 int
     59 igc_init_hw_base(struct igc_hw *hw)
     60 {
     61 	struct igc_mac_info *mac = &hw->mac;
     62 	uint16_t i, rar_count = mac->rar_entry_count;
     63 	int ret_val;
     64 
     65 	DEBUGFUNC("igc_init_hw_base");
     66 
     67 	/* Setup the receive address */
     68 	igc_init_rx_addrs_generic(hw, rar_count);
     69 
     70 	/* Zero out the Multicast HASH table */
     71 	DEBUGOUT("Zeroing the MTA\n");
     72 	for (i = 0; i < mac->mta_reg_count; i++)
     73 		IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, 0);
     74 
     75 	/* Zero out the Unicast HASH table */
     76 	DEBUGOUT("Zeroing the UTA\n");
     77 	for (i = 0; i < mac->uta_reg_count; i++)
     78 		IGC_WRITE_REG_ARRAY(hw, IGC_UTA, i, 0);
     79 
     80 	/* Setup link and flow control */
     81 	ret_val = mac->ops.setup_link(hw);
     82 	/*
     83 	 * Clear all of the statistics registers (clear on read).  It is
     84 	 * important that we do this after we have tried to establish link
     85 	 * because the symbol error count will increment wildly if there
     86 	 * is no link.
     87 	 */
     88 	igc_clear_hw_cntrs_base_generic(hw);
     89 
     90 	return ret_val;
     91 }
     92 
     93 /**
     94  * igc_power_down_phy_copper_base - Remove link during PHY power down
     95  * @hw: pointer to the HW structure
     96  *
     97  * In the case of a PHY power down to save power, or to turn off link during a
     98  * driver unload, or wake on lan is not enabled, remove the link.
     99  **/
    100 void
    101 igc_power_down_phy_copper_base(struct igc_hw *hw)
    102 {
    103 	struct igc_phy_info *phy = &hw->phy;
    104 
    105 	if (!(phy->ops.check_reset_block))
    106 		return;
    107 
    108 	/* If the management interface is not enabled, then power down */
    109 	if (phy->ops.check_reset_block(hw))
    110 		igc_power_down_phy_copper(hw);
    111 
    112 	return;
    113 }
    114