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igc_base.h revision 1.1 
      1 /*	$OpenBSD: igc_base.h,v 1.1 2021/10/31 14:52:57 patrick Exp $	*/
      2 /*-
      3  * Copyright 2021 Intel Corp
      4  * Copyright 2021 Rubicon Communications, LLC (Netgate)
      5  * SPDX-License-Identifier: BSD-3-Clause
      6  *
      7  * $FreeBSD$
      8  */
      9 
     10 #ifndef _IGC_BASE_H_
     11 #define _IGC_BASE_H_
     12 
     13 /* Forward declaration */
     14 struct igc_hw;
     15 
     16 int		igc_init_hw_base(struct igc_hw *hw);
     17 void		igc_power_down_phy_copper_base(struct igc_hw *hw);
     18 extern void	igc_rx_fifo_flush_base(struct igc_hw *hw);
     19 int		igc_acquire_phy_base(struct igc_hw *hw);
     20 void		igc_release_phy_base(struct igc_hw *hw);
     21 
     22 /* Transmit Descriptor - Advanced */
     23 union igc_adv_tx_desc {
     24 	struct {
     25 		uint64_t buffer_addr;	/* Address of descriptor's data buf */
     26 		uint32_t cmd_type_len;
     27 		uint32_t olinfo_status;
     28 	} read;
     29 	struct {
     30 		uint64_t rsvd;		/* Reserved */
     31 		uint32_t nxtseq_seed;
     32 		uint32_t status;
     33 	} wb;
     34 };
     35 
     36 /* Context descriptors */
     37 struct igc_adv_tx_context_desc {
     38 	uint32_t vlan_macip_lens;
     39 	union {
     40 		uint32_t launch_time;
     41 		uint32_t seqnum_seed;
     42 	};
     43 	uint32_t type_tucmd_mlhl;
     44 	uint32_t mss_l4len_idx;
     45 };
     46 
     47 /* Adv Transmit Descriptor Config Masks */
     48 #define IGC_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
     49 #define IGC_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
     50 #define IGC_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
     51 #define IGC_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
     52 #define IGC_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
     53 #define IGC_ADVTXD_DCMD_DDTYP_ISCSI	0x10000000 /* DDP hdr type or iSCSI */
     54 #define IGC_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
     55 #define IGC_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
     56 #define IGC_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
     57 #define IGC_ADVTXD_MAC_LINKSEC	0x00040000 /* Apply LinkSec on pkt */
     58 #define IGC_ADVTXD_MAC_TSTAMP	0x00080000 /* IEEE1588 Timestamp pkt */
     59 #define IGC_ADVTXD_STAT_SN_CRC	0x00000002 /* NXTSEQ/SEED prsnt in WB */
     60 #define IGC_ADVTXD_IDX_SHIFT	4 /* Adv desc Index shift */
     61 #define IGC_ADVTXD_POPTS_ISCO_1ST	0x00000000 /* 1st TSO of iSCSI PDU */
     62 #define IGC_ADVTXD_POPTS_ISCO_MDL	0x00000800 /* Middle TSO of iSCSI PDU */
     63 #define IGC_ADVTXD_POPTS_ISCO_LAST	0x00001000 /* Last TSO of iSCSI PDU */
     64 /* 1st & Last TSO-full iSCSI PDU*/
     65 #define IGC_ADVTXD_POPTS_ISCO_FULL	0x00001800
     66 #define IGC_ADVTXD_POPTS_IPSEC	0x00000400 /* IPSec offload request */
     67 #define IGC_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
     68 
     69 /* Advanced Transmit Context Descriptor Config */
     70 #define IGC_ADVTXD_MACLEN_SHIFT		9 /* Adv ctxt desc mac len shift */
     71 #define IGC_ADVTXD_VLAN_SHIFT		16 /* Adv ctxt vlan tag shift */
     72 #define IGC_ADVTXD_TUCMD_IPV4		0x00000400 /* IP Packet Type: 1=IPv4 */
     73 #define IGC_ADVTXD_TUCMD_IPV6		0x00000000 /* IP Packet Type: 0=IPv6 */
     74 #define IGC_ADVTXD_TUCMD_L4T_UDP	0x00000000 /* L4 Packet TYPE of UDP */
     75 #define IGC_ADVTXD_TUCMD_L4T_TCP	0x00000800 /* L4 Packet TYPE of TCP */
     76 #define IGC_ADVTXD_TUCMD_L4T_SCTP	0x00001000 /* L4 Packet TYPE of SCTP */
     77 #define IGC_ADVTXD_TUCMD_IPSEC_TYPE_ESP	0x00002000 /* IPSec Type ESP */
     78 /* IPSec Encrypt Enable for ESP */
     79 #define IGC_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN	0x00004000
     80 /* Req requires Markers and CRC */
     81 #define IGC_ADVTXD_TUCMD_MKRREQ		0x00002000
     82 #define IGC_ADVTXD_L4LEN_SHIFT		8 	/* Adv ctxt L4LEN shift */
     83 #define IGC_ADVTXD_MSS_SHIFT		16	/* Adv ctxt MSS shift */
     84 /* Adv ctxt IPSec SA IDX mask */
     85 #define IGC_ADVTXD_IPSEC_SA_INDEX_MASK	0x000000FF
     86 /* Adv ctxt IPSec ESP len mask */
     87 #define IGC_ADVTXD_IPSEC_ESP_LEN_MASK	0x000000FF
     88 
     89 #define IGC_RAR_ENTRIES_BASE		16
     90 
     91 /* Receive Descriptor - Advanced */
     92 union igc_adv_rx_desc {
     93 	struct {
     94 		uint64_t pkt_addr; /* Packet buffer address */
     95 		uint64_t hdr_addr; /* Header buffer address */
     96 	} read;
     97 	struct {
     98 		struct {
     99 			union {
    100 				uint32_t data;
    101 				struct {
    102 					uint16_t pkt_info; /* Pkt type */
    103 					/* Split Header, header buffer len */
    104 					uint16_t hdr_info;
    105 				} hs_rss;
    106 			} lo_dword;
    107 			union {
    108 				uint32_t rss; /* RSS hash */
    109 				struct {
    110 					uint16_t ip_id; /* IP id */
    111 					uint16_t csum; /* Packet checksum */
    112 				} csum_ip;
    113 			} hi_dword;
    114 		} lower;
    115 		struct {
    116 			uint32_t status_error; /* ext status/error */
    117 			uint16_t length; /* Packet length */
    118 			uint16_t vlan; /* VLAN tag */
    119 		} upper;
    120 	} wb;  /* writeback */
    121 };
    122 
    123 /* Additional Transmit Descriptor Control definitions */
    124 #define IGC_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
    125 
    126 /* Additional Receive Descriptor Control definitions */
    127 #define IGC_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
    128 
    129 /* SRRCTL bit definitions */
    130 #define IGC_SRRCTL_BSIZEPKT_SHIFT	10	/* Shift _right_ */
    131 #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT	2	/* Shift _left_ */
    132 #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
    133 
    134 #endif /* _IGC_BASE_H_ */
    135