igc_i225.h revision 1.2.2.2
1 1.2.2.2 martin /* $NetBSD: igc_i225.h,v 1.2.2.2 2023/10/08 13:19:34 martin Exp $ */ 2 1.2.2.2 martin /* $OpenBSD: igc_i225.h,v 1.2 2023/02/03 11:31:52 mbuhl Exp $ */ 3 1.2.2.2 martin /*- 4 1.2.2.2 martin * Copyright 2021 Intel Corp 5 1.2.2.2 martin * Copyright 2021 Rubicon Communications, LLC (Netgate) 6 1.2.2.2 martin * SPDX-License-Identifier: BSD-3-Clause 7 1.2.2.2 martin * 8 1.2.2.2 martin * $FreeBSD$ 9 1.2.2.2 martin */ 10 1.2.2.2 martin 11 1.2.2.2 martin #ifndef _IGC_I225_H_ 12 1.2.2.2 martin #define _IGC_I225_H_ 13 1.2.2.2 martin 14 1.2.2.2 martin #include <dev/pci/igc/igc_hw.h> 15 1.2.2.2 martin 16 1.2.2.2 martin bool igc_get_flash_presence_i225(struct igc_hw *); 17 1.2.2.2 martin int igc_update_flash_i225(struct igc_hw *); 18 1.2.2.2 martin int igc_update_nvm_checksum_i225(struct igc_hw *); 19 1.2.2.2 martin int igc_validate_nvm_checksum_i225(struct igc_hw *); 20 1.2.2.2 martin int igc_write_nvm_srwr_i225(struct igc_hw *, uint16_t, uint16_t, 21 1.2.2.2 martin uint16_t *); 22 1.2.2.2 martin int igc_read_nvm_srrd_i225(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 23 1.2.2.2 martin int igc_set_flsw_flash_burst_counter_i225(struct igc_hw *, uint32_t); 24 1.2.2.2 martin int igc_write_erase_flash_command_i225(struct igc_hw *, uint32_t, uint32_t); 25 1.2.2.2 martin int igc_check_for_link_i225(struct igc_hw *); 26 1.2.2.2 martin int igc_acquire_swfw_sync_i225(struct igc_hw *, uint16_t); 27 1.2.2.2 martin void igc_release_swfw_sync_i225(struct igc_hw *, uint16_t); 28 1.2.2.2 martin int igc_set_ltr_i225(struct igc_hw *, bool); 29 1.2.2.2 martin int igc_init_hw_i225(struct igc_hw *); 30 1.2.2.2 martin int igc_setup_copper_link_i225(struct igc_hw *); 31 1.2.2.2 martin int igc_set_eee_i225(struct igc_hw *, bool, bool, bool); 32 1.2.2.2 martin 33 1.2.2.2 martin #define ID_LED_DEFAULT_I225 \ 34 1.2.2.2 martin ((ID_LED_OFF1_ON2 << 8) | (ID_LED_DEF1_DEF2 << 4) | (ID_LED_OFF1_OFF2)) 35 1.2.2.2 martin 36 1.2.2.2 martin #define ID_LED_DEFAULT_I225_SERDES \ 37 1.2.2.2 martin ((ID_LED_DEF1_DEF2 << 8) | (ID_LED_DEF1_DEF2 << 4) | (ID_LED_OFF1_ON2)) 38 1.2.2.2 martin 39 1.2.2.2 martin /* NVM offset defaults for I225 devices */ 40 1.2.2.2 martin #define NVM_INIT_CTRL_2_DEFAULT_I225 0x7243 41 1.2.2.2 martin #define NVM_INIT_CTRL_4_DEFAULT_I225 0x00C1 42 1.2.2.2 martin #define NVM_LED_1_CFG_DEFAULT_I225 0x0184 43 1.2.2.2 martin #define NVM_LED_0_2_CFG_DEFAULT_I225 0x200C 44 1.2.2.2 martin 45 1.2.2.2 martin #define IGC_MRQC_ENABLE_RSS_4Q 0x00000002 46 1.2.2.2 martin #define IGC_MRQC_ENABLE_VMDQ 0x00000003 47 1.2.2.2 martin #define IGC_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 48 1.2.2.2 martin #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 49 1.2.2.2 martin #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 50 1.2.2.2 martin #define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 51 1.2.2.2 martin #define IGC_I225_SHADOW_RAM_SIZE 4096 52 1.2.2.2 martin #define IGC_I225_ERASE_CMD_OPCODE 0x02000000 53 1.2.2.2 martin #define IGC_I225_WRITE_CMD_OPCODE 0x01000000 54 1.2.2.2 martin #define IGC_FLSWCTL_DONE 0x40000000 55 1.2.2.2 martin #define IGC_FLSWCTL_CMDV 0x10000000 56 1.2.2.2 martin 57 1.2.2.2 martin /* SRRCTL bit definitions */ 58 1.2.2.2 martin #define IGC_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 59 1.2.2.2 martin #define IGC_SRRCTL_DESCTYPE_LEGACY 0x00000000 60 1.2.2.2 martin #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 61 1.2.2.2 martin #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 62 1.2.2.2 martin #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 63 1.2.2.2 martin #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 64 1.2.2.2 martin #define IGC_SRRCTL_DESCTYPE_MASK 0x0E000000 65 1.2.2.2 martin #define IGC_SRRCTL_DROP_EN 0x80000000 66 1.2.2.2 martin #define IGC_SRRCTL_BSIZEPKT_MASK 0x0000007F 67 1.2.2.2 martin #define IGC_SRRCTL_BSIZEHDR_MASK 0x00003F00 68 1.2.2.2 martin 69 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_MASK 0x0000000F 70 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_SHIFT 12 71 1.2.2.2 martin #define IGC_RXDADV_HDRBUFLEN_MASK 0x7FE0 72 1.2.2.2 martin #define IGC_RXDADV_HDRBUFLEN_SHIFT 5 73 1.2.2.2 martin #define IGC_RXDADV_SPLITHEADER_EN 0x00001000 74 1.2.2.2 martin #define IGC_RXDADV_SPH 0x8000 75 1.2.2.2 martin #define IGC_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ 76 1.2.2.2 martin #define IGC_RXDADV_ERR_HBO 0x00800000 77 1.2.2.2 martin 78 1.2.2.2 martin /* RSS Hash results */ 79 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_NONE 0x00000000 80 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 81 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_IPV4 0x00000002 82 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 83 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_IPV6_EX 0x00000004 84 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_IPV6 0x00000005 85 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 86 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 87 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 88 1.2.2.2 martin #define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 89 1.2.2.2 martin 90 1.2.2.2 martin /* RSS Packet Types as indicated in the receive descriptor */ 91 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_ILMASK 0x000000F0 92 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_TLMASK 0x00000F00 93 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_NONE 0x00000000 94 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ 95 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */ 96 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */ 97 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */ 98 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 99 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 100 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 101 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 102 1.2.2.2 martin 103 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 104 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 105 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 106 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 107 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 108 1.2.2.2 martin #define IGC_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 109 1.2.2.2 martin 110 1.2.2.2 martin #endif /* _IGC_I225_H_ */ 111
Indexes created Thu Oct 02 01:09:59 GMT 2025