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igc_i225.h revision 1.2
      1 /*	$NetBSD: igc_i225.h,v 1.2 2023/10/04 07:35:27 rin Exp $	*/
      2 /*	$OpenBSD: igc_i225.h,v 1.2 2023/02/03 11:31:52 mbuhl Exp $	*/
      3 /*-
      4  * Copyright 2021 Intel Corp
      5  * Copyright 2021 Rubicon Communications, LLC (Netgate)
      6  * SPDX-License-Identifier: BSD-3-Clause
      7  *
      8  * $FreeBSD$
      9  */
     10 
     11 #ifndef _IGC_I225_H_
     12 #define _IGC_I225_H_
     13 
     14 #include <dev/pci/igc/igc_hw.h>
     15 
     16 bool	igc_get_flash_presence_i225(struct igc_hw *);
     17 int	igc_update_flash_i225(struct igc_hw *);
     18 int	igc_update_nvm_checksum_i225(struct igc_hw *);
     19 int	igc_validate_nvm_checksum_i225(struct igc_hw *);
     20 int	igc_write_nvm_srwr_i225(struct igc_hw *, uint16_t, uint16_t,
     21 	    uint16_t *);
     22 int	igc_read_nvm_srrd_i225(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
     23 int	igc_set_flsw_flash_burst_counter_i225(struct igc_hw *, uint32_t);
     24 int	igc_write_erase_flash_command_i225(struct igc_hw *, uint32_t, uint32_t);
     25 int	igc_check_for_link_i225(struct igc_hw *);
     26 int	igc_acquire_swfw_sync_i225(struct igc_hw *, uint16_t);
     27 void	igc_release_swfw_sync_i225(struct igc_hw *, uint16_t);
     28 int	igc_set_ltr_i225(struct igc_hw *, bool);
     29 int	igc_init_hw_i225(struct igc_hw *);
     30 int	igc_setup_copper_link_i225(struct igc_hw *);
     31 int	igc_set_eee_i225(struct igc_hw *, bool, bool, bool);
     32 
     33 #define ID_LED_DEFAULT_I225						\
     34 	((ID_LED_OFF1_ON2  << 8) | (ID_LED_DEF1_DEF2 << 4) | (ID_LED_OFF1_OFF2))
     35 
     36 #define ID_LED_DEFAULT_I225_SERDES					\
     37 	((ID_LED_DEF1_DEF2 << 8) | (ID_LED_DEF1_DEF2 << 4) | (ID_LED_OFF1_ON2))
     38 
     39 /* NVM offset defaults for I225 devices */
     40 #define NVM_INIT_CTRL_2_DEFAULT_I225	0x7243
     41 #define NVM_INIT_CTRL_4_DEFAULT_I225	0x00C1
     42 #define NVM_LED_1_CFG_DEFAULT_I225	0x0184
     43 #define NVM_LED_0_2_CFG_DEFAULT_I225	0x200C
     44 
     45 #define IGC_MRQC_ENABLE_RSS_4Q		0x00000002
     46 #define IGC_MRQC_ENABLE_VMDQ		0x00000003
     47 #define IGC_MRQC_ENABLE_VMDQ_RSS_2Q	0x00000005
     48 #define IGC_MRQC_RSS_FIELD_IPV4_UDP	0x00400000
     49 #define IGC_MRQC_RSS_FIELD_IPV6_UDP	0x00800000
     50 #define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX	0x01000000
     51 #define IGC_I225_SHADOW_RAM_SIZE	4096
     52 #define IGC_I225_ERASE_CMD_OPCODE	0x02000000
     53 #define IGC_I225_WRITE_CMD_OPCODE	0x01000000
     54 #define IGC_FLSWCTL_DONE		0x40000000
     55 #define IGC_FLSWCTL_CMDV		0x10000000
     56 
     57 /* SRRCTL bit definitions */
     58 #define IGC_SRRCTL_BSIZEHDRSIZE_MASK			0x00000F00
     59 #define IGC_SRRCTL_DESCTYPE_LEGACY			0x00000000
     60 #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT			0x04000000
     61 #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS		0x0A000000
     62 #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION		0x06000000
     63 #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT	0x08000000
     64 #define IGC_SRRCTL_DESCTYPE_MASK			0x0E000000
     65 #define IGC_SRRCTL_DROP_EN				0x80000000
     66 #define IGC_SRRCTL_BSIZEPKT_MASK			0x0000007F
     67 #define IGC_SRRCTL_BSIZEHDR_MASK			0x00003F00
     68 
     69 #define IGC_RXDADV_RSSTYPE_MASK		0x0000000F
     70 #define IGC_RXDADV_RSSTYPE_SHIFT	12
     71 #define IGC_RXDADV_HDRBUFLEN_MASK	0x7FE0
     72 #define IGC_RXDADV_HDRBUFLEN_SHIFT	5
     73 #define IGC_RXDADV_SPLITHEADER_EN	0x00001000
     74 #define IGC_RXDADV_SPH			0x8000
     75 #define IGC_RXDADV_STAT_TS		0x10000	/* Pkt was time stamped */
     76 #define IGC_RXDADV_ERR_HBO		0x00800000
     77 
     78 /* RSS Hash results */
     79 #define IGC_RXDADV_RSSTYPE_NONE		0x00000000
     80 #define IGC_RXDADV_RSSTYPE_IPV4_TCP	0x00000001
     81 #define IGC_RXDADV_RSSTYPE_IPV4		0x00000002
     82 #define IGC_RXDADV_RSSTYPE_IPV6_TCP	0x00000003
     83 #define IGC_RXDADV_RSSTYPE_IPV6_EX	0x00000004
     84 #define IGC_RXDADV_RSSTYPE_IPV6		0x00000005
     85 #define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX	0x00000006
     86 #define IGC_RXDADV_RSSTYPE_IPV4_UDP	0x00000007
     87 #define IGC_RXDADV_RSSTYPE_IPV6_UDP	0x00000008
     88 #define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX	0x00000009
     89 
     90 /* RSS Packet Types as indicated in the receive descriptor */
     91 #define IGC_RXDADV_PKTTYPE_ILMASK	0x000000F0
     92 #define IGC_RXDADV_PKTTYPE_TLMASK	0x00000F00
     93 #define IGC_RXDADV_PKTTYPE_NONE		0x00000000
     94 #define IGC_RXDADV_PKTTYPE_IPV4		0x00000010 /* IPV4 hdr present */
     95 #define IGC_RXDADV_PKTTYPE_IPV4_EX	0x00000020 /* IPV4 hdr + extensions */
     96 #define IGC_RXDADV_PKTTYPE_IPV6		0x00000040 /* IPV6 hdr present */
     97 #define IGC_RXDADV_PKTTYPE_IPV6_EX	0x00000080 /* IPV6 hdr + extensions */
     98 #define IGC_RXDADV_PKTTYPE_TCP		0x00000100 /* TCP hdr present */
     99 #define IGC_RXDADV_PKTTYPE_UDP		0x00000200 /* UDP hdr present */
    100 #define IGC_RXDADV_PKTTYPE_SCTP		0x00000400 /* SCTP hdr present */
    101 #define IGC_RXDADV_PKTTYPE_NFS		0x00000800 /* NFS hdr present */
    102 
    103 #define IGC_RXDADV_PKTTYPE_IPSEC_ESP	0x00001000 /* IPSec ESP */
    104 #define IGC_RXDADV_PKTTYPE_IPSEC_AH	0x00002000 /* IPSec AH */
    105 #define IGC_RXDADV_PKTTYPE_LINKSEC	0x00004000 /* LinkSec Encap */
    106 #define IGC_RXDADV_PKTTYPE_ETQF		0x00008000 /* PKTTYPE is ETQF index */
    107 #define IGC_RXDADV_PKTTYPE_ETQF_MASK	0x00000070 /* ETQF has 8 indices */
    108 #define IGC_RXDADV_PKTTYPE_ETQF_SHIFT	4 /* Right-shift 4 bits */
    109 
    110 #endif	/* _IGC_I225_H_ */
    111