igc_phy.h revision 1.1
1 /* $OpenBSD: igc_phy.h,v 1.2 2022/05/11 06:14:15 kevlo Exp $ */ 2 /*- 3 * Copyright 2021 Intel Corp 4 * Copyright 2021 Rubicon Communications, LLC (Netgate) 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * $FreeBSD$ 8 */ 9 10 #ifndef _IGC_PHY_H_ 11 #define _IGC_PHY_H_ 12 13 void igc_init_phy_ops_generic(struct igc_hw *); 14 int igc_null_read_reg(struct igc_hw *, uint32_t, uint16_t *); 15 void igc_null_phy_generic(struct igc_hw *); 16 int igc_null_lplu_state(struct igc_hw *, bool); 17 int igc_null_write_reg(struct igc_hw *, uint32_t, uint16_t); 18 int igc_null_set_page(struct igc_hw *, uint16_t); 19 int igc_check_downshift_generic(struct igc_hw *); 20 int igc_check_reset_block_generic(struct igc_hw *); 21 int igc_get_phy_id(struct igc_hw *); 22 int igc_phy_hw_reset_generic(struct igc_hw *); 23 int igc_phy_reset_dsp_generic(struct igc_hw *); 24 int igc_set_d3_lplu_state_generic(struct igc_hw *, bool); 25 int igc_setup_copper_link_generic(struct igc_hw *); 26 int igc_phy_has_link_generic(struct igc_hw *, uint32_t, uint32_t, bool *); 27 int igc_determine_phy_address(struct igc_hw *); 28 int igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *, uint16_t *); 29 int igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *, uint16_t *); 30 void igc_power_up_phy_copper(struct igc_hw *); 31 void igc_power_down_phy_copper(struct igc_hw *); 32 int igc_read_phy_reg_mdic(struct igc_hw *, uint32_t offset, uint16_t *); 33 int igc_write_phy_reg_mdic(struct igc_hw *, uint32_t offset, uint16_t); 34 int igc_read_xmdio_reg(struct igc_hw *, uint16_t, uint8_t, uint16_t *); 35 int igc_write_xmdio_reg(struct igc_hw *, uint16_t, uint8_t, uint16_t); 36 int igc_write_phy_reg_gpy(struct igc_hw *, uint32_t, uint16_t); 37 int igc_read_phy_reg_gpy(struct igc_hw *, uint32_t, uint16_t *); 38 int igc_wait_autoneg(struct igc_hw *); 39 40 /* IGP01IGC Specific Registers */ 41 #define IGP01IGC_PHY_PORT_CONFIG 0x10 /* Port Config */ 42 #define IGP01IGC_PHY_PORT_STATUS 0x11 /* Status */ 43 #define IGP01IGC_PHY_PORT_CTRL 0x12 /* Control */ 44 #define IGP01IGC_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 45 #define IGP02IGC_PHY_POWER_MGMT 0x19 /* Power Management */ 46 #define IGP01IGC_PHY_PAGE_SELECT 0x1F /* Page Select */ 47 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 48 #define IGP_PAGE_SHIFT 5 49 #define PHY_REG_MASK 0x1F 50 #define IGC_I225_PHPM 0x0E14 /* I225 PHY Power Management */ 51 #define IGC_I225_PHPM_DIS_1000_D3 0x0008 /* Disable 1G in D3 */ 52 #define IGC_I225_PHPM_LINK_ENERGY 0x0010 /* Link Energy Detect */ 53 #define IGC_I225_PHPM_GO_LINKD 0x0020 /* Go Link Disconnect */ 54 #define IGC_I225_PHPM_DIS_1000 0x0040 /* Disable 1G globally */ 55 #define IGC_I225_PHPM_SPD_B2B_EN 0x0080 /* Smart Power Down Back2Back */ 56 #define IGC_I225_PHPM_RST_COMPL 0x0100 /* PHY Reset Completed */ 57 #define IGC_I225_PHPM_DIS_100_D3 0x0200 /* Disable 100M in D3 */ 58 #define IGC_I225_PHPM_ULP 0x0400 /* Ultra Low-Power Mode */ 59 #define IGC_I225_PHPM_DIS_2500 0x0800 /* Disable 2.5G globally */ 60 #define IGC_I225_PHPM_DIS_2500_D3 0x1000 /* Disable 2.5G in D3 */ 61 /* GPY211 - I225 defines */ 62 #define GPY_MMD_MASK 0xFFFF0000 63 #define GPY_MMD_SHIFT 16 64 #define GPY_REG_MASK 0x0000FFFF 65 #define IGP01IGC_PHY_PCS_INIT_REG 0x00B4 66 #define IGP01IGC_PHY_POLARITY_MASK 0x0078 67 68 #define IGP01IGC_PSCR_AUTO_MDIX 0x1000 69 #define IGP01IGC_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 70 71 #define IGP01IGC_PSCFR_SMART_SPEED 0x0080 72 73 #define IGP02IGC_PM_SPD 0x0001 /* Smart Power Down */ 74 #define IGP02IGC_PM_D0_LPLU 0x0002 /* For D0a states */ 75 #define IGP02IGC_PM_D3_LPLU 0x0004 /* For all other states */ 76 77 #define IGP01IGC_PLHR_SS_DOWNGRADE 0x8000 78 79 #define IGP01IGC_PSSR_POLARITY_REVERSED 0x0002 80 #define IGP01IGC_PSSR_MDIX 0x0800 81 #define IGP01IGC_PSSR_SPEED_MASK 0xC000 82 #define IGP01IGC_PSSR_SPEED_1000MBPS 0xC000 83 84 #define IGP02IGC_PHY_CHANNEL_NUM 4 85 #define IGP02IGC_PHY_AGC_A 0x11B1 86 #define IGP02IGC_PHY_AGC_B 0x12B1 87 #define IGP02IGC_PHY_AGC_C 0x14B1 88 #define IGP02IGC_PHY_AGC_D 0x18B1 89 90 #define IGP02IGC_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ 91 #define IGP02IGC_AGC_LENGTH_MASK 0x7F 92 #define IGP02IGC_AGC_RANGE 15 93 94 #define IGC_CABLE_LENGTH_UNDEFINED 0xFF 95 96 #define IGC_KMRNCTRLSTA_OFFSET 0x001F0000 97 #define IGC_KMRNCTRLSTA_OFFSET_SHIFT 16 98 #define IGC_KMRNCTRLSTA_REN 0x00200000 99 #define IGC_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 100 #define IGC_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 101 #define IGC_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 102 #define IGC_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 103 #define IGC_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 104 105 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 106 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ 107 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ 108 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 109 110 /* IFE PHY Extended Status Control */ 111 #define IFE_PESC_POLARITY_REVERSED 0x0100 112 113 /* IFE PHY Special Control */ 114 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 115 #define IFE_PSC_FORCE_POLARITY 0x0020 116 117 /* IFE PHY Special Control and LED Control */ 118 #define IFE_PSCL_PROBE_MODE 0x0020 119 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 120 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 121 122 /* IFE PHY MDIX Control */ 123 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 124 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 125 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ 126 127 #endif /* _IGC_PHY_H_ */ 128
Indexes created Wed Sep 24 14:09:57 GMT 2025