igma.c revision 1.2.4.3
1 1.2.4.2 tls /* $NetBSD: igma.c,v 1.2.4.3 2017/12/03 11:37:08 jdolecek Exp $ */ 2 1.2.4.2 tls 3 1.2.4.2 tls /* 4 1.2.4.2 tls * Copyright (c) 2014 Michael van Elst 5 1.2.4.2 tls * 6 1.2.4.2 tls * Permission to use, copy, modify, and distribute this software for any 7 1.2.4.2 tls * purpose with or without fee is hereby granted, provided that the above 8 1.2.4.2 tls * copyright notice and this permission notice appear in all copies. 9 1.2.4.2 tls * 10 1.2.4.2 tls * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 1.2.4.2 tls * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 1.2.4.2 tls * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 1.2.4.2 tls * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 1.2.4.2 tls * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 1.2.4.2 tls * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 1.2.4.2 tls * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 1.2.4.2 tls */ 18 1.2.4.2 tls 19 1.2.4.2 tls /* 20 1.2.4.2 tls * Intel Graphic Media Accelerator 21 1.2.4.2 tls */ 22 1.2.4.2 tls 23 1.2.4.2 tls #include <sys/cdefs.h> 24 1.2.4.2 tls __KERNEL_RCSID(0, "$NetBSD: igma.c,v 1.2.4.3 2017/12/03 11:37:08 jdolecek Exp $"); 25 1.2.4.2 tls 26 1.2.4.2 tls #include "vga.h" 27 1.2.4.2 tls 28 1.2.4.2 tls #include <sys/param.h> 29 1.2.4.2 tls #include <sys/systm.h> 30 1.2.4.2 tls #include <sys/device.h> 31 1.2.4.2 tls #include <sys/bus.h> 32 1.2.4.2 tls 33 1.2.4.2 tls #include <dev/pci/pcireg.h> 34 1.2.4.2 tls #include <dev/pci/pcivar.h> 35 1.2.4.2 tls #include <dev/pci/pcidevs.h> 36 1.2.4.2 tls #include <dev/pci/pciio.h> 37 1.2.4.2 tls 38 1.2.4.2 tls #include <dev/i2c/i2cvar.h> 39 1.2.4.2 tls #include <dev/i2c/i2c_bitbang.h> 40 1.2.4.2 tls #include <dev/i2c/ddcvar.h> 41 1.2.4.2 tls 42 1.2.4.2 tls #include <dev/videomode/videomode.h> 43 1.2.4.2 tls #include <dev/videomode/edidvar.h> 44 1.2.4.2 tls 45 1.2.4.2 tls #include <dev/wscons/wsdisplayvar.h> 46 1.2.4.2 tls 47 1.2.4.2 tls #if NVGA > 0 48 1.2.4.2 tls #include <dev/ic/mc6845reg.h> 49 1.2.4.2 tls #include <dev/ic/pcdisplayvar.h> 50 1.2.4.2 tls #include <dev/ic/vgareg.h> 51 1.2.4.2 tls #include <dev/ic/vgavar.h> 52 1.2.4.2 tls #endif 53 1.2.4.2 tls 54 1.2.4.2 tls #include <dev/pci/igmareg.h> 55 1.2.4.2 tls #include <dev/pci/igmavar.h> 56 1.2.4.2 tls 57 1.2.4.2 tls #include "igmafb.h" 58 1.2.4.2 tls 59 1.2.4.2 tls struct igma_softc; 60 1.2.4.2 tls struct igma_i2c { 61 1.2.4.2 tls kmutex_t ii_lock; 62 1.2.4.2 tls struct igma_softc *ii_sc; 63 1.2.4.2 tls bus_addr_t ii_reg; 64 1.2.4.2 tls struct i2c_controller ii_i2c; 65 1.2.4.2 tls const char *ii_name; 66 1.2.4.2 tls u_int32_t ii_dir; 67 1.2.4.2 tls }; 68 1.2.4.2 tls 69 1.2.4.2 tls struct igma_softc { 70 1.2.4.2 tls device_t sc_dev; 71 1.2.4.2 tls struct igma_chip sc_chip; 72 1.2.4.2 tls struct igma_i2c sc_ii[GMBUS_NUM_PORTS]; 73 1.2.4.2 tls }; 74 1.2.4.2 tls 75 1.2.4.2 tls static int igma_match(device_t, cfdata_t, void *); 76 1.2.4.2 tls static void igma_attach(device_t, device_t, void *); 77 1.2.4.2 tls static int igma_print(void *, const char *); 78 1.2.4.2 tls 79 1.2.4.2 tls static void igma_i2c_attach(struct igma_softc *); 80 1.2.4.2 tls 81 1.2.4.2 tls CFATTACH_DECL_NEW(igma, sizeof(struct igma_softc), 82 1.2.4.2 tls igma_match, igma_attach, NULL, NULL); 83 1.2.4.2 tls 84 1.2.4.2 tls static int igma_i2c_acquire_bus(void *, int); 85 1.2.4.2 tls static void igma_i2c_release_bus(void *, int); 86 1.2.4.2 tls static int igma_i2c_send_start(void *, int); 87 1.2.4.2 tls static int igma_i2c_send_stop(void *, int); 88 1.2.4.2 tls static int igma_i2c_initiate_xfer(void *, i2c_addr_t, int); 89 1.2.4.2 tls static int igma_i2c_read_byte(void *, uint8_t *, int); 90 1.2.4.2 tls static int igma_i2c_write_byte(void *, uint8_t, int); 91 1.2.4.2 tls static void igma_i2cbb_set_bits(void *, uint32_t); 92 1.2.4.2 tls static void igma_i2cbb_set_dir(void *, uint32_t); 93 1.2.4.2 tls static uint32_t igma_i2cbb_read(void *); 94 1.2.4.2 tls 95 1.2.4.2 tls static void igma_reg_barrier(const struct igma_chip *, int); 96 1.2.4.2 tls static u_int32_t igma_reg_read(const struct igma_chip *, int); 97 1.2.4.2 tls static void igma_reg_write(const struct igma_chip *, int, u_int32_t); 98 1.2.4.2 tls static u_int8_t igma_vga_read(const struct igma_chip *, int); 99 1.2.4.2 tls static void igma_vga_write(const struct igma_chip *, int , u_int8_t); 100 1.2.4.2 tls #if 0 101 1.2.4.2 tls static u_int8_t igma_crtc_read(const struct igma_chip *, int); 102 1.2.4.2 tls static void igma_crtc_write(const struct igma_chip *, int, u_int8_t); 103 1.2.4.2 tls #endif 104 1.2.4.2 tls 105 1.2.4.2 tls static const struct i2c_bitbang_ops igma_i2cbb_ops = { 106 1.2.4.2 tls igma_i2cbb_set_bits, 107 1.2.4.2 tls igma_i2cbb_set_dir, 108 1.2.4.2 tls igma_i2cbb_read, 109 1.2.4.2 tls { 1, 2, 0, 1 } 110 1.2.4.2 tls }; 111 1.2.4.2 tls 112 1.2.4.2 tls static const struct igma_chip_ops igma_bus_ops = { 113 1.2.4.2 tls igma_reg_barrier, 114 1.2.4.2 tls igma_reg_read, 115 1.2.4.2 tls igma_reg_write, 116 1.2.4.2 tls igma_vga_read, 117 1.2.4.2 tls igma_vga_write, 118 1.2.4.2 tls #if 0 119 1.2.4.2 tls igma_crtc_read, 120 1.2.4.2 tls igma_crtc_write, 121 1.2.4.2 tls #endif 122 1.2.4.2 tls }; 123 1.2.4.2 tls 124 1.2.4.2 tls static struct igma_product { 125 1.2.4.2 tls u_int16_t product; 126 1.2.4.2 tls int gentype; 127 1.2.4.2 tls int num_pipes; 128 1.2.4.2 tls } const igma_products[] = { 129 1.2.4.2 tls /* i830 */ 130 1.2.4.2 tls { PCI_PRODUCT_INTEL_82830MP_IV, 200,2 }, 131 1.2.4.2 tls /* i845g */ 132 1.2.4.2 tls { PCI_PRODUCT_INTEL_82845G_IGD, 200,2 }, 133 1.2.4.2 tls /* i85x */ 134 1.2.4.2 tls { PCI_PRODUCT_INTEL_82855GM_IGD, 200,2 }, 135 1.2.4.2 tls // 0x358e ? 136 1.2.4.2 tls /* i865g */ 137 1.2.4.2 tls { PCI_PRODUCT_INTEL_82865_IGD, 200,2 }, 138 1.2.4.2 tls /* i915g */ 139 1.2.4.2 tls { PCI_PRODUCT_INTEL_82915G_IGD, 200,2 }, 140 1.2.4.2 tls { PCI_PRODUCT_INTEL_E7221_IGD, 200,2 }, 141 1.2.4.2 tls /* i915gm */ 142 1.2.4.2 tls { PCI_PRODUCT_INTEL_82915GM_IGD, 300,2 }, 143 1.2.4.2 tls /* i945g */ 144 1.2.4.2 tls { PCI_PRODUCT_INTEL_82945P_IGD, 300,2 }, 145 1.2.4.2 tls /* i945gm */ 146 1.2.4.2 tls { PCI_PRODUCT_INTEL_82945GM_IGD, 300,2 }, 147 1.2.4.2 tls { PCI_PRODUCT_INTEL_82945GM_IGD_1, 300,2 }, 148 1.2.4.2 tls { PCI_PRODUCT_INTEL_82945GME_IGD, 300,2 }, 149 1.2.4.2 tls /* i965g */ 150 1.2.4.2 tls { PCI_PRODUCT_INTEL_82946GZ_IGD, 300,2 }, 151 1.2.4.2 tls { PCI_PRODUCT_INTEL_82G35_IGD, 300,2 }, 152 1.2.4.2 tls { PCI_PRODUCT_INTEL_82G35_IGD_1, 300,2 }, 153 1.2.4.2 tls { PCI_PRODUCT_INTEL_82965Q_IGD, 300,2 }, 154 1.2.4.2 tls { PCI_PRODUCT_INTEL_82965Q_IGD_1, 300,2 }, 155 1.2.4.2 tls { PCI_PRODUCT_INTEL_82965G_IGD, 300,2 }, 156 1.2.4.2 tls { PCI_PRODUCT_INTEL_82965G_IGD_1, 300,2 }, 157 1.2.4.2 tls /* g33 */ 158 1.2.4.2 tls { PCI_PRODUCT_INTEL_82G33_IGD, 300,2 }, 159 1.2.4.2 tls { PCI_PRODUCT_INTEL_82G33_IGD_1, 300,2 }, 160 1.2.4.2 tls { PCI_PRODUCT_INTEL_82Q33_IGD, 300,2 }, 161 1.2.4.2 tls { PCI_PRODUCT_INTEL_82Q33_IGD_1, 300,2 }, 162 1.2.4.2 tls { PCI_PRODUCT_INTEL_82Q35_IGD, 300,2 }, 163 1.2.4.2 tls { PCI_PRODUCT_INTEL_82Q35_IGD_1, 300,2 }, 164 1.2.4.2 tls /* pineview */ 165 1.2.4.2 tls { PCI_PRODUCT_INTEL_PINEVIEW_IGD, 350,2 }, 166 1.2.4.2 tls { PCI_PRODUCT_INTEL_PINEVIEW_M_IGD, 350,2 }, 167 1.2.4.2 tls /* i965gm */ 168 1.2.4.2 tls { PCI_PRODUCT_INTEL_82965PM_IGD, 400,2 }, 169 1.2.4.2 tls { PCI_PRODUCT_INTEL_82965PM_IGD_1, 400,2 }, 170 1.2.4.2 tls { PCI_PRODUCT_INTEL_82965GME_IGD, 400,2 }, 171 1.2.4.2 tls /* gm45 */ 172 1.2.4.2 tls { PCI_PRODUCT_INTEL_82GM45_IGD, 450,2 }, 173 1.2.4.2 tls { PCI_PRODUCT_INTEL_82GM45_IGD_1, 450,2 }, 174 1.2.4.2 tls /* g45 */ 175 1.2.4.2 tls { PCI_PRODUCT_INTEL_82IGD_E_IGD, 450,2 }, 176 1.2.4.2 tls { PCI_PRODUCT_INTEL_82Q45_IGD, 450,2 }, 177 1.2.4.2 tls { PCI_PRODUCT_INTEL_82G45_IGD, 450,2 }, 178 1.2.4.2 tls { PCI_PRODUCT_INTEL_82G41_IGD, 450,2 }, 179 1.2.4.2 tls { PCI_PRODUCT_INTEL_82B43_IGD, 450,2 }, 180 1.2.4.2 tls // 0x2e92 ? 181 1.2.4.2 tls /* ironlake d */ 182 1.2.4.2 tls { PCI_PRODUCT_INTEL_IRONLAKE_D_IGD, 500,2 }, 183 1.2.4.2 tls /* ironlake m */ 184 1.2.4.2 tls { PCI_PRODUCT_INTEL_IRONLAKE_M_IGD, 500,2 }, 185 1.2.4.2 tls /* sandy bridge */ 186 1.2.4.2 tls { PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD, 600,2 }, 187 1.2.4.2 tls { PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD_1, 600,2 }, 188 1.2.4.2 tls { PCI_PRODUCT_INTEL_SANDYBRIDGE_IGD_2, 600,2 }, 189 1.2.4.2 tls /* sandy bridge m */ 190 1.2.4.2 tls { PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD, 600,2 }, 191 1.2.4.2 tls { PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD_1, 600,2 }, 192 1.2.4.2 tls { PCI_PRODUCT_INTEL_SANDYBRIDGE_M_IGD_2, 600,2 }, 193 1.2.4.2 tls /* sandy bridge s */ 194 1.2.4.2 tls { PCI_PRODUCT_INTEL_SANDYBRIDGE_S_IGD, 600,2 }, 195 1.2.4.2 tls /* ivy bridge */ 196 1.2.4.2 tls { PCI_PRODUCT_INTEL_IVYBRIDGE_IGD, 700,3 }, 197 1.2.4.2 tls { PCI_PRODUCT_INTEL_IVYBRIDGE_IGD_1, 700,3 }, 198 1.2.4.2 tls /* ivy bridge m */ 199 1.2.4.2 tls { PCI_PRODUCT_INTEL_IVYBRIDGE_M_IGD, 700,3 }, 200 1.2.4.2 tls { PCI_PRODUCT_INTEL_IVYBRIDGE_M_IGD_1, 700,3 }, 201 1.2.4.2 tls /* ivy bridge s */ 202 1.2.4.2 tls { PCI_PRODUCT_INTEL_IVYBRIDGE_S_IGD, 700,3 }, 203 1.2.4.2 tls { PCI_PRODUCT_INTEL_IVYBRIDGE_S_IGD_1, 700,3 }, 204 1.2.4.2 tls #if 0 205 1.2.4.2 tls /* valleyview d */ 206 1.2.4.2 tls /* valleyview m */ 207 1.2.4.2 tls { PCI_PRODUCT_INTEL_HASWELL_IGD_1, 800,3 }, 208 1.2.4.2 tls /* haswell d */ 209 1.2.4.2 tls { PCI_PRODUCT_INTEL_HASWELL_IGD, 800,3 }, 210 1.2.4.2 tls { PCI_PRODUCT_INTEL_HASWELL_IGD_1, 800,3 }, 211 1.2.4.2 tls /* haswell m */ 212 1.2.4.2 tls /* broadwell d */ 213 1.2.4.2 tls /* broadwell m */ 214 1.2.4.2 tls #endif 215 1.2.4.2 tls }; 216 1.2.4.2 tls 217 1.2.4.2 tls static int 218 1.2.4.2 tls igma_newpch_match(const struct pci_attach_args *pa) 219 1.2.4.2 tls { 220 1.2.4.2 tls if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 221 1.2.4.2 tls return 0; 222 1.2.4.2 tls switch (0xff00 & PCI_PRODUCT(pa->pa_id)) { 223 1.2.4.2 tls case 0x3b00: /* ibex peak */ 224 1.2.4.2 tls case 0x1c00: /* cougar point */ 225 1.2.4.2 tls case 0x1e00: /* panther point */ 226 1.2.4.2 tls case 0x8c00: /* lynx point */ 227 1.2.4.2 tls case 0x9c00: /* lynx point lp */ 228 1.2.4.2 tls return 1; 229 1.2.4.2 tls } 230 1.2.4.2 tls 231 1.2.4.2 tls return 0; 232 1.2.4.2 tls } 233 1.2.4.2 tls 234 1.2.4.2 tls static const struct igma_product * 235 1.2.4.2 tls igma_lookup(const struct pci_attach_args *pa) 236 1.2.4.2 tls { 237 1.2.4.2 tls const struct igma_product *ip; 238 1.2.4.2 tls int i; 239 1.2.4.2 tls 240 1.2.4.2 tls if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 241 1.2.4.2 tls return NULL; 242 1.2.4.2 tls for (i=0; i < __arraycount(igma_products); ++i) { 243 1.2.4.2 tls ip = &igma_products[i]; 244 1.2.4.2 tls if (PCI_PRODUCT(pa->pa_id) == ip->product) 245 1.2.4.2 tls return ip; 246 1.2.4.2 tls } 247 1.2.4.2 tls return NULL; 248 1.2.4.2 tls } 249 1.2.4.2 tls 250 1.2.4.2 tls static void 251 1.2.4.2 tls igma_product_to_chip(const struct pci_attach_args *pa, struct igma_chip *cd) 252 1.2.4.2 tls { 253 1.2.4.2 tls const struct igma_product *ip; 254 1.2.4.2 tls struct pci_attach_args PA; 255 1.2.4.2 tls 256 1.2.4.2 tls ip = igma_lookup(pa); 257 1.2.4.2 tls KASSERT(ip != NULL); 258 1.2.4.2 tls 259 1.2.4.2 tls cd->ops = &igma_bus_ops; 260 1.2.4.2 tls cd->num_gmbus = 6; 261 1.2.4.2 tls cd->num_pipes = ip->num_pipes; 262 1.2.4.2 tls cd->quirks = 0; 263 1.2.4.2 tls cd->backlight_factor = 1; 264 1.2.4.2 tls 265 1.2.4.2 tls cd->gpio_offset = OLD_GPIOA; 266 1.2.4.2 tls cd->vga_cntrl = PCH_VGA_CNTRL; 267 1.2.4.2 tls cd->backlight_cntrl = OLD_BLC_PWM_CTL; 268 1.2.4.2 tls cd->backlight_cntrl2 = OLD_BLC_PWM_CTL2; 269 1.2.4.2 tls 270 1.2.4.2 tls PA = *pa; 271 1.2.4.2 tls if (pci_find_device(&PA, igma_newpch_match)) { 272 1.2.4.2 tls cd->gpio_offset = PCH_GPIOA; 273 1.2.4.2 tls cd->vga_cntrl = CPU_VGA_CNTRL; 274 1.2.4.2 tls cd->backlight_cntrl = CPU_BLC_PWM_CTL; 275 1.2.4.2 tls cd->backlight_cntrl2 = CPU_BLC_PWM_CTL2; 276 1.2.4.2 tls } 277 1.2.4.2 tls 278 1.2.4.2 tls switch (ip->gentype) { 279 1.2.4.2 tls case 200: 280 1.2.4.2 tls cd->backlight_factor = 2; 281 1.2.4.2 tls break; 282 1.2.4.2 tls case 300: 283 1.2.4.2 tls case 350: 284 1.2.4.2 tls cd->backlight_factor = 2; 285 1.2.4.2 tls cd->quirks |= IGMA_PFITDISABLE_QUIRK; 286 1.2.4.2 tls break; 287 1.2.4.2 tls case 450: 288 1.2.4.2 tls cd->pri_cntrl = PRI_CTRL_NOTRICKLE; 289 1.2.4.2 tls cd->quirks |= IGMA_PLANESTART_QUIRK; 290 1.2.4.2 tls break; 291 1.2.4.2 tls default: 292 1.2.4.2 tls cd->pri_cntrl = 0; 293 1.2.4.2 tls break; 294 1.2.4.2 tls } 295 1.2.4.2 tls } 296 1.2.4.2 tls 297 1.2.4.2 tls static void 298 1.2.4.2 tls igma_adjust_chip(struct igma_softc *sc, struct igma_chip *cd) 299 1.2.4.2 tls { 300 1.2.4.2 tls const struct igma_chip_ops *co = cd->ops; 301 1.2.4.2 tls u_int32_t reg; 302 1.2.4.2 tls 303 1.2.4.2 tls reg = co->read_reg(cd, cd->vga_cntrl); 304 1.2.4.2 tls if (reg & VGA_PIPE_B_SELECT) 305 1.2.4.2 tls cd->use_pipe = 1; 306 1.2.4.2 tls } 307 1.2.4.2 tls 308 1.2.4.2 tls static int 309 1.2.4.2 tls igma_print(void *aux, const char *pnp) 310 1.2.4.2 tls { 311 1.2.4.2 tls if (pnp) 312 1.2.4.2 tls aprint_normal("drm at %s", pnp); 313 1.2.4.2 tls return (UNCONF); 314 1.2.4.2 tls } 315 1.2.4.2 tls 316 1.2.4.2 tls static int 317 1.2.4.2 tls igma_match(device_t parent, cfdata_t match, void *aux) 318 1.2.4.2 tls { 319 1.2.4.2 tls struct pci_attach_args *pa = (struct pci_attach_args *)aux; 320 1.2.4.2 tls const struct igma_product *ip; 321 1.2.4.2 tls 322 1.2.4.2 tls if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY) 323 1.2.4.2 tls return 0; 324 1.2.4.2 tls 325 1.2.4.2 tls ip = igma_lookup(pa); 326 1.2.4.2 tls if (ip != NULL) 327 1.2.4.2 tls return 100; 328 1.2.4.2 tls 329 1.2.4.2 tls return 0; 330 1.2.4.2 tls } 331 1.2.4.2 tls 332 1.2.4.2 tls static void 333 1.2.4.2 tls igma_attach(device_t parent, device_t self, void *aux) 334 1.2.4.2 tls { 335 1.2.4.2 tls struct igma_softc *sc = device_private(self); 336 1.2.4.2 tls const struct pci_attach_args *pa = (struct pci_attach_args *)aux; 337 1.2.4.2 tls struct igma_attach_args iaa; 338 1.2.4.2 tls bus_space_tag_t gttmmt, gmt, regt; 339 1.2.4.2 tls bus_space_handle_t gttmmh, gmh, regh; 340 1.2.4.2 tls bus_addr_t gttmmb, gmb; 341 1.2.4.2 tls 342 1.2.4.2 tls pci_aprint_devinfo(pa, NULL); 343 1.2.4.2 tls 344 1.2.4.2 tls sc->sc_dev = self; 345 1.2.4.2 tls 346 1.2.4.2 tls /* Initialize according to chip type */ 347 1.2.4.2 tls igma_product_to_chip(pa, &sc->sc_chip); 348 1.2.4.2 tls 349 1.2.4.2 tls if (pci_mapreg_map(pa, PCI_BAR0, PCI_MAPREG_TYPE_MEM, 350 1.2.4.2 tls BUS_SPACE_MAP_LINEAR, 351 1.2.4.2 tls >tmmt, >tmmh, >tmmb, NULL)) { 352 1.2.4.2 tls aprint_error_dev(sc->sc_dev, "unable to map GTTMM\n"); 353 1.2.4.2 tls return; 354 1.2.4.2 tls } 355 1.2.4.2 tls sc->sc_chip.mmiot = gttmmt; 356 1.2.4.2 tls if (bus_space_subregion(gttmmt, gttmmh, 0, 2*1024*1024, 357 1.2.4.2 tls &sc->sc_chip.mmioh)) { 358 1.2.4.2 tls aprint_error_dev(sc->sc_dev, "unable to submap MMIO\n"); 359 1.2.4.2 tls return; 360 1.2.4.2 tls } 361 1.2.4.2 tls sc->sc_chip.gttt = gttmmt; 362 1.2.4.2 tls if (bus_space_subregion(gttmmt, gttmmh, 2*1024*1024, 2*1024*1024, 363 1.2.4.2 tls &sc->sc_chip.gtth)) { 364 1.2.4.2 tls aprint_error_dev(sc->sc_dev, "unable to submap GTT\n"); 365 1.2.4.2 tls return; 366 1.2.4.2 tls } 367 1.2.4.2 tls 368 1.2.4.2 tls if (pci_mapreg_map(pa, PCI_BAR2, PCI_MAPREG_TYPE_MEM, 369 1.2.4.2 tls BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE, 370 1.2.4.2 tls &gmt, &gmh, &gmb, NULL)) { 371 1.2.4.2 tls aprint_error_dev(sc->sc_dev, "unable to map aperture\n"); 372 1.2.4.2 tls return; 373 1.2.4.2 tls } 374 1.2.4.2 tls sc->sc_chip.gmt = gmt; 375 1.2.4.2 tls sc->sc_chip.gmh = gmh; 376 1.2.4.2 tls sc->sc_chip.gmb = gmb; 377 1.2.4.2 tls 378 1.2.4.2 tls if (pci_mapreg_map(pa, PCI_BAR4, PCI_MAPREG_TYPE_IO, 0, 379 1.2.4.2 tls ®t, ®h, NULL, NULL)) { 380 1.2.4.2 tls aprint_error_dev(sc->sc_dev, "unable to map IO registers\n"); 381 1.2.4.2 tls return; 382 1.2.4.2 tls } 383 1.2.4.2 tls 384 1.2.4.2 tls #if NVGA > 0 385 1.2.4.2 tls iaa.iaa_console = vga_cndetach() ? true : false; 386 1.2.4.2 tls #else 387 1.2.4.2 tls iaa.iaa_console = 0; 388 1.2.4.2 tls #endif 389 1.2.4.2 tls sc->sc_chip.vgat = regt; 390 1.2.4.2 tls if (bus_space_map(regt, 0x3c0, 0x10, 0, &sc->sc_chip.vgah)) { 391 1.2.4.2 tls aprint_error_dev(sc->sc_dev, "unable to map VGA registers\n"); 392 1.2.4.2 tls return; 393 1.2.4.2 tls } 394 1.2.4.2 tls 395 1.2.4.2 tls /* Check hardware for more information */ 396 1.2.4.2 tls igma_adjust_chip(sc, &sc->sc_chip); 397 1.2.4.2 tls 398 1.2.4.2 tls aprint_normal("%s: VGA_CNTRL: 0x%x\n",device_xname(sc->sc_dev), 399 1.2.4.2 tls sc->sc_chip.vga_cntrl); 400 1.2.4.2 tls aprint_normal("%s: GPIO_OFFSET: 0x%x\n",device_xname(sc->sc_dev), 401 1.2.4.2 tls sc->sc_chip.gpio_offset); 402 1.2.4.2 tls aprint_normal("%s: BACKLIGHT_CTRL: 0x%x\n",device_xname(sc->sc_dev), 403 1.2.4.2 tls sc->sc_chip.backlight_cntrl); 404 1.2.4.2 tls aprint_normal("%s: BACKLIGHT_CTRL2: 0x%x\n",device_xname(sc->sc_dev), 405 1.2.4.2 tls sc->sc_chip.backlight_cntrl2); 406 1.2.4.2 tls 407 1.2.4.2 tls #if NIGMAFB > 0 408 1.2.4.2 tls strcpy(iaa.iaa_name, "igmafb"); 409 1.2.4.2 tls iaa.iaa_chip = sc->sc_chip; 410 1.2.4.2 tls config_found_ia(sc->sc_dev, "igmabus", &iaa, igma_print); 411 1.2.4.2 tls #endif 412 1.2.4.2 tls 413 1.2.4.2 tls igma_i2c_attach(sc); 414 1.2.4.2 tls } 415 1.2.4.2 tls 416 1.2.4.2 tls static void 417 1.2.4.2 tls igma_i2c_attach(struct igma_softc *sc) 418 1.2.4.2 tls { 419 1.2.4.2 tls struct igma_i2c *ii; 420 1.2.4.2 tls int i; 421 1.2.4.2 tls #if 0 422 1.2.4.2 tls struct i2cbus_attach_args iba; 423 1.2.4.2 tls #endif 424 1.2.4.2 tls 425 1.2.4.2 tls for (i=0; i<sc->sc_chip.num_gmbus; ++i) { 426 1.2.4.2 tls ii = &sc->sc_ii[i]; 427 1.2.4.2 tls ii->ii_sc = sc; 428 1.2.4.2 tls 429 1.2.4.2 tls /* XXX */ 430 1.2.4.2 tls ii->ii_reg = sc->sc_chip.gpio_offset - PCH_GPIOA; 431 1.2.4.2 tls switch (i) { 432 1.2.4.2 tls case 0: 433 1.2.4.2 tls ii->ii_reg += PCH_GPIOB; 434 1.2.4.2 tls ii->ii_name = "ssc"; 435 1.2.4.2 tls break; 436 1.2.4.2 tls case 1: 437 1.2.4.2 tls ii->ii_reg += PCH_GPIOA; 438 1.2.4.2 tls ii->ii_name = "vga"; 439 1.2.4.2 tls break; 440 1.2.4.2 tls case 2: 441 1.2.4.2 tls ii->ii_reg += PCH_GPIOC; 442 1.2.4.2 tls ii->ii_name = "panel"; 443 1.2.4.2 tls break; 444 1.2.4.2 tls case 3: 445 1.2.4.2 tls ii->ii_reg += PCH_GPIOD; 446 1.2.4.2 tls ii->ii_name = "dpc"; 447 1.2.4.2 tls break; 448 1.2.4.2 tls case 4: 449 1.2.4.2 tls ii->ii_reg += PCH_GPIOE; 450 1.2.4.2 tls ii->ii_name = "dpb"; 451 1.2.4.2 tls break; 452 1.2.4.2 tls case 5: 453 1.2.4.2 tls ii->ii_reg += PCH_GPIOF; 454 1.2.4.2 tls ii->ii_name = "dpd"; 455 1.2.4.2 tls break; 456 1.2.4.2 tls default: 457 1.2.4.2 tls panic("don't know GMBUS %d\n",i); 458 1.2.4.2 tls } 459 1.2.4.2 tls 460 1.2.4.2 tls mutex_init(&ii->ii_lock, MUTEX_DEFAULT, IPL_NONE); 461 1.2.4.2 tls 462 1.2.4.2 tls ii->ii_i2c.ic_cookie = ii; 463 1.2.4.2 tls ii->ii_i2c.ic_acquire_bus = igma_i2c_acquire_bus; 464 1.2.4.2 tls ii->ii_i2c.ic_release_bus = igma_i2c_release_bus; 465 1.2.4.2 tls ii->ii_i2c.ic_send_start = igma_i2c_send_start; 466 1.2.4.2 tls ii->ii_i2c.ic_send_stop = igma_i2c_send_stop; 467 1.2.4.2 tls ii->ii_i2c.ic_initiate_xfer = igma_i2c_initiate_xfer; 468 1.2.4.2 tls ii->ii_i2c.ic_read_byte = igma_i2c_read_byte; 469 1.2.4.2 tls ii->ii_i2c.ic_write_byte = igma_i2c_write_byte; 470 1.2.4.2 tls ii->ii_i2c.ic_exec = NULL; 471 1.2.4.2 tls 472 1.2.4.2 tls #if 0 473 1.2.4.3 jdolecek memset(&iba, 0, sizeof(iba)); 474 1.2.4.2 tls iba.iba_type = I2C_TYPE_SMBUS; 475 1.2.4.2 tls iba.iba_tag = &ii->ii_i2c; 476 1.2.4.2 tls config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print); 477 1.2.4.2 tls #endif 478 1.2.4.2 tls } 479 1.2.4.2 tls } 480 1.2.4.2 tls 481 1.2.4.2 tls /* 482 1.2.4.2 tls * I2C interface 483 1.2.4.2 tls */ 484 1.2.4.2 tls 485 1.2.4.2 tls static int 486 1.2.4.2 tls igma_i2c_acquire_bus(void *cookie, int flags) 487 1.2.4.2 tls { 488 1.2.4.2 tls struct igma_i2c *ii = cookie; 489 1.2.4.2 tls mutex_enter(&ii->ii_lock); 490 1.2.4.2 tls return 0; 491 1.2.4.2 tls } 492 1.2.4.2 tls 493 1.2.4.2 tls static void 494 1.2.4.2 tls igma_i2c_release_bus(void *cookie, int flags) 495 1.2.4.2 tls { 496 1.2.4.2 tls struct igma_i2c *ii = cookie; 497 1.2.4.2 tls mutex_exit(&ii->ii_lock); 498 1.2.4.2 tls } 499 1.2.4.2 tls 500 1.2.4.2 tls static int 501 1.2.4.2 tls igma_i2c_send_start(void *cookie, int flags) 502 1.2.4.2 tls { 503 1.2.4.2 tls return i2c_bitbang_send_start(cookie, flags, &igma_i2cbb_ops); 504 1.2.4.2 tls } 505 1.2.4.2 tls 506 1.2.4.2 tls static int 507 1.2.4.2 tls igma_i2c_send_stop(void *cookie, int flags) 508 1.2.4.2 tls { 509 1.2.4.2 tls return i2c_bitbang_send_stop(cookie, flags, &igma_i2cbb_ops); 510 1.2.4.2 tls } 511 1.2.4.2 tls 512 1.2.4.2 tls static int 513 1.2.4.2 tls igma_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 514 1.2.4.2 tls { 515 1.2.4.2 tls return i2c_bitbang_initiate_xfer(cookie, addr, flags, &igma_i2cbb_ops); 516 1.2.4.2 tls } 517 1.2.4.2 tls 518 1.2.4.2 tls static int 519 1.2.4.2 tls igma_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 520 1.2.4.2 tls { 521 1.2.4.2 tls return i2c_bitbang_read_byte(cookie, valp, flags, &igma_i2cbb_ops); 522 1.2.4.2 tls } 523 1.2.4.2 tls 524 1.2.4.2 tls static int 525 1.2.4.2 tls igma_i2c_write_byte(void *cookie, uint8_t val, int flags) 526 1.2.4.2 tls { 527 1.2.4.2 tls return i2c_bitbang_write_byte(cookie, val, flags, &igma_i2cbb_ops); 528 1.2.4.2 tls } 529 1.2.4.2 tls 530 1.2.4.2 tls static void 531 1.2.4.2 tls igma_i2cbb_set_bits(void *cookie, uint32_t bits) 532 1.2.4.2 tls { 533 1.2.4.2 tls struct igma_i2c *ii = cookie; 534 1.2.4.2 tls struct igma_softc *sc = ii->ii_sc; 535 1.2.4.2 tls const struct igma_chip *cd = &sc->sc_chip; 536 1.2.4.2 tls const struct igma_chip_ops *co = cd->ops; 537 1.2.4.2 tls uint32_t reg; 538 1.2.4.2 tls 539 1.2.4.2 tls reg = co->read_reg(cd, ii->ii_reg); 540 1.2.4.2 tls reg &= GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE; 541 1.2.4.2 tls 542 1.2.4.2 tls if ((bits | ii->ii_dir) & 1) 543 1.2.4.2 tls /* make data input, signal is pulled high */ 544 1.2.4.2 tls reg |= GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 545 1.2.4.2 tls else 546 1.2.4.2 tls /* make data output, signal is driven low */ 547 1.2.4.2 tls reg |= GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK 548 1.2.4.2 tls | GPIO_DATA_VAL_MASK; 549 1.2.4.2 tls 550 1.2.4.2 tls if (bits & 2) 551 1.2.4.2 tls /* make clock input, signal is pulled high */ 552 1.2.4.2 tls reg |= GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 553 1.2.4.2 tls else 554 1.2.4.2 tls /* make clock output, signal is driven low */ 555 1.2.4.2 tls reg |= GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK 556 1.2.4.2 tls | GPIO_CLOCK_VAL_MASK; 557 1.2.4.2 tls 558 1.2.4.2 tls co->write_reg(cd, ii->ii_reg, reg); 559 1.2.4.2 tls #if 1 560 1.2.4.2 tls reg = co->read_reg(cd, ii->ii_reg); 561 1.2.4.2 tls #else 562 1.2.4.2 tls co->barrier(cd, ii->ii_reg); 563 1.2.4.2 tls #endif 564 1.2.4.2 tls } 565 1.2.4.2 tls 566 1.2.4.2 tls static void 567 1.2.4.2 tls igma_i2cbb_set_dir(void *cookie, uint32_t bits) 568 1.2.4.2 tls { 569 1.2.4.2 tls struct igma_i2c *ii = cookie; 570 1.2.4.2 tls 571 1.2.4.2 tls ii->ii_dir = bits; 572 1.2.4.2 tls } 573 1.2.4.2 tls 574 1.2.4.2 tls static uint32_t 575 1.2.4.2 tls igma_i2cbb_read(void *cookie) 576 1.2.4.2 tls { 577 1.2.4.2 tls struct igma_i2c *ii = cookie; 578 1.2.4.2 tls struct igma_softc *sc = ii->ii_sc; 579 1.2.4.2 tls const struct igma_chip *cd = &sc->sc_chip; 580 1.2.4.2 tls const struct igma_chip_ops *co = cd->ops; 581 1.2.4.2 tls uint32_t reg; 582 1.2.4.2 tls int sda, scl; 583 1.2.4.2 tls 584 1.2.4.2 tls reg = co->read_reg(cd, ii->ii_reg); 585 1.2.4.2 tls 586 1.2.4.2 tls sda = reg & GPIO_DATA_VAL_IN; 587 1.2.4.2 tls scl = reg & GPIO_CLOCK_VAL_IN; 588 1.2.4.2 tls 589 1.2.4.2 tls reg = (sda ? 1 : 0) | (scl ? 2 : 0); 590 1.2.4.2 tls return reg; 591 1.2.4.2 tls } 592 1.2.4.2 tls 593 1.2.4.2 tls static void 594 1.2.4.2 tls igma_reg_barrier(const struct igma_chip *cd, int r) 595 1.2.4.2 tls { 596 1.2.4.2 tls bus_space_barrier(cd->mmiot, cd->mmioh, r, sizeof(u_int32_t), 597 1.2.4.2 tls BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 598 1.2.4.2 tls } 599 1.2.4.2 tls 600 1.2.4.2 tls static u_int32_t 601 1.2.4.2 tls igma_reg_read(const struct igma_chip *cd, int r) 602 1.2.4.2 tls { 603 1.2.4.2 tls return bus_space_read_4(cd->mmiot, cd->mmioh, r); 604 1.2.4.2 tls } 605 1.2.4.2 tls 606 1.2.4.2 tls static void 607 1.2.4.2 tls igma_reg_write(const struct igma_chip *cd, int r, u_int32_t v) 608 1.2.4.2 tls { 609 1.2.4.2 tls bus_space_write_4(cd->mmiot, cd->mmioh, r, v); 610 1.2.4.2 tls } 611 1.2.4.2 tls 612 1.2.4.2 tls static u_int8_t 613 1.2.4.2 tls igma_vga_read(const struct igma_chip *cd, int r) 614 1.2.4.2 tls { 615 1.2.4.2 tls bus_space_write_1(cd->vgat, cd->vgah, 0x4, r | 0x20); 616 1.2.4.2 tls return bus_space_read_1(cd->vgat, cd->vgah, 0x5); 617 1.2.4.2 tls } 618 1.2.4.2 tls 619 1.2.4.2 tls static void 620 1.2.4.2 tls igma_vga_write(const struct igma_chip *cd, int r, u_int8_t v) 621 1.2.4.2 tls { 622 1.2.4.2 tls bus_space_write_1(cd->vgat, cd->vgah, 0x4, r | 0x20); 623 1.2.4.2 tls bus_space_write_1(cd->vgat, cd->vgah, 0x5, v); 624 1.2.4.2 tls } 625 1.2.4.2 tls 626 1.2.4.2 tls #if 0 627 1.2.4.2 tls static u_int8_t 628 1.2.4.2 tls igma_crtc_read(const struct igma_chip *cd, int r) 629 1.2.4.2 tls { 630 1.2.4.2 tls bus_space_write_1(cd->crtct, cd->crtch, 0x4, r); 631 1.2.4.2 tls return bus_space_read_1(cd->crtct, cd->crtch, 0x5); 632 1.2.4.2 tls } 633 1.2.4.2 tls 634 1.2.4.2 tls static void 635 1.2.4.2 tls igma_crtc_write(const struct igma_chip *cd, int r, u_int8_t v) 636 1.2.4.2 tls { 637 1.2.4.2 tls bus_space_write_1(cd->crtct, cd->crtch, 0x4, r); 638 1.2.4.2 tls bus_space_write_1(cd->crtct, cd->crtch, 0x5, v); 639 1.2.4.2 tls } 640 1.2.4.2 tls #endif 641
Indexes created Fri Oct 03 02:09:57 GMT 2025