igmafb.c revision 1.1.10.2
1 1.1.10.2 tls /* $NetBSD: igmafb.c,v 1.1.10.2 2014/08/20 00:03:48 tls Exp $ */ 2 1.1.10.2 tls 3 1.1.10.2 tls /* 4 1.1.10.2 tls * Copyright (c) 2012 Michael van Elst 5 1.1.10.2 tls * 6 1.1.10.2 tls * Permission to use, copy, modify, and distribute this software for any 7 1.1.10.2 tls * purpose with or without fee is hereby granted, provided that the above 8 1.1.10.2 tls * copyright notice and this permission notice appear in all copies. 9 1.1.10.2 tls * 10 1.1.10.2 tls * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 1.1.10.2 tls * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 1.1.10.2 tls * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 1.1.10.2 tls * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 1.1.10.2 tls * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 1.1.10.2 tls * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 1.1.10.2 tls * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 1.1.10.2 tls */ 18 1.1.10.2 tls 19 1.1.10.2 tls /* 20 1.1.10.2 tls * Intel Graphic Media Accelerator 21 1.1.10.2 tls */ 22 1.1.10.2 tls 23 1.1.10.2 tls #include <sys/cdefs.h> 24 1.1.10.2 tls __KERNEL_RCSID(0, "$NetBSD: igmafb.c,v 1.1.10.2 2014/08/20 00:03:48 tls Exp $"); 25 1.1.10.2 tls 26 1.1.10.2 tls #include <sys/param.h> 27 1.1.10.2 tls #include <sys/systm.h> 28 1.1.10.2 tls #include <sys/device.h> 29 1.1.10.2 tls #include <sys/bus.h> 30 1.1.10.2 tls #include <sys/kmem.h> 31 1.1.10.2 tls 32 1.1.10.2 tls #include <dev/pci/pcireg.h> 33 1.1.10.2 tls #include <dev/pci/pcivar.h> 34 1.1.10.2 tls #include <dev/pci/pcidevs.h> 35 1.1.10.2 tls #include <dev/pci/pciio.h> 36 1.1.10.2 tls 37 1.1.10.2 tls #include <dev/videomode/videomode.h> 38 1.1.10.2 tls 39 1.1.10.2 tls #include <dev/wscons/wsdisplayvar.h> 40 1.1.10.2 tls #include <dev/wscons/wsconsio.h> 41 1.1.10.2 tls #include <dev/wsfont/wsfont.h> 42 1.1.10.2 tls #include <dev/rasops/rasops.h> 43 1.1.10.2 tls #include <dev/wscons/wsdisplay_vconsvar.h> 44 1.1.10.2 tls #include <dev/pci/wsdisplay_pci.h> 45 1.1.10.2 tls 46 1.1.10.2 tls #include <dev/pci/igmareg.h> 47 1.1.10.2 tls #include <dev/pci/igmavar.h> 48 1.1.10.2 tls 49 1.1.10.2 tls #include "opt_voyagerfb.h" 50 1.1.10.2 tls 51 1.1.10.2 tls struct igmafb_softc { 52 1.1.10.2 tls device_t sc_dev; 53 1.1.10.2 tls 54 1.1.10.2 tls int sc_width; 55 1.1.10.2 tls int sc_height; 56 1.1.10.2 tls int sc_depth; 57 1.1.10.2 tls int sc_stride; 58 1.1.10.2 tls void *sc_fbaddr; 59 1.1.10.2 tls bus_size_t sc_fbsize; 60 1.1.10.2 tls struct vcons_screen sc_console_screen; 61 1.1.10.2 tls struct wsscreen_descr sc_defaultscreen_descr; 62 1.1.10.2 tls const struct wsscreen_descr *sc_screens[1]; 63 1.1.10.2 tls struct wsscreen_list sc_screenlist; 64 1.1.10.2 tls struct vcons_data vd; 65 1.1.10.2 tls 66 1.1.10.2 tls struct igma_chip sc_chip; 67 1.1.10.2 tls void *sc_vga_save; 68 1.1.10.2 tls 69 1.1.10.2 tls int sc_backlight; 70 1.1.10.2 tls int sc_brightness; 71 1.1.10.2 tls int sc_brightness_max; 72 1.1.10.2 tls }; 73 1.1.10.2 tls 74 1.1.10.2 tls static int igmafb_match(device_t, cfdata_t, void *); 75 1.1.10.2 tls static void igmafb_attach(device_t, device_t, void *); 76 1.1.10.2 tls 77 1.1.10.2 tls CFATTACH_DECL_NEW(igmafb, sizeof(struct igmafb_softc), 78 1.1.10.2 tls igmafb_match, igmafb_attach, NULL, NULL); 79 1.1.10.2 tls 80 1.1.10.2 tls static int igmafb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 81 1.1.10.2 tls static paddr_t igmafb_mmap(void *, void *, off_t, int); 82 1.1.10.2 tls static void igmafb_pollc(void *v, int); 83 1.1.10.2 tls 84 1.1.10.2 tls static /*const*/ struct wsdisplay_accessops igmafb_accessops = { 85 1.1.10.2 tls igmafb_ioctl, 86 1.1.10.2 tls igmafb_mmap, 87 1.1.10.2 tls NULL, /* alloc_screen */ 88 1.1.10.2 tls NULL, /* free_screen */ 89 1.1.10.2 tls NULL, /* show_screen */ 90 1.1.10.2 tls NULL, /* load_font */ 91 1.1.10.2 tls igmafb_pollc, /* pollc */ 92 1.1.10.2 tls NULL /* scroll */ 93 1.1.10.2 tls }; 94 1.1.10.2 tls 95 1.1.10.2 tls static void igmafb_init_screen(void *, struct vcons_screen *, int, long *); 96 1.1.10.2 tls static void igmafb_guess_size(struct igmafb_softc *, int *, int*); 97 1.1.10.2 tls static void igmafb_set_mode(struct igmafb_softc *, bool); 98 1.1.10.2 tls 99 1.1.10.2 tls static void igmafb_planestart_quirk(struct igmafb_softc *); 100 1.1.10.2 tls static void igmafb_pfitdisable_quirk(struct igmafb_softc *); 101 1.1.10.2 tls 102 1.1.10.2 tls static void igmafb_get_brightness_max(struct igmafb_softc *, int *); 103 1.1.10.2 tls static void igmafb_get_brightness(struct igmafb_softc *, int *); 104 1.1.10.2 tls static void igmafb_set_brightness(struct igmafb_softc *, int); 105 1.1.10.2 tls 106 1.1.10.2 tls static int 107 1.1.10.2 tls igmafb_match(device_t parent, cfdata_t match, void *aux) 108 1.1.10.2 tls { 109 1.1.10.2 tls struct igma_attach_args *iaa = (struct igma_attach_args *)aux; 110 1.1.10.2 tls 111 1.1.10.2 tls if (strcmp(iaa->iaa_name, "igmafb") == 0) return 100; 112 1.1.10.2 tls return 0; 113 1.1.10.2 tls } 114 1.1.10.2 tls 115 1.1.10.2 tls static void 116 1.1.10.2 tls igmafb_attach(device_t parent, device_t self, void *aux) 117 1.1.10.2 tls { 118 1.1.10.2 tls struct igmafb_softc *sc = device_private(self); 119 1.1.10.2 tls struct igma_attach_args *iaa = (struct igma_attach_args *)aux; 120 1.1.10.2 tls struct rasops_info *ri; 121 1.1.10.2 tls prop_dictionary_t dict; 122 1.1.10.2 tls bool is_console; 123 1.1.10.2 tls unsigned long defattr; 124 1.1.10.2 tls struct wsemuldisplaydev_attach_args waa; 125 1.1.10.2 tls 126 1.1.10.2 tls sc->sc_dev = self; 127 1.1.10.2 tls 128 1.1.10.2 tls aprint_normal("\n"); 129 1.1.10.2 tls 130 1.1.10.2 tls dict = device_properties(self); 131 1.1.10.2 tls prop_dictionary_get_bool(dict, "is_console", &is_console); 132 1.1.10.2 tls if (iaa->iaa_console) 133 1.1.10.2 tls is_console = true; 134 1.1.10.2 tls 135 1.1.10.2 tls sc->sc_chip = iaa->iaa_chip; 136 1.1.10.2 tls 137 1.1.10.2 tls sc->sc_fbaddr = bus_space_vaddr(sc->sc_chip.gmt, sc->sc_chip.gmh); 138 1.1.10.2 tls sc->sc_fbsize = 16 * 1024 * 1024; 139 1.1.10.2 tls 140 1.1.10.2 tls igmafb_guess_size(sc, &sc->sc_width, &sc->sc_height); 141 1.1.10.2 tls sc->sc_depth = 32; 142 1.1.10.2 tls sc->sc_stride = (sc->sc_width*4 + 511)/512*512; 143 1.1.10.2 tls 144 1.1.10.2 tls aprint_normal("%s: %d x %d, %d bit, stride %d\n", device_xname(self), 145 1.1.10.2 tls sc->sc_width, sc->sc_height, sc->sc_depth, sc->sc_stride); 146 1.1.10.2 tls 147 1.1.10.2 tls aprint_normal("%s: %d MB video memory at 0x%p\n", device_xname(self), 148 1.1.10.2 tls (int)sc->sc_fbsize >> 20, (void *)sc->sc_chip.gmb); 149 1.1.10.2 tls 150 1.1.10.2 tls sc->sc_vga_save = kmem_alloc(256*1024, KM_SLEEP); 151 1.1.10.2 tls 152 1.1.10.2 tls igmafb_get_brightness(sc, &sc->sc_brightness); 153 1.1.10.2 tls igmafb_get_brightness_max(sc, &sc->sc_brightness_max); 154 1.1.10.2 tls sc->sc_backlight = sc->sc_brightness != 0; 155 1.1.10.2 tls 156 1.1.10.2 tls sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 157 1.1.10.2 tls "default", 158 1.1.10.2 tls 0, 0, 159 1.1.10.2 tls NULL, 160 1.1.10.2 tls 8, 16, 161 1.1.10.2 tls WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 162 1.1.10.2 tls NULL 163 1.1.10.2 tls }; 164 1.1.10.2 tls sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 165 1.1.10.2 tls sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 166 1.1.10.2 tls 167 1.1.10.2 tls vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 168 1.1.10.2 tls &igmafb_accessops); 169 1.1.10.2 tls sc->vd.init_screen = igmafb_init_screen; 170 1.1.10.2 tls 171 1.1.10.2 tls /* enable hardware display */ 172 1.1.10.2 tls igmafb_set_mode(sc, true); 173 1.1.10.2 tls 174 1.1.10.2 tls ri = &sc->sc_console_screen.scr_ri; 175 1.1.10.2 tls 176 1.1.10.2 tls if (is_console) { 177 1.1.10.2 tls vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 178 1.1.10.2 tls &defattr); 179 1.1.10.2 tls 180 1.1.10.2 tls sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC 181 1.1.10.2 tls | VCONS_NO_COPYROWS | VCONS_NO_COPYCOLS; 182 1.1.10.2 tls vcons_redraw_screen(&sc->sc_console_screen); 183 1.1.10.2 tls 184 1.1.10.2 tls sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 185 1.1.10.2 tls sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 186 1.1.10.2 tls sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 187 1.1.10.2 tls sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 188 1.1.10.2 tls 189 1.1.10.2 tls wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 190 1.1.10.2 tls defattr); 191 1.1.10.2 tls vcons_replay_msgbuf(&sc->sc_console_screen); 192 1.1.10.2 tls } else { 193 1.1.10.2 tls if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 194 1.1.10.2 tls /* do some minimal setup to avoid weirdness later */ 195 1.1.10.2 tls vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 196 1.1.10.2 tls &defattr); 197 1.1.10.2 tls } else 198 1.1.10.2 tls (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 199 1.1.10.2 tls } 200 1.1.10.2 tls 201 1.1.10.2 tls waa.console = is_console; 202 1.1.10.2 tls waa.scrdata = &sc->sc_screenlist; 203 1.1.10.2 tls waa.accessops = &igmafb_accessops; 204 1.1.10.2 tls waa.accesscookie = &sc->vd; 205 1.1.10.2 tls 206 1.1.10.2 tls config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 207 1.1.10.2 tls } 208 1.1.10.2 tls 209 1.1.10.2 tls /* 210 1.1.10.2 tls * wsdisplay accessops 211 1.1.10.2 tls */ 212 1.1.10.2 tls 213 1.1.10.2 tls static int 214 1.1.10.2 tls igmafb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, 215 1.1.10.2 tls struct lwp *l) 216 1.1.10.2 tls { 217 1.1.10.2 tls struct vcons_data *vd = v; 218 1.1.10.2 tls struct igmafb_softc *sc = vd->cookie; 219 1.1.10.2 tls struct wsdisplay_fbinfo *wdf; 220 1.1.10.2 tls struct vcons_screen *ms = vd->active; 221 1.1.10.2 tls struct wsdisplayio_fbinfo *fbi; 222 1.1.10.2 tls struct wsdisplay_param *param; 223 1.1.10.2 tls int val; 224 1.1.10.2 tls 225 1.1.10.2 tls switch (cmd) { 226 1.1.10.2 tls case WSDISPLAYIO_GTYPE: 227 1.1.10.2 tls *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 228 1.1.10.2 tls return 0; 229 1.1.10.2 tls case WSDISPLAYIO_GINFO: 230 1.1.10.2 tls if (ms == NULL) 231 1.1.10.2 tls return ENODEV; 232 1.1.10.2 tls wdf = data; 233 1.1.10.2 tls wdf->width = ms->scr_ri.ri_width; 234 1.1.10.2 tls wdf->height = ms->scr_ri.ri_height; 235 1.1.10.2 tls wdf->depth = ms->scr_ri.ri_depth; 236 1.1.10.2 tls wdf->cmsize = 256; /* XXX */ 237 1.1.10.2 tls return 0; 238 1.1.10.2 tls case WSDISPLAYIO_LINEBYTES: 239 1.1.10.2 tls if (ms == NULL) 240 1.1.10.2 tls return ENODEV; 241 1.1.10.2 tls *(u_int *)data = ms->scr_ri.ri_stride; 242 1.1.10.2 tls return 0; 243 1.1.10.2 tls case WSDISPLAYIO_GET_FBINFO: 244 1.1.10.2 tls fbi = data; 245 1.1.10.2 tls return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 246 1.1.10.2 tls case WSDISPLAYIO_SVIDEO: 247 1.1.10.2 tls val = (*(u_int *)data) != WSDISPLAYIO_VIDEO_OFF; 248 1.1.10.2 tls sc->sc_backlight = val; 249 1.1.10.2 tls if (val) 250 1.1.10.2 tls igmafb_set_brightness(sc, sc->sc_brightness); 251 1.1.10.2 tls else 252 1.1.10.2 tls igmafb_set_brightness(sc, 0); 253 1.1.10.2 tls return 0; 254 1.1.10.2 tls case WSDISPLAYIO_GETPARAM: 255 1.1.10.2 tls param = (struct wsdisplay_param *)data; 256 1.1.10.2 tls switch (param->param) { 257 1.1.10.2 tls case WSDISPLAYIO_PARAM_BRIGHTNESS: 258 1.1.10.2 tls param->min = 0; 259 1.1.10.2 tls param->max = 255; 260 1.1.10.2 tls if (sc->sc_backlight) 261 1.1.10.2 tls igmafb_get_brightness(sc, &val); 262 1.1.10.2 tls else 263 1.1.10.2 tls val = sc->sc_brightness; 264 1.1.10.2 tls val = val * 255 / sc->sc_brightness_max; 265 1.1.10.2 tls param->curval = val; 266 1.1.10.2 tls return 0; 267 1.1.10.2 tls case WSDISPLAYIO_PARAM_BACKLIGHT: 268 1.1.10.2 tls param->min = 0; 269 1.1.10.2 tls param->max = 1; 270 1.1.10.2 tls param->curval = sc->sc_backlight; 271 1.1.10.2 tls return 0; 272 1.1.10.2 tls } 273 1.1.10.2 tls return EPASSTHROUGH; 274 1.1.10.2 tls case WSDISPLAYIO_SETPARAM: 275 1.1.10.2 tls param = (struct wsdisplay_param *)data; 276 1.1.10.2 tls switch (param->param) { 277 1.1.10.2 tls case WSDISPLAYIO_PARAM_BRIGHTNESS: 278 1.1.10.2 tls val = param->curval; 279 1.1.10.2 tls if (val < 0) 280 1.1.10.2 tls val = 0; 281 1.1.10.2 tls if (val > 255) 282 1.1.10.2 tls val = 255; 283 1.1.10.2 tls val = val * sc->sc_brightness_max / 255; 284 1.1.10.2 tls sc->sc_brightness = val; 285 1.1.10.2 tls if (sc->sc_backlight) 286 1.1.10.2 tls igmafb_set_brightness(sc, val); 287 1.1.10.2 tls return 0; 288 1.1.10.2 tls case WSDISPLAYIO_PARAM_BACKLIGHT: 289 1.1.10.2 tls val = param->curval; 290 1.1.10.2 tls sc->sc_backlight = val; 291 1.1.10.2 tls if (val) 292 1.1.10.2 tls igmafb_set_brightness(sc, sc->sc_brightness); 293 1.1.10.2 tls else 294 1.1.10.2 tls igmafb_set_brightness(sc, 0); 295 1.1.10.2 tls return 0; 296 1.1.10.2 tls } 297 1.1.10.2 tls return EPASSTHROUGH; 298 1.1.10.2 tls } 299 1.1.10.2 tls 300 1.1.10.2 tls return EPASSTHROUGH; 301 1.1.10.2 tls } 302 1.1.10.2 tls 303 1.1.10.2 tls static paddr_t 304 1.1.10.2 tls igmafb_mmap(void *v, void *vs, off_t offset, int prot) 305 1.1.10.2 tls { 306 1.1.10.2 tls struct vcons_data *vd = v; 307 1.1.10.2 tls struct igmafb_softc *sc = vd->cookie; 308 1.1.10.2 tls 309 1.1.10.2 tls if ((offset & PAGE_MASK) != 0) 310 1.1.10.2 tls return -1; 311 1.1.10.2 tls 312 1.1.10.2 tls if (offset < 0 || offset >= sc->sc_fbsize) 313 1.1.10.2 tls return -1; 314 1.1.10.2 tls 315 1.1.10.2 tls return bus_space_mmap(sc->sc_chip.gmt, sc->sc_chip.gmb, offset, prot, 316 1.1.10.2 tls BUS_SPACE_MAP_LINEAR); 317 1.1.10.2 tls } 318 1.1.10.2 tls 319 1.1.10.2 tls static void 320 1.1.10.2 tls igmafb_pollc(void *v, int on) 321 1.1.10.2 tls { 322 1.1.10.2 tls struct vcons_data *vd = v; 323 1.1.10.2 tls struct igmafb_softc *sc = vd->cookie; 324 1.1.10.2 tls 325 1.1.10.2 tls if (sc == NULL) 326 1.1.10.2 tls return; 327 1.1.10.2 tls if (sc->sc_console_screen.scr_vd == NULL) 328 1.1.10.2 tls return; 329 1.1.10.2 tls 330 1.1.10.2 tls if (on) 331 1.1.10.2 tls vcons_enable_polling(&sc->vd); 332 1.1.10.2 tls else 333 1.1.10.2 tls vcons_disable_polling(&sc->vd); 334 1.1.10.2 tls } 335 1.1.10.2 tls 336 1.1.10.2 tls static void 337 1.1.10.2 tls igmafb_init_screen(void *cookie, struct vcons_screen *scr, 338 1.1.10.2 tls int existing, long *defattr) 339 1.1.10.2 tls { 340 1.1.10.2 tls struct igmafb_softc *sc = cookie; 341 1.1.10.2 tls struct rasops_info *ri = &scr->scr_ri; 342 1.1.10.2 tls 343 1.1.10.2 tls memset(ri, 0, sizeof(struct rasops_info)); 344 1.1.10.2 tls 345 1.1.10.2 tls ri->ri_depth = sc->sc_depth; 346 1.1.10.2 tls ri->ri_width = sc->sc_width; 347 1.1.10.2 tls ri->ri_height = sc->sc_height; 348 1.1.10.2 tls ri->ri_stride = sc->sc_stride; 349 1.1.10.2 tls ri->ri_flg = RI_CENTER | RI_FULLCLEAR; 350 1.1.10.2 tls 351 1.1.10.2 tls ri->ri_bits = (char *)sc->sc_fbaddr; 352 1.1.10.2 tls 353 1.1.10.2 tls if (existing) { 354 1.1.10.2 tls ri->ri_flg |= RI_CLEAR; 355 1.1.10.2 tls } 356 1.1.10.2 tls 357 1.1.10.2 tls switch (sc->sc_depth) { 358 1.1.10.2 tls case 32: 359 1.1.10.2 tls ri->ri_rnum = 8; 360 1.1.10.2 tls ri->ri_gnum = 8; 361 1.1.10.2 tls ri->ri_bnum = 8; 362 1.1.10.2 tls ri->ri_rpos = 16; 363 1.1.10.2 tls ri->ri_gpos = 8; 364 1.1.10.2 tls ri->ri_bpos = 0; 365 1.1.10.2 tls break; 366 1.1.10.2 tls } 367 1.1.10.2 tls 368 1.1.10.2 tls rasops_init(ri, 0, 0); 369 1.1.10.2 tls ri->ri_caps = WSSCREEN_WSCOLORS; 370 1.1.10.2 tls 371 1.1.10.2 tls rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 372 1.1.10.2 tls sc->sc_width / ri->ri_font->fontwidth); 373 1.1.10.2 tls 374 1.1.10.2 tls ri->ri_hw = scr; 375 1.1.10.2 tls } 376 1.1.10.2 tls 377 1.1.10.2 tls static void 378 1.1.10.2 tls igmafb_guess_size(struct igmafb_softc *sc, int *widthp, int *heightp) 379 1.1.10.2 tls { 380 1.1.10.2 tls const struct igma_chip *cd = &sc->sc_chip; 381 1.1.10.2 tls const struct igma_chip_ops *co = cd->ops; 382 1.1.10.2 tls int pipe = cd->use_pipe; 383 1.1.10.2 tls u_int32_t r; 384 1.1.10.2 tls 385 1.1.10.2 tls r = co->read_reg(cd, PIPE_HTOTAL(pipe)); 386 1.1.10.2 tls *widthp = PIPE_HTOTAL_GET_ACTIVE(r); 387 1.1.10.2 tls r = co->read_reg(cd, PIPE_VTOTAL(pipe)); 388 1.1.10.2 tls *heightp = PIPE_VTOTAL_GET_ACTIVE(r); 389 1.1.10.2 tls 390 1.1.10.2 tls aprint_normal("%s: vga active size %d x %d\n", 391 1.1.10.2 tls device_xname(sc->sc_dev), 392 1.1.10.2 tls *widthp, *heightp); 393 1.1.10.2 tls 394 1.1.10.2 tls if (*widthp < 640 || *heightp < 400) { 395 1.1.10.2 tls r = co->read_reg(cd, PF_WINSZ(pipe)); 396 1.1.10.2 tls *widthp = PF_WINSZ_GET_WIDTH(r); 397 1.1.10.2 tls *heightp = PF_WINSZ_GET_HEIGHT(r); 398 1.1.10.2 tls 399 1.1.10.2 tls aprint_normal("%s: window size %d x %d\n", 400 1.1.10.2 tls device_xname(sc->sc_dev), 401 1.1.10.2 tls *widthp, *heightp); 402 1.1.10.2 tls } 403 1.1.10.2 tls 404 1.1.10.2 tls if (*widthp < 640) *widthp = 640; 405 1.1.10.2 tls if (*heightp < 400) *heightp = 400; 406 1.1.10.2 tls } 407 1.1.10.2 tls 408 1.1.10.2 tls static void 409 1.1.10.2 tls igmafb_set_mode(struct igmafb_softc *sc, bool enable) 410 1.1.10.2 tls { 411 1.1.10.2 tls const struct igma_chip *cd = &sc->sc_chip; 412 1.1.10.2 tls const struct igma_chip_ops *co = cd->ops; 413 1.1.10.2 tls int pipe = cd->use_pipe; 414 1.1.10.2 tls u_int32_t r; 415 1.1.10.2 tls u_int8_t b; 416 1.1.10.2 tls int i; 417 1.1.10.2 tls 418 1.1.10.2 tls if (enable) { 419 1.1.10.2 tls /* disable VGA machinery */ 420 1.1.10.2 tls b = co->read_vga(cd, 0x01); 421 1.1.10.2 tls co->write_vga(cd, 0x01, b | 0x20); 422 1.1.10.2 tls 423 1.1.10.2 tls /* disable VGA compatible display */ 424 1.1.10.2 tls r = co->read_reg(cd, sc->sc_chip.vga_cntrl); 425 1.1.10.2 tls co->write_reg(cd, sc->sc_chip.vga_cntrl, r | VGA_CNTRL_DISABLE); 426 1.1.10.2 tls 427 1.1.10.2 tls /* save VGA memory */ 428 1.1.10.2 tls memcpy(sc->sc_vga_save, sc->sc_fbaddr, 256*1024); 429 1.1.10.2 tls 430 1.1.10.2 tls /* configure panel fitter */ 431 1.1.10.2 tls co->write_reg(cd, PF_WINPOS(pipe), 432 1.1.10.2 tls PF_WINPOS_VAL(0, 0)); 433 1.1.10.2 tls co->write_reg(cd, PF_WINSZ(pipe), 434 1.1.10.2 tls PF_WINSZ_VAL(sc->sc_width, sc->sc_height)); 435 1.1.10.2 tls 436 1.1.10.2 tls /* pipe size */ 437 1.1.10.2 tls co->write_reg(cd, PIPE_SRCSZ(pipe), 438 1.1.10.2 tls PIPE_SRCSZ_VAL(sc->sc_width, sc->sc_height)); 439 1.1.10.2 tls 440 1.1.10.2 tls /* enable pipe */ 441 1.1.10.2 tls co->write_reg(cd, PIPE_CONF(pipe), 442 1.1.10.2 tls PIPE_CONF_ENABLE | PIPE_CONF_8BPP); 443 1.1.10.2 tls 444 1.1.10.2 tls /* configure planes */ 445 1.1.10.2 tls r = co->read_reg(cd, PRI_CTRL(pipe)); 446 1.1.10.2 tls r &= ~(PRI_CTRL_PIXFMTMSK | PRI_CTRL_TILED); 447 1.1.10.2 tls r |= PRI_CTRL_ENABLE | PRI_CTRL_BGR; 448 1.1.10.2 tls co->write_reg(cd, PRI_CTRL(pipe), r | cd->pri_cntrl); 449 1.1.10.2 tls co->write_reg(cd, PRI_LINOFF(pipe), 0); 450 1.1.10.2 tls co->write_reg(cd, PRI_STRIDE(pipe), sc->sc_stride); 451 1.1.10.2 tls co->write_reg(cd, PRI_SURF(pipe), 0); 452 1.1.10.2 tls co->write_reg(cd, PRI_TILEOFF(pipe), 0); 453 1.1.10.2 tls 454 1.1.10.2 tls if (cd->quirks & IGMA_PLANESTART_QUIRK) 455 1.1.10.2 tls igmafb_planestart_quirk(sc); 456 1.1.10.2 tls 457 1.1.10.2 tls if (cd->quirks & IGMA_PFITDISABLE_QUIRK) 458 1.1.10.2 tls igmafb_pfitdisable_quirk(sc); 459 1.1.10.2 tls } else { 460 1.1.10.2 tls /* disable planes */ 461 1.1.10.2 tls co->write_reg(cd, PRI_CTRL(pipe), 0 | cd->pri_cntrl); 462 1.1.10.2 tls co->write_reg(cd, PRI_LINOFF(pipe), 0); 463 1.1.10.2 tls co->write_reg(cd, PRI_STRIDE(pipe), 2560); 464 1.1.10.2 tls co->write_reg(cd, PRI_SURF(pipe), 0); 465 1.1.10.2 tls co->write_reg(cd, PRI_TILEOFF(pipe), 0); 466 1.1.10.2 tls 467 1.1.10.2 tls /* pipe size */ 468 1.1.10.2 tls co->write_reg(cd, PIPE_SRCSZ(pipe), 469 1.1.10.2 tls PIPE_SRCSZ_VAL(720,400)); 470 1.1.10.2 tls 471 1.1.10.2 tls /* disable pipe */ 472 1.1.10.2 tls co->write_reg(cd, PIPE_CONF(pipe), 0); 473 1.1.10.2 tls for (i=0; i<10; ++i) { 474 1.1.10.2 tls delay(10); 475 1.1.10.2 tls if ((co->read_reg(cd, PIPE_CONF(pipe)) & PIPE_CONF_STATE) == 0) 476 1.1.10.2 tls break; 477 1.1.10.2 tls } 478 1.1.10.2 tls 479 1.1.10.2 tls /* workaround before enabling VGA */ 480 1.1.10.2 tls r = co->read_reg(cd, 0x42000); 481 1.1.10.2 tls co->write_reg(cd, 0x42000, (r & 0x1fffffff) | 0xa0000000); 482 1.1.10.2 tls r = co->read_reg(cd, 0x42004); 483 1.1.10.2 tls co->write_reg(cd, 0x42004, (r & 0xfbffffff) | 0x00000000); 484 1.1.10.2 tls 485 1.1.10.2 tls /* configure panel fitter */ 486 1.1.10.2 tls co->write_reg(cd, PF_WINPOS(pipe), 487 1.1.10.2 tls PF_WINPOS_VAL(0, 0)); 488 1.1.10.2 tls co->write_reg(cd, PF_WINSZ(pipe), 489 1.1.10.2 tls PF_WINSZ_VAL(sc->sc_width, sc->sc_height)); 490 1.1.10.2 tls 491 1.1.10.2 tls /* enable VGA compatible display */ 492 1.1.10.2 tls r = co->read_reg(cd, sc->sc_chip.vga_cntrl); 493 1.1.10.2 tls co->write_reg(cd, sc->sc_chip.vga_cntrl, r & ~VGA_CNTRL_DISABLE); 494 1.1.10.2 tls 495 1.1.10.2 tls /* enable VGA machinery */ 496 1.1.10.2 tls b = co->read_vga(cd, 0x01); 497 1.1.10.2 tls co->write_vga(cd, 0x01, b & ~0x20); 498 1.1.10.2 tls 499 1.1.10.2 tls /* restore VGA memory */ 500 1.1.10.2 tls memcpy(sc->sc_fbaddr, sc->sc_vga_save, 256*1024); 501 1.1.10.2 tls 502 1.1.10.2 tls /* enable pipe again */ 503 1.1.10.2 tls co->write_reg(cd, PIPE_CONF(pipe), 504 1.1.10.2 tls PIPE_CONF_ENABLE | PIPE_CONF_6BPP | PIPE_CONF_DITHER); 505 1.1.10.2 tls } 506 1.1.10.2 tls } 507 1.1.10.2 tls 508 1.1.10.2 tls static void 509 1.1.10.2 tls igmafb_planestart_quirk(struct igmafb_softc *sc) 510 1.1.10.2 tls { 511 1.1.10.2 tls const struct igma_chip *cd = &sc->sc_chip; 512 1.1.10.2 tls const struct igma_chip_ops *co = cd->ops; 513 1.1.10.2 tls int pipe = cd->use_pipe; 514 1.1.10.2 tls u_int32_t cntrl, fwbcl; 515 1.1.10.2 tls 516 1.1.10.2 tls /* disable self refresh */ 517 1.1.10.2 tls fwbcl = co->read_reg(cd, FW_BLC_SELF); 518 1.1.10.2 tls co->write_reg(cd, FW_BLC_SELF, fwbcl & ~FW_BLC_SELF_EN); 519 1.1.10.2 tls 520 1.1.10.2 tls cntrl = co->read_reg(cd, CUR_CNTR(pipe)); 521 1.1.10.2 tls co->write_reg(cd, CUR_CNTR(pipe), 1<<5 | 0x07); 522 1.1.10.2 tls 523 1.1.10.2 tls /* "wait for vblank" */ 524 1.1.10.2 tls delay(40000); 525 1.1.10.2 tls 526 1.1.10.2 tls co->write_reg(cd, CUR_CNTR(pipe), cntrl); 527 1.1.10.2 tls co->write_reg(cd, CUR_BASE(pipe), 528 1.1.10.2 tls co->read_reg(cd, CUR_BASE(pipe))); 529 1.1.10.2 tls 530 1.1.10.2 tls co->write_reg(cd, FW_BLC_SELF, fwbcl); 531 1.1.10.2 tls } 532 1.1.10.2 tls 533 1.1.10.2 tls static void 534 1.1.10.2 tls igmafb_pfitdisable_quirk(struct igmafb_softc *sc) 535 1.1.10.2 tls { 536 1.1.10.2 tls const struct igma_chip *cd = &sc->sc_chip; 537 1.1.10.2 tls const struct igma_chip_ops *co = cd->ops; 538 1.1.10.2 tls u_int32_t r; 539 1.1.10.2 tls 540 1.1.10.2 tls /* disable i965 panel fitter */ 541 1.1.10.2 tls r = co->read_reg(cd, PF_CTRL_I965); 542 1.1.10.2 tls co->write_reg(cd, PF_CTRL_I965, r & ~PF_ENABLE); 543 1.1.10.2 tls } 544 1.1.10.2 tls 545 1.1.10.2 tls static void 546 1.1.10.2 tls igmafb_get_brightness_max(struct igmafb_softc *sc, int *valp) 547 1.1.10.2 tls { 548 1.1.10.2 tls const struct igma_chip *cd = &sc->sc_chip; 549 1.1.10.2 tls const struct igma_chip_ops *co = cd->ops; 550 1.1.10.2 tls u_int32_t r, f; 551 1.1.10.2 tls 552 1.1.10.2 tls r = co->read_reg(cd, cd->backlight_cntrl); 553 1.1.10.2 tls f = BACKLIGHT_GET_FREQ(r); 554 1.1.10.2 tls if (f == 0) { 555 1.1.10.2 tls r = co->read_reg(cd, RAWCLK_FREQ); 556 1.1.10.2 tls f = r * 1000000 / (200 * 128); 557 1.1.10.2 tls if (f == 0 || f > 32767) 558 1.1.10.2 tls f = 125 * 100000 / (200 * 128); 559 1.1.10.2 tls } 560 1.1.10.2 tls 561 1.1.10.2 tls *valp = f; 562 1.1.10.2 tls } 563 1.1.10.2 tls 564 1.1.10.2 tls static void 565 1.1.10.2 tls igmafb_get_brightness(struct igmafb_softc *sc, int *valp) 566 1.1.10.2 tls { 567 1.1.10.2 tls const struct igma_chip *cd = &sc->sc_chip; 568 1.1.10.2 tls const struct igma_chip_ops *co = cd->ops; 569 1.1.10.2 tls u_int32_t r, v; 570 1.1.10.2 tls 571 1.1.10.2 tls r = co->read_reg(cd, cd->backlight_cntrl); 572 1.1.10.2 tls v = BACKLIGHT_GET_CYCLE(r); 573 1.1.10.2 tls *valp = v; 574 1.1.10.2 tls } 575 1.1.10.2 tls 576 1.1.10.2 tls static void 577 1.1.10.2 tls igmafb_set_brightness(struct igmafb_softc *sc, int val) 578 1.1.10.2 tls { 579 1.1.10.2 tls const struct igma_chip *cd = &sc->sc_chip; 580 1.1.10.2 tls const struct igma_chip_ops *co = cd->ops; 581 1.1.10.2 tls u_int32_t r, f, l; 582 1.1.10.2 tls 583 1.1.10.2 tls r = co->read_reg(cd, cd->backlight_cntrl); 584 1.1.10.2 tls f = BACKLIGHT_GET_FREQ(r); 585 1.1.10.2 tls l = BACKLIGHT_GET_LEGACY(r); 586 1.1.10.2 tls 587 1.1.10.2 tls co->write_reg(cd, cd->backlight_cntrl, 588 1.1.10.2 tls BACKLIGHT_VAL(f,l,val)); 589 1.1.10.2 tls } 590 1.1.10.2 tls 591
Indexes created Fri Oct 17 23:09:53 GMT 2025