ismt.c revision 1.3.2.4
1 1.3.2.2 skrll /*- 2 1.3.2.2 skrll * Copyright (c) 2016 The NetBSD Foundation, Inc. 3 1.3.2.2 skrll * All rights reserved. 4 1.3.2.2 skrll * 5 1.3.2.2 skrll * This code is derived from software contributed to The NetBSD Foundation 6 1.3.2.2 skrll * by Masanobu SAITOH. 7 1.3.2.2 skrll * 8 1.3.2.2 skrll * Redistribution and use in source and binary forms, with or without 9 1.3.2.2 skrll * modification, are permitted provided that the following conditions 10 1.3.2.2 skrll * are met: 11 1.3.2.2 skrll * 1. Redistributions of source code must retain the above copyright 12 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer. 13 1.3.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 14 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer in the 15 1.3.2.2 skrll * documentation and/or other materials provided with the distribution. 16 1.3.2.2 skrll * 17 1.3.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 1.3.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 1.3.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 1.3.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 1.3.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 1.3.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 1.3.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 1.3.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 1.3.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 1.3.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 1.3.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 28 1.3.2.2 skrll */ 29 1.3.2.2 skrll 30 1.3.2.2 skrll /*- 31 1.3.2.2 skrll * Copyright (C) 2014 Intel Corporation 32 1.3.2.2 skrll * All rights reserved. 33 1.3.2.2 skrll * 34 1.3.2.2 skrll * Redistribution and use in source and binary forms, with or without 35 1.3.2.2 skrll * modification, are permitted provided that the following conditions 36 1.3.2.2 skrll * are met: 37 1.3.2.2 skrll * 1. Redistributions of source code must retain the above copyright 38 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer. 39 1.3.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 40 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer in the 41 1.3.2.2 skrll * documentation and/or other materials provided with the distribution. 42 1.3.2.2 skrll * 3. Neither the name of Intel Corporation nor the names of its 43 1.3.2.2 skrll * contributors may be used to endorse or promote products derived from 44 1.3.2.2 skrll * this software without specific prior written permission. 45 1.3.2.2 skrll * 46 1.3.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 1.3.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 1.3.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 1.3.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 1.3.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 1.3.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 1.3.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 1.3.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 1.3.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 1.3.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 1.3.2.2 skrll * SUCH DAMAGE. 57 1.3.2.2 skrll */ 58 1.3.2.2 skrll 59 1.3.2.2 skrll #include <sys/cdefs.h> 60 1.3.2.2 skrll #if 0 61 1.3.2.2 skrll __FBSDID("$FreeBSD: head/sys/dev/ismt/ismt.c 266474 2014-05-20 19:55:06Z jimharris $"); 62 1.3.2.2 skrll #endif 63 1.3.2.4 skrll __KERNEL_RCSID(0, "$NetBSD: ismt.c,v 1.3.2.4 2017/08/28 17:52:06 skrll Exp $"); 64 1.3.2.2 skrll 65 1.3.2.2 skrll #include <sys/param.h> 66 1.3.2.2 skrll #include <sys/systm.h> 67 1.3.2.2 skrll #include <sys/device.h> 68 1.3.2.2 skrll #include <sys/errno.h> 69 1.3.2.2 skrll #include <sys/kernel.h> 70 1.3.2.2 skrll #include <sys/module.h> 71 1.3.2.2 skrll #include <sys/mutex.h> 72 1.3.2.2 skrll #include <sys/proc.h> 73 1.3.2.2 skrll 74 1.3.2.2 skrll #include <sys/bus.h> 75 1.3.2.2 skrll 76 1.3.2.2 skrll #include <dev/pci/pcidevs.h> 77 1.3.2.2 skrll #include <dev/pci/pcireg.h> 78 1.3.2.2 skrll #include <dev/pci/pcivar.h> 79 1.3.2.2 skrll 80 1.3.2.2 skrll #include <dev/i2c/i2cvar.h> 81 1.3.2.2 skrll 82 1.3.2.2 skrll #define ISMT_DESC_ENTRIES 32 83 1.3.2.2 skrll 84 1.3.2.2 skrll /* Hardware Descriptor Constants - Control Field */ 85 1.3.2.2 skrll #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ 86 1.3.2.2 skrll #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ 87 1.3.2.2 skrll #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ 88 1.3.2.2 skrll #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ 89 1.3.2.2 skrll #define ISMT_DESC_I2C 0x20 /* I2C Enable */ 90 1.3.2.2 skrll #define ISMT_DESC_INT 0x40 /* Interrupt */ 91 1.3.2.2 skrll #define ISMT_DESC_SOE 0x80 /* Stop On Error */ 92 1.3.2.2 skrll 93 1.3.2.2 skrll /* Hardware Descriptor Constants - Status Field */ 94 1.3.2.2 skrll #define ISMT_DESC_SCS 0x01 /* Success */ 95 1.3.2.2 skrll #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ 96 1.3.2.2 skrll #define ISMT_DESC_NAK 0x08 /* NAK Received */ 97 1.3.2.2 skrll #define ISMT_DESC_CRC 0x10 /* CRC Error */ 98 1.3.2.2 skrll #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ 99 1.3.2.2 skrll #define ISMT_DESC_COL 0x40 /* Collisions */ 100 1.3.2.2 skrll #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ 101 1.3.2.2 skrll 102 1.3.2.2 skrll /* Macros */ 103 1.3.2.2 skrll #define ISMT_DESC_ADDR_RW(addr, is_read) (((addr) << 1) | (is_read)) 104 1.3.2.2 skrll 105 1.3.2.2 skrll /* iSMT General Register address offsets (SMBBAR + <addr>) */ 106 1.3.2.2 skrll #define ISMT_GR_GCTRL 0x000 /* General Control */ 107 1.3.2.2 skrll #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ 108 1.3.2.2 skrll #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ 109 1.3.2.2 skrll #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ 110 1.3.2.2 skrll #define ISMT_GR_ERRSTS 0x018 /* Error Status */ 111 1.3.2.2 skrll #define ISMT_GR_ERRINFO 0x01c /* Error Information */ 112 1.3.2.2 skrll 113 1.3.2.2 skrll /* iSMT Master Registers */ 114 1.3.2.2 skrll #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ 115 1.3.2.2 skrll #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ 116 1.3.2.2 skrll #define ISMT_MSTR_MSTS 0x10c /* Master Status */ 117 1.3.2.2 skrll #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ 118 1.3.2.2 skrll #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ 119 1.3.2.2 skrll 120 1.3.2.2 skrll /* iSMT Miscellaneous Registers */ 121 1.3.2.2 skrll #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ 122 1.3.2.2 skrll 123 1.3.2.2 skrll /* General Control Register (GCTRL) bit definitions */ 124 1.3.2.2 skrll #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ 125 1.3.2.2 skrll #define ISMT_GCTRL_KILL 0x08 /* Kill */ 126 1.3.2.2 skrll #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ 127 1.3.2.2 skrll 128 1.3.2.2 skrll /* Master Control Register (MCTRL) bit definitions */ 129 1.3.2.2 skrll #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ 130 1.3.2.2 skrll #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ 131 1.3.2.2 skrll #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ 132 1.3.2.2 skrll 133 1.3.2.2 skrll /* Master Status Register (MSTS) bit definitions */ 134 1.3.2.2 skrll #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ 135 1.3.2.2 skrll #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ 136 1.3.2.2 skrll #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ 137 1.3.2.2 skrll #define ISMT_MSTS_IP 0x01 /* In Progress */ 138 1.3.2.2 skrll 139 1.3.2.2 skrll /* Master Descriptor Size (MDS) bit definitions */ 140 1.3.2.2 skrll #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ 141 1.3.2.2 skrll 142 1.3.2.2 skrll /* SMBus PHY Global Timing Register (SPGT) bit definitions */ 143 1.3.2.2 skrll #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ 144 1.3.2.2 skrll #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ 145 1.3.2.2 skrll #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ 146 1.3.2.2 skrll #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ 147 1.3.2.2 skrll #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ 148 1.3.2.2 skrll 149 1.3.2.2 skrll /* MSI Control Register (MSICTL) bit definitions */ 150 1.3.2.2 skrll #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ 151 1.3.2.2 skrll 152 1.3.2.2 skrll #define ISMT_MAX_BLOCK_SIZE 32 /* per SMBus spec */ 153 1.3.2.2 skrll 154 1.3.2.2 skrll #define ISMT_INTR_TIMEOUT (hz / 50) /* 0.02s */ 155 1.3.2.2 skrll #define ISMT_POLL_DELAY 100 /* 100usec */ 156 1.3.2.2 skrll #define ISMT_POLL_COUNT 200 /* 100usec * 200 = 0.02s */ 157 1.3.2.2 skrll 158 1.3.2.2 skrll //#define ISMT_DEBUG aprint_debug_dev 159 1.3.2.2 skrll #ifndef ISMT_DEBUG 160 1.3.2.2 skrll #define ISMT_DEBUG(...) 161 1.3.2.2 skrll #endif 162 1.3.2.2 skrll 163 1.3.2.2 skrll #define ISMT_LOW(a) ((a) & 0xFFFFFFFFULL) 164 1.3.2.2 skrll #define ISMT_HIGH(a) (((uint64_t)(a) >> 32) & 0xFFFFFFFFFULL) 165 1.3.2.2 skrll 166 1.3.2.2 skrll /* iSMT Hardware Descriptor */ 167 1.3.2.2 skrll struct ismt_desc { 168 1.3.2.2 skrll uint8_t tgtaddr_rw; /* target address & r/w bit */ 169 1.3.2.2 skrll uint8_t wr_len_cmd; /* write length in bytes or a command */ 170 1.3.2.2 skrll uint8_t rd_len; /* read length */ 171 1.3.2.2 skrll uint8_t control; /* control bits */ 172 1.3.2.2 skrll uint8_t status; /* status bits */ 173 1.3.2.2 skrll uint8_t retry; /* collision retry and retry count */ 174 1.3.2.2 skrll uint8_t rxbytes; /* received bytes */ 175 1.3.2.2 skrll uint8_t txbytes; /* transmitted bytes */ 176 1.3.2.2 skrll uint32_t dptr_low; /* lower 32 bit of the data pointer */ 177 1.3.2.2 skrll uint32_t dptr_high; /* upper 32 bit of the data pointer */ 178 1.3.2.2 skrll } __packed; 179 1.3.2.2 skrll 180 1.3.2.2 skrll #define DESC_SIZE (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)) 181 1.3.2.2 skrll 182 1.3.2.2 skrll #define DMA_BUFFER_SIZE 64 183 1.3.2.2 skrll 184 1.3.2.2 skrll struct ismt_softc { 185 1.3.2.2 skrll device_t pcidev; 186 1.3.2.2 skrll device_t smbdev; 187 1.3.2.2 skrll 188 1.3.2.2 skrll struct i2c_controller sc_i2c_tag; 189 1.3.2.2 skrll kmutex_t sc_i2c_mutex; 190 1.3.2.2 skrll 191 1.3.2.2 skrll pci_chipset_tag_t sc_pc; 192 1.3.2.2 skrll pcitag_t sc_pcitag; 193 1.3.2.2 skrll pci_intr_handle_t *sc_pihp; 194 1.3.2.2 skrll void *sc_ih; 195 1.3.2.2 skrll 196 1.3.2.2 skrll bus_space_tag_t mmio_tag; 197 1.3.2.2 skrll bus_space_handle_t mmio_handle; 198 1.3.2.2 skrll bus_size_t mmio_size; 199 1.3.2.2 skrll 200 1.3.2.2 skrll uint8_t head; 201 1.3.2.2 skrll 202 1.3.2.2 skrll struct ismt_desc *desc; 203 1.3.2.2 skrll bus_dma_tag_t desc_dma_tag; 204 1.3.2.2 skrll bus_dmamap_t desc_dma_map; 205 1.3.2.2 skrll bus_dma_segment_t desc_dma_seg; 206 1.3.2.2 skrll int desc_rseg; 207 1.3.2.2 skrll 208 1.3.2.2 skrll uint8_t *dma_buffer; 209 1.3.2.2 skrll bus_dma_tag_t dma_buffer_dma_tag; 210 1.3.2.2 skrll bus_dmamap_t dma_buffer_dma_map; 211 1.3.2.2 skrll bus_dma_segment_t dma_buffer_dma_seg; 212 1.3.2.2 skrll int dma_buffer_rseg; 213 1.3.2.2 skrll 214 1.3.2.2 skrll uint8_t using_msi; 215 1.3.2.2 skrll }; 216 1.3.2.2 skrll 217 1.3.2.2 skrll static int ismt_intr(void *); 218 1.3.2.2 skrll static int ismt_i2c_acquire_bus(void *, int); 219 1.3.2.2 skrll static void ismt_i2c_release_bus(void *, int); 220 1.3.2.2 skrll static int ismt_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 221 1.3.2.2 skrll size_t, void *, size_t, int); 222 1.3.2.2 skrll static struct ismt_desc *ismt_alloc_desc(struct ismt_softc *); 223 1.3.2.2 skrll static int ismt_submit(struct ismt_softc *, struct ismt_desc *, 224 1.3.2.2 skrll i2c_addr_t, uint8_t, int); 225 1.3.2.2 skrll static int ismt_quick(struct ismt_softc *, i2c_addr_t, i2c_op_t, int); 226 1.3.2.2 skrll static int ismt_sendb(struct ismt_softc *, i2c_addr_t, i2c_op_t, char, 227 1.3.2.2 skrll int); 228 1.3.2.2 skrll static int ismt_recvb(struct ismt_softc *, i2c_addr_t, i2c_op_t, int); 229 1.3.2.2 skrll static int ismt_writeb(struct ismt_softc *, i2c_addr_t, i2c_op_t, uint8_t, 230 1.3.2.2 skrll char, int); 231 1.3.2.2 skrll static int ismt_writew(struct ismt_softc *, i2c_addr_t, i2c_op_t, uint8_t, 232 1.3.2.2 skrll uint16_t, int); 233 1.3.2.2 skrll static int ismt_readb(struct ismt_softc *, i2c_addr_t, i2c_op_t, char, 234 1.3.2.2 skrll int); 235 1.3.2.2 skrll static int ismt_readw(struct ismt_softc *, i2c_addr_t, i2c_op_t, char, 236 1.3.2.2 skrll int); 237 1.3.2.2 skrll 238 1.3.2.2 skrll static int ismt_match(device_t, cfdata_t, void *); 239 1.3.2.2 skrll static void ismt_attach(device_t, device_t, void *); 240 1.3.2.2 skrll static int ismt_detach(device_t, int); 241 1.3.2.2 skrll static int ismt_rescan(device_t, const char *, const int *); 242 1.3.2.2 skrll static void ismt_config_interrupts(device_t); 243 1.3.2.2 skrll static void ismt_chdet(device_t, device_t); 244 1.3.2.2 skrll 245 1.3.2.2 skrll CFATTACH_DECL3_NEW(ismt, sizeof(struct ismt_softc), 246 1.3.2.2 skrll ismt_match, ismt_attach, ismt_detach, NULL, ismt_rescan, ismt_chdet, 247 1.3.2.2 skrll DVF_DETACH_SHUTDOWN); 248 1.3.2.2 skrll 249 1.3.2.2 skrll static int 250 1.3.2.2 skrll ismt_intr(void *arg) 251 1.3.2.2 skrll { 252 1.3.2.2 skrll struct ismt_softc *sc = arg; 253 1.3.2.2 skrll uint32_t val; 254 1.3.2.2 skrll 255 1.3.2.2 skrll val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MSTS); 256 1.3.2.2 skrll if ((sc->using_msi == 0) 257 1.3.2.2 skrll && (val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)) == 0) 258 1.3.2.2 skrll return 0; /* Not for me */ 259 1.3.2.2 skrll 260 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s MSTS = 0x%08x\n", __func__, val); 261 1.3.2.2 skrll 262 1.3.2.2 skrll val |= (ISMT_MSTS_MIS | ISMT_MSTS_MEIS); 263 1.3.2.2 skrll bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MSTS, val); 264 1.3.2.2 skrll 265 1.3.2.2 skrll if (sc->using_msi) 266 1.3.2.2 skrll wakeup(sc); 267 1.3.2.2 skrll 268 1.3.2.2 skrll return 1; 269 1.3.2.2 skrll } 270 1.3.2.2 skrll 271 1.3.2.2 skrll static int 272 1.3.2.2 skrll ismt_i2c_acquire_bus(void *cookie, int flags) 273 1.3.2.2 skrll { 274 1.3.2.2 skrll struct ismt_softc *sc = cookie; 275 1.3.2.2 skrll 276 1.3.2.2 skrll mutex_enter(&sc->sc_i2c_mutex); 277 1.3.2.2 skrll return 0; 278 1.3.2.2 skrll } 279 1.3.2.2 skrll 280 1.3.2.2 skrll static void 281 1.3.2.2 skrll ismt_i2c_release_bus(void *cookie, int flags) 282 1.3.2.2 skrll { 283 1.3.2.2 skrll struct ismt_softc *sc = cookie; 284 1.3.2.2 skrll 285 1.3.2.2 skrll mutex_exit(&sc->sc_i2c_mutex); 286 1.3.2.2 skrll } 287 1.3.2.2 skrll 288 1.3.2.2 skrll static int 289 1.3.2.2 skrll ismt_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 290 1.3.2.2 skrll const void *cmd, size_t cmdlen, void *buf, size_t buflen, int flags) 291 1.3.2.2 skrll { 292 1.3.2.2 skrll struct ismt_softc *sc = cookie; 293 1.3.2.2 skrll uint8_t *p = buf; 294 1.3.2.2 skrll int rv; 295 1.3.2.2 skrll 296 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "exec: op %d, addr 0x%02x, cmdlen %zu, " 297 1.3.2.2 skrll " buflen %zu, flags 0x%02x\n", op, addr, cmdlen, buflen, flags); 298 1.3.2.2 skrll 299 1.3.2.2 skrll if ((cmdlen == 0) && (buflen == 0)) 300 1.3.2.2 skrll return ismt_quick(sc, addr, op, flags); 301 1.3.2.2 skrll 302 1.3.2.2 skrll if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 303 1.3.2.2 skrll rv = ismt_recvb(sc, addr, op, flags); 304 1.3.2.2 skrll if (rv == -1) 305 1.3.2.2 skrll return -1; 306 1.3.2.2 skrll *p = (uint8_t)rv; 307 1.3.2.2 skrll return 0; 308 1.3.2.2 skrll } 309 1.3.2.2 skrll 310 1.3.2.2 skrll if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 311 1.3.2.2 skrll rv = ismt_readb(sc, addr, op, *(const uint8_t*)cmd, flags); 312 1.3.2.2 skrll if (rv == -1) 313 1.3.2.2 skrll return -1; 314 1.3.2.2 skrll *p = (uint8_t)rv; 315 1.3.2.2 skrll return 0; 316 1.3.2.2 skrll } 317 1.3.2.2 skrll 318 1.3.2.2 skrll if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 2)) { 319 1.3.2.2 skrll rv = ismt_readw(sc, addr, op, *(const uint8_t*)cmd, flags); 320 1.3.2.2 skrll if (rv == -1) 321 1.3.2.2 skrll return -1; 322 1.3.2.2 skrll *(uint16_t *)p = (uint16_t)rv; 323 1.3.2.2 skrll return 0; 324 1.3.2.2 skrll } 325 1.3.2.2 skrll 326 1.3.2.2 skrll if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) 327 1.3.2.2 skrll return ismt_sendb(sc, addr, op, *(uint8_t*)buf, flags); 328 1.3.2.2 skrll 329 1.3.2.2 skrll if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) 330 1.3.2.2 skrll return ismt_writeb(sc, addr, op, *(const uint8_t*)cmd, 331 1.3.2.2 skrll *(uint8_t*)buf, flags); 332 1.3.2.2 skrll 333 1.3.2.2 skrll if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 2)) 334 1.3.2.2 skrll return ismt_writew(sc, addr, op, 335 1.3.2.2 skrll *(const uint8_t*)cmd, *((uint16_t *)buf), flags); 336 1.3.2.2 skrll 337 1.3.2.2 skrll return -1; 338 1.3.2.2 skrll } 339 1.3.2.2 skrll 340 1.3.2.2 skrll static struct ismt_desc * 341 1.3.2.2 skrll ismt_alloc_desc(struct ismt_softc *sc) 342 1.3.2.2 skrll { 343 1.3.2.2 skrll struct ismt_desc *desc; 344 1.3.2.2 skrll 345 1.3.2.2 skrll KASSERT(mutex_owned(&sc->sc_i2c_mutex)); 346 1.3.2.2 skrll 347 1.3.2.2 skrll desc = &sc->desc[sc->head++]; 348 1.3.2.2 skrll if (sc->head == ISMT_DESC_ENTRIES) 349 1.3.2.2 skrll sc->head = 0; 350 1.3.2.2 skrll 351 1.3.2.2 skrll memset(desc, 0, sizeof(*desc)); 352 1.3.2.2 skrll 353 1.3.2.2 skrll return (desc); 354 1.3.2.2 skrll } 355 1.3.2.2 skrll 356 1.3.2.2 skrll static int 357 1.3.2.2 skrll ismt_submit(struct ismt_softc *sc, struct ismt_desc *desc, i2c_addr_t slave, 358 1.3.2.2 skrll uint8_t is_read, int flags) 359 1.3.2.2 skrll { 360 1.3.2.2 skrll uint32_t err, fmhp, val; 361 1.3.2.2 skrll int timeout, i; 362 1.3.2.2 skrll 363 1.3.2.2 skrll if (sc->using_msi == 0) 364 1.3.2.2 skrll flags |= I2C_F_POLL; 365 1.3.2.2 skrll desc->control |= ISMT_DESC_FAIR; 366 1.3.2.2 skrll if ((flags & I2C_F_POLL) == 0) 367 1.3.2.2 skrll desc->control |= ISMT_DESC_INT; 368 1.3.2.2 skrll 369 1.3.2.2 skrll desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(slave, is_read); 370 1.3.2.2 skrll desc->dptr_low = ISMT_LOW(sc->dma_buffer_dma_map->dm_segs[0].ds_addr); 371 1.3.2.2 skrll desc->dptr_high = ISMT_HIGH(sc->dma_buffer_dma_map->dm_segs[0].ds_addr); 372 1.3.2.2 skrll 373 1.3.2.2 skrll bus_dmamap_sync(sc->desc_dma_tag, sc->desc_dma_map, 374 1.3.2.2 skrll desc - &sc->desc[0], sizeof(struct ismt_desc), 375 1.3.2.2 skrll BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 376 1.3.2.2 skrll 377 1.3.2.2 skrll fmhp = sc->head << 16; 378 1.3.2.2 skrll val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL); 379 1.3.2.2 skrll val &= ~ISMT_MCTRL_FMHP; 380 1.3.2.2 skrll val |= fmhp; 381 1.3.2.2 skrll bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL, val); 382 1.3.2.2 skrll 383 1.3.2.2 skrll /* set the start bit */ 384 1.3.2.2 skrll val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL); 385 1.3.2.2 skrll val |= ISMT_MCTRL_SS; 386 1.3.2.2 skrll bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL, val); 387 1.3.2.2 skrll 388 1.3.2.2 skrll i = 0; 389 1.3.2.2 skrll if ((flags & I2C_F_POLL) == 0) { 390 1.3.2.2 skrll timeout = ISMT_INTR_TIMEOUT; 391 1.3.2.2 skrll if (timeout == 0) 392 1.3.2.2 skrll timeout = 1; 393 1.3.2.2 skrll err = tsleep(sc, PWAIT, "ismt_wait", timeout); 394 1.3.2.2 skrll if (err != 0) { 395 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s timeout\n", __func__); 396 1.3.2.2 skrll return -1; 397 1.3.2.2 skrll } 398 1.3.2.2 skrll } else { 399 1.3.2.2 skrll /* Polling */ 400 1.3.2.2 skrll for (i = 0; i < ISMT_POLL_COUNT; i++) { 401 1.3.2.2 skrll val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, 402 1.3.2.2 skrll ISMT_MSTR_MSTS); 403 1.3.2.2 skrll if ((val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)) != 0) { 404 1.3.2.2 skrll ismt_intr(sc); 405 1.3.2.2 skrll err = 0; 406 1.3.2.2 skrll break; 407 1.3.2.2 skrll } 408 1.3.2.2 skrll delay(ISMT_POLL_DELAY); 409 1.3.2.2 skrll } 410 1.3.2.2 skrll if (i >= ISMT_POLL_COUNT) { 411 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s polling timeout. " 412 1.3.2.2 skrll "MSTS = %08x\n", __func__, val); 413 1.3.2.2 skrll return -1; 414 1.3.2.2 skrll } 415 1.3.2.2 skrll } 416 1.3.2.2 skrll 417 1.3.2.2 skrll bus_dmamap_sync(sc->desc_dma_tag, sc->desc_dma_map, 418 1.3.2.2 skrll desc - &sc->desc[0], sizeof(struct ismt_desc), 419 1.3.2.2 skrll BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 420 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s status=0x%02x\n", __func__, desc->status); 421 1.3.2.2 skrll 422 1.3.2.2 skrll if (desc->status & ISMT_DESC_SCS) 423 1.3.2.2 skrll return 0; 424 1.3.2.2 skrll 425 1.3.2.2 skrll if (desc->status & ISMT_DESC_NAK) 426 1.3.2.2 skrll return -1; 427 1.3.2.2 skrll 428 1.3.2.2 skrll if (desc->status & ISMT_DESC_CRC) 429 1.3.2.2 skrll return -1; 430 1.3.2.2 skrll 431 1.3.2.2 skrll if (desc->status & ISMT_DESC_COL) 432 1.3.2.2 skrll return -1; 433 1.3.2.2 skrll 434 1.3.2.2 skrll if (desc->status & ISMT_DESC_LPR) 435 1.3.2.2 skrll return -1; 436 1.3.2.2 skrll 437 1.3.2.2 skrll if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) 438 1.3.2.2 skrll return -1; 439 1.3.2.2 skrll 440 1.3.2.2 skrll return -1; 441 1.3.2.2 skrll } 442 1.3.2.2 skrll 443 1.3.2.2 skrll static int 444 1.3.2.2 skrll ismt_quick(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, int flags) 445 1.3.2.2 skrll { 446 1.3.2.2 skrll struct ismt_desc *desc; 447 1.3.2.2 skrll int is_read; 448 1.3.2.2 skrll 449 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 450 1.3.2.2 skrll 451 1.3.2.2 skrll desc = ismt_alloc_desc(sc); 452 1.3.2.2 skrll is_read = I2C_OP_READ_P(op); 453 1.3.2.2 skrll return (ismt_submit(sc, desc, slave, is_read, flags)); 454 1.3.2.2 skrll } 455 1.3.2.2 skrll 456 1.3.2.2 skrll static int 457 1.3.2.2 skrll ismt_sendb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char byte, 458 1.3.2.2 skrll int flags) 459 1.3.2.2 skrll { 460 1.3.2.2 skrll struct ismt_desc *desc; 461 1.3.2.2 skrll 462 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 463 1.3.2.2 skrll 464 1.3.2.2 skrll desc = ismt_alloc_desc(sc); 465 1.3.2.2 skrll desc->control = ISMT_DESC_CWRL; 466 1.3.2.2 skrll desc->wr_len_cmd = byte; 467 1.3.2.2 skrll 468 1.3.2.2 skrll return (ismt_submit(sc, desc, slave, 0, flags)); 469 1.3.2.2 skrll } 470 1.3.2.2 skrll 471 1.3.2.2 skrll static int 472 1.3.2.2 skrll ismt_recvb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, int flags) 473 1.3.2.2 skrll { 474 1.3.2.2 skrll struct ismt_desc *desc; 475 1.3.2.2 skrll int err; 476 1.3.2.2 skrll 477 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 478 1.3.2.2 skrll 479 1.3.2.2 skrll desc = ismt_alloc_desc(sc); 480 1.3.2.2 skrll desc->rd_len = 1; 481 1.3.2.2 skrll 482 1.3.2.2 skrll err = ismt_submit(sc, desc, slave, 1, flags); 483 1.3.2.2 skrll 484 1.3.2.2 skrll if (err != 0) 485 1.3.2.2 skrll return (err); 486 1.3.2.2 skrll 487 1.3.2.2 skrll return sc->dma_buffer[0]; 488 1.3.2.2 skrll } 489 1.3.2.2 skrll 490 1.3.2.2 skrll static int 491 1.3.2.2 skrll ismt_writeb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, uint8_t cmd, 492 1.3.2.2 skrll char byte, int flags) 493 1.3.2.2 skrll { 494 1.3.2.2 skrll struct ismt_desc *desc; 495 1.3.2.2 skrll 496 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 497 1.3.2.2 skrll 498 1.3.2.2 skrll desc = ismt_alloc_desc(sc); 499 1.3.2.2 skrll desc->wr_len_cmd = 2; 500 1.3.2.2 skrll sc->dma_buffer[0] = cmd; 501 1.3.2.2 skrll sc->dma_buffer[1] = byte; 502 1.3.2.2 skrll 503 1.3.2.2 skrll return (ismt_submit(sc, desc, slave, 0, flags)); 504 1.3.2.2 skrll } 505 1.3.2.2 skrll 506 1.3.2.2 skrll static int 507 1.3.2.2 skrll ismt_writew(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, uint8_t cmd, 508 1.3.2.2 skrll uint16_t word, int flags) 509 1.3.2.2 skrll { 510 1.3.2.2 skrll struct ismt_desc *desc; 511 1.3.2.2 skrll 512 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 513 1.3.2.2 skrll 514 1.3.2.2 skrll desc = ismt_alloc_desc(sc); 515 1.3.2.2 skrll desc->wr_len_cmd = 3; 516 1.3.2.2 skrll sc->dma_buffer[0] = cmd; 517 1.3.2.2 skrll sc->dma_buffer[1] = word & 0xFF; 518 1.3.2.2 skrll sc->dma_buffer[2] = word >> 8; 519 1.3.2.2 skrll 520 1.3.2.2 skrll return (ismt_submit(sc, desc, slave, 0, flags)); 521 1.3.2.2 skrll } 522 1.3.2.2 skrll 523 1.3.2.2 skrll static int 524 1.3.2.2 skrll ismt_readb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, 525 1.3.2.2 skrll int flags) 526 1.3.2.2 skrll { 527 1.3.2.2 skrll struct ismt_desc *desc; 528 1.3.2.2 skrll int err; 529 1.3.2.2 skrll 530 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 531 1.3.2.2 skrll 532 1.3.2.2 skrll desc = ismt_alloc_desc(sc); 533 1.3.2.2 skrll desc->control = ISMT_DESC_CWRL; 534 1.3.2.2 skrll desc->wr_len_cmd = cmd; 535 1.3.2.2 skrll desc->rd_len = 1; 536 1.3.2.2 skrll 537 1.3.2.2 skrll err = ismt_submit(sc, desc, slave, 1, flags); 538 1.3.2.2 skrll 539 1.3.2.2 skrll if (err != 0) 540 1.3.2.2 skrll return (err); 541 1.3.2.2 skrll 542 1.3.2.2 skrll return sc->dma_buffer[0]; 543 1.3.2.2 skrll } 544 1.3.2.2 skrll 545 1.3.2.2 skrll static int 546 1.3.2.2 skrll ismt_readw(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, 547 1.3.2.2 skrll int flags) 548 1.3.2.2 skrll { 549 1.3.2.2 skrll struct ismt_desc *desc; 550 1.3.2.2 skrll uint16_t word; 551 1.3.2.2 skrll int err; 552 1.3.2.2 skrll 553 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 554 1.3.2.2 skrll 555 1.3.2.2 skrll desc = ismt_alloc_desc(sc); 556 1.3.2.2 skrll desc->control = ISMT_DESC_CWRL; 557 1.3.2.2 skrll desc->wr_len_cmd = cmd; 558 1.3.2.2 skrll desc->rd_len = 2; 559 1.3.2.2 skrll 560 1.3.2.2 skrll err = ismt_submit(sc, desc, slave, 1, flags); 561 1.3.2.2 skrll 562 1.3.2.2 skrll if (err != 0) 563 1.3.2.2 skrll return (err); 564 1.3.2.2 skrll 565 1.3.2.2 skrll word = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); 566 1.3.2.2 skrll 567 1.3.2.2 skrll return word; 568 1.3.2.2 skrll } 569 1.3.2.2 skrll 570 1.3.2.2 skrll #if 0 571 1.3.2.2 skrll static int 572 1.3.2.2 skrll ismt_pcall(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, 573 1.3.2.2 skrll uint16_t sdata, uint16_t *rdata, int flags) 574 1.3.2.2 skrll { 575 1.3.2.2 skrll struct ismt_desc *desc; 576 1.3.2.2 skrll int err; 577 1.3.2.2 skrll 578 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 579 1.3.2.2 skrll 580 1.3.2.2 skrll desc = ismt_alloc_desc(sc); 581 1.3.2.2 skrll desc->wr_len_cmd = 3; 582 1.3.2.2 skrll desc->rd_len = 2; 583 1.3.2.2 skrll sc->dma_buffer[0] = cmd; 584 1.3.2.2 skrll sc->dma_buffer[1] = sdata & 0xff; 585 1.3.2.2 skrll sc->dma_buffer[2] = sdata >> 8; 586 1.3.2.2 skrll 587 1.3.2.2 skrll err = ismt_submit(sc, desc, slave, 0, flags); 588 1.3.2.2 skrll 589 1.3.2.2 skrll if (err != 0) 590 1.3.2.2 skrll return (err); 591 1.3.2.2 skrll 592 1.3.2.2 skrll *rdata = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); 593 1.3.2.2 skrll 594 1.3.2.2 skrll return (err); 595 1.3.2.2 skrll } 596 1.3.2.2 skrll 597 1.3.2.2 skrll static int 598 1.3.2.2 skrll ismt_bwrite(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, 599 1.3.2.2 skrll u_char count, char *buf, int flags) 600 1.3.2.2 skrll { 601 1.3.2.2 skrll struct ismt_desc *desc; 602 1.3.2.2 skrll 603 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 604 1.3.2.2 skrll 605 1.3.2.2 skrll if (count == 0 || count > ISMT_MAX_BLOCK_SIZE) 606 1.3.2.2 skrll return -1; 607 1.3.2.2 skrll 608 1.3.2.2 skrll desc = ismt_alloc_desc(sc); 609 1.3.2.2 skrll desc->control = ISMT_DESC_I2C; 610 1.3.2.2 skrll desc->wr_len_cmd = count + 1; 611 1.3.2.2 skrll sc->dma_buffer[0] = cmd; 612 1.3.2.2 skrll memcpy(&sc->dma_buffer[1], buf, count); 613 1.3.2.2 skrll 614 1.3.2.2 skrll return (ismt_submit(sc, desc, slave, 0, flags)); 615 1.3.2.2 skrll } 616 1.3.2.2 skrll 617 1.3.2.2 skrll static int 618 1.3.2.2 skrll ismt_bread(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, 619 1.3.2.2 skrll u_char *count, char *buf, int flags) 620 1.3.2.2 skrll { 621 1.3.2.2 skrll struct ismt_desc *desc; 622 1.3.2.2 skrll int err; 623 1.3.2.2 skrll 624 1.3.2.2 skrll ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 625 1.3.2.2 skrll 626 1.3.2.2 skrll if (*count == 0 || *count > ISMT_MAX_BLOCK_SIZE) 627 1.3.2.2 skrll return -1; 628 1.3.2.2 skrll 629 1.3.2.2 skrll desc = ismt_alloc_desc(sc); 630 1.3.2.2 skrll desc->control = ISMT_DESC_I2C | ISMT_DESC_CWRL; 631 1.3.2.2 skrll desc->wr_len_cmd = cmd; 632 1.3.2.2 skrll desc->rd_len = *count; 633 1.3.2.2 skrll 634 1.3.2.2 skrll err = ismt_submit(sc, desc, slave, 0, flags); 635 1.3.2.2 skrll 636 1.3.2.2 skrll if (err != 0) 637 1.3.2.2 skrll return (err); 638 1.3.2.2 skrll 639 1.3.2.2 skrll memcpy(buf, sc->dma_buffer, desc->rxbytes); 640 1.3.2.2 skrll *count = desc->rxbytes; 641 1.3.2.2 skrll 642 1.3.2.2 skrll return (err); 643 1.3.2.2 skrll } 644 1.3.2.2 skrll #endif 645 1.3.2.2 skrll 646 1.3.2.2 skrll static int 647 1.3.2.2 skrll ismt_detach(device_t self, int flags) 648 1.3.2.2 skrll { 649 1.3.2.2 skrll struct ismt_softc *sc; 650 1.3.2.2 skrll int rv = 0; 651 1.3.2.2 skrll 652 1.3.2.2 skrll ISMT_DEBUG(self, "%s\n", __func__); 653 1.3.2.2 skrll sc = device_private(self); 654 1.3.2.2 skrll if (sc->smbdev != NULL) { 655 1.3.2.2 skrll rv = config_detach(sc->smbdev, flags); 656 1.3.2.2 skrll if (rv != 0) 657 1.3.2.2 skrll return rv; 658 1.3.2.2 skrll } 659 1.3.2.2 skrll if (sc->sc_ih != NULL) { 660 1.3.2.2 skrll pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 661 1.3.2.2 skrll sc->sc_ih = NULL; 662 1.3.2.2 skrll } 663 1.3.2.2 skrll if (sc->sc_pihp != NULL) { 664 1.3.2.2 skrll pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 665 1.3.2.2 skrll sc->sc_pihp = NULL; 666 1.3.2.2 skrll } 667 1.3.2.2 skrll 668 1.3.2.2 skrll bus_dmamap_unload(sc->desc_dma_tag, sc->desc_dma_map); 669 1.3.2.2 skrll bus_dmamap_unload(sc->dma_buffer_dma_tag, sc->dma_buffer_dma_map); 670 1.3.2.2 skrll 671 1.3.2.2 skrll bus_dmamem_free(sc->desc_dma_tag, &sc->desc_dma_seg, sc->desc_rseg); 672 1.3.2.2 skrll bus_dmamem_free(sc->dma_buffer_dma_tag, &sc->dma_buffer_dma_seg, 673 1.3.2.2 skrll sc->dma_buffer_rseg); 674 1.3.2.2 skrll 675 1.3.2.2 skrll if (sc->mmio_size) 676 1.3.2.2 skrll bus_space_unmap(sc->mmio_tag, sc->mmio_handle, sc->mmio_size); 677 1.3.2.2 skrll 678 1.3.2.2 skrll mutex_destroy(&sc->sc_i2c_mutex); 679 1.3.2.2 skrll return rv; 680 1.3.2.2 skrll } 681 1.3.2.2 skrll 682 1.3.2.2 skrll static void 683 1.3.2.2 skrll ismt_attach(device_t parent, device_t self, void *aux) 684 1.3.2.2 skrll { 685 1.3.2.2 skrll struct ismt_softc *sc = device_private(self); 686 1.3.2.2 skrll struct pci_attach_args *pa = aux; 687 1.3.2.2 skrll const char *intrstr = NULL; 688 1.3.2.2 skrll char intrbuf[PCI_INTRSTR_LEN]; 689 1.3.2.2 skrll pcireg_t reg; 690 1.3.2.2 skrll int val; 691 1.3.2.2 skrll 692 1.3.2.2 skrll sc->pcidev = self; 693 1.3.2.2 skrll sc->sc_pc = pa->pa_pc; 694 1.3.2.2 skrll sc->sc_pcitag = pa->pa_tag; 695 1.3.2.2 skrll 696 1.3.2.2 skrll /* Enable busmastering */ 697 1.3.2.2 skrll reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 698 1.3.2.2 skrll reg |= PCI_COMMAND_MASTER_ENABLE; 699 1.3.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 700 1.3.2.2 skrll 701 1.3.2.2 skrll pci_aprint_devinfo(pa, NULL); 702 1.3.2.2 skrll 703 1.3.2.2 skrll /* Map mem space */ 704 1.3.2.2 skrll if (pci_mapreg_map(pa, PCI_BAR0, PCI_MAPREG_TYPE_MEM, 0, 705 1.3.2.2 skrll &sc->mmio_tag, &sc->mmio_handle, NULL, &sc->mmio_size)) { 706 1.3.2.2 skrll aprint_error_dev(self, "can't map mem space\n"); 707 1.3.2.2 skrll goto fail; 708 1.3.2.2 skrll } 709 1.3.2.2 skrll 710 1.3.2.2 skrll if (pci_dma64_available(pa)) { 711 1.3.2.2 skrll sc->desc_dma_tag = pa->pa_dmat64; 712 1.3.2.2 skrll sc->dma_buffer_dma_tag = pa->pa_dmat64; 713 1.3.2.2 skrll } else { 714 1.3.2.2 skrll sc->desc_dma_tag = pa->pa_dmat; 715 1.3.2.2 skrll sc->dma_buffer_dma_tag = pa->pa_dmat; 716 1.3.2.2 skrll } 717 1.3.2.2 skrll bus_dmamem_alloc(sc->desc_dma_tag, DESC_SIZE, PAGE_SIZE, 0, 718 1.3.2.2 skrll &sc->desc_dma_seg, ISMT_DESC_ENTRIES, &sc->desc_rseg, 719 1.3.2.2 skrll BUS_DMA_WAITOK); 720 1.3.2.2 skrll bus_dmamem_alloc(sc->dma_buffer_dma_tag, DMA_BUFFER_SIZE, PAGE_SIZE, 0, 721 1.3.2.2 skrll &sc->dma_buffer_dma_seg, 1, &sc->dma_buffer_rseg, BUS_DMA_WAITOK); 722 1.3.2.2 skrll 723 1.3.2.2 skrll bus_dmamem_map(sc->desc_dma_tag, &sc->desc_dma_seg, 724 1.3.2.2 skrll sc->desc_rseg, DESC_SIZE, (void **)&sc->desc, BUS_DMA_COHERENT); 725 1.3.2.2 skrll bus_dmamem_map(sc->dma_buffer_dma_tag, &sc->dma_buffer_dma_seg, 726 1.3.2.2 skrll sc->dma_buffer_rseg, DMA_BUFFER_SIZE, (void **)&sc->dma_buffer, 727 1.3.2.2 skrll BUS_DMA_COHERENT); 728 1.3.2.2 skrll 729 1.3.2.2 skrll bus_dmamap_create(sc->desc_dma_tag, DESC_SIZE, 1, 730 1.3.2.2 skrll DESC_SIZE, 0, 0, &sc->desc_dma_map); 731 1.3.2.2 skrll bus_dmamap_create(sc->dma_buffer_dma_tag, DMA_BUFFER_SIZE, 1, 732 1.3.2.2 skrll DMA_BUFFER_SIZE, 0, 0, &sc->dma_buffer_dma_map); 733 1.3.2.2 skrll 734 1.3.2.2 skrll bus_dmamap_load(sc->desc_dma_tag, 735 1.3.2.2 skrll sc->desc_dma_map, sc->desc, DESC_SIZE, NULL, 0); 736 1.3.2.2 skrll bus_dmamap_load(sc->dma_buffer_dma_tag, 737 1.3.2.2 skrll sc->dma_buffer_dma_map, sc->dma_buffer, DMA_BUFFER_SIZE, 738 1.3.2.2 skrll NULL, 0); 739 1.3.2.2 skrll 740 1.3.2.2 skrll bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDBA, 741 1.3.2.2 skrll ISMT_LOW(sc->desc_dma_map->dm_segs[0].ds_addr)); 742 1.3.2.2 skrll bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDBA + 4, 743 1.3.2.2 skrll ISMT_HIGH(sc->desc_dma_map->dm_segs[0].ds_addr)); 744 1.3.2.2 skrll 745 1.3.2.2 skrll /* initialize the Master Control Register (MCTRL) */ 746 1.3.2.2 skrll bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL, 747 1.3.2.2 skrll ISMT_MCTRL_MEIE); 748 1.3.2.2 skrll 749 1.3.2.2 skrll /* initialize the Master Status Register (MSTS) */ 750 1.3.2.2 skrll bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MSTS, 0); 751 1.3.2.2 skrll 752 1.3.2.2 skrll /* initialize the Master Descriptor Size (MDS) */ 753 1.3.2.2 skrll val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDS); 754 1.3.2.2 skrll val &= ~ISMT_MDS_MASK; 755 1.3.2.2 skrll val |= (ISMT_DESC_ENTRIES - 1); 756 1.3.2.2 skrll bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDS, val); 757 1.3.2.2 skrll 758 1.3.2.2 skrll if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 759 1.3.2.2 skrll aprint_error_dev(self, "couldn't map interrupt\n"); 760 1.3.2.2 skrll return; 761 1.3.2.2 skrll } 762 1.3.2.2 skrll intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], intrbuf, 763 1.3.2.2 skrll sizeof(intrbuf)); 764 1.3.2.4 skrll sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, sc->sc_pihp[0], 765 1.3.2.4 skrll IPL_BIO, ismt_intr, sc, device_xname(self)); 766 1.3.2.2 skrll if (sc->sc_ih == NULL) { 767 1.3.2.2 skrll aprint_error_dev(sc->pcidev, "unable to establish %s\n", 768 1.3.2.3 skrll (pci_intr_type(pa->pa_pc, sc->sc_pihp[0]) 769 1.3.2.2 skrll == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx"); 770 1.3.2.2 skrll /* Polling */ 771 1.3.2.2 skrll } 772 1.3.2.2 skrll 773 1.3.2.3 skrll if (pci_intr_type(pa->pa_pc, sc->sc_pihp[0]) == PCI_INTR_TYPE_MSI) 774 1.3.2.2 skrll sc->using_msi = 1; 775 1.3.2.2 skrll 776 1.3.2.2 skrll aprint_normal_dev(sc->pcidev, "interrupting at %s\n", intrstr); 777 1.3.2.2 skrll 778 1.3.2.2 skrll sc->smbdev = NULL; 779 1.3.2.2 skrll mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 780 1.3.2.2 skrll if (!pmf_device_register(self, NULL, NULL)) 781 1.3.2.2 skrll aprint_error_dev(self, "couldn't establish power handler\n"); 782 1.3.2.2 skrll 783 1.3.2.2 skrll config_interrupts(self, ismt_config_interrupts); 784 1.3.2.2 skrll return; 785 1.3.2.2 skrll 786 1.3.2.2 skrll fail: 787 1.3.2.2 skrll ismt_detach(sc->pcidev, 0); 788 1.3.2.2 skrll 789 1.3.2.2 skrll return; 790 1.3.2.2 skrll } 791 1.3.2.2 skrll 792 1.3.2.2 skrll static int 793 1.3.2.2 skrll ismt_match(device_t parent, cfdata_t match, void *aux) 794 1.3.2.2 skrll { 795 1.3.2.2 skrll struct pci_attach_args *pa = aux; 796 1.3.2.2 skrll 797 1.3.2.2 skrll if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 798 1.3.2.2 skrll return 0; 799 1.3.2.2 skrll 800 1.3.2.2 skrll switch (PCI_PRODUCT(pa->pa_id)) { 801 1.3.2.2 skrll case PCI_PRODUCT_INTEL_S1200_SMBUS_0: 802 1.3.2.2 skrll case PCI_PRODUCT_INTEL_S1200_SMBUS_1: 803 1.3.2.2 skrll case PCI_PRODUCT_INTEL_C2000_SMBUS: 804 1.3.2.4 skrll case PCI_PRODUCT_INTEL_C3K_SMBUS: 805 1.3.2.2 skrll break; 806 1.3.2.2 skrll default: 807 1.3.2.2 skrll return 0; 808 1.3.2.2 skrll } 809 1.3.2.2 skrll 810 1.3.2.2 skrll return 1; 811 1.3.2.2 skrll } 812 1.3.2.2 skrll 813 1.3.2.2 skrll static int 814 1.3.2.2 skrll ismt_rescan(device_t self, const char *ifattr, const int *flags) 815 1.3.2.2 skrll { 816 1.3.2.2 skrll struct ismt_softc *sc = device_private(self); 817 1.3.2.2 skrll struct i2cbus_attach_args iba; 818 1.3.2.2 skrll 819 1.3.2.2 skrll if (!ifattr_match(ifattr, "i2cbus")) 820 1.3.2.2 skrll return 0; 821 1.3.2.2 skrll 822 1.3.2.2 skrll if (sc->smbdev) 823 1.3.2.2 skrll return 0; 824 1.3.2.2 skrll 825 1.3.2.2 skrll /* Attach I2C bus */ 826 1.3.2.2 skrll sc->sc_i2c_tag.ic_cookie = sc; 827 1.3.2.2 skrll sc->sc_i2c_tag.ic_acquire_bus = ismt_i2c_acquire_bus; 828 1.3.2.2 skrll sc->sc_i2c_tag.ic_release_bus = ismt_i2c_release_bus; 829 1.3.2.2 skrll sc->sc_i2c_tag.ic_exec = ismt_i2c_exec; 830 1.3.2.2 skrll 831 1.3.2.2 skrll memset(&iba, 0, sizeof(iba)); 832 1.3.2.2 skrll iba.iba_type = I2C_TYPE_SMBUS; 833 1.3.2.2 skrll iba.iba_tag = &sc->sc_i2c_tag; 834 1.3.2.2 skrll sc->smbdev = config_found_ia(self, ifattr, &iba, iicbus_print); 835 1.3.2.2 skrll 836 1.3.2.2 skrll return 0; 837 1.3.2.2 skrll } 838 1.3.2.2 skrll 839 1.3.2.2 skrll static void 840 1.3.2.2 skrll ismt_config_interrupts(device_t self) 841 1.3.2.2 skrll { 842 1.3.2.2 skrll int flags = 0; 843 1.3.2.2 skrll 844 1.3.2.2 skrll ismt_rescan(self, "i2cbus", &flags); 845 1.3.2.2 skrll } 846 1.3.2.2 skrll 847 1.3.2.2 skrll static void 848 1.3.2.2 skrll ismt_chdet(device_t self, device_t child) 849 1.3.2.2 skrll { 850 1.3.2.2 skrll struct ismt_softc *sc = device_private(self); 851 1.3.2.2 skrll 852 1.3.2.2 skrll if (sc->smbdev == child) 853 1.3.2.2 skrll sc->smbdev = NULL; 854 1.3.2.2 skrll 855 1.3.2.2 skrll } 856 1.3.2.2 skrll 857 1.3.2.2 skrll MODULE(MODULE_CLASS_DRIVER, ismt, "pci"); 858 1.3.2.2 skrll 859 1.3.2.2 skrll #ifdef _MODULE 860 1.3.2.2 skrll #include "ioconf.c" 861 1.3.2.2 skrll #endif 862 1.3.2.2 skrll 863 1.3.2.2 skrll static int 864 1.3.2.2 skrll ismt_modcmd(modcmd_t cmd, void *opaque) 865 1.3.2.2 skrll { 866 1.3.2.2 skrll int error = 0; 867 1.3.2.2 skrll 868 1.3.2.2 skrll switch (cmd) { 869 1.3.2.2 skrll case MODULE_CMD_INIT: 870 1.3.2.2 skrll #ifdef _MODULE 871 1.3.2.2 skrll error = config_init_component(cfdriver_ioconf_ismt, 872 1.3.2.2 skrll cfattach_ioconf_ismt, cfdata_ioconf_ismt); 873 1.3.2.2 skrll #endif 874 1.3.2.2 skrll return error; 875 1.3.2.2 skrll case MODULE_CMD_FINI: 876 1.3.2.2 skrll #ifdef _MODULE 877 1.3.2.2 skrll error = config_fini_component(cfdriver_ioconf_ismt, 878 1.3.2.2 skrll cfattach_ioconf_ismt, cfdata_ioconf_ismt); 879 1.3.2.2 skrll #endif 880 1.3.2.2 skrll return error; 881 1.3.2.2 skrll default: 882 1.3.2.2 skrll return ENOTTY; 883 1.3.2.2 skrll } 884 1.3.2.2 skrll } 885
Indexes created Thu Oct 16 14:10:15 GMT 2025