ismt.c revision 1.7
1 /*- 2 * Copyright (c) 2016 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Masanobu SAITOH. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /*- 31 * Copyright (C) 2014 Intel Corporation 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. Neither the name of Intel Corporation nor the names of its 43 * contributors may be used to endorse or promote products derived from 44 * this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 #if 0 61 __FBSDID("$FreeBSD: head/sys/dev/ismt/ismt.c 266474 2014-05-20 19:55:06Z jimharris $"); 62 #endif 63 __KERNEL_RCSID(0, "$NetBSD: ismt.c,v 1.7 2019/12/22 23:23:32 thorpej Exp $"); 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/device.h> 68 #include <sys/errno.h> 69 #include <sys/kernel.h> 70 #include <sys/module.h> 71 #include <sys/proc.h> 72 73 #include <sys/bus.h> 74 75 #include <dev/pci/pcidevs.h> 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 79 #include <dev/i2c/i2cvar.h> 80 81 #define ISMT_DESC_ENTRIES 32 82 83 /* Hardware Descriptor Constants - Control Field */ 84 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ 85 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ 86 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ 87 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ 88 #define ISMT_DESC_I2C 0x20 /* I2C Enable */ 89 #define ISMT_DESC_INT 0x40 /* Interrupt */ 90 #define ISMT_DESC_SOE 0x80 /* Stop On Error */ 91 92 /* Hardware Descriptor Constants - Status Field */ 93 #define ISMT_DESC_SCS 0x01 /* Success */ 94 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ 95 #define ISMT_DESC_NAK 0x08 /* NAK Received */ 96 #define ISMT_DESC_CRC 0x10 /* CRC Error */ 97 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ 98 #define ISMT_DESC_COL 0x40 /* Collisions */ 99 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ 100 101 /* Macros */ 102 #define ISMT_DESC_ADDR_RW(addr, is_read) (((addr) << 1) | (is_read)) 103 104 /* iSMT General Register address offsets (SMBBAR + <addr>) */ 105 #define ISMT_GR_GCTRL 0x000 /* General Control */ 106 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ 107 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ 108 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ 109 #define ISMT_GR_ERRSTS 0x018 /* Error Status */ 110 #define ISMT_GR_ERRINFO 0x01c /* Error Information */ 111 112 /* iSMT Master Registers */ 113 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ 114 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ 115 #define ISMT_MSTR_MSTS 0x10c /* Master Status */ 116 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ 117 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ 118 119 /* iSMT Miscellaneous Registers */ 120 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ 121 122 /* General Control Register (GCTRL) bit definitions */ 123 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ 124 #define ISMT_GCTRL_KILL 0x08 /* Kill */ 125 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ 126 127 /* Master Control Register (MCTRL) bit definitions */ 128 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ 129 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ 130 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ 131 132 /* Master Status Register (MSTS) bit definitions */ 133 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ 134 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ 135 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ 136 #define ISMT_MSTS_IP 0x01 /* In Progress */ 137 138 /* Master Descriptor Size (MDS) bit definitions */ 139 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ 140 141 /* SMBus PHY Global Timing Register (SPGT) bit definitions */ 142 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ 143 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ 144 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ 145 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ 146 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ 147 148 /* MSI Control Register (MSICTL) bit definitions */ 149 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ 150 151 #define ISMT_MAX_BLOCK_SIZE 32 /* per SMBus spec */ 152 153 #define ISMT_INTR_TIMEOUT (hz / 50) /* 0.02s */ 154 #define ISMT_POLL_DELAY 100 /* 100usec */ 155 #define ISMT_POLL_COUNT 200 /* 100usec * 200 = 0.02s */ 156 157 //#define ISMT_DEBUG aprint_debug_dev 158 #ifndef ISMT_DEBUG 159 #define ISMT_DEBUG(...) 160 #endif 161 162 #define ISMT_LOW(a) ((a) & 0xFFFFFFFFULL) 163 #define ISMT_HIGH(a) (((uint64_t)(a) >> 32) & 0xFFFFFFFFFULL) 164 165 /* iSMT Hardware Descriptor */ 166 struct ismt_desc { 167 uint8_t tgtaddr_rw; /* target address & r/w bit */ 168 uint8_t wr_len_cmd; /* write length in bytes or a command */ 169 uint8_t rd_len; /* read length */ 170 uint8_t control; /* control bits */ 171 uint8_t status; /* status bits */ 172 uint8_t retry; /* collision retry and retry count */ 173 uint8_t rxbytes; /* received bytes */ 174 uint8_t txbytes; /* transmitted bytes */ 175 uint32_t dptr_low; /* lower 32 bit of the data pointer */ 176 uint32_t dptr_high; /* upper 32 bit of the data pointer */ 177 } __packed; 178 179 #define DESC_SIZE (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)) 180 181 #define DMA_BUFFER_SIZE 64 182 183 struct ismt_softc { 184 device_t pcidev; 185 device_t smbdev; 186 187 struct i2c_controller sc_i2c_tag; 188 189 pci_chipset_tag_t sc_pc; 190 pcitag_t sc_pcitag; 191 pci_intr_handle_t *sc_pihp; 192 void *sc_ih; 193 194 bus_space_tag_t mmio_tag; 195 bus_space_handle_t mmio_handle; 196 bus_size_t mmio_size; 197 198 uint8_t head; 199 200 struct ismt_desc *desc; 201 bus_dma_tag_t desc_dma_tag; 202 bus_dmamap_t desc_dma_map; 203 bus_dma_segment_t desc_dma_seg; 204 int desc_rseg; 205 206 uint8_t *dma_buffer; 207 bus_dma_tag_t dma_buffer_dma_tag; 208 bus_dmamap_t dma_buffer_dma_map; 209 bus_dma_segment_t dma_buffer_dma_seg; 210 int dma_buffer_rseg; 211 212 uint8_t using_msi; 213 }; 214 215 static int ismt_intr(void *); 216 static int ismt_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 217 size_t, void *, size_t, int); 218 static struct ismt_desc *ismt_alloc_desc(struct ismt_softc *); 219 static int ismt_submit(struct ismt_softc *, struct ismt_desc *, 220 i2c_addr_t, uint8_t, int); 221 static int ismt_quick(struct ismt_softc *, i2c_addr_t, i2c_op_t, int); 222 static int ismt_sendb(struct ismt_softc *, i2c_addr_t, i2c_op_t, char, 223 int); 224 static int ismt_recvb(struct ismt_softc *, i2c_addr_t, i2c_op_t, int); 225 static int ismt_writeb(struct ismt_softc *, i2c_addr_t, i2c_op_t, uint8_t, 226 char, int); 227 static int ismt_writew(struct ismt_softc *, i2c_addr_t, i2c_op_t, uint8_t, 228 uint16_t, int); 229 static int ismt_readb(struct ismt_softc *, i2c_addr_t, i2c_op_t, char, 230 int); 231 static int ismt_readw(struct ismt_softc *, i2c_addr_t, i2c_op_t, char, 232 int); 233 234 static int ismt_match(device_t, cfdata_t, void *); 235 static void ismt_attach(device_t, device_t, void *); 236 static int ismt_detach(device_t, int); 237 static int ismt_rescan(device_t, const char *, const int *); 238 static void ismt_config_interrupts(device_t); 239 static void ismt_chdet(device_t, device_t); 240 241 CFATTACH_DECL3_NEW(ismt, sizeof(struct ismt_softc), 242 ismt_match, ismt_attach, ismt_detach, NULL, ismt_rescan, ismt_chdet, 243 DVF_DETACH_SHUTDOWN); 244 245 static int 246 ismt_intr(void *arg) 247 { 248 struct ismt_softc *sc = arg; 249 uint32_t val; 250 251 val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MSTS); 252 if ((sc->using_msi == 0) 253 && (val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)) == 0) 254 return 0; /* Not for me */ 255 256 ISMT_DEBUG(sc->pcidev, "%s MSTS = 0x%08x\n", __func__, val); 257 258 val |= (ISMT_MSTS_MIS | ISMT_MSTS_MEIS); 259 bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MSTS, val); 260 261 if (sc->using_msi) 262 wakeup(sc); 263 264 return 1; 265 } 266 267 static int 268 ismt_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 269 const void *cmd, size_t cmdlen, void *buf, size_t buflen, int flags) 270 { 271 struct ismt_softc *sc = cookie; 272 uint8_t *p = buf; 273 int rv; 274 275 ISMT_DEBUG(sc->pcidev, "exec: op %d, addr 0x%02x, cmdlen %zu, " 276 " buflen %zu, flags 0x%02x\n", op, addr, cmdlen, buflen, flags); 277 278 if ((cmdlen == 0) && (buflen == 0)) 279 return ismt_quick(sc, addr, op, flags); 280 281 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 282 rv = ismt_recvb(sc, addr, op, flags); 283 if (rv == -1) 284 return -1; 285 *p = (uint8_t)rv; 286 return 0; 287 } 288 289 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 290 rv = ismt_readb(sc, addr, op, *(const uint8_t*)cmd, flags); 291 if (rv == -1) 292 return -1; 293 *p = (uint8_t)rv; 294 return 0; 295 } 296 297 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 2)) { 298 rv = ismt_readw(sc, addr, op, *(const uint8_t*)cmd, flags); 299 if (rv == -1) 300 return -1; 301 *(uint16_t *)p = (uint16_t)rv; 302 return 0; 303 } 304 305 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) 306 return ismt_sendb(sc, addr, op, *(uint8_t*)buf, flags); 307 308 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) 309 return ismt_writeb(sc, addr, op, *(const uint8_t*)cmd, 310 *(uint8_t*)buf, flags); 311 312 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 2)) 313 return ismt_writew(sc, addr, op, 314 *(const uint8_t*)cmd, *((uint16_t *)buf), flags); 315 316 return -1; 317 } 318 319 static struct ismt_desc * 320 ismt_alloc_desc(struct ismt_softc *sc) 321 { 322 struct ismt_desc *desc; 323 324 desc = &sc->desc[sc->head++]; 325 if (sc->head == ISMT_DESC_ENTRIES) 326 sc->head = 0; 327 328 memset(desc, 0, sizeof(*desc)); 329 330 return (desc); 331 } 332 333 static int 334 ismt_submit(struct ismt_softc *sc, struct ismt_desc *desc, i2c_addr_t slave, 335 uint8_t is_read, int flags) 336 { 337 uint32_t err, fmhp, val; 338 int timeout, i; 339 340 if (sc->using_msi == 0) 341 flags |= I2C_F_POLL; 342 desc->control |= ISMT_DESC_FAIR; 343 if ((flags & I2C_F_POLL) == 0) 344 desc->control |= ISMT_DESC_INT; 345 346 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(slave, is_read); 347 desc->dptr_low = ISMT_LOW(sc->dma_buffer_dma_map->dm_segs[0].ds_addr); 348 desc->dptr_high = ISMT_HIGH(sc->dma_buffer_dma_map->dm_segs[0].ds_addr); 349 350 bus_dmamap_sync(sc->desc_dma_tag, sc->desc_dma_map, 351 desc - &sc->desc[0], sizeof(struct ismt_desc), 352 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 353 354 fmhp = sc->head << 16; 355 val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL); 356 val &= ~ISMT_MCTRL_FMHP; 357 val |= fmhp; 358 bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL, val); 359 360 /* set the start bit */ 361 val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL); 362 val |= ISMT_MCTRL_SS; 363 bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL, val); 364 365 i = 0; 366 if ((flags & I2C_F_POLL) == 0) { 367 timeout = ISMT_INTR_TIMEOUT; 368 if (timeout == 0) 369 timeout = 1; 370 err = tsleep(sc, PWAIT, "ismt_wait", timeout); 371 if (err != 0) { 372 ISMT_DEBUG(sc->pcidev, "%s timeout\n", __func__); 373 return -1; 374 } 375 } else { 376 /* Polling */ 377 for (i = 0; i < ISMT_POLL_COUNT; i++) { 378 val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, 379 ISMT_MSTR_MSTS); 380 if ((val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)) != 0) { 381 ismt_intr(sc); 382 err = 0; 383 break; 384 } 385 delay(ISMT_POLL_DELAY); 386 } 387 if (i >= ISMT_POLL_COUNT) { 388 ISMT_DEBUG(sc->pcidev, "%s polling timeout. " 389 "MSTS = %08x\n", __func__, val); 390 return -1; 391 } 392 } 393 394 bus_dmamap_sync(sc->desc_dma_tag, sc->desc_dma_map, 395 desc - &sc->desc[0], sizeof(struct ismt_desc), 396 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 397 ISMT_DEBUG(sc->pcidev, "%s status=0x%02x\n", __func__, desc->status); 398 399 if (desc->status & ISMT_DESC_SCS) 400 return 0; 401 402 if (desc->status & ISMT_DESC_NAK) 403 return -1; 404 405 if (desc->status & ISMT_DESC_CRC) 406 return -1; 407 408 if (desc->status & ISMT_DESC_COL) 409 return -1; 410 411 if (desc->status & ISMT_DESC_LPR) 412 return -1; 413 414 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) 415 return -1; 416 417 return -1; 418 } 419 420 static int 421 ismt_quick(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, int flags) 422 { 423 struct ismt_desc *desc; 424 int is_read; 425 426 ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 427 428 desc = ismt_alloc_desc(sc); 429 is_read = I2C_OP_READ_P(op); 430 return (ismt_submit(sc, desc, slave, is_read, flags)); 431 } 432 433 static int 434 ismt_sendb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char byte, 435 int flags) 436 { 437 struct ismt_desc *desc; 438 439 ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 440 441 desc = ismt_alloc_desc(sc); 442 desc->control = ISMT_DESC_CWRL; 443 desc->wr_len_cmd = byte; 444 445 return (ismt_submit(sc, desc, slave, 0, flags)); 446 } 447 448 static int 449 ismt_recvb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, int flags) 450 { 451 struct ismt_desc *desc; 452 int err; 453 454 ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 455 456 desc = ismt_alloc_desc(sc); 457 desc->rd_len = 1; 458 459 err = ismt_submit(sc, desc, slave, 1, flags); 460 461 if (err != 0) 462 return (err); 463 464 return sc->dma_buffer[0]; 465 } 466 467 static int 468 ismt_writeb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, uint8_t cmd, 469 char byte, int flags) 470 { 471 struct ismt_desc *desc; 472 473 ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 474 475 desc = ismt_alloc_desc(sc); 476 desc->wr_len_cmd = 2; 477 sc->dma_buffer[0] = cmd; 478 sc->dma_buffer[1] = byte; 479 480 return (ismt_submit(sc, desc, slave, 0, flags)); 481 } 482 483 static int 484 ismt_writew(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, uint8_t cmd, 485 uint16_t word, int flags) 486 { 487 struct ismt_desc *desc; 488 489 ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 490 491 desc = ismt_alloc_desc(sc); 492 desc->wr_len_cmd = 3; 493 sc->dma_buffer[0] = cmd; 494 sc->dma_buffer[1] = word & 0xFF; 495 sc->dma_buffer[2] = word >> 8; 496 497 return (ismt_submit(sc, desc, slave, 0, flags)); 498 } 499 500 static int 501 ismt_readb(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, 502 int flags) 503 { 504 struct ismt_desc *desc; 505 int err; 506 507 ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 508 509 desc = ismt_alloc_desc(sc); 510 desc->control = ISMT_DESC_CWRL; 511 desc->wr_len_cmd = cmd; 512 desc->rd_len = 1; 513 514 err = ismt_submit(sc, desc, slave, 1, flags); 515 516 if (err != 0) 517 return (err); 518 519 return sc->dma_buffer[0]; 520 } 521 522 static int 523 ismt_readw(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, 524 int flags) 525 { 526 struct ismt_desc *desc; 527 uint16_t word; 528 int err; 529 530 ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 531 532 desc = ismt_alloc_desc(sc); 533 desc->control = ISMT_DESC_CWRL; 534 desc->wr_len_cmd = cmd; 535 desc->rd_len = 2; 536 537 err = ismt_submit(sc, desc, slave, 1, flags); 538 539 if (err != 0) 540 return (err); 541 542 word = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); 543 544 return word; 545 } 546 547 #if 0 548 static int 549 ismt_pcall(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, 550 uint16_t sdata, uint16_t *rdata, int flags) 551 { 552 struct ismt_desc *desc; 553 int err; 554 555 ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 556 557 desc = ismt_alloc_desc(sc); 558 desc->wr_len_cmd = 3; 559 desc->rd_len = 2; 560 sc->dma_buffer[0] = cmd; 561 sc->dma_buffer[1] = sdata & 0xff; 562 sc->dma_buffer[2] = sdata >> 8; 563 564 err = ismt_submit(sc, desc, slave, 0, flags); 565 566 if (err != 0) 567 return (err); 568 569 *rdata = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); 570 571 return (err); 572 } 573 574 static int 575 ismt_bwrite(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, 576 u_char count, char *buf, int flags) 577 { 578 struct ismt_desc *desc; 579 580 ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 581 582 if (count == 0 || count > ISMT_MAX_BLOCK_SIZE) 583 return -1; 584 585 desc = ismt_alloc_desc(sc); 586 desc->control = ISMT_DESC_I2C; 587 desc->wr_len_cmd = count + 1; 588 sc->dma_buffer[0] = cmd; 589 memcpy(&sc->dma_buffer[1], buf, count); 590 591 return (ismt_submit(sc, desc, slave, 0, flags)); 592 } 593 594 static int 595 ismt_bread(struct ismt_softc *sc, i2c_addr_t slave, i2c_op_t op, char cmd, 596 u_char *count, char *buf, int flags) 597 { 598 struct ismt_desc *desc; 599 int err; 600 601 ISMT_DEBUG(sc->pcidev, "%s\n", __func__); 602 603 if (*count == 0 || *count > ISMT_MAX_BLOCK_SIZE) 604 return -1; 605 606 desc = ismt_alloc_desc(sc); 607 desc->control = ISMT_DESC_I2C | ISMT_DESC_CWRL; 608 desc->wr_len_cmd = cmd; 609 desc->rd_len = *count; 610 611 err = ismt_submit(sc, desc, slave, 0, flags); 612 613 if (err != 0) 614 return (err); 615 616 memcpy(buf, sc->dma_buffer, desc->rxbytes); 617 *count = desc->rxbytes; 618 619 return (err); 620 } 621 #endif 622 623 static int 624 ismt_detach(device_t self, int flags) 625 { 626 struct ismt_softc *sc; 627 int rv = 0; 628 629 ISMT_DEBUG(self, "%s\n", __func__); 630 sc = device_private(self); 631 if (sc->smbdev != NULL) { 632 rv = config_detach(sc->smbdev, flags); 633 if (rv != 0) 634 return rv; 635 } 636 if (sc->sc_ih != NULL) { 637 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 638 sc->sc_ih = NULL; 639 } 640 if (sc->sc_pihp != NULL) { 641 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 642 sc->sc_pihp = NULL; 643 } 644 645 bus_dmamap_unload(sc->desc_dma_tag, sc->desc_dma_map); 646 bus_dmamap_unload(sc->dma_buffer_dma_tag, sc->dma_buffer_dma_map); 647 648 bus_dmamem_free(sc->desc_dma_tag, &sc->desc_dma_seg, sc->desc_rseg); 649 bus_dmamem_free(sc->dma_buffer_dma_tag, &sc->dma_buffer_dma_seg, 650 sc->dma_buffer_rseg); 651 652 if (sc->mmio_size) 653 bus_space_unmap(sc->mmio_tag, sc->mmio_handle, sc->mmio_size); 654 655 iic_tag_fini(&sc->sc_i2c_tag); 656 return rv; 657 } 658 659 static void 660 ismt_attach(device_t parent, device_t self, void *aux) 661 { 662 struct ismt_softc *sc = device_private(self); 663 struct pci_attach_args *pa = aux; 664 const char *intrstr = NULL; 665 char intrbuf[PCI_INTRSTR_LEN]; 666 pcireg_t reg; 667 int val; 668 669 sc->pcidev = self; 670 sc->sc_pc = pa->pa_pc; 671 sc->sc_pcitag = pa->pa_tag; 672 673 /* Enable busmastering */ 674 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 675 reg |= PCI_COMMAND_MASTER_ENABLE; 676 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg); 677 678 pci_aprint_devinfo(pa, NULL); 679 680 /* Map mem space */ 681 if (pci_mapreg_map(pa, PCI_BAR0, PCI_MAPREG_TYPE_MEM, 0, 682 &sc->mmio_tag, &sc->mmio_handle, NULL, &sc->mmio_size)) { 683 aprint_error_dev(self, "can't map mem space\n"); 684 goto fail; 685 } 686 687 if (pci_dma64_available(pa)) { 688 sc->desc_dma_tag = pa->pa_dmat64; 689 sc->dma_buffer_dma_tag = pa->pa_dmat64; 690 } else { 691 sc->desc_dma_tag = pa->pa_dmat; 692 sc->dma_buffer_dma_tag = pa->pa_dmat; 693 } 694 bus_dmamem_alloc(sc->desc_dma_tag, DESC_SIZE, PAGE_SIZE, 0, 695 &sc->desc_dma_seg, ISMT_DESC_ENTRIES, &sc->desc_rseg, 696 BUS_DMA_WAITOK); 697 bus_dmamem_alloc(sc->dma_buffer_dma_tag, DMA_BUFFER_SIZE, PAGE_SIZE, 0, 698 &sc->dma_buffer_dma_seg, 1, &sc->dma_buffer_rseg, BUS_DMA_WAITOK); 699 700 bus_dmamem_map(sc->desc_dma_tag, &sc->desc_dma_seg, 701 sc->desc_rseg, DESC_SIZE, (void **)&sc->desc, BUS_DMA_COHERENT); 702 bus_dmamem_map(sc->dma_buffer_dma_tag, &sc->dma_buffer_dma_seg, 703 sc->dma_buffer_rseg, DMA_BUFFER_SIZE, (void **)&sc->dma_buffer, 704 BUS_DMA_COHERENT); 705 706 bus_dmamap_create(sc->desc_dma_tag, DESC_SIZE, 1, 707 DESC_SIZE, 0, 0, &sc->desc_dma_map); 708 bus_dmamap_create(sc->dma_buffer_dma_tag, DMA_BUFFER_SIZE, 1, 709 DMA_BUFFER_SIZE, 0, 0, &sc->dma_buffer_dma_map); 710 711 bus_dmamap_load(sc->desc_dma_tag, 712 sc->desc_dma_map, sc->desc, DESC_SIZE, NULL, 0); 713 bus_dmamap_load(sc->dma_buffer_dma_tag, 714 sc->dma_buffer_dma_map, sc->dma_buffer, DMA_BUFFER_SIZE, 715 NULL, 0); 716 717 bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDBA, 718 ISMT_LOW(sc->desc_dma_map->dm_segs[0].ds_addr)); 719 bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDBA + 4, 720 ISMT_HIGH(sc->desc_dma_map->dm_segs[0].ds_addr)); 721 722 /* initialize the Master Control Register (MCTRL) */ 723 bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MCTRL, 724 ISMT_MCTRL_MEIE); 725 726 /* initialize the Master Status Register (MSTS) */ 727 bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MSTS, 0); 728 729 /* initialize the Master Descriptor Size (MDS) */ 730 val = bus_space_read_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDS); 731 val &= ~ISMT_MDS_MASK; 732 val |= (ISMT_DESC_ENTRIES - 1); 733 bus_space_write_4(sc->mmio_tag, sc->mmio_handle, ISMT_MSTR_MDS, val); 734 735 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 736 aprint_error_dev(self, "couldn't map interrupt\n"); 737 return; 738 } 739 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], intrbuf, 740 sizeof(intrbuf)); 741 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, sc->sc_pihp[0], 742 IPL_BIO, ismt_intr, sc, device_xname(self)); 743 if (sc->sc_ih == NULL) { 744 aprint_error_dev(sc->pcidev, "unable to establish %s\n", 745 (pci_intr_type(pa->pa_pc, sc->sc_pihp[0]) 746 == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx"); 747 /* Polling */ 748 } 749 750 if (pci_intr_type(pa->pa_pc, sc->sc_pihp[0]) == PCI_INTR_TYPE_MSI) 751 sc->using_msi = 1; 752 753 aprint_normal_dev(sc->pcidev, "interrupting at %s\n", intrstr); 754 755 sc->smbdev = NULL; 756 if (!pmf_device_register(self, NULL, NULL)) 757 aprint_error_dev(self, "couldn't establish power handler\n"); 758 759 config_interrupts(self, ismt_config_interrupts); 760 return; 761 762 fail: 763 ismt_detach(sc->pcidev, 0); 764 765 return; 766 } 767 768 static int 769 ismt_match(device_t parent, cfdata_t match, void *aux) 770 { 771 struct pci_attach_args *pa = aux; 772 773 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 774 return 0; 775 776 switch (PCI_PRODUCT(pa->pa_id)) { 777 case PCI_PRODUCT_INTEL_S1200_SMBUS_0: 778 case PCI_PRODUCT_INTEL_S1200_SMBUS_1: 779 case PCI_PRODUCT_INTEL_C2000_SMBUS: 780 case PCI_PRODUCT_INTEL_C3K_SMBUS: 781 break; 782 default: 783 return 0; 784 } 785 786 return 1; 787 } 788 789 static int 790 ismt_rescan(device_t self, const char *ifattr, const int *flags) 791 { 792 struct ismt_softc *sc = device_private(self); 793 struct i2cbus_attach_args iba; 794 795 if (!ifattr_match(ifattr, "i2cbus")) 796 return 0; 797 798 if (sc->smbdev) 799 return 0; 800 801 /* Attach I2C bus */ 802 iic_tag_init(&sc->sc_i2c_tag); 803 sc->sc_i2c_tag.ic_cookie = sc; 804 sc->sc_i2c_tag.ic_exec = ismt_i2c_exec; 805 806 memset(&iba, 0, sizeof(iba)); 807 iba.iba_tag = &sc->sc_i2c_tag; 808 sc->smbdev = config_found_ia(self, ifattr, &iba, iicbus_print); 809 810 return 0; 811 } 812 813 static void 814 ismt_config_interrupts(device_t self) 815 { 816 int flags = 0; 817 818 ismt_rescan(self, "i2cbus", &flags); 819 } 820 821 static void 822 ismt_chdet(device_t self, device_t child) 823 { 824 struct ismt_softc *sc = device_private(self); 825 826 if (sc->smbdev == child) 827 sc->smbdev = NULL; 828 829 } 830 831 MODULE(MODULE_CLASS_DRIVER, ismt, "pci"); 832 833 #ifdef _MODULE 834 #include "ioconf.c" 835 #endif 836 837 static int 838 ismt_modcmd(modcmd_t cmd, void *opaque) 839 { 840 int error = 0; 841 842 switch (cmd) { 843 case MODULE_CMD_INIT: 844 #ifdef _MODULE 845 error = config_init_component(cfdriver_ioconf_ismt, 846 cfattach_ioconf_ismt, cfdata_ioconf_ismt); 847 #endif 848 return error; 849 case MODULE_CMD_FINI: 850 #ifdef _MODULE 851 error = config_fini_component(cfdriver_ioconf_ismt, 852 cfattach_ioconf_ismt, cfdata_ioconf_ismt); 853 #endif 854 return error; 855 default: 856 return ENOTTY; 857 } 858 } 859
Indexes created Mon Sep 29 21:09:56 GMT 2025