isp_pci.c revision 1.17.2.1 1 1.17.2.1 cgd /* $NetBSD: isp_pci.c,v 1.17.2.1 1998/11/07 05:55:55 cgd Exp $ */
2 1.1 cgd /*
3 1.1 cgd * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
4 1.1 cgd *
5 1.17.2.1 cgd *---------------------------------------
6 1.17.2.1 cgd * Copyright (c) 1997, 1998 by Matthew Jacob
7 1.17.2.1 cgd * NASA/Ames Research Center
8 1.1 cgd * All rights reserved.
9 1.17.2.1 cgd *---------------------------------------
10 1.1 cgd *
11 1.1 cgd * Redistribution and use in source and binary forms, with or without
12 1.1 cgd * modification, are permitted provided that the following conditions
13 1.1 cgd * are met:
14 1.1 cgd * 1. Redistributions of source code must retain the above copyright
15 1.1 cgd * notice immediately at the beginning of the file, without modification,
16 1.1 cgd * this list of conditions, and the following disclaimer.
17 1.1 cgd * 2. Redistributions in binary form must reproduce the above copyright
18 1.1 cgd * notice, this list of conditions and the following disclaimer in the
19 1.1 cgd * documentation and/or other materials provided with the distribution.
20 1.1 cgd * 3. The name of the author may not be used to endorse or promote products
21 1.1 cgd * derived from this software without specific prior written permission.
22 1.1 cgd *
23 1.1 cgd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 1.1 cgd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 1.1 cgd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 1.1 cgd * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 1.1 cgd * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 1.1 cgd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 1.1 cgd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 1.1 cgd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 1.1 cgd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 1.1 cgd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 1.1 cgd * SUCH DAMAGE.
34 1.17.2.1 cgd *
35 1.1 cgd */
36 1.1 cgd
37 1.17.2.1 cgd #include <dev/ic/isp_netbsd.h>
38 1.17.2.1 cgd #include <dev/microcode/isp/asm_pci.h>
39 1.17.2.1 cgd
40 1.1 cgd #include <dev/pci/pcireg.h>
41 1.1 cgd #include <dev/pci/pcivar.h>
42 1.1 cgd #include <dev/pci/pcidevs.h>
43 1.3 cgd
44 1.1 cgd static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int));
45 1.1 cgd static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t));
46 1.13 thorpej static int isp_pci_mbxdma __P((struct ispsoftc *));
47 1.16 bouyer static int isp_pci_dmasetup __P((struct ispsoftc *, struct scsipi_xfer *,
48 1.13 thorpej ispreq_t *, u_int8_t *, u_int8_t));
49 1.16 bouyer static void isp_pci_dmateardown __P((struct ispsoftc *, struct scsipi_xfer *,
50 1.13 thorpej u_int32_t));
51 1.1 cgd static void isp_pci_reset1 __P((struct ispsoftc *));
52 1.15 mjacob static void isp_pci_dumpregs __P((struct ispsoftc *));
53 1.17.2.1 cgd static int isp_pci_intr __P((void *));
54 1.1 cgd
55 1.1 cgd static struct ispmdvec mdvec = {
56 1.1 cgd isp_pci_rd_reg,
57 1.1 cgd isp_pci_wr_reg,
58 1.1 cgd isp_pci_mbxdma,
59 1.1 cgd isp_pci_dmasetup,
60 1.13 thorpej isp_pci_dmateardown,
61 1.1 cgd NULL,
62 1.1 cgd isp_pci_reset1,
63 1.15 mjacob isp_pci_dumpregs,
64 1.5 cgd ISP_RISC_CODE,
65 1.1 cgd ISP_CODE_LENGTH,
66 1.1 cgd ISP_CODE_ORG,
67 1.15 mjacob ISP_CODE_VERSION,
68 1.17.2.1 cgd BIU_BURST_ENABLE, /* default to 8 byte burst */
69 1.17.2.1 cgd 0
70 1.15 mjacob };
71 1.15 mjacob
72 1.15 mjacob static struct ispmdvec mdvec_2100 = {
73 1.15 mjacob isp_pci_rd_reg,
74 1.15 mjacob isp_pci_wr_reg,
75 1.15 mjacob isp_pci_mbxdma,
76 1.15 mjacob isp_pci_dmasetup,
77 1.15 mjacob isp_pci_dmateardown,
78 1.15 mjacob NULL,
79 1.15 mjacob isp_pci_reset1,
80 1.15 mjacob isp_pci_dumpregs,
81 1.15 mjacob ISP2100_RISC_CODE,
82 1.15 mjacob ISP2100_CODE_LENGTH,
83 1.15 mjacob ISP2100_CODE_ORG,
84 1.15 mjacob ISP2100_CODE_VERSION,
85 1.17.2.1 cgd BIU_BURST_ENABLE, /* default to 8 byte burst */
86 1.17.2.1 cgd 0 /* Not relevant to the 2100 */
87 1.1 cgd };
88 1.1 cgd
89 1.1 cgd #define PCI_QLOGIC_ISP \
90 1.1 cgd ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
91 1.1 cgd
92 1.15 mjacob #ifndef PCI_PRODUCT_QLOGIC_ISP2100
93 1.15 mjacob #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
94 1.15 mjacob #endif
95 1.15 mjacob #define PCI_QLOGIC_ISP2100 \
96 1.15 mjacob ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
97 1.15 mjacob
98 1.6 cgd #define IO_MAP_REG 0x10
99 1.6 cgd #define MEM_MAP_REG 0x14
100 1.6 cgd
101 1.1 cgd
102 1.1 cgd #ifdef __BROKEN_INDIRECT_CONFIG
103 1.1 cgd static int isp_pci_probe __P((struct device *, void *, void *));
104 1.1 cgd #else
105 1.1 cgd static int isp_pci_probe __P((struct device *, struct cfdata *, void *));
106 1.1 cgd #endif
107 1.1 cgd static void isp_pci_attach __P((struct device *, struct device *, void *));
108 1.1 cgd
109 1.1 cgd struct isp_pcisoftc {
110 1.1 cgd struct ispsoftc pci_isp;
111 1.15 mjacob pci_chipset_tag_t pci_pc;
112 1.15 mjacob pcitag_t pci_tag;
113 1.6 cgd bus_space_tag_t pci_st;
114 1.6 cgd bus_space_handle_t pci_sh;
115 1.13 thorpej bus_dma_tag_t pci_dmat;
116 1.15 mjacob bus_dmamap_t pci_scratch_dmap; /* for fcp only */
117 1.13 thorpej bus_dmamap_t pci_rquest_dmap;
118 1.13 thorpej bus_dmamap_t pci_result_dmap;
119 1.15 mjacob bus_dmamap_t pci_xfer_dmap[MAXISPREQUEST];
120 1.1 cgd void * pci_ih;
121 1.1 cgd };
122 1.1 cgd
123 1.1 cgd struct cfattach isp_pci_ca = {
124 1.1 cgd sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach
125 1.1 cgd };
126 1.1 cgd
127 1.1 cgd static int
128 1.1 cgd isp_pci_probe(parent, match, aux)
129 1.1 cgd struct device *parent;
130 1.1 cgd #ifdef __BROKEN_INDIRECT_CONFIG
131 1.17.2.1 cgd void *match;
132 1.1 cgd #else
133 1.17.2.1 cgd struct cfdata *match;
134 1.1 cgd #endif
135 1.17.2.1 cgd void *aux;
136 1.1 cgd {
137 1.1 cgd struct pci_attach_args *pa = aux;
138 1.1 cgd
139 1.15 mjacob if (pa->pa_id == PCI_QLOGIC_ISP ||
140 1.15 mjacob pa->pa_id == PCI_QLOGIC_ISP2100) {
141 1.1 cgd return (1);
142 1.1 cgd } else {
143 1.1 cgd return (0);
144 1.1 cgd }
145 1.1 cgd }
146 1.1 cgd
147 1.1 cgd
148 1.1 cgd static void
149 1.1 cgd isp_pci_attach(parent, self, aux)
150 1.1 cgd struct device *parent, *self;
151 1.1 cgd void *aux;
152 1.1 cgd {
153 1.17.2.1 cgd #ifdef DEBUG
154 1.17.2.1 cgd static char oneshot = 1;
155 1.17.2.1 cgd #endif
156 1.1 cgd struct pci_attach_args *pa = aux;
157 1.1 cgd struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self;
158 1.17.2.1 cgd struct ispsoftc *isp = &pcs->pci_isp;
159 1.11 cgd bus_space_tag_t st, iot, memt;
160 1.11 cgd bus_space_handle_t sh, ioh, memh;
161 1.1 cgd pci_intr_handle_t ih;
162 1.1 cgd const char *intrstr;
163 1.15 mjacob int ioh_valid, memh_valid, i;
164 1.17.2.1 cgd ISP_LOCKVAL_DECL;
165 1.1 cgd
166 1.12 cgd ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
167 1.11 cgd PCI_MAPREG_TYPE_IO, 0,
168 1.11 cgd &iot, &ioh, NULL, NULL) == 0);
169 1.12 cgd memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG,
170 1.11 cgd PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
171 1.11 cgd &memt, &memh, NULL, NULL) == 0);
172 1.11 cgd
173 1.11 cgd if (memh_valid) {
174 1.11 cgd st = memt;
175 1.11 cgd sh = memh;
176 1.11 cgd } else if (ioh_valid) {
177 1.11 cgd st = iot;
178 1.11 cgd sh = ioh;
179 1.6 cgd } else {
180 1.11 cgd printf(": unable to map device registers\n");
181 1.9 cgd return;
182 1.1 cgd }
183 1.1 cgd printf("\n");
184 1.1 cgd
185 1.6 cgd pcs->pci_st = st;
186 1.6 cgd pcs->pci_sh = sh;
187 1.13 thorpej pcs->pci_dmat = pa->pa_dmat;
188 1.15 mjacob pcs->pci_pc = pa->pa_pc;
189 1.15 mjacob pcs->pci_tag = pa->pa_tag;
190 1.15 mjacob if (pa->pa_id == PCI_QLOGIC_ISP) {
191 1.17.2.1 cgd isp->isp_mdvec = &mdvec;
192 1.17.2.1 cgd isp->isp_type = ISP_HA_SCSI_UNKNOWN;
193 1.17.2.1 cgd isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT);
194 1.17.2.1 cgd if (isp->isp_param == NULL) {
195 1.15 mjacob printf("%s: couldn't allocate sdparam table\n",
196 1.17.2.1 cgd isp->isp_name);
197 1.17.2.1 cgd return;
198 1.15 mjacob }
199 1.17.2.1 cgd bzero(isp->isp_param, sizeof (sdparam));
200 1.15 mjacob } else if (pa->pa_id == PCI_QLOGIC_ISP2100) {
201 1.15 mjacob u_int32_t data;
202 1.17.2.1 cgd isp->isp_mdvec = &mdvec_2100;
203 1.15 mjacob if (ioh_valid == 0) {
204 1.15 mjacob printf("%s: warning, ISP2100 cannot use I/O Space"
205 1.17.2.1 cgd " Mappings\n", isp->isp_name);
206 1.15 mjacob } else {
207 1.15 mjacob pcs->pci_st = iot;
208 1.15 mjacob pcs->pci_sh = ioh;
209 1.15 mjacob }
210 1.15 mjacob
211 1.15 mjacob #if 0
212 1.17.2.1 cgd printf("%s: PCIREGS cmd=%x bhlc=%x\n", isp->isp_name,
213 1.15 mjacob pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG),
214 1.15 mjacob pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG));
215 1.15 mjacob #endif
216 1.17.2.1 cgd isp->isp_type = ISP_HA_FC_2100;
217 1.17.2.1 cgd isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT);
218 1.17.2.1 cgd if (isp->isp_param == NULL) {
219 1.15 mjacob printf("%s: couldn't allocate fcparam table\n",
220 1.17.2.1 cgd isp->isp_name);
221 1.17.2.1 cgd return;
222 1.15 mjacob }
223 1.17.2.1 cgd bzero(isp->isp_param, sizeof (fcparam));
224 1.15 mjacob
225 1.15 mjacob data = pci_conf_read(pa->pa_pc, pa->pa_tag,
226 1.15 mjacob PCI_COMMAND_STATUS_REG);
227 1.15 mjacob data |= PCI_COMMAND_MASTER_ENABLE |
228 1.15 mjacob PCI_COMMAND_INVALIDATE_ENABLE;
229 1.15 mjacob pci_conf_write(pa->pa_pc, pa->pa_tag,
230 1.15 mjacob PCI_COMMAND_STATUS_REG, data);
231 1.15 mjacob /*
232 1.15 mjacob * Wierd- we need to clear the lsb in offset 0x30 to take the
233 1.15 mjacob * chip out of reset state.
234 1.15 mjacob */
235 1.15 mjacob data = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x30);
236 1.15 mjacob data &= ~1;
237 1.15 mjacob pci_conf_write(pa->pa_pc, pa->pa_tag, 0x30, data);
238 1.15 mjacob #if 0
239 1.15 mjacob /*
240 1.15 mjacob * XXX: Need to get the actual revision number of the 2100 FB
241 1.15 mjacob */
242 1.15 mjacob data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
243 1.15 mjacob data &= ~0xffff;
244 1.15 mjacob data |= 0xf801;
245 1.15 mjacob pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
246 1.15 mjacob printf("%s: setting latency to %x and cache line size to %x\n",
247 1.17.2.1 cgd isp->isp_name, (data >> 8) & 0xff,
248 1.15 mjacob data & 0xff);
249 1.15 mjacob #endif
250 1.15 mjacob } else {
251 1.15 mjacob return;
252 1.15 mjacob }
253 1.17.2.1 cgd #ifdef DEBUG
254 1.17.2.1 cgd if (oneshot) {
255 1.17.2.1 cgd oneshot = 0;
256 1.17.2.1 cgd printf("Qlogic ISP Driver, NetBSD (pci) Platform Version "
257 1.17.2.1 cgd "%d.%d Core Version %d.%d\n",
258 1.17.2.1 cgd ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
259 1.17.2.1 cgd ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
260 1.17.2.1 cgd }
261 1.17.2.1 cgd #endif
262 1.17.2.1 cgd ISP_LOCK(isp);
263 1.17.2.1 cgd isp_reset(isp);
264 1.17.2.1 cgd if (isp->isp_state != ISP_RESETSTATE) {
265 1.17.2.1 cgd ISP_UNLOCK(isp);
266 1.17.2.1 cgd free(isp->isp_param, M_DEVBUF);
267 1.1 cgd return;
268 1.1 cgd }
269 1.17.2.1 cgd isp_init(isp);
270 1.17.2.1 cgd if (isp->isp_state != ISP_INITSTATE) {
271 1.17.2.1 cgd isp_uninit(isp);
272 1.17.2.1 cgd ISP_UNLOCK(isp);
273 1.17.2.1 cgd free(isp->isp_param, M_DEVBUF);
274 1.1 cgd return;
275 1.1 cgd }
276 1.1 cgd
277 1.1 cgd if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
278 1.1 cgd pa->pa_intrline, &ih)) {
279 1.17.2.1 cgd printf("%s: couldn't map interrupt\n", isp->isp_name);
280 1.17.2.1 cgd isp_uninit(isp);
281 1.17.2.1 cgd ISP_UNLOCK(isp);
282 1.17.2.1 cgd free(isp->isp_param, M_DEVBUF);
283 1.1 cgd return;
284 1.1 cgd }
285 1.1 cgd
286 1.1 cgd intrstr = pci_intr_string(pa->pa_pc, ih);
287 1.1 cgd if (intrstr == NULL)
288 1.1 cgd intrstr = "<I dunno>";
289 1.1 cgd pcs->pci_ih =
290 1.17.2.1 cgd pci_intr_establish(pa->pa_pc, ih, IPL_BIO, isp_pci_intr, isp);
291 1.1 cgd if (pcs->pci_ih == NULL) {
292 1.1 cgd printf("%s: couldn't establish interrupt at %s\n",
293 1.17.2.1 cgd isp->isp_name, intrstr);
294 1.17.2.1 cgd isp_uninit(isp);
295 1.17.2.1 cgd ISP_UNLOCK(isp);
296 1.17.2.1 cgd free(isp->isp_param, M_DEVBUF);
297 1.1 cgd return;
298 1.1 cgd }
299 1.17.2.1 cgd printf("%s: interrupting at %s\n", isp->isp_name, intrstr);
300 1.1 cgd
301 1.1 cgd /*
302 1.13 thorpej * Create the DMA maps for the data transfers.
303 1.13 thorpej */
304 1.17.2.1 cgd for (i = 0; i < RQUEST_QUEUE_LEN; i++) {
305 1.13 thorpej if (bus_dmamap_create(pcs->pci_dmat, MAXPHYS,
306 1.13 thorpej (MAXPHYS / NBPG) + 1, MAXPHYS, 0, BUS_DMA_NOWAIT,
307 1.13 thorpej &pcs->pci_xfer_dmap[i])) {
308 1.13 thorpej printf("%s: can't create dma maps\n",
309 1.17.2.1 cgd isp->isp_name);
310 1.17.2.1 cgd isp_uninit(isp);
311 1.17.2.1 cgd ISP_UNLOCK(isp);
312 1.13 thorpej return;
313 1.13 thorpej }
314 1.13 thorpej }
315 1.13 thorpej /*
316 1.1 cgd * Do Generic attach now.
317 1.1 cgd */
318 1.17.2.1 cgd isp_attach(isp);
319 1.17.2.1 cgd if (isp->isp_state != ISP_RUNSTATE) {
320 1.17.2.1 cgd isp_uninit(isp);
321 1.17.2.1 cgd free(isp->isp_param, M_DEVBUF);
322 1.1 cgd }
323 1.17.2.1 cgd ISP_UNLOCK(isp);
324 1.1 cgd }
325 1.1 cgd
326 1.15 mjacob #define PCI_BIU_REGS_OFF BIU_REGS_OFF
327 1.1 cgd
328 1.1 cgd static u_int16_t
329 1.1 cgd isp_pci_rd_reg(isp, regoff)
330 1.1 cgd struct ispsoftc *isp;
331 1.1 cgd int regoff;
332 1.1 cgd {
333 1.15 mjacob u_int16_t rv;
334 1.1 cgd struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
335 1.15 mjacob int offset, oldsxp = 0;
336 1.15 mjacob
337 1.1 cgd if ((regoff & BIU_BLOCK) != 0) {
338 1.1 cgd offset = PCI_BIU_REGS_OFF;
339 1.1 cgd } else if ((regoff & MBOX_BLOCK) != 0) {
340 1.15 mjacob if (isp->isp_type & ISP_HA_SCSI)
341 1.15 mjacob offset = PCI_MBOX_REGS_OFF;
342 1.15 mjacob else
343 1.15 mjacob offset = PCI_MBOX_REGS2100_OFF;
344 1.1 cgd } else if ((regoff & SXP_BLOCK) != 0) {
345 1.1 cgd offset = PCI_SXP_REGS_OFF;
346 1.1 cgd /*
347 1.15 mjacob * We will assume that someone has paused the RISC processor.
348 1.1 cgd */
349 1.15 mjacob oldsxp = isp_pci_rd_reg(isp, BIU_CONF1);
350 1.15 mjacob isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP);
351 1.1 cgd } else {
352 1.1 cgd offset = PCI_RISC_REGS_OFF;
353 1.1 cgd }
354 1.1 cgd regoff &= 0xff;
355 1.1 cgd offset += regoff;
356 1.15 mjacob rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
357 1.15 mjacob if ((regoff & SXP_BLOCK) != 0) {
358 1.15 mjacob isp_pci_wr_reg(isp, BIU_CONF1, oldsxp);
359 1.15 mjacob }
360 1.15 mjacob return (rv);
361 1.1 cgd }
362 1.1 cgd
363 1.1 cgd static void
364 1.1 cgd isp_pci_wr_reg(isp, regoff, val)
365 1.1 cgd struct ispsoftc *isp;
366 1.1 cgd int regoff;
367 1.1 cgd u_int16_t val;
368 1.1 cgd {
369 1.1 cgd struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
370 1.15 mjacob int offset, oldsxp = 0;
371 1.1 cgd if ((regoff & BIU_BLOCK) != 0) {
372 1.1 cgd offset = PCI_BIU_REGS_OFF;
373 1.1 cgd } else if ((regoff & MBOX_BLOCK) != 0) {
374 1.15 mjacob if (isp->isp_type & ISP_HA_SCSI)
375 1.15 mjacob offset = PCI_MBOX_REGS_OFF;
376 1.15 mjacob else
377 1.15 mjacob offset = PCI_MBOX_REGS2100_OFF;
378 1.1 cgd } else if ((regoff & SXP_BLOCK) != 0) {
379 1.1 cgd offset = PCI_SXP_REGS_OFF;
380 1.1 cgd /*
381 1.15 mjacob * We will assume that someone has paused the RISC processor.
382 1.1 cgd */
383 1.15 mjacob oldsxp = isp_pci_rd_reg(isp, BIU_CONF1);
384 1.15 mjacob isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP);
385 1.1 cgd } else {
386 1.1 cgd offset = PCI_RISC_REGS_OFF;
387 1.1 cgd }
388 1.1 cgd regoff &= 0xff;
389 1.1 cgd offset += regoff;
390 1.6 cgd bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
391 1.15 mjacob if ((regoff & SXP_BLOCK) != 0) {
392 1.15 mjacob isp_pci_wr_reg(isp, BIU_CONF1, oldsxp);
393 1.15 mjacob }
394 1.1 cgd }
395 1.1 cgd
396 1.13 thorpej static int
397 1.13 thorpej isp_pci_mbxdma(isp)
398 1.1 cgd struct ispsoftc *isp;
399 1.1 cgd {
400 1.13 thorpej struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
401 1.13 thorpej bus_dma_segment_t seg;
402 1.13 thorpej bus_size_t len;
403 1.15 mjacob fcparam *fcp;
404 1.13 thorpej int rseg;
405 1.13 thorpej
406 1.13 thorpej /*
407 1.13 thorpej * Allocate and map the request queue.
408 1.13 thorpej */
409 1.17.2.1 cgd len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN);
410 1.13 thorpej if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
411 1.13 thorpej BUS_DMA_NOWAIT) ||
412 1.13 thorpej bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
413 1.13 thorpej (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMAMEM_NOSYNC))
414 1.13 thorpej return (1);
415 1.13 thorpej if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
416 1.13 thorpej &pci->pci_rquest_dmap) ||
417 1.13 thorpej bus_dmamap_load(pci->pci_dmat, pci->pci_rquest_dmap,
418 1.13 thorpej (caddr_t)isp->isp_rquest, len, NULL, BUS_DMA_NOWAIT))
419 1.13 thorpej return (1);
420 1.13 thorpej
421 1.13 thorpej isp->isp_rquest_dma = pci->pci_rquest_dmap->dm_segs[0].ds_addr;
422 1.13 thorpej
423 1.13 thorpej /*
424 1.13 thorpej * Allocate and map the result queue.
425 1.13 thorpej */
426 1.17.2.1 cgd len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN);
427 1.13 thorpej if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
428 1.13 thorpej BUS_DMA_NOWAIT) ||
429 1.13 thorpej bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
430 1.13 thorpej (caddr_t *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMAMEM_NOSYNC))
431 1.13 thorpej return (1);
432 1.13 thorpej if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
433 1.13 thorpej &pci->pci_result_dmap) ||
434 1.13 thorpej bus_dmamap_load(pci->pci_dmat, pci->pci_result_dmap,
435 1.13 thorpej (caddr_t)isp->isp_result, len, NULL, BUS_DMA_NOWAIT))
436 1.13 thorpej return (1);
437 1.15 mjacob isp->isp_result_dma = pci->pci_result_dmap->dm_segs[0].ds_addr;
438 1.1 cgd
439 1.15 mjacob if (isp->isp_type & ISP_HA_SCSI) {
440 1.15 mjacob return (0);
441 1.15 mjacob }
442 1.1 cgd
443 1.15 mjacob fcp = isp->isp_param;
444 1.15 mjacob len = ISP2100_SCRLEN;
445 1.15 mjacob if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
446 1.15 mjacob BUS_DMA_NOWAIT) ||
447 1.15 mjacob bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
448 1.15 mjacob (caddr_t *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMAMEM_NOSYNC))
449 1.15 mjacob return (1);
450 1.15 mjacob if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
451 1.15 mjacob &pci->pci_scratch_dmap) ||
452 1.15 mjacob bus_dmamap_load(pci->pci_dmat, pci->pci_scratch_dmap,
453 1.15 mjacob (caddr_t)fcp->isp_scratch, len, NULL, BUS_DMA_NOWAIT))
454 1.15 mjacob return (1);
455 1.15 mjacob fcp->isp_scdma = pci->pci_scratch_dmap->dm_segs[0].ds_addr;
456 1.13 thorpej return (0);
457 1.1 cgd }
458 1.1 cgd
459 1.1 cgd static int
460 1.1 cgd isp_pci_dmasetup(isp, xs, rq, iptrp, optr)
461 1.1 cgd struct ispsoftc *isp;
462 1.16 bouyer struct scsipi_xfer *xs;
463 1.1 cgd ispreq_t *rq;
464 1.1 cgd u_int8_t *iptrp;
465 1.1 cgd u_int8_t optr;
466 1.1 cgd {
467 1.13 thorpej struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
468 1.15 mjacob bus_dmamap_t dmap = pci->pci_xfer_dmap[rq->req_handle - 1];
469 1.1 cgd ispcontreq_t *crq;
470 1.17 mjacob int segcnt, seg, error, ovseg, seglim, drq;
471 1.1 cgd
472 1.1 cgd if (xs->datalen == 0) {
473 1.1 cgd rq->req_seg_count = 1;
474 1.17.2.1 cgd goto mbxsync;
475 1.1 cgd }
476 1.1 cgd
477 1.17.2.1 cgd if (rq->req_handle > RQUEST_QUEUE_LEN || rq->req_handle < 1) {
478 1.14 thorpej panic("%s: bad handle (%d) in isp_pci_dmasetup\n",
479 1.13 thorpej isp->isp_name, rq->req_handle);
480 1.13 thorpej /* NOTREACHED */
481 1.13 thorpej }
482 1.13 thorpej
483 1.1 cgd if (xs->flags & SCSI_DATA_IN) {
484 1.17 mjacob drq = REQFLAG_DATA_IN;
485 1.1 cgd } else {
486 1.17 mjacob drq = REQFLAG_DATA_OUT;
487 1.1 cgd }
488 1.1 cgd
489 1.15 mjacob if (isp->isp_type & ISP_HA_FC) {
490 1.15 mjacob seglim = ISP_RQDSEG_T2;
491 1.15 mjacob ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen;
492 1.17 mjacob ((ispreqt2_t *)rq)->req_flags |= drq;
493 1.15 mjacob } else {
494 1.15 mjacob seglim = ISP_RQDSEG;
495 1.17 mjacob rq->req_flags |= drq;
496 1.15 mjacob }
497 1.13 thorpej error = bus_dmamap_load(pci->pci_dmat, dmap, xs->data, xs->datalen,
498 1.13 thorpej NULL, xs->flags & SCSI_NOSLEEP ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
499 1.17.2.1 cgd if (error) {
500 1.17.2.1 cgd XS_SETERR(xs, HBA_BOTCH);
501 1.17.2.1 cgd return (CMD_COMPLETE);
502 1.17.2.1 cgd }
503 1.13 thorpej
504 1.13 thorpej segcnt = dmap->dm_nsegs;
505 1.13 thorpej
506 1.13 thorpej for (seg = 0, rq->req_seg_count = 0;
507 1.15 mjacob seg < segcnt && rq->req_seg_count < seglim;
508 1.15 mjacob seg++, rq->req_seg_count++) {
509 1.15 mjacob if (isp->isp_type & ISP_HA_FC) {
510 1.15 mjacob ispreqt2_t *rq2 = (ispreqt2_t *)rq;
511 1.15 mjacob rq2->req_dataseg[rq2->req_seg_count].ds_count =
512 1.15 mjacob dmap->dm_segs[seg].ds_len;
513 1.15 mjacob rq2->req_dataseg[rq2->req_seg_count].ds_base =
514 1.15 mjacob dmap->dm_segs[seg].ds_addr;
515 1.15 mjacob } else {
516 1.15 mjacob rq->req_dataseg[rq->req_seg_count].ds_count =
517 1.15 mjacob dmap->dm_segs[seg].ds_len;
518 1.15 mjacob rq->req_dataseg[rq->req_seg_count].ds_base =
519 1.15 mjacob dmap->dm_segs[seg].ds_addr;
520 1.15 mjacob }
521 1.1 cgd }
522 1.1 cgd
523 1.13 thorpej if (seg == segcnt)
524 1.17.2.1 cgd goto dmasync;
525 1.1 cgd
526 1.1 cgd do {
527 1.15 mjacob crq = (ispcontreq_t *)
528 1.15 mjacob ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp);
529 1.17.2.1 cgd *iptrp = (*iptrp + 1) & (RQUEST_QUEUE_LEN - 1);
530 1.1 cgd if (*iptrp == optr) {
531 1.1 cgd printf("%s: Request Queue Overflow++\n",
532 1.1 cgd isp->isp_name);
533 1.13 thorpej bus_dmamap_unload(pci->pci_dmat, dmap);
534 1.17.2.1 cgd XS_SETERR(xs, HBA_BOTCH);
535 1.17.2.1 cgd return (CMD_COMPLETE);
536 1.1 cgd }
537 1.1 cgd rq->req_header.rqs_entry_count++;
538 1.1 cgd bzero((void *)crq, sizeof (*crq));
539 1.1 cgd crq->req_header.rqs_entry_count = 1;
540 1.1 cgd crq->req_header.rqs_entry_type = RQSTYPE_DATASEG;
541 1.13 thorpej
542 1.13 thorpej for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG;
543 1.13 thorpej rq->req_seg_count++, seg++, ovseg++) {
544 1.13 thorpej crq->req_dataseg[ovseg].ds_count =
545 1.13 thorpej dmap->dm_segs[seg].ds_len;
546 1.13 thorpej crq->req_dataseg[ovseg].ds_base =
547 1.13 thorpej dmap->dm_segs[seg].ds_addr;
548 1.1 cgd }
549 1.13 thorpej } while (seg < segcnt);
550 1.13 thorpej
551 1.17.2.1 cgd dmasync:
552 1.17.2.1 cgd bus_dmamap_sync(pci->pci_dmat, dmap,
553 1.17.2.1 cgd (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD :
554 1.17.2.1 cgd BUS_DMASYNC_PREWRITE);
555 1.17.2.1 cgd
556 1.17.2.1 cgd mbxsync:
557 1.17.2.1 cgd
558 1.17.2.1 cgd bus_dmamap_sync(pci->pci_dmat, pci->pci_rquest_dmap,
559 1.17.2.1 cgd BUS_DMASYNC_PREWRITE);
560 1.17.2.1 cgd return (CMD_QUEUED);
561 1.17.2.1 cgd }
562 1.17.2.1 cgd
563 1.17.2.1 cgd static int
564 1.17.2.1 cgd isp_pci_intr(arg)
565 1.17.2.1 cgd void *arg;
566 1.17.2.1 cgd {
567 1.17.2.1 cgd struct isp_pcisoftc *pci = (struct isp_pcisoftc *)arg;
568 1.17.2.1 cgd bus_dmamap_sync(pci->pci_dmat, pci->pci_result_dmap,
569 1.17.2.1 cgd BUS_DMASYNC_POSTREAD);
570 1.17.2.1 cgd return (isp_intr(arg));
571 1.13 thorpej }
572 1.13 thorpej
573 1.13 thorpej static void
574 1.13 thorpej isp_pci_dmateardown(isp, xs, handle)
575 1.13 thorpej struct ispsoftc *isp;
576 1.16 bouyer struct scsipi_xfer *xs;
577 1.13 thorpej u_int32_t handle;
578 1.13 thorpej {
579 1.13 thorpej struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
580 1.13 thorpej bus_dmamap_t dmap = pci->pci_xfer_dmap[handle];
581 1.13 thorpej
582 1.17.2.1 cgd bus_dmamap_sync(pci->pci_dmat, dmap,
583 1.17.2.1 cgd xs->flags & SCSI_DATA_IN ?
584 1.13 thorpej BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
585 1.13 thorpej bus_dmamap_unload(pci->pci_dmat, dmap);
586 1.1 cgd }
587 1.1 cgd
588 1.1 cgd static void
589 1.1 cgd isp_pci_reset1(isp)
590 1.1 cgd struct ispsoftc *isp;
591 1.1 cgd {
592 1.1 cgd /* Make sure the BIOS is disabled */
593 1.1 cgd isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
594 1.15 mjacob }
595 1.15 mjacob
596 1.15 mjacob static void
597 1.15 mjacob isp_pci_dumpregs(isp)
598 1.15 mjacob struct ispsoftc *isp;
599 1.15 mjacob {
600 1.15 mjacob struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
601 1.15 mjacob printf("%s: PCI Status Command/Status=%x\n", pci->pci_isp.isp_name,
602 1.15 mjacob pci_conf_read(pci->pci_pc, pci->pci_tag, PCI_COMMAND_STATUS_REG));
603 1.1 cgd }
604