isp_pci.c revision 1.101
1 /* $NetBSD: isp_pci.c,v 1.101 2007/05/24 21:30:44 mjacob Exp $ */ 2 /* 3 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 4 * All rights reserved. 5 * 6 * Additional Copyright (C) 2000-2007 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.101 2007/05/24 21:30:44 mjacob Exp $"); 36 37 #include <dev/ic/isp_netbsd.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <uvm/uvm_extern.h> 42 #include <sys/reboot.h> 43 44 static uint32_t isp_pci_rd_reg(struct ispsoftc *, int); 45 static void isp_pci_wr_reg(struct ispsoftc *, int, uint32_t); 46 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 47 static uint32_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 48 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, uint32_t); 49 #endif 50 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 51 !defined(ISP_DISABLE_2200_SUPPORT) && \ 52 !defined(ISP_DISABLE_1020_SUPPORT) && \ 53 !defined(ISP_DISABLE_1080_SUPPORT) && \ 54 !defined(ISP_DISABLE_12160_SUPPORT) 55 static int 56 isp_pci_rd_isr(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 57 #endif 58 #if !defined(ISP_DISABLE_2300_SUPPORT) 59 static int 60 isp_pci_rd_isr_2300(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 61 #endif 62 #if !defined(ISP_DISABLE_2400_SUPPORT) 63 static uint32_t isp_pci_rd_reg_2400(struct ispsoftc *, int); 64 static void isp_pci_wr_reg_2400(struct ispsoftc *, int, uint32_t); 65 static int 66 isp_pci_rd_isr_2400(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 67 static int isp2400_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, 68 uint32_t *, uint32_t); 69 #endif 70 static int isp_pci_mbxdma(struct ispsoftc *); 71 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, 72 uint32_t *, uint32_t); 73 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, uint32_t); 74 static void isp_pci_reset0(struct ispsoftc *); 75 static void isp_pci_reset1(struct ispsoftc *); 76 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 77 static int isp_pci_intr(void *); 78 79 #if defined(ISP_DISABLE_1020_SUPPORT) || defined(ISP_DISABLE_FW) 80 #define ISP_1040_RISC_CODE NULL 81 #else 82 #define ISP_1040_RISC_CODE (const uint16_t *) isp_1040_risc_code 83 #include <dev/microcode/isp/asm_1040.h> 84 #endif 85 86 #if defined(ISP_DISABLE_1080_SUPPORT) || defined(ISP_DISABLE_FW) 87 #define ISP_1080_RISC_CODE NULL 88 #else 89 #define ISP_1080_RISC_CODE (const uint16_t *) isp_1080_risc_code 90 #include <dev/microcode/isp/asm_1080.h> 91 #endif 92 93 #if defined(ISP_DISABLE_12160_SUPPORT) || defined(ISP_DISABLE_FW) 94 #define ISP_12160_RISC_CODE NULL 95 #else 96 #define ISP_12160_RISC_CODE (const uint16_t *) isp_12160_risc_code 97 #include <dev/microcode/isp/asm_12160.h> 98 #endif 99 100 #if defined(ISP_DISABLE_2100_SUPPORT) || defined(ISP_DISABLE_FW) 101 #define ISP_2100_RISC_CODE NULL 102 #else 103 #define ISP_2100_RISC_CODE (const uint16_t *) isp_2100_risc_code 104 #include <dev/microcode/isp/asm_2100.h> 105 #endif 106 107 #if defined(ISP_DISABLE_2200_SUPPORT) || defined(ISP_DISABLE_FW) 108 #define ISP_2200_RISC_CODE NULL 109 #else 110 #define ISP_2200_RISC_CODE (const uint16_t *) isp_2200_risc_code 111 #include <dev/microcode/isp/asm_2200.h> 112 #endif 113 114 #if defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_FW) 115 #define ISP_2300_RISC_CODE NULL 116 #define ISP_2322_RISC_CODE NULL 117 #else 118 #define ISP_2300_RISC_CODE (const uint16_t *) isp_2300_risc_code 119 #include <dev/microcode/isp/asm_2300.h> 120 #define ISP_2322_RISC_CODE (const uint16_t *) isp_2322_risc_code 121 #include <dev/microcode/isp/asm_2322.h> 122 #endif 123 124 #if defined(ISP_DISABLE_2400_SUPPORT) || defined(ISP_DISABLE_FW) 125 #define ISP_2400_RISC_CODE NULL 126 #else 127 #define ISP_2400_RISC_CODE (const uint32_t *) isp_2400_risc_code 128 #include <dev/microcode/isp/asm_2400.h> 129 #endif 130 131 #ifndef ISP_DISABLE_1020_SUPPORT 132 static struct ispmdvec mdvec = { 133 isp_pci_rd_isr, 134 isp_pci_rd_reg, 135 isp_pci_wr_reg, 136 isp_pci_mbxdma, 137 isp_pci_dmasetup, 138 isp_pci_dmateardown, 139 isp_pci_reset0, 140 isp_pci_reset1, 141 isp_pci_dumpregs, 142 ISP_1040_RISC_CODE, 143 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 144 0 145 }; 146 #endif 147 148 #ifndef ISP_DISABLE_1080_SUPPORT 149 static struct ispmdvec mdvec_1080 = { 150 isp_pci_rd_isr, 151 isp_pci_rd_reg_1080, 152 isp_pci_wr_reg_1080, 153 isp_pci_mbxdma, 154 isp_pci_dmasetup, 155 isp_pci_dmateardown, 156 isp_pci_reset0, 157 isp_pci_reset1, 158 isp_pci_dumpregs, 159 ISP_1080_RISC_CODE, 160 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 161 0 162 }; 163 #endif 164 165 #ifndef ISP_DISABLE_12160_SUPPORT 166 static struct ispmdvec mdvec_12160 = { 167 isp_pci_rd_isr, 168 isp_pci_rd_reg_1080, 169 isp_pci_wr_reg_1080, 170 isp_pci_mbxdma, 171 isp_pci_dmasetup, 172 isp_pci_dmateardown, 173 isp_pci_reset0, 174 isp_pci_reset1, 175 isp_pci_dumpregs, 176 ISP_12160_RISC_CODE, 177 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 178 0 179 }; 180 #endif 181 182 #ifndef ISP_DISABLE_2100_SUPPORT 183 static struct ispmdvec mdvec_2100 = { 184 isp_pci_rd_isr, 185 isp_pci_rd_reg, 186 isp_pci_wr_reg, 187 isp_pci_mbxdma, 188 isp_pci_dmasetup, 189 isp_pci_dmateardown, 190 isp_pci_reset0, 191 isp_pci_reset1, 192 isp_pci_dumpregs, 193 ISP_2100_RISC_CODE, 194 0, 195 0 196 }; 197 #endif 198 199 #ifndef ISP_DISABLE_2200_SUPPORT 200 static struct ispmdvec mdvec_2200 = { 201 isp_pci_rd_isr, 202 isp_pci_rd_reg, 203 isp_pci_wr_reg, 204 isp_pci_mbxdma, 205 isp_pci_dmasetup, 206 isp_pci_dmateardown, 207 isp_pci_reset0, 208 isp_pci_reset1, 209 isp_pci_dumpregs, 210 ISP_2200_RISC_CODE, 211 0, 212 0 213 }; 214 #endif 215 216 #ifndef ISP_DISABLE_2300_SUPPORT 217 static struct ispmdvec mdvec_2300 = { 218 isp_pci_rd_isr_2300, 219 isp_pci_rd_reg, 220 isp_pci_wr_reg, 221 isp_pci_mbxdma, 222 isp_pci_dmasetup, 223 isp_pci_dmateardown, 224 isp_pci_reset0, 225 isp_pci_reset1, 226 isp_pci_dumpregs, 227 ISP_2300_RISC_CODE, 228 0, 229 0 230 }; 231 #endif 232 233 #ifndef ISP_DISABLE_2400_SUPPORT 234 static struct ispmdvec mdvec_2400 = { 235 isp_pci_rd_isr_2400, 236 isp_pci_rd_reg_2400, 237 isp_pci_wr_reg_2400, 238 isp_pci_mbxdma, 239 isp2400_pci_dmasetup, 240 isp_pci_dmateardown, 241 isp_pci_reset0, 242 isp_pci_reset1, 243 NULL, 244 ISP_2400_RISC_CODE, 245 0, 246 0 247 }; 248 #endif 249 250 #ifndef PCI_VENDOR_QLOGIC 251 #define PCI_VENDOR_QLOGIC 0x1077 252 #endif 253 254 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 255 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 256 #endif 257 258 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 259 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 260 #endif 261 262 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 263 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 264 #endif 265 266 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 267 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 268 #endif 269 270 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 271 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 272 #endif 273 274 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 275 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 276 #endif 277 278 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 279 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 280 #endif 281 282 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 283 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 284 #endif 285 286 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 287 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 288 #endif 289 290 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 291 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 292 #endif 293 294 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 295 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 296 #endif 297 298 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 299 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 300 #endif 301 302 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 303 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 304 #endif 305 306 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 307 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 308 #endif 309 310 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 311 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 312 #endif 313 314 315 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 316 317 #define PCI_QLOGIC_ISP1080 \ 318 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 319 320 #define PCI_QLOGIC_ISP10160 \ 321 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 322 323 #define PCI_QLOGIC_ISP12160 \ 324 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 325 326 #define PCI_QLOGIC_ISP1240 \ 327 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 328 329 #define PCI_QLOGIC_ISP1280 \ 330 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 331 332 #define PCI_QLOGIC_ISP2100 \ 333 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 334 335 #define PCI_QLOGIC_ISP2200 \ 336 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 337 338 #define PCI_QLOGIC_ISP2300 \ 339 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 340 341 #define PCI_QLOGIC_ISP2312 \ 342 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 343 344 #define PCI_QLOGIC_ISP2322 \ 345 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 346 347 #define PCI_QLOGIC_ISP2422 \ 348 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 349 350 #define PCI_QLOGIC_ISP2432 \ 351 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 352 353 #define PCI_QLOGIC_ISP6312 \ 354 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 355 356 #define PCI_QLOGIC_ISP6322 \ 357 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 358 359 #define IO_MAP_REG 0x10 360 #define MEM_MAP_REG 0x14 361 #define PCIR_ROMADDR 0x30 362 363 #define PCI_DFLT_LTNCY 0x40 364 #define PCI_DFLT_LNSZ 0x10 365 366 static int isp_pci_probe(struct device *, struct cfdata *, void *); 367 static void isp_pci_attach(struct device *, struct device *, void *); 368 369 struct isp_pcisoftc { 370 struct ispsoftc pci_isp; 371 pci_chipset_tag_t pci_pc; 372 pcitag_t pci_tag; 373 bus_space_tag_t pci_st; 374 bus_space_handle_t pci_sh; 375 bus_dmamap_t *pci_xfer_dmap; 376 void * pci_ih; 377 int16_t pci_poff[_NREG_BLKS]; 378 }; 379 380 CFATTACH_DECL(isp_pci, sizeof (struct isp_pcisoftc), 381 isp_pci_probe, isp_pci_attach, NULL, NULL); 382 383 #ifdef DEBUG 384 const char vstring[] = 385 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 386 #endif 387 388 static int 389 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux) 390 { 391 struct pci_attach_args *pa = aux; 392 switch (pa->pa_id) { 393 #ifndef ISP_DISABLE_1020_SUPPORT 394 case PCI_QLOGIC_ISP: 395 return (1); 396 #endif 397 #ifndef ISP_DISABLE_1080_SUPPORT 398 case PCI_QLOGIC_ISP1080: 399 case PCI_QLOGIC_ISP1240: 400 case PCI_QLOGIC_ISP1280: 401 return (1); 402 #endif 403 #ifndef ISP_DISABLE_12160_SUPPORT 404 case PCI_QLOGIC_ISP10160: 405 case PCI_QLOGIC_ISP12160: 406 return (1); 407 #endif 408 #ifndef ISP_DISABLE_2100_SUPPORT 409 case PCI_QLOGIC_ISP2100: 410 return (1); 411 #endif 412 #ifndef ISP_DISABLE_2200_SUPPORT 413 case PCI_QLOGIC_ISP2200: 414 return (1); 415 #endif 416 #ifndef ISP_DISABLE_2300_SUPPORT 417 case PCI_QLOGIC_ISP2300: 418 case PCI_QLOGIC_ISP2312: 419 case PCI_QLOGIC_ISP2322: 420 case PCI_QLOGIC_ISP6312: 421 case PCI_QLOGIC_ISP6322: 422 return (1); 423 #endif 424 #ifndef ISP_DISABLE_2400_SUPPORT 425 case PCI_QLOGIC_ISP2422: 426 case PCI_QLOGIC_ISP2432: 427 return (1); 428 #endif 429 default: 430 return (0); 431 } 432 } 433 434 435 static void 436 isp_pci_attach(struct device *parent, struct device *self, void *aux) 437 { 438 #ifdef DEBUG 439 static char oneshot = 1; 440 #endif 441 static const char nomem[] = "\n%s: no mem for sdparam table\n"; 442 uint32_t data, rev, linesz = PCI_DFLT_LNSZ; 443 struct pci_attach_args *pa = aux; 444 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 445 struct ispsoftc *isp = &pcs->pci_isp; 446 bus_space_tag_t st, iot, memt; 447 bus_space_handle_t sh, ioh, memh; 448 pci_intr_handle_t ih; 449 pcireg_t mem_type; 450 const char *dstring; 451 const char *intrstr; 452 int ioh_valid, memh_valid; 453 454 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 455 PCI_MAPREG_TYPE_IO, 0, 456 &iot, &ioh, NULL, NULL) == 0); 457 458 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG); 459 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) { 460 memh_valid = 0; 461 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT && 462 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) { 463 memh_valid = 0; 464 } else { 465 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0, 466 &memt, &memh, NULL, NULL) == 0); 467 } 468 if (memh_valid) { 469 st = memt; 470 sh = memh; 471 } else if (ioh_valid) { 472 st = iot; 473 sh = ioh; 474 } else { 475 printf(": unable to map device registers\n"); 476 return; 477 } 478 dstring = "\n"; 479 480 pcs->pci_st = st; 481 pcs->pci_sh = sh; 482 pcs->pci_pc = pa->pa_pc; 483 pcs->pci_tag = pa->pa_tag; 484 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 485 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 486 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 487 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 488 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 489 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 490 491 #ifndef ISP_DISABLE_1020_SUPPORT 492 if (pa->pa_id == PCI_QLOGIC_ISP) { 493 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n"; 494 isp->isp_mdvec = &mdvec; 495 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 496 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 497 if (isp->isp_param == NULL) { 498 printf(nomem, isp->isp_name); 499 return; 500 } 501 memset(isp->isp_param, 0, sizeof (sdparam)); 502 } 503 #endif 504 #ifndef ISP_DISABLE_1080_SUPPORT 505 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 506 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n"; 507 isp->isp_mdvec = &mdvec_1080; 508 isp->isp_type = ISP_HA_SCSI_1080; 509 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 510 if (isp->isp_param == NULL) { 511 printf(nomem, isp->isp_name); 512 return; 513 } 514 memset(isp->isp_param, 0, sizeof (sdparam)); 515 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 516 ISP1080_DMA_REGS_OFF; 517 } 518 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 519 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n"; 520 isp->isp_mdvec = &mdvec_1080; 521 isp->isp_type = ISP_HA_SCSI_1240; 522 isp->isp_param = 523 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 524 if (isp->isp_param == NULL) { 525 printf(nomem, isp->isp_name); 526 return; 527 } 528 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 529 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 530 ISP1080_DMA_REGS_OFF; 531 } 532 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 533 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n"; 534 isp->isp_mdvec = &mdvec_1080; 535 isp->isp_type = ISP_HA_SCSI_1280; 536 isp->isp_param = 537 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 538 if (isp->isp_param == NULL) { 539 printf(nomem, isp->isp_name); 540 return; 541 } 542 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 543 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 544 ISP1080_DMA_REGS_OFF; 545 } 546 #endif 547 #ifndef ISP_DISABLE_12160_SUPPORT 548 if (pa->pa_id == PCI_QLOGIC_ISP10160) { 549 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n"; 550 isp->isp_mdvec = &mdvec_12160; 551 isp->isp_type = ISP_HA_SCSI_10160; 552 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 553 if (isp->isp_param == NULL) { 554 printf(nomem, isp->isp_name); 555 return; 556 } 557 memset(isp->isp_param, 0, sizeof (sdparam)); 558 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 559 ISP1080_DMA_REGS_OFF; 560 } 561 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 562 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n"; 563 isp->isp_mdvec = &mdvec_12160; 564 isp->isp_type = ISP_HA_SCSI_12160; 565 isp->isp_param = 566 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 567 if (isp->isp_param == NULL) { 568 printf(nomem, isp->isp_name); 569 return; 570 } 571 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 572 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 573 ISP1080_DMA_REGS_OFF; 574 } 575 #endif 576 #ifndef ISP_DISABLE_2100_SUPPORT 577 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 578 dstring = ": QLogic FC-AL HBA\n"; 579 isp->isp_mdvec = &mdvec_2100; 580 isp->isp_type = ISP_HA_FC_2100; 581 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 582 if (isp->isp_param == NULL) { 583 printf(nomem, isp->isp_name); 584 return; 585 } 586 memset(isp->isp_param, 0, sizeof (fcparam)); 587 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 588 PCI_MBOX_REGS2100_OFF; 589 if (rev < 3) { 590 /* 591 * XXX: Need to get the actual revision 592 * XXX: number of the 2100 FB. At any rate, 593 * XXX: lower cache line size for early revision 594 * XXX; boards. 595 */ 596 linesz = 1; 597 } 598 } 599 #endif 600 #ifndef ISP_DISABLE_2200_SUPPORT 601 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 602 dstring = ": QLogic FC-AL and Fabric HBA\n"; 603 isp->isp_mdvec = &mdvec_2200; 604 isp->isp_type = ISP_HA_FC_2200; 605 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 606 if (isp->isp_param == NULL) { 607 printf(nomem, isp->isp_name); 608 return; 609 } 610 memset(isp->isp_param, 0, sizeof (fcparam)); 611 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 612 PCI_MBOX_REGS2100_OFF; 613 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 614 } 615 #endif 616 #ifndef ISP_DISABLE_2300_SUPPORT 617 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 618 pa->pa_id == PCI_QLOGIC_ISP2312 || 619 pa->pa_id == PCI_QLOGIC_ISP6312) { 620 isp->isp_mdvec = &mdvec_2300; 621 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 622 pa->pa_id == PCI_QLOGIC_ISP6312) { 623 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n"; 624 isp->isp_type = ISP_HA_FC_2300; 625 } else { 626 dstring = 627 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n"; 628 isp->isp_port = pa->pa_function; 629 } 630 isp->isp_type = ISP_HA_FC_2312; 631 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 632 if (isp->isp_param == NULL) { 633 printf(nomem, isp->isp_name); 634 return; 635 } 636 memset(isp->isp_param, 0, sizeof (fcparam)); 637 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 638 PCI_MBOX_REGS2300_OFF; 639 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 640 } 641 if (pa->pa_id == PCI_QLOGIC_ISP2322 || 642 pa->pa_id == PCI_QLOGIC_ISP6322) { 643 isp->isp_mdvec = &mdvec_2300; 644 dstring = ": QLogic FC-AL and 2Gbps Fabric PCI-E HBA\n"; 645 isp->isp_type = ISP_HA_FC_2322; 646 isp->isp_port = pa->pa_function; 647 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 648 if (isp->isp_param == NULL) { 649 printf(nomem, isp->isp_name); 650 return; 651 } 652 memset(isp->isp_param, 0, sizeof (fcparam)); 653 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 654 PCI_MBOX_REGS2300_OFF; 655 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 656 } 657 #endif 658 #ifndef ISP_DISABLE_2400_SUPPORT 659 if (pa->pa_id == PCI_QLOGIC_ISP2422 || 660 pa->pa_id == PCI_QLOGIC_ISP2432) { 661 isp->isp_mdvec = &mdvec_2400; 662 if (pa->pa_id == PCI_QLOGIC_ISP2422) { 663 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-X HBA\n"; 664 } else { 665 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-E HBA\n"; 666 } 667 isp->isp_type = ISP_HA_FC_2400; 668 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 669 if (isp->isp_param == NULL) { 670 printf(nomem, isp->isp_name); 671 return; 672 } 673 memset(isp->isp_param, 0, sizeof (fcparam)); 674 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 675 PCI_MBOX_REGS2400_OFF; 676 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 677 } 678 #endif 679 /* 680 * Set up logging levels. 681 */ 682 #ifdef ISP_LOGDEFAULT 683 isp->isp_dblev = ISP_LOGDEFAULT; 684 #else 685 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 686 if (bootverbose) 687 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 688 #ifdef SCSIDEBUG 689 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2; 690 #endif 691 #endif 692 if (isp->isp_dblev & ISP_LOGCONFIG) { 693 printf("\n"); 694 } else { 695 printf(dstring); 696 } 697 698 #ifdef DEBUG 699 if (oneshot) { 700 oneshot = 0; 701 isp_prt(isp, ISP_LOGCONFIG, vstring, 702 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 703 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 704 } 705 #endif 706 707 isp->isp_dmatag = pa->pa_dmat; 708 isp->isp_revision = rev; 709 710 /* 711 * Make sure that command register set sanely. 712 */ 713 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 714 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 715 716 /* 717 * Not so sure about these- but I think it's important that they get 718 * enabled...... 719 */ 720 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 721 if (IS_2300(isp)) { /* per QLogic errata */ 722 data &= ~PCI_COMMAND_INVALIDATE_ENABLE; 723 } 724 if (IS_23XX(isp)) { 725 isp->isp_touched = 1; 726 } 727 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 728 729 /* 730 * Make sure that the latency timer, cache line size, 731 * and ROM is disabled. 732 */ 733 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 734 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 735 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 736 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 737 data |= (linesz << PCI_CACHELINE_SHIFT); 738 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 739 740 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 741 data &= ~1; 742 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 743 744 if (pci_intr_map(pa, &ih)) { 745 printf("%s: couldn't map interrupt\n", isp->isp_name); 746 free(isp->isp_param, M_DEVBUF); 747 return; 748 } 749 intrstr = pci_intr_string(pa->pa_pc, ih); 750 if (intrstr == NULL) 751 intrstr = "<I dunno>"; 752 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 753 isp_pci_intr, isp); 754 if (pcs->pci_ih == NULL) { 755 printf("%s: couldn't establish interrupt at %s\n", 756 isp->isp_name, intrstr); 757 free(isp->isp_param, M_DEVBUF); 758 return; 759 } 760 761 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 762 763 if (IS_FC(isp)) { 764 DEFAULT_NODEWWN(isp) = 0x400000007F000002ULL; 765 DEFAULT_PORTWWN(isp) = 0x400000007F000002ULL; 766 } 767 768 isp->isp_confopts = self->dv_cfdata->cf_flags; 769 isp->isp_role = ISP_DEFAULT_ROLES; 770 ISP_LOCK(isp); 771 isp_reset(isp); 772 if (isp->isp_state != ISP_RESETSTATE) { 773 ISP_UNLOCK(isp); 774 free(isp->isp_param, M_DEVBUF); 775 return; 776 } 777 isp_init(isp); 778 if (isp->isp_state != ISP_INITSTATE) { 779 isp_uninit(isp); 780 ISP_UNLOCK(isp); 781 free(isp->isp_param, M_DEVBUF); 782 return; 783 } 784 /* 785 * Do platform attach. 786 */ 787 ISP_UNLOCK(isp); 788 isp_attach(isp); 789 if (isp->isp_state != ISP_RUNSTATE) { 790 ISP_LOCK(isp); 791 isp_uninit(isp); 792 free(isp->isp_param, M_DEVBUF); 793 ISP_UNLOCK(isp); 794 } 795 } 796 797 #define IspVirt2Off(a, x) \ 798 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 799 _BLK_REG_SHFT] + ((x) & 0xff)) 800 801 #define BXR2(pcs, off) \ 802 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 803 #define BXW2(pcs, off, v) \ 804 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 805 #define BXR4(pcs, off) \ 806 bus_space_read_4(pcs->pci_st, pcs->pci_sh, off) 807 #define BXW4(pcs, off, v) \ 808 bus_space_write_4(pcs->pci_st, pcs->pci_sh, off, v) 809 810 811 static int 812 isp_pci_rd_debounced(struct ispsoftc *isp, int off, uint16_t *rp) 813 { 814 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 815 uint16_t val0, val1; 816 int i = 0; 817 818 do { 819 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 820 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 821 } while (val0 != val1 && ++i < 1000); 822 if (val0 != val1) { 823 return (1); 824 } 825 *rp = val0; 826 return (0); 827 } 828 829 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 830 !defined(ISP_DISABLE_2200_SUPPORT) && \ 831 !defined(ISP_DISABLE_1020_SUPPORT) && \ 832 !defined(ISP_DISABLE_1080_SUPPORT) && \ 833 !defined(ISP_DISABLE_12160_SUPPORT) 834 static int 835 isp_pci_rd_isr(struct ispsoftc *isp, uint32_t *isrp, 836 uint16_t *semap, uint16_t *mbp) 837 { 838 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 839 uint16_t isr, sema; 840 841 if (IS_2100(isp)) { 842 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 843 return (0); 844 } 845 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 846 return (0); 847 } 848 } else { 849 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 850 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 851 } 852 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 853 isr &= INT_PENDING_MASK(isp); 854 sema &= BIU_SEMA_LOCK; 855 if (isr == 0 && sema == 0) { 856 return (0); 857 } 858 *isrp = isr; 859 if ((*semap = sema) != 0) { 860 if (IS_2100(isp)) { 861 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 862 return (0); 863 } 864 } else { 865 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 866 } 867 } 868 return (1); 869 } 870 #endif 871 872 #ifndef ISP_DISABLE_2300_SUPPORT 873 static int 874 isp_pci_rd_isr_2300(struct ispsoftc *isp, uint32_t *isrp, 875 uint16_t *semap, uint16_t *mbox0p) 876 { 877 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 878 uint32_t r2hisr; 879 880 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 881 *isrp = 0; 882 return (0); 883 } 884 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 885 IspVirt2Off(pcs, BIU_R2HSTSLO)); 886 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 887 if ((r2hisr & BIU_R2HST_INTR) == 0) { 888 *isrp = 0; 889 return (0); 890 } 891 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 892 case ISPR2HST_ROM_MBX_OK: 893 case ISPR2HST_ROM_MBX_FAIL: 894 case ISPR2HST_MBX_OK: 895 case ISPR2HST_MBX_FAIL: 896 case ISPR2HST_ASYNC_EVENT: 897 *isrp = r2hisr & 0xffff; 898 *mbox0p = (r2hisr >> 16); 899 *semap = 1; 900 return (1); 901 case ISPR2HST_RIO_16: 902 *isrp = r2hisr & 0xffff; 903 *mbox0p = ASYNC_RIO1; 904 *semap = 1; 905 return (1); 906 case ISPR2HST_FPOST: 907 *isrp = r2hisr & 0xffff; 908 *mbox0p = ASYNC_CMD_CMPLT; 909 *semap = 1; 910 return (1); 911 case ISPR2HST_FPOST_CTIO: 912 *isrp = r2hisr & 0xffff; 913 *mbox0p = ASYNC_CTIO_DONE; 914 *semap = 1; 915 return (1); 916 case ISPR2HST_RSPQ_UPDATE: 917 *isrp = r2hisr & 0xffff; 918 *mbox0p = 0; 919 *semap = 0; 920 return (1); 921 default: 922 return (0); 923 } 924 } 925 #endif 926 927 #ifndef ISP_DISABLE_2400_SUPPORT 928 static int 929 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, 930 uint16_t *semap, uint16_t *mbox0p) 931 { 932 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 933 uint32_t r2hisr; 934 935 r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU2400_R2HSTSLO)); 936 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 937 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 938 *isrp = 0; 939 return (0); 940 } 941 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 942 case ISP2400R2HST_ROM_MBX_OK: 943 case ISP2400R2HST_ROM_MBX_FAIL: 944 case ISP2400R2HST_MBX_OK: 945 case ISP2400R2HST_MBX_FAIL: 946 case ISP2400R2HST_ASYNC_EVENT: 947 *isrp = r2hisr & 0xffff; 948 *mbox0p = (r2hisr >> 16); 949 *semap = 1; 950 return (1); 951 case ISP2400R2HST_RSPQ_UPDATE: 952 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 953 case ISP2400R2HST_ATIO_RQST_UPDATE: 954 *isrp = r2hisr & 0xffff; 955 *mbox0p = 0; 956 *semap = 0; 957 return (1); 958 default: 959 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 960 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 961 return (0); 962 } 963 } 964 965 static uint32_t 966 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 967 { 968 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 969 uint32_t rv; 970 int block = regoff & _BLK_REG_MASK; 971 972 switch (block) { 973 case BIU_BLOCK: 974 break; 975 case MBOX_BLOCK: 976 return (BXR2(pcs, IspVirt2Off(pcs, regoff))); 977 case SXP_BLOCK: 978 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 979 return (0xffffffff); 980 case RISC_BLOCK: 981 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 982 return (0xffffffff); 983 case DMA_BLOCK: 984 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 985 return (0xffffffff); 986 default: 987 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 988 return (0xffffffff); 989 } 990 991 992 switch (regoff) { 993 case BIU2400_FLASH_ADDR: 994 case BIU2400_FLASH_DATA: 995 case BIU2400_ICR: 996 case BIU2400_ISR: 997 case BIU2400_CSR: 998 case BIU2400_REQINP: 999 case BIU2400_REQOUTP: 1000 case BIU2400_RSPINP: 1001 case BIU2400_RSPOUTP: 1002 case BIU2400_PRI_RQINP: 1003 case BIU2400_PRI_RSPINP: 1004 case BIU2400_ATIO_RSPINP: 1005 case BIU2400_ATIO_REQINP: 1006 case BIU2400_HCCR: 1007 case BIU2400_GPIOD: 1008 case BIU2400_GPIOE: 1009 case BIU2400_HSEMA: 1010 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1011 break; 1012 case BIU2400_R2HSTSLO: 1013 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1014 break; 1015 case BIU2400_R2HSTSHI: 1016 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)) >> 16; 1017 break; 1018 default: 1019 isp_prt(isp, ISP_LOGERR, 1020 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1021 rv = 0xffffffff; 1022 break; 1023 } 1024 return (rv); 1025 } 1026 1027 static void 1028 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1029 { 1030 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1031 int block = regoff & _BLK_REG_MASK; 1032 volatile int junk; 1033 1034 switch (block) { 1035 case BIU_BLOCK: 1036 break; 1037 case MBOX_BLOCK: 1038 BXW2(pcs, IspVirt2Off(pcs, regoff), val); 1039 junk = BXR2(pcs, IspVirt2Off(pcs, regoff)); 1040 return; 1041 case SXP_BLOCK: 1042 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1043 return; 1044 case RISC_BLOCK: 1045 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1046 return; 1047 case DMA_BLOCK: 1048 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1049 return; 1050 default: 1051 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1052 regoff); 1053 break; 1054 } 1055 1056 switch (regoff) { 1057 case BIU2400_FLASH_ADDR: 1058 case BIU2400_FLASH_DATA: 1059 case BIU2400_ICR: 1060 case BIU2400_ISR: 1061 case BIU2400_CSR: 1062 case BIU2400_REQINP: 1063 case BIU2400_REQOUTP: 1064 case BIU2400_RSPINP: 1065 case BIU2400_RSPOUTP: 1066 case BIU2400_PRI_RQINP: 1067 case BIU2400_PRI_RSPINP: 1068 case BIU2400_ATIO_RSPINP: 1069 case BIU2400_ATIO_REQINP: 1070 case BIU2400_HCCR: 1071 case BIU2400_GPIOD: 1072 case BIU2400_GPIOE: 1073 case BIU2400_HSEMA: 1074 BXW4(pcs, IspVirt2Off(pcs, regoff), val); 1075 junk = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1076 break; 1077 default: 1078 isp_prt(isp, ISP_LOGERR, 1079 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1080 break; 1081 } 1082 } 1083 #endif 1084 1085 static uint32_t 1086 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 1087 { 1088 uint32_t rv; 1089 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1090 int oldconf = 0; 1091 1092 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1093 /* 1094 * We will assume that someone has paused the RISC processor. 1095 */ 1096 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1097 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1098 oldconf | BIU_PCI_CONF1_SXP); 1099 } 1100 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1101 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1102 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1103 } 1104 return (rv); 1105 } 1106 1107 static void 1108 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, uint32_t val) 1109 { 1110 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1111 int oldconf = 0; 1112 1113 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1114 /* 1115 * We will assume that someone has paused the RISC processor. 1116 */ 1117 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1118 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1119 oldconf | BIU_PCI_CONF1_SXP); 1120 } 1121 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1122 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1123 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1124 } 1125 } 1126 1127 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 1128 static uint32_t 1129 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 1130 { 1131 uint16_t rv, oc = 0; 1132 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1133 1134 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1135 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1136 uint16_t tc; 1137 /* 1138 * We will assume that someone has paused the RISC processor. 1139 */ 1140 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1141 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1142 if (regoff & SXP_BANK1_SELECT) 1143 tc |= BIU_PCI1080_CONF1_SXP1; 1144 else 1145 tc |= BIU_PCI1080_CONF1_SXP0; 1146 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1147 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1148 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1149 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1150 oc | BIU_PCI1080_CONF1_DMA); 1151 } 1152 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1153 if (oc) { 1154 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1155 } 1156 return (rv); 1157 } 1158 1159 static void 1160 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, uint32_t val) 1161 { 1162 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1163 int oc = 0; 1164 1165 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1166 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1167 uint16_t tc; 1168 /* 1169 * We will assume that someone has paused the RISC processor. 1170 */ 1171 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1172 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1173 if (regoff & SXP_BANK1_SELECT) 1174 tc |= BIU_PCI1080_CONF1_SXP1; 1175 else 1176 tc |= BIU_PCI1080_CONF1_SXP0; 1177 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1178 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1179 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1180 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1181 oc | BIU_PCI1080_CONF1_DMA); 1182 } 1183 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1184 if (oc) { 1185 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1186 } 1187 } 1188 #endif 1189 1190 static int 1191 isp_pci_mbxdma(struct ispsoftc *isp) 1192 { 1193 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1194 bus_dma_tag_t dmat = isp->isp_dmatag; 1195 bus_dma_segment_t sg; 1196 bus_size_t len; 1197 fcparam *fcp; 1198 int rs, i; 1199 1200 if (isp->isp_rquest_dma) /* been here before? */ 1201 return (0); 1202 1203 len = isp->isp_maxcmds * sizeof (XS_T *); 1204 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 1205 if (isp->isp_xflist == NULL) { 1206 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 1207 return (1); 1208 } 1209 memset(isp->isp_xflist, 0, len); 1210 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 1211 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1212 if (pcs->pci_xfer_dmap == NULL) { 1213 free(isp->isp_xflist, M_DEVBUF); 1214 isp->isp_xflist = NULL; 1215 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array"); 1216 return (1); 1217 } 1218 for (i = 0; i < isp->isp_maxcmds; i++) { 1219 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 1220 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 1221 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps"); 1222 break; 1223 } 1224 } 1225 if (i < isp->isp_maxcmds) { 1226 while (--i >= 0) { 1227 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1228 } 1229 free(isp->isp_xflist, M_DEVBUF); 1230 free(pcs->pci_xfer_dmap, M_DEVBUF); 1231 isp->isp_xflist = NULL; 1232 pcs->pci_xfer_dmap = NULL; 1233 return (1); 1234 } 1235 1236 /* 1237 * Allocate and map the request queue. 1238 */ 1239 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1240 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 0)) { 1241 goto dmafail; 1242 } 1243 if (bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 1244 (void *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1245 goto dmafail; 1246 } 1247 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 1248 &isp->isp_rqdmap)) { 1249 goto dmafail; 1250 } 1251 if (bus_dmamap_load(dmat, isp->isp_rqdmap, isp->isp_rquest, len, NULL, 1252 BUS_DMA_NOWAIT)) { 1253 goto dmafail; 1254 } 1255 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 1256 1257 /* 1258 * Allocate and map the result queue. 1259 */ 1260 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1261 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 1262 BUS_DMA_NOWAIT)) { 1263 goto dmafail; 1264 } 1265 if (bus_dmamem_map(dmat, &sg, rs, len, 1266 (void *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1267 goto dmafail; 1268 } 1269 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 1270 &isp->isp_rsdmap)) { 1271 goto dmafail; 1272 } 1273 if (bus_dmamap_load(dmat, isp->isp_rsdmap, isp->isp_result, len, NULL, 1274 BUS_DMA_NOWAIT)) { 1275 goto dmafail; 1276 } 1277 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 1278 1279 if (IS_SCSI(isp)) { 1280 return (0); 1281 } 1282 1283 /* 1284 * Allocate and map an FC scratch area 1285 */ 1286 fcp = isp->isp_param; 1287 len = ISP2100_SCRLEN; 1288 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 1289 BUS_DMA_NOWAIT)) { 1290 goto dmafail; 1291 } 1292 if (bus_dmamem_map(dmat, &sg, rs, len, 1293 (void *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1294 goto dmafail; 1295 } 1296 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 1297 &isp->isp_scdmap)) { 1298 goto dmafail; 1299 } 1300 if (bus_dmamap_load(dmat, isp->isp_scdmap, fcp->isp_scratch, len, NULL, 1301 BUS_DMA_NOWAIT)) { 1302 goto dmafail; 1303 } 1304 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 1305 return (0); 1306 dmafail: 1307 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure"); 1308 for (i = 0; i < isp->isp_maxcmds; i++) { 1309 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1310 } 1311 free(isp->isp_xflist, M_DEVBUF); 1312 free(pcs->pci_xfer_dmap, M_DEVBUF); 1313 isp->isp_xflist = NULL; 1314 pcs->pci_xfer_dmap = NULL; 1315 return (1); 1316 } 1317 1318 static int 1319 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq, 1320 uint32_t *nxtip, uint32_t optr) 1321 { 1322 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1323 bus_dmamap_t dmap; 1324 uint32_t starti = isp->isp_reqidx, nxti = *nxtip; 1325 ispreq_t *qep; 1326 int segcnt, seg, error, ovseg, seglim, drq; 1327 1328 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, starti); 1329 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 1330 if (xs->datalen == 0) { 1331 rq->req_seg_count = 1; 1332 goto mbxsync; 1333 } 1334 if (xs->xs_control & XS_CTL_DATA_IN) { 1335 drq = REQFLAG_DATA_IN; 1336 } else { 1337 drq = REQFLAG_DATA_OUT; 1338 } 1339 1340 if (IS_FC(isp)) { 1341 seglim = ISP_RQDSEG_T2; 1342 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 1343 ((ispreqt2_t *)rq)->req_flags |= drq; 1344 } else { 1345 rq->req_flags |= drq; 1346 if (XS_CDBLEN(xs) > 12) { 1347 seglim = 0; 1348 } else { 1349 seglim = ISP_RQDSEG; 1350 } 1351 } 1352 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 1353 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 1354 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 1355 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1356 if (error) { 1357 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", error); 1358 XS_SETERR(xs, HBA_BOTCH); 1359 if (error == EAGAIN || error == ENOMEM) 1360 return (CMD_EAGAIN); 1361 else 1362 return (CMD_COMPLETE); 1363 } 1364 1365 segcnt = dmap->dm_nsegs; 1366 1367 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 1368 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 1369 "write from", xs->data, segcnt); 1370 1371 for (seg = 0, rq->req_seg_count = 0; 1372 seglim && seg < segcnt && rq->req_seg_count < seglim; 1373 seg++, rq->req_seg_count++) { 1374 if (IS_FC(isp)) { 1375 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1376 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1377 dmap->dm_segs[seg].ds_len; 1378 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1379 dmap->dm_segs[seg].ds_addr; 1380 } else { 1381 rq->req_dataseg[rq->req_seg_count].ds_count = 1382 dmap->dm_segs[seg].ds_len; 1383 rq->req_dataseg[rq->req_seg_count].ds_base = 1384 dmap->dm_segs[seg].ds_addr; 1385 } 1386 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 1387 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 1388 (unsigned long) dmap->dm_segs[seg].ds_len); 1389 } 1390 1391 if (seg == segcnt) { 1392 goto dmasync; 1393 } 1394 1395 do { 1396 uint32_t onxti; 1397 ispcontreq_t *crq, *cqe, local; 1398 1399 crq = &local; 1400 1401 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1402 onxti = nxti; 1403 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1404 if (nxti == optr) { 1405 isp_prt(isp, ISP_LOGERR, "Request Queue Overflow++"); 1406 bus_dmamap_unload(isp->isp_dmatag, dmap); 1407 XS_SETERR(xs, HBA_BOTCH); 1408 return (CMD_EAGAIN); 1409 } 1410 rq->req_header.rqs_entry_count++; 1411 memset((void *)crq, 0, sizeof (*crq)); 1412 crq->req_header.rqs_entry_count = 1; 1413 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1414 1415 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 1416 rq->req_seg_count++, seg++, ovseg++) { 1417 crq->req_dataseg[ovseg].ds_count = 1418 dmap->dm_segs[seg].ds_len; 1419 crq->req_dataseg[ovseg].ds_base = 1420 dmap->dm_segs[seg].ds_addr; 1421 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 1422 rq->req_header.rqs_entry_count - 1, 1423 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 1424 (unsigned long) dmap->dm_segs[seg].ds_len); 1425 } 1426 isp_put_cont_req(isp, crq, cqe); 1427 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1428 } while (seg < segcnt); 1429 1430 1431 dmasync: 1432 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1433 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 1434 BUS_DMASYNC_PREWRITE); 1435 1436 mbxsync: 1437 switch (rq->req_header.rqs_entry_type) { 1438 case RQSTYPE_REQUEST: 1439 isp_put_request(isp, rq, qep); 1440 break; 1441 case RQSTYPE_CMDONLY: 1442 isp_put_extended_request(isp, (ispextreq_t *)rq, 1443 (ispextreq_t *)qep); 1444 break; 1445 case RQSTYPE_T2RQS: 1446 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1447 break; 1448 } 1449 *nxtip = nxti; 1450 return (CMD_QUEUED); 1451 } 1452 1453 1454 #if !defined(ISP_DISABLE_2400_SUPPORT) 1455 static int 1456 isp2400_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, 1457 ispreq_t *ispreq, uint32_t *nxtip, uint32_t optr) 1458 { 1459 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1460 bus_dmamap_t dmap; 1461 bus_dma_segment_t *dm_segs, *eseg; 1462 uint32_t starti = isp->isp_reqidx, nxti = *nxtip; 1463 ispreqt7_t *rq; 1464 void *qep; 1465 int nseg, datalen, error, seglim; 1466 1467 rq = (ispreqt7_t *) ispreq; 1468 qep = ISP_QUEUE_ENTRY(isp->isp_rquest, starti); 1469 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 1470 if (xs->datalen == 0) { 1471 rq->req_seg_count = 1; 1472 goto mbxsync; 1473 } 1474 1475 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 1476 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 1477 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 1478 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1479 if (error) { 1480 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", error); 1481 XS_SETERR(xs, HBA_BOTCH); 1482 if (error == EAGAIN || error == ENOMEM) { 1483 return (CMD_EAGAIN); 1484 } else { 1485 return (CMD_COMPLETE); 1486 } 1487 } 1488 1489 nseg = dmap->dm_nsegs; 1490 dm_segs = dmap->dm_segs; 1491 1492 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 1493 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 1494 "write from", xs->data, nseg); 1495 1496 /* 1497 * We're passed an initial partially filled in entry that 1498 * has most fields filled in except for data transfer 1499 * related values. 1500 * 1501 * Our job is to fill in the initial request queue entry and 1502 * then to start allocating and filling in continuation entries 1503 * until we've covered the entire transfer. 1504 */ 1505 rq->req_header.rqs_entry_type = RQSTYPE_T7RQS; 1506 rq->req_dl = xs->datalen; 1507 datalen = xs->datalen; 1508 if (xs->xs_control & XS_CTL_DATA_IN) { 1509 rq->req_alen_datadir = 0x2; 1510 } else { 1511 rq->req_alen_datadir = 0x1; 1512 } 1513 1514 eseg = dm_segs + nseg; 1515 1516 rq->req_dataseg.ds_base = DMA_LO32(dm_segs->ds_addr); 1517 rq->req_dataseg.ds_basehi = DMA_HI32(dm_segs->ds_addr); 1518 rq->req_dataseg.ds_count = dm_segs->ds_len; 1519 1520 datalen -= dm_segs->ds_len; 1521 1522 dm_segs++; 1523 rq->req_seg_count++; 1524 1525 while (datalen > 0 && dm_segs != eseg) { 1526 uint32_t onxti; 1527 ispcontreq64_t local, *crq = &local, *cqe; 1528 1529 cqe = (ispcontreq64_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1530 onxti = nxti; 1531 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1532 if (nxti == optr) { 1533 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1534 return (CMD_EAGAIN); 1535 } 1536 rq->req_header.rqs_entry_count++; 1537 MEMZERO((void *)crq, sizeof (*crq)); 1538 crq->req_header.rqs_entry_count = 1; 1539 crq->req_header.rqs_entry_type = RQSTYPE_A64_CONT; 1540 1541 seglim = 0; 1542 while (datalen > 0 && seglim < ISP_CDSEG64 && dm_segs != eseg) { 1543 crq->req_dataseg[seglim].ds_base = 1544 DMA_LO32(dm_segs->ds_addr); 1545 crq->req_dataseg[seglim].ds_basehi = 1546 DMA_HI32(dm_segs->ds_addr); 1547 crq->req_dataseg[seglim].ds_count = 1548 dm_segs->ds_len; 1549 rq->req_seg_count++; 1550 dm_segs++; 1551 seglim++; 1552 datalen -= dm_segs->ds_len; 1553 } 1554 if (isp->isp_dblev & ISP_LOGDEBUG1) { 1555 isp_print_bytes(isp, "Continuation", QENTRY_LEN, crq); 1556 } 1557 isp_put_cont64_req(isp, crq, cqe); 1558 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1559 } 1560 *nxtip = nxti; 1561 1562 1563 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1564 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 1565 BUS_DMASYNC_PREWRITE); 1566 1567 mbxsync: 1568 isp_put_request_t7(isp, rq, qep); 1569 *nxtip = nxti; 1570 return (CMD_QUEUED); 1571 } 1572 #endif 1573 1574 static int 1575 isp_pci_intr(void *arg) 1576 { 1577 uint32_t isr; 1578 uint16_t sema, mbox; 1579 struct ispsoftc *isp = arg; 1580 1581 isp->isp_intcnt++; 1582 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1583 isp->isp_intbogus++; 1584 return (0); 1585 } else { 1586 isp->isp_osinfo.onintstack = 1; 1587 isp_intr(isp, isr, sema, mbox); 1588 isp->isp_osinfo.onintstack = 0; 1589 return (1); 1590 } 1591 } 1592 1593 static void 1594 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, uint32_t handle) 1595 { 1596 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1597 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 1598 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1599 xs->xs_control & XS_CTL_DATA_IN ? 1600 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1601 bus_dmamap_unload(isp->isp_dmatag, dmap); 1602 } 1603 1604 static void 1605 isp_pci_reset0(ispsoftc_t *isp) 1606 { 1607 ISP_DISABLE_INTS(isp); 1608 } 1609 1610 static void 1611 isp_pci_reset1(ispsoftc_t *isp) 1612 { 1613 if (!IS_24XX(isp)) { 1614 /* Make sure the BIOS is disabled */ 1615 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1616 } 1617 /* and enable interrupts */ 1618 ISP_ENABLE_INTS(isp); 1619 } 1620 1621 static void 1622 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1623 { 1624 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1625 if (msg) 1626 printf("%s: %s\n", isp->isp_name, msg); 1627 if (IS_SCSI(isp)) 1628 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1629 else 1630 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1631 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1632 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1633 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1634 1635 1636 if (IS_SCSI(isp)) { 1637 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1638 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1639 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1640 ISP_READ(isp, CDMA_FIFO_STS)); 1641 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1642 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1643 ISP_READ(isp, DDMA_FIFO_STS)); 1644 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1645 ISP_READ(isp, SXP_INTERRUPT), 1646 ISP_READ(isp, SXP_GROSS_ERR), 1647 ISP_READ(isp, SXP_PINS_CTRL)); 1648 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1649 } 1650 printf(" mbox regs: %x %x %x %x %x\n", 1651 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1652 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1653 ISP_READ(isp, OUTMAILBOX4)); 1654 printf(" PCI Status Command/Status=%x\n", 1655 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1656 } 1657
Indexes created Thu Sep 25 16:09:42 GMT 2025