isp_pci.c revision 1.109
1 /* $NetBSD: isp_pci.c,v 1.109 2009/06/25 23:44:02 mjacob Exp $ */ 2 /* 3 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 4 * All rights reserved. 5 * 6 * Additional Copyright (C) 2000-2007 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 33 */ 34 35 /* 36 * 24XX 4Gb material support provided by MetrumRG Associates. 37 * Many thanks are due to them. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.109 2009/06/25 23:44:02 mjacob Exp $"); 42 43 #include <dev/ic/isp_netbsd.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 #include <uvm/uvm_extern.h> 48 #include <sys/reboot.h> 49 50 static uint32_t isp_pci_rd_reg(struct ispsoftc *, int); 51 static void isp_pci_wr_reg(struct ispsoftc *, int, uint32_t); 52 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 53 static uint32_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 54 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, uint32_t); 55 #endif 56 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 57 !defined(ISP_DISABLE_2200_SUPPORT) && \ 58 !defined(ISP_DISABLE_1020_SUPPORT) && \ 59 !defined(ISP_DISABLE_1080_SUPPORT) && \ 60 !defined(ISP_DISABLE_12160_SUPPORT) 61 static int 62 isp_pci_rd_isr(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 63 #endif 64 #if !(defined(ISP_DISABLE_2300_SUPPORT) && defined(ISP_DISABLE_2322_SUPPORT)) 65 static int 66 isp_pci_rd_isr_2300(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 67 #endif 68 #if !defined(ISP_DISABLE_2400_SUPPORT) 69 static uint32_t isp_pci_rd_reg_2400(struct ispsoftc *, int); 70 static void isp_pci_wr_reg_2400(struct ispsoftc *, int, uint32_t); 71 static int 72 isp_pci_rd_isr_2400(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 73 #endif 74 static int isp_pci_mbxdma(struct ispsoftc *); 75 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, void *); 76 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, uint32_t); 77 static void isp_pci_reset0(struct ispsoftc *); 78 static void isp_pci_reset1(struct ispsoftc *); 79 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 80 static int isp_pci_intr(void *); 81 82 #if defined(ISP_DISABLE_1020_SUPPORT) || defined(ISP_DISABLE_FW) 83 #define ISP_1040_RISC_CODE NULL 84 #else 85 #define ISP_1040_RISC_CODE (const uint16_t *) isp_1040_risc_code 86 #include <dev/microcode/isp/asm_1040.h> 87 #endif 88 89 #if defined(ISP_DISABLE_1080_SUPPORT) || defined(ISP_DISABLE_FW) 90 #define ISP_1080_RISC_CODE NULL 91 #else 92 #define ISP_1080_RISC_CODE (const uint16_t *) isp_1080_risc_code 93 #include <dev/microcode/isp/asm_1080.h> 94 #endif 95 96 #if defined(ISP_DISABLE_12160_SUPPORT) || defined(ISP_DISABLE_FW) 97 #define ISP_12160_RISC_CODE NULL 98 #else 99 #define ISP_12160_RISC_CODE (const uint16_t *) isp_12160_risc_code 100 #include <dev/microcode/isp/asm_12160.h> 101 #endif 102 103 #if defined(ISP_DISABLE_2100_SUPPORT) || defined(ISP_DISABLE_FW) 104 #define ISP_2100_RISC_CODE NULL 105 #else 106 #define ISP_2100_RISC_CODE (const uint16_t *) isp_2100_risc_code 107 #include <dev/microcode/isp/asm_2100.h> 108 #endif 109 110 #if defined(ISP_DISABLE_2200_SUPPORT) || defined(ISP_DISABLE_FW) 111 #define ISP_2200_RISC_CODE NULL 112 #else 113 #define ISP_2200_RISC_CODE (const uint16_t *) isp_2200_risc_code 114 #include <dev/microcode/isp/asm_2200.h> 115 #endif 116 117 #if defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_FW) 118 #define ISP_2300_RISC_CODE NULL 119 #else 120 #define ISP_2300_RISC_CODE (const uint16_t *) isp_2300_risc_code 121 #include <dev/microcode/isp/asm_2300.h> 122 #endif 123 #if defined(ISP_DISABLE_2322_SUPPORT) || defined(ISP_DISABLE_FW) 124 #define ISP_2322_RISC_CODE NULL 125 #else 126 #define ISP_2322_RISC_CODE (const uint16_t *) isp_2322_risc_code 127 #include <dev/microcode/isp/asm_2322.h> 128 #endif 129 130 #if defined(ISP_DISABLE_2400_SUPPORT) || defined(ISP_DISABLE_FW) 131 #define ISP_2400_RISC_CODE NULL 132 #define ISP_2500_RISC_CODE NULL 133 #else 134 #define ISP_2400_RISC_CODE (const uint32_t *) isp_2400_risc_code 135 #define ISP_2500_RISC_CODE (const uint32_t *) isp_2500_risc_code 136 #include <dev/microcode/isp/asm_2400.h> 137 #include <dev/microcode/isp/asm_2500.h> 138 #endif 139 140 #ifndef ISP_DISABLE_1020_SUPPORT 141 static struct ispmdvec mdvec = { 142 isp_pci_rd_isr, 143 isp_pci_rd_reg, 144 isp_pci_wr_reg, 145 isp_pci_mbxdma, 146 isp_pci_dmasetup, 147 isp_pci_dmateardown, 148 isp_pci_reset0, 149 isp_pci_reset1, 150 isp_pci_dumpregs, 151 ISP_1040_RISC_CODE, 152 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 153 0 154 }; 155 #endif 156 157 #ifndef ISP_DISABLE_1080_SUPPORT 158 static struct ispmdvec mdvec_1080 = { 159 isp_pci_rd_isr, 160 isp_pci_rd_reg_1080, 161 isp_pci_wr_reg_1080, 162 isp_pci_mbxdma, 163 isp_pci_dmasetup, 164 isp_pci_dmateardown, 165 isp_pci_reset0, 166 isp_pci_reset1, 167 isp_pci_dumpregs, 168 ISP_1080_RISC_CODE, 169 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 170 0 171 }; 172 #endif 173 174 #ifndef ISP_DISABLE_12160_SUPPORT 175 static struct ispmdvec mdvec_12160 = { 176 isp_pci_rd_isr, 177 isp_pci_rd_reg_1080, 178 isp_pci_wr_reg_1080, 179 isp_pci_mbxdma, 180 isp_pci_dmasetup, 181 isp_pci_dmateardown, 182 isp_pci_reset0, 183 isp_pci_reset1, 184 isp_pci_dumpregs, 185 ISP_12160_RISC_CODE, 186 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 187 0 188 }; 189 #endif 190 191 #ifndef ISP_DISABLE_2100_SUPPORT 192 static struct ispmdvec mdvec_2100 = { 193 isp_pci_rd_isr, 194 isp_pci_rd_reg, 195 isp_pci_wr_reg, 196 isp_pci_mbxdma, 197 isp_pci_dmasetup, 198 isp_pci_dmateardown, 199 isp_pci_reset0, 200 isp_pci_reset1, 201 isp_pci_dumpregs, 202 ISP_2100_RISC_CODE, 203 0, 204 0 205 }; 206 #endif 207 208 #ifndef ISP_DISABLE_2200_SUPPORT 209 static struct ispmdvec mdvec_2200 = { 210 isp_pci_rd_isr, 211 isp_pci_rd_reg, 212 isp_pci_wr_reg, 213 isp_pci_mbxdma, 214 isp_pci_dmasetup, 215 isp_pci_dmateardown, 216 isp_pci_reset0, 217 isp_pci_reset1, 218 isp_pci_dumpregs, 219 ISP_2200_RISC_CODE, 220 0, 221 0 222 }; 223 #endif 224 225 #ifndef ISP_DISABLE_2300_SUPPORT 226 static struct ispmdvec mdvec_2300 = { 227 isp_pci_rd_isr_2300, 228 isp_pci_rd_reg, 229 isp_pci_wr_reg, 230 isp_pci_mbxdma, 231 isp_pci_dmasetup, 232 isp_pci_dmateardown, 233 isp_pci_reset0, 234 isp_pci_reset1, 235 isp_pci_dumpregs, 236 ISP_2300_RISC_CODE, 237 0, 238 0 239 }; 240 #endif 241 242 #ifndef ISP_DISABLE_2322_SUPPORT 243 static struct ispmdvec mdvec_2322 = { 244 isp_pci_rd_isr_2300, 245 isp_pci_rd_reg, 246 isp_pci_wr_reg, 247 isp_pci_mbxdma, 248 isp_pci_dmasetup, 249 isp_pci_dmateardown, 250 isp_pci_reset0, 251 isp_pci_reset1, 252 isp_pci_dumpregs, 253 ISP_2322_RISC_CODE, 254 0, 255 0 256 }; 257 #endif 258 259 #ifndef ISP_DISABLE_2400_SUPPORT 260 static struct ispmdvec mdvec_2400 = { 261 isp_pci_rd_isr_2400, 262 isp_pci_rd_reg_2400, 263 isp_pci_wr_reg_2400, 264 isp_pci_mbxdma, 265 isp_pci_dmasetup, 266 isp_pci_dmateardown, 267 isp_pci_reset0, 268 isp_pci_reset1, 269 NULL, 270 ISP_2400_RISC_CODE, 271 0, 272 0 273 }; 274 static struct ispmdvec mdvec_2500 = { 275 isp_pci_rd_isr_2400, 276 isp_pci_rd_reg_2400, 277 isp_pci_wr_reg_2400, 278 isp_pci_mbxdma, 279 isp_pci_dmasetup, 280 isp_pci_dmateardown, 281 isp_pci_reset0, 282 isp_pci_reset1, 283 NULL, 284 ISP_2500_RISC_CODE, 285 0, 286 0 287 }; 288 #endif 289 290 #ifndef PCI_VENDOR_QLOGIC 291 #define PCI_VENDOR_QLOGIC 0x1077 292 #endif 293 294 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 295 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 296 #endif 297 298 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 299 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 300 #endif 301 302 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 303 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 304 #endif 305 306 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 307 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 308 #endif 309 310 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 311 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 312 #endif 313 314 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 315 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 316 #endif 317 318 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 319 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 320 #endif 321 322 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 323 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 324 #endif 325 326 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 327 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 328 #endif 329 330 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 331 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 332 #endif 333 334 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 335 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 336 #endif 337 338 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 339 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 340 #endif 341 342 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 343 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 344 #endif 345 346 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 347 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 348 #endif 349 350 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 351 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 352 #endif 353 354 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 355 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 356 #endif 357 358 359 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 360 361 #define PCI_QLOGIC_ISP1080 \ 362 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 363 364 #define PCI_QLOGIC_ISP10160 \ 365 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 366 367 #define PCI_QLOGIC_ISP12160 \ 368 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 369 370 #define PCI_QLOGIC_ISP1240 \ 371 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 372 373 #define PCI_QLOGIC_ISP1280 \ 374 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 375 376 #define PCI_QLOGIC_ISP2100 \ 377 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 378 379 #define PCI_QLOGIC_ISP2200 \ 380 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 381 382 #define PCI_QLOGIC_ISP2300 \ 383 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 384 385 #define PCI_QLOGIC_ISP2312 \ 386 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 387 388 #define PCI_QLOGIC_ISP2322 \ 389 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 390 391 #define PCI_QLOGIC_ISP2422 \ 392 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 393 394 #define PCI_QLOGIC_ISP2432 \ 395 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 396 397 #define PCI_QLOGIC_ISP2532 \ 398 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 399 400 #define PCI_QLOGIC_ISP6312 \ 401 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 402 403 #define PCI_QLOGIC_ISP6322 \ 404 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 405 406 #define IO_MAP_REG 0x10 407 #define MEM_MAP_REG 0x14 408 #define PCIR_ROMADDR 0x30 409 410 #define PCI_DFLT_LTNCY 0x40 411 #define PCI_DFLT_LNSZ 0x10 412 413 static int isp_pci_probe(device_t, cfdata_t, void *); 414 static void isp_pci_attach(device_t, device_t, void *); 415 416 struct isp_pcisoftc { 417 struct ispsoftc pci_isp; 418 pci_chipset_tag_t pci_pc; 419 pcitag_t pci_tag; 420 bus_space_tag_t pci_st; 421 bus_space_handle_t pci_sh; 422 bus_dmamap_t *pci_xfer_dmap; 423 void * pci_ih; 424 int16_t pci_poff[_NREG_BLKS]; 425 }; 426 427 CFATTACH_DECL(isp_pci, sizeof (struct isp_pcisoftc), 428 isp_pci_probe, isp_pci_attach, NULL, NULL); 429 430 static int 431 isp_pci_probe(device_t parent, cfdata_t match, void *aux) 432 { 433 struct pci_attach_args *pa = aux; 434 switch (pa->pa_id) { 435 #ifndef ISP_DISABLE_1020_SUPPORT 436 case PCI_QLOGIC_ISP: 437 return (1); 438 #endif 439 #ifndef ISP_DISABLE_1080_SUPPORT 440 case PCI_QLOGIC_ISP1080: 441 case PCI_QLOGIC_ISP1240: 442 case PCI_QLOGIC_ISP1280: 443 return (1); 444 #endif 445 #ifndef ISP_DISABLE_12160_SUPPORT 446 case PCI_QLOGIC_ISP10160: 447 case PCI_QLOGIC_ISP12160: 448 return (1); 449 #endif 450 #ifndef ISP_DISABLE_2100_SUPPORT 451 case PCI_QLOGIC_ISP2100: 452 return (1); 453 #endif 454 #ifndef ISP_DISABLE_2200_SUPPORT 455 case PCI_QLOGIC_ISP2200: 456 return (1); 457 #endif 458 #ifndef ISP_DISABLE_2300_SUPPORT 459 case PCI_QLOGIC_ISP2300: 460 case PCI_QLOGIC_ISP2312: 461 case PCI_QLOGIC_ISP6312: 462 #endif 463 #ifndef ISP_DISABLE_2322_SUPPORT 464 case PCI_QLOGIC_ISP2322: 465 case PCI_QLOGIC_ISP6322: 466 return (1); 467 #endif 468 #ifndef ISP_DISABLE_2400_SUPPORT 469 case PCI_QLOGIC_ISP2422: 470 case PCI_QLOGIC_ISP2432: 471 case PCI_QLOGIC_ISP2532: 472 return (1); 473 #endif 474 default: 475 return (0); 476 } 477 } 478 479 static void 480 isp_pci_attach(device_t parent, device_t self, void *aux) 481 { 482 static const char nomem[] = "\n%s: no mem for sdparam table\n"; 483 uint32_t data, rev, linesz = PCI_DFLT_LNSZ; 484 struct pci_attach_args *pa = aux; 485 struct isp_pcisoftc *pcs = device_private(self); 486 struct ispsoftc *isp = &pcs->pci_isp; 487 bus_space_tag_t st, iot, memt; 488 bus_space_handle_t sh, ioh, memh; 489 pci_intr_handle_t ih; 490 pcireg_t mem_type; 491 const char *dstring; 492 const char *intrstr; 493 int ioh_valid, memh_valid; 494 size_t mamt; 495 496 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 497 PCI_MAPREG_TYPE_IO, 0, 498 &iot, &ioh, NULL, NULL) == 0); 499 500 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG); 501 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) { 502 memh_valid = 0; 503 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT && 504 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) { 505 memh_valid = 0; 506 } else { 507 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0, 508 &memt, &memh, NULL, NULL) == 0); 509 } 510 if (memh_valid) { 511 st = memt; 512 sh = memh; 513 } else if (ioh_valid) { 514 st = iot; 515 sh = ioh; 516 } else { 517 printf(": unable to map device registers\n"); 518 return; 519 } 520 dstring = "\n"; 521 522 isp->isp_nchan = 1; 523 mamt = 0; 524 525 pcs->pci_st = st; 526 pcs->pci_sh = sh; 527 pcs->pci_pc = pa->pa_pc; 528 pcs->pci_tag = pa->pa_tag; 529 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 530 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 531 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 532 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 533 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 534 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 535 536 537 #ifndef ISP_DISABLE_1020_SUPPORT 538 if (pa->pa_id == PCI_QLOGIC_ISP) { 539 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n"; 540 isp->isp_mdvec = &mdvec; 541 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 542 mamt = sizeof (sdparam); 543 } 544 #endif 545 #ifndef ISP_DISABLE_1080_SUPPORT 546 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 547 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n"; 548 isp->isp_mdvec = &mdvec_1080; 549 isp->isp_type = ISP_HA_SCSI_1080; 550 mamt = sizeof (sdparam); 551 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 552 ISP1080_DMA_REGS_OFF; 553 } 554 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 555 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n"; 556 isp->isp_mdvec = &mdvec_1080; 557 isp->isp_type = ISP_HA_SCSI_1240; 558 isp->isp_nchan++; 559 mamt = sizeof (sdparam) * 2; 560 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 561 ISP1080_DMA_REGS_OFF; 562 } 563 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 564 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n"; 565 isp->isp_mdvec = &mdvec_1080; 566 isp->isp_type = ISP_HA_SCSI_1280; 567 isp->isp_nchan++; 568 mamt = sizeof (sdparam) * 2; 569 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 570 ISP1080_DMA_REGS_OFF; 571 } 572 #endif 573 #ifndef ISP_DISABLE_12160_SUPPORT 574 if (pa->pa_id == PCI_QLOGIC_ISP10160) { 575 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n"; 576 isp->isp_mdvec = &mdvec_12160; 577 isp->isp_type = ISP_HA_SCSI_10160; 578 mamt = sizeof (sdparam); 579 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 580 ISP1080_DMA_REGS_OFF; 581 } 582 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 583 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n"; 584 isp->isp_mdvec = &mdvec_12160; 585 isp->isp_type = ISP_HA_SCSI_12160; 586 isp->isp_nchan++; 587 mamt = sizeof (sdparam) * 2; 588 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 589 ISP1080_DMA_REGS_OFF; 590 } 591 #endif 592 #ifndef ISP_DISABLE_2100_SUPPORT 593 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 594 dstring = ": QLogic FC-AL HBA\n"; 595 isp->isp_mdvec = &mdvec_2100; 596 isp->isp_type = ISP_HA_FC_2100; 597 mamt = sizeof (fcparam); 598 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 599 PCI_MBOX_REGS2100_OFF; 600 if (rev < 3) { 601 /* 602 * XXX: Need to get the actual revision 603 * XXX: number of the 2100 FB. At any rate, 604 * XXX: lower cache line size for early revision 605 * XXX; boards. 606 */ 607 linesz = 1; 608 } 609 } 610 #endif 611 #ifndef ISP_DISABLE_2200_SUPPORT 612 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 613 dstring = ": QLogic FC-AL and Fabric HBA\n"; 614 isp->isp_mdvec = &mdvec_2200; 615 isp->isp_type = ISP_HA_FC_2200; 616 mamt = sizeof (fcparam); 617 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 618 PCI_MBOX_REGS2100_OFF; 619 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 620 } 621 #endif 622 #ifndef ISP_DISABLE_2300_SUPPORT 623 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 624 pa->pa_id == PCI_QLOGIC_ISP2312 || 625 pa->pa_id == PCI_QLOGIC_ISP6312) { 626 isp->isp_mdvec = &mdvec_2300; 627 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 628 pa->pa_id == PCI_QLOGIC_ISP6312) { 629 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n"; 630 isp->isp_type = ISP_HA_FC_2300; 631 } else { 632 dstring = 633 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n"; 634 isp->isp_port = pa->pa_function; 635 } 636 isp->isp_type = ISP_HA_FC_2312; 637 mamt = sizeof (fcparam); 638 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 639 PCI_MBOX_REGS2300_OFF; 640 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 641 } 642 #endif 643 #ifndef ISP_DISABLE_2322_SUPPORT 644 if (pa->pa_id == PCI_QLOGIC_ISP2322 || 645 pa->pa_id == PCI_QLOGIC_ISP6322) { 646 isp->isp_mdvec = &mdvec_2322; 647 dstring = ": QLogic FC-AL and 2Gbps Fabric PCI-E HBA\n"; 648 isp->isp_type = ISP_HA_FC_2322; 649 isp->isp_port = pa->pa_function; 650 mamt = sizeof (fcparam); 651 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 652 PCI_MBOX_REGS2300_OFF; 653 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 654 } 655 #endif 656 #ifndef ISP_DISABLE_2400_SUPPORT 657 if (pa->pa_id == PCI_QLOGIC_ISP2422 || 658 pa->pa_id == PCI_QLOGIC_ISP2432) { 659 isp->isp_mdvec = &mdvec_2400; 660 if (pa->pa_id == PCI_QLOGIC_ISP2422) { 661 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-X HBA\n"; 662 } else { 663 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-E HBA\n"; 664 } 665 isp->isp_type = ISP_HA_FC_2400; 666 mamt = sizeof (fcparam); 667 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 668 PCI_MBOX_REGS2400_OFF; 669 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 670 } 671 if (pa->pa_id == PCI_QLOGIC_ISP2532) { 672 isp->isp_mdvec = &mdvec_2500; 673 dstring = ": QLogic FC-AL and 8Gbps Fabric PCI-E HBA\n"; 674 isp->isp_type = ISP_HA_FC_2500; 675 mamt = sizeof (fcparam); 676 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 677 PCI_MBOX_REGS2400_OFF; 678 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 679 } 680 #endif 681 if (mamt == 0) { 682 return; 683 } 684 685 isp->isp_param = malloc(mamt, M_DEVBUF, M_NOWAIT); 686 if (isp->isp_param == NULL) { 687 printf(nomem, device_xname(&isp->isp_osinfo.dev)); 688 return; 689 } 690 memset(isp->isp_param, 0, mamt); 691 mamt = sizeof (struct scsipi_channel) * isp->isp_nchan; 692 isp->isp_osinfo.chan = malloc(mamt, M_DEVBUF, M_NOWAIT); 693 if (isp->isp_osinfo.chan == NULL) { 694 free(isp->isp_param, M_DEVBUF); 695 printf(nomem, device_xname(&isp->isp_osinfo.dev)); 696 return; 697 } 698 memset(isp->isp_osinfo.chan, 0, mamt); 699 isp->isp_osinfo.adapter.adapt_nchannels = isp->isp_nchan; 700 701 /* 702 * Set up logging levels. 703 */ 704 #ifdef ISP_LOGDEFAULT 705 isp->isp_dblev = ISP_LOGDEFAULT; 706 #else 707 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 708 if (bootverbose) 709 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 710 #ifdef SCSIDEBUG 711 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2; 712 #endif 713 #endif 714 if (isp->isp_dblev & ISP_LOGCONFIG) { 715 printf("\n"); 716 } else { 717 printf(dstring); 718 } 719 720 isp->isp_dmatag = pa->pa_dmat; 721 isp->isp_revision = rev; 722 723 /* 724 * Make sure that command register set sanely. 725 */ 726 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 727 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 728 729 /* 730 * Not so sure about these- but I think it's important that they get 731 * enabled...... 732 */ 733 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 734 if (IS_2300(isp)) { /* per QLogic errata */ 735 data &= ~PCI_COMMAND_INVALIDATE_ENABLE; 736 } 737 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 738 739 /* 740 * Make sure that the latency timer, cache line size, 741 * and ROM is disabled. 742 */ 743 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 744 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 745 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 746 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 747 data |= (linesz << PCI_CACHELINE_SHIFT); 748 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 749 750 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 751 data &= ~1; 752 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 753 754 if (pci_intr_map(pa, &ih)) { 755 aprint_error_dev(&isp->isp_osinfo.dev, "couldn't map interrupt\n"); 756 free(isp->isp_param, M_DEVBUF); 757 free(isp->isp_osinfo.chan, M_DEVBUF); 758 return; 759 } 760 intrstr = pci_intr_string(pa->pa_pc, ih); 761 if (intrstr == NULL) 762 intrstr = "<I dunno>"; 763 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 764 isp_pci_intr, isp); 765 if (pcs->pci_ih == NULL) { 766 aprint_error_dev(&isp->isp_osinfo.dev, "couldn't establish interrupt at %s\n", 767 intrstr); 768 free(isp->isp_param, M_DEVBUF); 769 free(isp->isp_osinfo.chan, M_DEVBUF); 770 return; 771 } 772 773 printf("%s: interrupting at %s\n", device_xname(&isp->isp_osinfo.dev), intrstr); 774 775 isp->isp_confopts = self->dv_cfdata->cf_flags; 776 ISP_LOCK(isp); 777 isp_reset(isp, 1); 778 if (isp->isp_state != ISP_RESETSTATE) { 779 ISP_UNLOCK(isp); 780 free(isp->isp_param, M_DEVBUF); 781 free(isp->isp_osinfo.chan, M_DEVBUF); 782 return; 783 } 784 isp_init(isp); 785 if (isp->isp_state != ISP_INITSTATE) { 786 isp_uninit(isp); 787 ISP_UNLOCK(isp); 788 free(isp->isp_param, M_DEVBUF); 789 free(isp->isp_osinfo.chan, M_DEVBUF); 790 return; 791 } 792 /* 793 * Do platform attach. 794 */ 795 ISP_UNLOCK(isp); 796 isp_attach(isp); 797 } 798 799 #define IspVirt2Off(a, x) \ 800 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 801 _BLK_REG_SHFT] + ((x) & 0xff)) 802 803 #define BXR2(pcs, off) \ 804 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 805 #define BXW2(pcs, off, v) \ 806 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 807 #define BXR4(pcs, off) \ 808 bus_space_read_4(pcs->pci_st, pcs->pci_sh, off) 809 #define BXW4(pcs, off, v) \ 810 bus_space_write_4(pcs->pci_st, pcs->pci_sh, off, v) 811 812 813 static int 814 isp_pci_rd_debounced(struct ispsoftc *isp, int off, uint16_t *rp) 815 { 816 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 817 uint16_t val0, val1; 818 int i = 0; 819 820 do { 821 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 822 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 823 } while (val0 != val1 && ++i < 1000); 824 if (val0 != val1) { 825 return (1); 826 } 827 *rp = val0; 828 return (0); 829 } 830 831 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 832 !defined(ISP_DISABLE_2200_SUPPORT) && \ 833 !defined(ISP_DISABLE_1020_SUPPORT) && \ 834 !defined(ISP_DISABLE_1080_SUPPORT) && \ 835 !defined(ISP_DISABLE_12160_SUPPORT) 836 static int 837 isp_pci_rd_isr(struct ispsoftc *isp, uint32_t *isrp, 838 uint16_t *semap, uint16_t *mbp) 839 { 840 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 841 uint16_t isr, sema; 842 843 if (IS_2100(isp)) { 844 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 845 return (0); 846 } 847 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 848 return (0); 849 } 850 } else { 851 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 852 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 853 } 854 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 855 isr &= INT_PENDING_MASK(isp); 856 sema &= BIU_SEMA_LOCK; 857 if (isr == 0 && sema == 0) { 858 return (0); 859 } 860 *isrp = isr; 861 if ((*semap = sema) != 0) { 862 if (IS_2100(isp)) { 863 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 864 return (0); 865 } 866 } else { 867 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 868 } 869 } 870 return (1); 871 } 872 #endif 873 874 #if !(defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_2322_SUPPORT)) 875 static int 876 isp_pci_rd_isr_2300(struct ispsoftc *isp, uint32_t *isrp, 877 uint16_t *semap, uint16_t *mbox0p) 878 { 879 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 880 uint32_t r2hisr; 881 882 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 883 *isrp = 0; 884 return (0); 885 } 886 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 887 IspVirt2Off(pcs, BIU_R2HSTSLO)); 888 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 889 if ((r2hisr & BIU_R2HST_INTR) == 0) { 890 *isrp = 0; 891 return (0); 892 } 893 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 894 case ISPR2HST_ROM_MBX_OK: 895 case ISPR2HST_ROM_MBX_FAIL: 896 case ISPR2HST_MBX_OK: 897 case ISPR2HST_MBX_FAIL: 898 case ISPR2HST_ASYNC_EVENT: 899 *isrp = r2hisr & 0xffff; 900 *mbox0p = (r2hisr >> 16); 901 *semap = 1; 902 return (1); 903 case ISPR2HST_RIO_16: 904 *isrp = r2hisr & 0xffff; 905 *mbox0p = ASYNC_RIO1; 906 *semap = 1; 907 return (1); 908 case ISPR2HST_FPOST: 909 *isrp = r2hisr & 0xffff; 910 *mbox0p = ASYNC_CMD_CMPLT; 911 *semap = 1; 912 return (1); 913 case ISPR2HST_FPOST_CTIO: 914 *isrp = r2hisr & 0xffff; 915 *mbox0p = ASYNC_CTIO_DONE; 916 *semap = 1; 917 return (1); 918 case ISPR2HST_RSPQ_UPDATE: 919 *isrp = r2hisr & 0xffff; 920 *mbox0p = 0; 921 *semap = 0; 922 return (1); 923 default: 924 return (0); 925 } 926 } 927 #endif 928 929 #ifndef ISP_DISABLE_2400_SUPPORT 930 static int 931 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, 932 uint16_t *semap, uint16_t *mbox0p) 933 { 934 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 935 uint32_t r2hisr; 936 937 r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU2400_R2HSTSLO)); 938 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 939 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 940 *isrp = 0; 941 return (0); 942 } 943 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 944 case ISP2400R2HST_ROM_MBX_OK: 945 case ISP2400R2HST_ROM_MBX_FAIL: 946 case ISP2400R2HST_MBX_OK: 947 case ISP2400R2HST_MBX_FAIL: 948 case ISP2400R2HST_ASYNC_EVENT: 949 *isrp = r2hisr & 0xffff; 950 *mbox0p = (r2hisr >> 16); 951 *semap = 1; 952 return (1); 953 case ISP2400R2HST_RSPQ_UPDATE: 954 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 955 case ISP2400R2HST_ATIO_RQST_UPDATE: 956 *isrp = r2hisr & 0xffff; 957 *mbox0p = 0; 958 *semap = 0; 959 return (1); 960 default: 961 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 962 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 963 return (0); 964 } 965 } 966 967 static uint32_t 968 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 969 { 970 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 971 uint32_t rv; 972 int block = regoff & _BLK_REG_MASK; 973 974 switch (block) { 975 case BIU_BLOCK: 976 break; 977 case MBOX_BLOCK: 978 return (BXR2(pcs, IspVirt2Off(pcs, regoff))); 979 case SXP_BLOCK: 980 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 981 return (0xffffffff); 982 case RISC_BLOCK: 983 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 984 return (0xffffffff); 985 case DMA_BLOCK: 986 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 987 return (0xffffffff); 988 default: 989 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 990 return (0xffffffff); 991 } 992 993 994 switch (regoff) { 995 case BIU2400_FLASH_ADDR: 996 case BIU2400_FLASH_DATA: 997 case BIU2400_ICR: 998 case BIU2400_ISR: 999 case BIU2400_CSR: 1000 case BIU2400_REQINP: 1001 case BIU2400_REQOUTP: 1002 case BIU2400_RSPINP: 1003 case BIU2400_RSPOUTP: 1004 case BIU2400_PRI_REQINP: 1005 case BIU2400_PRI_REQOUTP: 1006 case BIU2400_ATIO_RSPINP: 1007 case BIU2400_ATIO_RSPOUTP: 1008 case BIU2400_HCCR: 1009 case BIU2400_GPIOD: 1010 case BIU2400_GPIOE: 1011 case BIU2400_HSEMA: 1012 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1013 break; 1014 case BIU2400_R2HSTSLO: 1015 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1016 break; 1017 case BIU2400_R2HSTSHI: 1018 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)) >> 16; 1019 break; 1020 default: 1021 isp_prt(isp, ISP_LOGERR, 1022 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1023 rv = 0xffffffff; 1024 break; 1025 } 1026 return (rv); 1027 } 1028 1029 static void 1030 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1031 { 1032 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1033 int block = regoff & _BLK_REG_MASK; 1034 volatile int junk; 1035 1036 switch (block) { 1037 case BIU_BLOCK: 1038 break; 1039 case MBOX_BLOCK: 1040 BXW2(pcs, IspVirt2Off(pcs, regoff), val); 1041 junk = BXR2(pcs, IspVirt2Off(pcs, regoff)); 1042 return; 1043 case SXP_BLOCK: 1044 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1045 return; 1046 case RISC_BLOCK: 1047 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1048 return; 1049 case DMA_BLOCK: 1050 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1051 return; 1052 default: 1053 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1054 regoff); 1055 break; 1056 } 1057 1058 switch (regoff) { 1059 case BIU2400_FLASH_ADDR: 1060 case BIU2400_FLASH_DATA: 1061 case BIU2400_ICR: 1062 case BIU2400_ISR: 1063 case BIU2400_CSR: 1064 case BIU2400_REQINP: 1065 case BIU2400_REQOUTP: 1066 case BIU2400_RSPINP: 1067 case BIU2400_RSPOUTP: 1068 case BIU2400_PRI_REQINP: 1069 case BIU2400_PRI_REQOUTP: 1070 case BIU2400_ATIO_RSPINP: 1071 case BIU2400_ATIO_RSPOUTP: 1072 case BIU2400_HCCR: 1073 case BIU2400_GPIOD: 1074 case BIU2400_GPIOE: 1075 case BIU2400_HSEMA: 1076 BXW4(pcs, IspVirt2Off(pcs, regoff), val); 1077 junk = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1078 break; 1079 default: 1080 isp_prt(isp, ISP_LOGERR, 1081 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1082 break; 1083 } 1084 } 1085 #endif 1086 1087 static uint32_t 1088 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 1089 { 1090 uint32_t rv; 1091 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1092 int oldconf = 0; 1093 1094 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1095 /* 1096 * We will assume that someone has paused the RISC processor. 1097 */ 1098 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1099 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1100 oldconf | BIU_PCI_CONF1_SXP); 1101 } 1102 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1103 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1104 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1105 } 1106 return (rv); 1107 } 1108 1109 static void 1110 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, uint32_t val) 1111 { 1112 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1113 int oldconf = 0; 1114 1115 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1116 /* 1117 * We will assume that someone has paused the RISC processor. 1118 */ 1119 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1120 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1121 oldconf | BIU_PCI_CONF1_SXP); 1122 } 1123 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1124 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1125 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1126 } 1127 } 1128 1129 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 1130 static uint32_t 1131 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 1132 { 1133 uint16_t rv, oc = 0; 1134 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1135 1136 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1137 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1138 uint16_t tc; 1139 /* 1140 * We will assume that someone has paused the RISC processor. 1141 */ 1142 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1143 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1144 if (regoff & SXP_BANK1_SELECT) 1145 tc |= BIU_PCI1080_CONF1_SXP1; 1146 else 1147 tc |= BIU_PCI1080_CONF1_SXP0; 1148 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1149 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1150 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1151 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1152 oc | BIU_PCI1080_CONF1_DMA); 1153 } 1154 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1155 if (oc) { 1156 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1157 } 1158 return (rv); 1159 } 1160 1161 static void 1162 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, uint32_t val) 1163 { 1164 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1165 int oc = 0; 1166 1167 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1168 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1169 uint16_t tc; 1170 /* 1171 * We will assume that someone has paused the RISC processor. 1172 */ 1173 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1174 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1175 if (regoff & SXP_BANK1_SELECT) 1176 tc |= BIU_PCI1080_CONF1_SXP1; 1177 else 1178 tc |= BIU_PCI1080_CONF1_SXP0; 1179 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1180 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1181 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1182 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1183 oc | BIU_PCI1080_CONF1_DMA); 1184 } 1185 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1186 if (oc) { 1187 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1188 } 1189 } 1190 #endif 1191 1192 static int 1193 isp_pci_mbxdma(struct ispsoftc *isp) 1194 { 1195 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1196 bus_dma_tag_t dmat = isp->isp_dmatag; 1197 bus_dma_segment_t sg; 1198 bus_size_t len, dbound; 1199 fcparam *fcp; 1200 int rs, i; 1201 1202 if (isp->isp_rquest_dma) /* been here before? */ 1203 return (0); 1204 1205 if (isp->isp_type <= ISP_HA_SCSI_1040B) { 1206 dbound = 1 << 24; 1207 } else { 1208 /* 1209 * For 32-bit PCI DMA, the range is 32 bits or zero :-) 1210 */ 1211 dbound = 0; 1212 } 1213 len = isp->isp_maxcmds * sizeof (XS_T *); 1214 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 1215 if (isp->isp_xflist == NULL) { 1216 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 1217 return (1); 1218 } 1219 memset(isp->isp_xflist, 0, len); 1220 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 1221 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1222 if (pcs->pci_xfer_dmap == NULL) { 1223 free(isp->isp_xflist, M_DEVBUF); 1224 isp->isp_xflist = NULL; 1225 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array"); 1226 return (1); 1227 } 1228 for (i = 0; i < isp->isp_maxcmds; i++) { 1229 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 1230 MAXPHYS, dbound, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 1231 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps"); 1232 break; 1233 } 1234 } 1235 if (i < isp->isp_maxcmds) { 1236 while (--i >= 0) { 1237 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1238 } 1239 free(isp->isp_xflist, M_DEVBUF); 1240 free(pcs->pci_xfer_dmap, M_DEVBUF); 1241 isp->isp_xflist = NULL; 1242 pcs->pci_xfer_dmap = NULL; 1243 return (1); 1244 } 1245 1246 /* 1247 * Allocate and map the request queue. 1248 */ 1249 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1250 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 0)) { 1251 goto dmafail; 1252 } 1253 if (bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 1254 (void *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1255 goto dmafail; 1256 } 1257 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1258 &isp->isp_rqdmap)) { 1259 goto dmafail; 1260 } 1261 if (bus_dmamap_load(dmat, isp->isp_rqdmap, isp->isp_rquest, len, NULL, 1262 BUS_DMA_NOWAIT)) { 1263 goto dmafail; 1264 } 1265 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 1266 1267 /* 1268 * Allocate and map the result queue. 1269 */ 1270 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1271 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 1272 BUS_DMA_NOWAIT)) { 1273 goto dmafail; 1274 } 1275 if (bus_dmamem_map(dmat, &sg, rs, len, 1276 (void *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1277 goto dmafail; 1278 } 1279 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1280 &isp->isp_rsdmap)) { 1281 goto dmafail; 1282 } 1283 if (bus_dmamap_load(dmat, isp->isp_rsdmap, isp->isp_result, len, NULL, 1284 BUS_DMA_NOWAIT)) { 1285 goto dmafail; 1286 } 1287 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 1288 1289 if (IS_SCSI(isp)) { 1290 return (0); 1291 } 1292 1293 /* 1294 * Allocate and map an FC scratch area 1295 */ 1296 fcp = isp->isp_param; 1297 len = ISP_FC_SCRLEN; 1298 if (bus_dmamem_alloc(dmat, len, sizeof (uint64_t), 0, &sg, 1, &rs, 1299 BUS_DMA_NOWAIT)) { 1300 goto dmafail; 1301 } 1302 if (bus_dmamem_map(dmat, &sg, rs, len, 1303 (void *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1304 goto dmafail; 1305 } 1306 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1307 &isp->isp_scdmap)) { 1308 goto dmafail; 1309 } 1310 if (bus_dmamap_load(dmat, isp->isp_scdmap, fcp->isp_scratch, len, NULL, 1311 BUS_DMA_NOWAIT)) { 1312 goto dmafail; 1313 } 1314 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 1315 return (0); 1316 dmafail: 1317 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure"); 1318 for (i = 0; i < isp->isp_maxcmds; i++) { 1319 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1320 } 1321 free(isp->isp_xflist, M_DEVBUF); 1322 free(pcs->pci_xfer_dmap, M_DEVBUF); 1323 isp->isp_xflist = NULL; 1324 pcs->pci_xfer_dmap = NULL; 1325 return (1); 1326 } 1327 1328 static int 1329 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, void *arg) 1330 { 1331 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1332 ispreq_t *rq = arg; 1333 bus_dmamap_t dmap; 1334 bus_dma_segment_t *dm_segs; 1335 uint32_t nsegs; 1336 isp_ddir_t ddir; 1337 1338 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 1339 if (xs->datalen == 0) { 1340 ddir = ISP_NOXFR; 1341 nsegs = 0; 1342 dm_segs = NULL; 1343 } else { 1344 int error; 1345 uint32_t flag, flg2; 1346 1347 if (sizeof (bus_addr_t) > 4) { 1348 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1349 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1350 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1351 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1352 } 1353 } 1354 1355 if (xs->xs_control & XS_CTL_DATA_IN) { 1356 flg2 = BUS_DMASYNC_PREREAD; 1357 flag = BUS_DMA_READ; 1358 ddir = ISP_FROM_DEVICE; 1359 } else { 1360 flg2 = BUS_DMASYNC_PREWRITE; 1361 flag = BUS_DMA_WRITE; 1362 ddir = ISP_TO_DEVICE; 1363 } 1364 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 1365 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | flag); 1366 if (error) { 1367 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", error); 1368 XS_SETERR(xs, HBA_BOTCH); 1369 if (error == EAGAIN || error == ENOMEM) { 1370 return (CMD_EAGAIN); 1371 } else { 1372 return (CMD_COMPLETE); 1373 } 1374 } 1375 dm_segs = dmap->dm_segs; 1376 nsegs = dmap->dm_nsegs; 1377 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, flg2); 1378 } 1379 1380 if (isp_send_cmd(isp, rq, dm_segs, nsegs, xs->datalen, ddir) != CMD_QUEUED) { 1381 return (CMD_EAGAIN); 1382 } else { 1383 return (CMD_QUEUED); 1384 } 1385 } 1386 1387 static int 1388 isp_pci_intr(void *arg) 1389 { 1390 uint32_t isr; 1391 uint16_t sema, mbox; 1392 struct ispsoftc *isp = arg; 1393 1394 isp->isp_intcnt++; 1395 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1396 isp->isp_intbogus++; 1397 return (0); 1398 } else { 1399 isp->isp_osinfo.onintstack = 1; 1400 isp_intr(isp, isr, sema, mbox); 1401 isp->isp_osinfo.onintstack = 0; 1402 return (1); 1403 } 1404 } 1405 1406 static void 1407 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, uint32_t handle) 1408 { 1409 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1410 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 1411 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1412 xs->xs_control & XS_CTL_DATA_IN ? 1413 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1414 bus_dmamap_unload(isp->isp_dmatag, dmap); 1415 } 1416 1417 static void 1418 isp_pci_reset0(ispsoftc_t *isp) 1419 { 1420 ISP_DISABLE_INTS(isp); 1421 } 1422 1423 static void 1424 isp_pci_reset1(ispsoftc_t *isp) 1425 { 1426 if (!IS_24XX(isp)) { 1427 /* Make sure the BIOS is disabled */ 1428 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1429 } 1430 /* and enable interrupts */ 1431 ISP_ENABLE_INTS(isp); 1432 } 1433 1434 static void 1435 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1436 { 1437 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1438 if (msg) 1439 printf("%s: %s\n", device_xname(&isp->isp_osinfo.dev), msg); 1440 if (IS_SCSI(isp)) 1441 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1442 else 1443 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1444 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1445 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1446 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1447 1448 1449 if (IS_SCSI(isp)) { 1450 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1451 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1452 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1453 ISP_READ(isp, CDMA_FIFO_STS)); 1454 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1455 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1456 ISP_READ(isp, DDMA_FIFO_STS)); 1457 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1458 ISP_READ(isp, SXP_INTERRUPT), 1459 ISP_READ(isp, SXP_GROSS_ERR), 1460 ISP_READ(isp, SXP_PINS_CTRL)); 1461 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1462 } 1463 printf(" mbox regs: %x %x %x %x %x\n", 1464 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1465 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1466 ISP_READ(isp, OUTMAILBOX4)); 1467 printf(" PCI Status Command/Status=%x\n", 1468 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1469 } 1470
Indexes created Fri Sep 26 20:09:58 GMT 2025