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isp_pci.c revision 1.113
      1 /* $NetBSD: isp_pci.c,v 1.113 2010/11/13 13:52:07 uebayasi Exp $ */
      2 /*
      3  * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration
      4  * All rights reserved.
      5  *
      6  * Additional Copyright (C) 2000-2007 by Matthew Jacob
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. The name of the author may not be used to endorse or promote products
     17  *    derived from this software without specific prior written permission
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 /*
     32  * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
     33  */
     34 
     35 /*
     36  * 24XX 4Gb material support provided by MetrumRG Associates.
     37  * Many thanks are due to them.
     38  */
     39 
     40 #include <sys/cdefs.h>
     41 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.113 2010/11/13 13:52:07 uebayasi Exp $");
     42 
     43 #include <dev/ic/isp_netbsd.h>
     44 #include <dev/pci/pcireg.h>
     45 #include <dev/pci/pcivar.h>
     46 #include <dev/pci/pcidevs.h>
     47 #include <sys/reboot.h>
     48 
     49 static uint32_t isp_pci_rd_reg(struct ispsoftc *, int);
     50 static void isp_pci_wr_reg(struct ispsoftc *, int, uint32_t);
     51 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
     52 static uint32_t isp_pci_rd_reg_1080(struct ispsoftc *, int);
     53 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, uint32_t);
     54 #endif
     55 #if !defined(ISP_DISABLE_2100_SUPPORT) && \
     56 	 !defined(ISP_DISABLE_2200_SUPPORT) && \
     57 	 !defined(ISP_DISABLE_1020_SUPPORT) && \
     58 	 !defined(ISP_DISABLE_1080_SUPPORT) && \
     59 	 !defined(ISP_DISABLE_12160_SUPPORT)
     60 static int
     61 isp_pci_rd_isr(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
     62 #endif
     63 #if !(defined(ISP_DISABLE_2300_SUPPORT) && defined(ISP_DISABLE_2322_SUPPORT))
     64 static int
     65 isp_pci_rd_isr_2300(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
     66 #endif
     67 #if !defined(ISP_DISABLE_2400_SUPPORT)
     68 static uint32_t isp_pci_rd_reg_2400(struct ispsoftc *, int);
     69 static void isp_pci_wr_reg_2400(struct ispsoftc *, int, uint32_t);
     70 static int
     71 isp_pci_rd_isr_2400(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
     72 #endif
     73 static int isp_pci_mbxdma(struct ispsoftc *);
     74 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, void *);
     75 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, uint32_t);
     76 static void isp_pci_reset0(struct ispsoftc *);
     77 static void isp_pci_reset1(struct ispsoftc *);
     78 static void isp_pci_dumpregs(struct ispsoftc *, const char *);
     79 static int isp_pci_intr(void *);
     80 
     81 #if	defined(ISP_DISABLE_1020_SUPPORT) || defined(ISP_DISABLE_FW)
     82 #define	ISP_1040_RISC_CODE	NULL
     83 #else
     84 #define	ISP_1040_RISC_CODE	(const uint16_t *) isp_1040_risc_code
     85 #include <dev/microcode/isp/asm_1040.h>
     86 #endif
     87 
     88 #if	defined(ISP_DISABLE_1080_SUPPORT) || defined(ISP_DISABLE_FW)
     89 #define	ISP_1080_RISC_CODE	NULL
     90 #else
     91 #define	ISP_1080_RISC_CODE	(const uint16_t *) isp_1080_risc_code
     92 #include <dev/microcode/isp/asm_1080.h>
     93 #endif
     94 
     95 #if	defined(ISP_DISABLE_12160_SUPPORT) || defined(ISP_DISABLE_FW)
     96 #define	ISP_12160_RISC_CODE	NULL
     97 #else
     98 #define	ISP_12160_RISC_CODE	(const uint16_t *) isp_12160_risc_code
     99 #include <dev/microcode/isp/asm_12160.h>
    100 #endif
    101 
    102 #if	defined(ISP_DISABLE_2100_SUPPORT) || defined(ISP_DISABLE_FW)
    103 #define	ISP_2100_RISC_CODE	NULL
    104 #else
    105 #define	ISP_2100_RISC_CODE	(const uint16_t *) isp_2100_risc_code
    106 #include <dev/microcode/isp/asm_2100.h>
    107 #endif
    108 
    109 #if	defined(ISP_DISABLE_2200_SUPPORT) || defined(ISP_DISABLE_FW)
    110 #define	ISP_2200_RISC_CODE	NULL
    111 #else
    112 #define	ISP_2200_RISC_CODE	(const uint16_t *) isp_2200_risc_code
    113 #include <dev/microcode/isp/asm_2200.h>
    114 #endif
    115 
    116 #if	defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_FW)
    117 #define	ISP_2300_RISC_CODE	NULL
    118 #else
    119 #define	ISP_2300_RISC_CODE	(const uint16_t *) isp_2300_risc_code
    120 #include <dev/microcode/isp/asm_2300.h>
    121 #endif
    122 #if	defined(ISP_DISABLE_2322_SUPPORT) || defined(ISP_DISABLE_FW)
    123 #define	ISP_2322_RISC_CODE	NULL
    124 #else
    125 #define	ISP_2322_RISC_CODE	(const uint16_t *) isp_2322_risc_code
    126 #include <dev/microcode/isp/asm_2322.h>
    127 #endif
    128 
    129 #if	defined(ISP_DISABLE_2400_SUPPORT) || defined(ISP_DISABLE_FW)
    130 #define	ISP_2400_RISC_CODE	NULL
    131 #define	ISP_2500_RISC_CODE	NULL
    132 #else
    133 #define	ISP_2400_RISC_CODE	(const uint32_t *) isp_2400_risc_code
    134 #define	ISP_2500_RISC_CODE	(const uint32_t *) isp_2500_risc_code
    135 #include <dev/microcode/isp/asm_2400.h>
    136 #include <dev/microcode/isp/asm_2500.h>
    137 #endif
    138 
    139 #ifndef	ISP_DISABLE_1020_SUPPORT
    140 static struct ispmdvec mdvec = {
    141 	isp_pci_rd_isr,
    142 	isp_pci_rd_reg,
    143 	isp_pci_wr_reg,
    144 	isp_pci_mbxdma,
    145 	isp_pci_dmasetup,
    146 	isp_pci_dmateardown,
    147 	isp_pci_reset0,
    148 	isp_pci_reset1,
    149 	isp_pci_dumpregs,
    150 	ISP_1040_RISC_CODE,
    151 	BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
    152 	0
    153 };
    154 #endif
    155 
    156 #ifndef	ISP_DISABLE_1080_SUPPORT
    157 static struct ispmdvec mdvec_1080 = {
    158 	isp_pci_rd_isr,
    159 	isp_pci_rd_reg_1080,
    160 	isp_pci_wr_reg_1080,
    161 	isp_pci_mbxdma,
    162 	isp_pci_dmasetup,
    163 	isp_pci_dmateardown,
    164 	isp_pci_reset0,
    165 	isp_pci_reset1,
    166 	isp_pci_dumpregs,
    167 	ISP_1080_RISC_CODE,
    168 	BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
    169 	0
    170 };
    171 #endif
    172 
    173 #ifndef	ISP_DISABLE_12160_SUPPORT
    174 static struct ispmdvec mdvec_12160 = {
    175 	isp_pci_rd_isr,
    176 	isp_pci_rd_reg_1080,
    177 	isp_pci_wr_reg_1080,
    178 	isp_pci_mbxdma,
    179 	isp_pci_dmasetup,
    180 	isp_pci_dmateardown,
    181 	isp_pci_reset0,
    182 	isp_pci_reset1,
    183 	isp_pci_dumpregs,
    184 	ISP_12160_RISC_CODE,
    185 	BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
    186 	0
    187 };
    188 #endif
    189 
    190 #ifndef	ISP_DISABLE_2100_SUPPORT
    191 static struct ispmdvec mdvec_2100 = {
    192 	isp_pci_rd_isr,
    193 	isp_pci_rd_reg,
    194 	isp_pci_wr_reg,
    195 	isp_pci_mbxdma,
    196 	isp_pci_dmasetup,
    197 	isp_pci_dmateardown,
    198 	isp_pci_reset0,
    199 	isp_pci_reset1,
    200 	isp_pci_dumpregs,
    201 	ISP_2100_RISC_CODE,
    202 	0,
    203 	0
    204 };
    205 #endif
    206 
    207 #ifndef	ISP_DISABLE_2200_SUPPORT
    208 static struct ispmdvec mdvec_2200 = {
    209 	isp_pci_rd_isr,
    210 	isp_pci_rd_reg,
    211 	isp_pci_wr_reg,
    212 	isp_pci_mbxdma,
    213 	isp_pci_dmasetup,
    214 	isp_pci_dmateardown,
    215 	isp_pci_reset0,
    216 	isp_pci_reset1,
    217 	isp_pci_dumpregs,
    218 	ISP_2200_RISC_CODE,
    219 	0,
    220 	0
    221 };
    222 #endif
    223 
    224 #ifndef ISP_DISABLE_2300_SUPPORT
    225 static struct ispmdvec mdvec_2300 = {
    226 	isp_pci_rd_isr_2300,
    227 	isp_pci_rd_reg,
    228 	isp_pci_wr_reg,
    229 	isp_pci_mbxdma,
    230 	isp_pci_dmasetup,
    231 	isp_pci_dmateardown,
    232 	isp_pci_reset0,
    233 	isp_pci_reset1,
    234 	isp_pci_dumpregs,
    235 	ISP_2300_RISC_CODE,
    236 	0,
    237 	0
    238 };
    239 #endif
    240 
    241 #ifndef ISP_DISABLE_2322_SUPPORT
    242 static struct ispmdvec mdvec_2322 = {
    243 	isp_pci_rd_isr_2300,
    244 	isp_pci_rd_reg,
    245 	isp_pci_wr_reg,
    246 	isp_pci_mbxdma,
    247 	isp_pci_dmasetup,
    248 	isp_pci_dmateardown,
    249 	isp_pci_reset0,
    250 	isp_pci_reset1,
    251 	isp_pci_dumpregs,
    252 	ISP_2322_RISC_CODE,
    253 	0,
    254 	0
    255 };
    256 #endif
    257 
    258 #ifndef	ISP_DISABLE_2400_SUPPORT
    259 static struct ispmdvec mdvec_2400 = {
    260 	isp_pci_rd_isr_2400,
    261 	isp_pci_rd_reg_2400,
    262 	isp_pci_wr_reg_2400,
    263 	isp_pci_mbxdma,
    264 	isp_pci_dmasetup,
    265 	isp_pci_dmateardown,
    266 	isp_pci_reset0,
    267 	isp_pci_reset1,
    268 	NULL,
    269 	ISP_2400_RISC_CODE,
    270 	0,
    271 	0
    272 };
    273 static struct ispmdvec mdvec_2500 = {
    274 	isp_pci_rd_isr_2400,
    275 	isp_pci_rd_reg_2400,
    276 	isp_pci_wr_reg_2400,
    277 	isp_pci_mbxdma,
    278 	isp_pci_dmasetup,
    279 	isp_pci_dmateardown,
    280 	isp_pci_reset0,
    281 	isp_pci_reset1,
    282 	NULL,
    283 	ISP_2500_RISC_CODE,
    284 	0,
    285 	0
    286 };
    287 #endif
    288 
    289 #ifndef	PCI_VENDOR_QLOGIC
    290 #define	PCI_VENDOR_QLOGIC	0x1077
    291 #endif
    292 
    293 #ifndef	PCI_PRODUCT_QLOGIC_ISP1020
    294 #define	PCI_PRODUCT_QLOGIC_ISP1020	0x1020
    295 #endif
    296 
    297 #ifndef	PCI_PRODUCT_QLOGIC_ISP1080
    298 #define	PCI_PRODUCT_QLOGIC_ISP1080	0x1080
    299 #endif
    300 
    301 #ifndef	PCI_PRODUCT_QLOGIC_ISP1240
    302 #define	PCI_PRODUCT_QLOGIC_ISP1240	0x1240
    303 #endif
    304 
    305 #ifndef	PCI_PRODUCT_QLOGIC_ISP1280
    306 #define	PCI_PRODUCT_QLOGIC_ISP1280	0x1280
    307 #endif
    308 
    309 #ifndef	PCI_PRODUCT_QLOGIC_ISP10160
    310 #define	PCI_PRODUCT_QLOGIC_ISP10160	0x1016
    311 #endif
    312 
    313 #ifndef	PCI_PRODUCT_QLOGIC_ISP12160
    314 #define	PCI_PRODUCT_QLOGIC_ISP12160	0x1216
    315 #endif
    316 
    317 #ifndef	PCI_PRODUCT_QLOGIC_ISP2100
    318 #define	PCI_PRODUCT_QLOGIC_ISP2100	0x2100
    319 #endif
    320 
    321 #ifndef	PCI_PRODUCT_QLOGIC_ISP2200
    322 #define	PCI_PRODUCT_QLOGIC_ISP2200	0x2200
    323 #endif
    324 
    325 #ifndef	PCI_PRODUCT_QLOGIC_ISP2300
    326 #define	PCI_PRODUCT_QLOGIC_ISP2300	0x2300
    327 #endif
    328 
    329 #ifndef	PCI_PRODUCT_QLOGIC_ISP2312
    330 #define	PCI_PRODUCT_QLOGIC_ISP2312	0x2312
    331 #endif
    332 
    333 #ifndef	PCI_PRODUCT_QLOGIC_ISP2322
    334 #define	PCI_PRODUCT_QLOGIC_ISP2322	0x2322
    335 #endif
    336 
    337 #ifndef	PCI_PRODUCT_QLOGIC_ISP2422
    338 #define	PCI_PRODUCT_QLOGIC_ISP2422	0x2422
    339 #endif
    340 
    341 #ifndef	PCI_PRODUCT_QLOGIC_ISP2432
    342 #define	PCI_PRODUCT_QLOGIC_ISP2432	0x2432
    343 #endif
    344 
    345 #ifndef	PCI_PRODUCT_QLOGIC_ISP2532
    346 #define	PCI_PRODUCT_QLOGIC_ISP2532	0x2532
    347 #endif
    348 
    349 #ifndef	PCI_PRODUCT_QLOGIC_ISP6312
    350 #define	PCI_PRODUCT_QLOGIC_ISP6312	0x6312
    351 #endif
    352 
    353 #ifndef	PCI_PRODUCT_QLOGIC_ISP6322
    354 #define	PCI_PRODUCT_QLOGIC_ISP6322	0x6322
    355 #endif
    356 
    357 
    358 #define	PCI_QLOGIC_ISP	((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
    359 
    360 #define	PCI_QLOGIC_ISP1080	\
    361 	((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
    362 
    363 #define	PCI_QLOGIC_ISP10160	\
    364 	((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC)
    365 
    366 #define	PCI_QLOGIC_ISP12160	\
    367 	((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
    368 
    369 #define	PCI_QLOGIC_ISP1240	\
    370 	((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
    371 
    372 #define	PCI_QLOGIC_ISP1280	\
    373 	((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
    374 
    375 #define	PCI_QLOGIC_ISP2100	\
    376 	((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
    377 
    378 #define	PCI_QLOGIC_ISP2200	\
    379 	((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
    380 
    381 #define	PCI_QLOGIC_ISP2300	\
    382 	((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC)
    383 
    384 #define	PCI_QLOGIC_ISP2312	\
    385 	((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC)
    386 
    387 #define	PCI_QLOGIC_ISP2322	\
    388 	((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC)
    389 
    390 #define	PCI_QLOGIC_ISP2422	\
    391 	((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC)
    392 
    393 #define	PCI_QLOGIC_ISP2432	\
    394 	((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC)
    395 
    396 #define	PCI_QLOGIC_ISP2532	\
    397 	((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC)
    398 
    399 #define	PCI_QLOGIC_ISP6312	\
    400 	((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC)
    401 
    402 #define	PCI_QLOGIC_ISP6322	\
    403 	((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC)
    404 
    405 #define	IO_MAP_REG	0x10
    406 #define	MEM_MAP_REG	0x14
    407 #define	PCIR_ROMADDR	0x30
    408 
    409 #define	PCI_DFLT_LTNCY	0x40
    410 #define	PCI_DFLT_LNSZ	0x10
    411 
    412 static int isp_pci_probe(device_t, cfdata_t, void *);
    413 static void isp_pci_attach(device_t, device_t, void *);
    414 
    415 struct isp_pcisoftc {
    416 	struct ispsoftc		pci_isp;
    417 	pci_chipset_tag_t	pci_pc;
    418 	pcitag_t		pci_tag;
    419 	bus_space_tag_t		pci_st;
    420 	bus_space_handle_t	pci_sh;
    421 	bus_dmamap_t		*pci_xfer_dmap;
    422 	void *			pci_ih;
    423 	int16_t			pci_poff[_NREG_BLKS];
    424 };
    425 
    426 CFATTACH_DECL_NEW(isp_pci, sizeof (struct isp_pcisoftc),
    427     isp_pci_probe, isp_pci_attach, NULL, NULL);
    428 
    429 static int
    430 isp_pci_probe(device_t parent, cfdata_t match, void *aux)
    431 {
    432 	struct pci_attach_args *pa = aux;
    433 	switch (pa->pa_id) {
    434 #ifndef	ISP_DISABLE_1020_SUPPORT
    435 	case PCI_QLOGIC_ISP:
    436 		return (1);
    437 #endif
    438 #ifndef	ISP_DISABLE_1080_SUPPORT
    439 	case PCI_QLOGIC_ISP1080:
    440 	case PCI_QLOGIC_ISP1240:
    441 	case PCI_QLOGIC_ISP1280:
    442 		return (1);
    443 #endif
    444 #ifndef	ISP_DISABLE_12160_SUPPORT
    445 	case PCI_QLOGIC_ISP10160:
    446 	case PCI_QLOGIC_ISP12160:
    447 		return (1);
    448 #endif
    449 #ifndef	ISP_DISABLE_2100_SUPPORT
    450 	case PCI_QLOGIC_ISP2100:
    451 		return (1);
    452 #endif
    453 #ifndef	ISP_DISABLE_2200_SUPPORT
    454 	case PCI_QLOGIC_ISP2200:
    455 		return (1);
    456 #endif
    457 #ifndef	ISP_DISABLE_2300_SUPPORT
    458 	case PCI_QLOGIC_ISP2300:
    459 	case PCI_QLOGIC_ISP2312:
    460 	case PCI_QLOGIC_ISP6312:
    461 #endif
    462 #ifndef	ISP_DISABLE_2322_SUPPORT
    463 	case PCI_QLOGIC_ISP2322:
    464 	case PCI_QLOGIC_ISP6322:
    465 		return (1);
    466 #endif
    467 #ifndef	ISP_DISABLE_2400_SUPPORT
    468 	case PCI_QLOGIC_ISP2422:
    469 	case PCI_QLOGIC_ISP2432:
    470 	case PCI_QLOGIC_ISP2532:
    471 		return (1);
    472 #endif
    473 	default:
    474 		return (0);
    475 	}
    476 }
    477 
    478 static void
    479 isp_pci_attach(device_t parent, device_t self, void *aux)
    480 {
    481 	static const char nomem[] = "\n%s: no mem for sdparam table\n";
    482 	uint32_t data, rev, linesz = PCI_DFLT_LNSZ;
    483 	struct pci_attach_args *pa = aux;
    484 	struct isp_pcisoftc *pcs = device_private(self);
    485 	struct ispsoftc *isp = &pcs->pci_isp;
    486 	bus_space_tag_t st, iot, memt;
    487 	bus_space_handle_t sh, ioh, memh;
    488 	pci_intr_handle_t ih;
    489 	pcireg_t mem_type;
    490 	const char *dstring;
    491 	const char *intrstr;
    492 	int ioh_valid, memh_valid;
    493 	size_t mamt;
    494 
    495 	isp->isp_osinfo.dev = self;
    496 
    497 	ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
    498 	    PCI_MAPREG_TYPE_IO, 0,
    499 	    &iot, &ioh, NULL, NULL) == 0);
    500 
    501 	mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG);
    502 	if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) {
    503 		memh_valid = 0;
    504 	} else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT &&
    505 	    PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) {
    506 		memh_valid = 0;
    507 	} else {
    508 		memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0,
    509 		    &memt, &memh, NULL, NULL) == 0);
    510 	}
    511 	if (memh_valid) {
    512 		st = memt;
    513 		sh = memh;
    514 	} else if (ioh_valid) {
    515 		st = iot;
    516 		sh = ioh;
    517 	} else {
    518 		printf(": unable to map device registers\n");
    519 		return;
    520 	}
    521 	dstring = "\n";
    522 
    523 	isp->isp_nchan = 1;
    524 	mamt = 0;
    525 
    526 	pcs->pci_st = st;
    527 	pcs->pci_sh = sh;
    528 	pcs->pci_pc = pa->pa_pc;
    529 	pcs->pci_tag = pa->pa_tag;
    530 	pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
    531 	pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
    532 	pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
    533 	pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
    534 	pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
    535 	rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff;
    536 
    537 
    538 #ifndef	ISP_DISABLE_1020_SUPPORT
    539 	if (pa->pa_id == PCI_QLOGIC_ISP) {
    540 		dstring = ": QLogic 1020 Fast Wide SCSI HBA\n";
    541 		isp->isp_mdvec = &mdvec;
    542 		isp->isp_type = ISP_HA_SCSI_UNKNOWN;
    543 		mamt = sizeof (sdparam);
    544 	}
    545 #endif
    546 #ifndef	ISP_DISABLE_1080_SUPPORT
    547 	if (pa->pa_id == PCI_QLOGIC_ISP1080) {
    548 		dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n";
    549 		isp->isp_mdvec = &mdvec_1080;
    550 		isp->isp_type = ISP_HA_SCSI_1080;
    551 		mamt = sizeof (sdparam);
    552 		pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
    553 		    ISP1080_DMA_REGS_OFF;
    554 	}
    555 	if (pa->pa_id == PCI_QLOGIC_ISP1240) {
    556 		dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n";
    557 		isp->isp_mdvec = &mdvec_1080;
    558 		isp->isp_type = ISP_HA_SCSI_1240;
    559 		isp->isp_nchan++;
    560 		mamt = sizeof (sdparam) * 2;
    561 		pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
    562 		    ISP1080_DMA_REGS_OFF;
    563 	}
    564 	if (pa->pa_id == PCI_QLOGIC_ISP1280) {
    565 		dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n";
    566 		isp->isp_mdvec = &mdvec_1080;
    567 		isp->isp_type = ISP_HA_SCSI_1280;
    568 		isp->isp_nchan++;
    569 		mamt = sizeof (sdparam) * 2;
    570 		pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
    571 		    ISP1080_DMA_REGS_OFF;
    572 	}
    573 #endif
    574 #ifndef	ISP_DISABLE_12160_SUPPORT
    575 	if (pa->pa_id == PCI_QLOGIC_ISP10160) {
    576 		dstring = ": QLogic Ultra-3 Wide SCSI HBA\n";
    577 		isp->isp_mdvec = &mdvec_12160;
    578 		isp->isp_type = ISP_HA_SCSI_10160;
    579 		mamt = sizeof (sdparam);
    580 		pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
    581 		    ISP1080_DMA_REGS_OFF;
    582 	}
    583 	if (pa->pa_id == PCI_QLOGIC_ISP12160) {
    584 		dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n";
    585 		isp->isp_mdvec = &mdvec_12160;
    586 		isp->isp_type = ISP_HA_SCSI_12160;
    587 		isp->isp_nchan++;
    588 		mamt = sizeof (sdparam) * 2;
    589 		pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
    590 		    ISP1080_DMA_REGS_OFF;
    591 	}
    592 #endif
    593 #ifndef	ISP_DISABLE_2100_SUPPORT
    594 	if (pa->pa_id == PCI_QLOGIC_ISP2100) {
    595 		dstring = ": QLogic FC-AL HBA\n";
    596 		isp->isp_mdvec = &mdvec_2100;
    597 		isp->isp_type = ISP_HA_FC_2100;
    598 		mamt = sizeof (fcparam);
    599 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
    600 		    PCI_MBOX_REGS2100_OFF;
    601 		if (rev < 3) {
    602 			/*
    603 			 * XXX: Need to get the actual revision
    604 			 * XXX: number of the 2100 FB. At any rate,
    605 			 * XXX: lower cache line size for early revision
    606 			 * XXX; boards.
    607 			 */
    608 			linesz = 1;
    609 		}
    610 	}
    611 #endif
    612 #ifndef	ISP_DISABLE_2200_SUPPORT
    613 	if (pa->pa_id == PCI_QLOGIC_ISP2200) {
    614 		dstring = ": QLogic FC-AL and Fabric HBA\n";
    615 		isp->isp_mdvec = &mdvec_2200;
    616 		isp->isp_type = ISP_HA_FC_2200;
    617 		mamt = sizeof (fcparam);
    618 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
    619 		    PCI_MBOX_REGS2100_OFF;
    620 		data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
    621 	}
    622 #endif
    623 #ifndef	ISP_DISABLE_2300_SUPPORT
    624 	if (pa->pa_id == PCI_QLOGIC_ISP2300 ||
    625 	    pa->pa_id == PCI_QLOGIC_ISP2312 ||
    626 	    pa->pa_id == PCI_QLOGIC_ISP6312) {
    627 		isp->isp_mdvec = &mdvec_2300;
    628 		if (pa->pa_id == PCI_QLOGIC_ISP2300 ||
    629 		    pa->pa_id == PCI_QLOGIC_ISP6312) {
    630 			dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n";
    631 			isp->isp_type = ISP_HA_FC_2300;
    632 		} else {
    633 			dstring =
    634 			    ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n";
    635 			isp->isp_port = pa->pa_function;
    636 		}
    637 		isp->isp_type = ISP_HA_FC_2312;
    638 		mamt = sizeof (fcparam);
    639 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
    640 		    PCI_MBOX_REGS2300_OFF;
    641 		data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
    642 	}
    643 #endif
    644 #ifndef	ISP_DISABLE_2322_SUPPORT
    645 	if (pa->pa_id == PCI_QLOGIC_ISP2322 ||
    646 	    pa->pa_id == PCI_QLOGIC_ISP6322) {
    647 		isp->isp_mdvec = &mdvec_2322;
    648 		dstring = ": QLogic FC-AL and 2Gbps Fabric PCI-E HBA\n";
    649 		isp->isp_type = ISP_HA_FC_2322;
    650 		isp->isp_port = pa->pa_function;
    651 		mamt = sizeof (fcparam);
    652 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
    653 		    PCI_MBOX_REGS2300_OFF;
    654 		data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
    655 	}
    656 #endif
    657 #ifndef	ISP_DISABLE_2400_SUPPORT
    658 	if (pa->pa_id == PCI_QLOGIC_ISP2422 ||
    659 	    pa->pa_id == PCI_QLOGIC_ISP2432) {
    660 		isp->isp_mdvec = &mdvec_2400;
    661 		if (pa->pa_id == PCI_QLOGIC_ISP2422) {
    662 			dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-X HBA\n";
    663 		} else {
    664 			dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-E HBA\n";
    665 		}
    666 		isp->isp_type = ISP_HA_FC_2400;
    667 		isp->isp_port = pa->pa_function;
    668 		mamt = sizeof (fcparam);
    669 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
    670 		    PCI_MBOX_REGS2400_OFF;
    671 		data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
    672 	}
    673 	if (pa->pa_id == PCI_QLOGIC_ISP2532) {
    674 		isp->isp_mdvec = &mdvec_2500;
    675 		dstring = ": QLogic FC-AL and 8Gbps Fabric PCI-E HBA\n";
    676 		isp->isp_type = ISP_HA_FC_2500;
    677 		isp->isp_port = pa->pa_function;
    678 		mamt = sizeof (fcparam);
    679 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
    680 		    PCI_MBOX_REGS2400_OFF;
    681 		data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
    682 	}
    683 #endif
    684 	if (mamt == 0) {
    685 		return;
    686 	}
    687 
    688 	isp->isp_param = malloc(mamt, M_DEVBUF, M_NOWAIT);
    689 	if (isp->isp_param == NULL) {
    690 		printf(nomem, device_xname(self));
    691 		return;
    692 	}
    693 	memset(isp->isp_param, 0, mamt);
    694 	mamt = sizeof (struct scsipi_channel) * isp->isp_nchan;
    695 	isp->isp_osinfo.chan = malloc(mamt, M_DEVBUF, M_NOWAIT);
    696 	if (isp->isp_osinfo.chan == NULL) {
    697 		free(isp->isp_param, M_DEVBUF);
    698 		printf(nomem, device_xname(self));
    699 		return;
    700 	}
    701 	memset(isp->isp_osinfo.chan, 0, mamt);
    702 	isp->isp_osinfo.adapter.adapt_nchannels = isp->isp_nchan;
    703 
    704 	/*
    705 	 * Set up logging levels.
    706 	 */
    707 #ifdef	ISP_LOGDEFAULT
    708 	isp->isp_dblev = ISP_LOGDEFAULT;
    709 #else
    710 	isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
    711 	if (bootverbose)
    712 		isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
    713 #ifdef	SCSIDEBUG
    714 	isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2;
    715 #endif
    716 #endif
    717 	if (isp->isp_dblev & ISP_LOGCONFIG) {
    718 		printf("\n");
    719 	} else {
    720 		printf(dstring);
    721 	}
    722 
    723 	isp->isp_dmatag = pa->pa_dmat;
    724 	isp->isp_revision = rev;
    725 
    726 	/*
    727 	 * Make sure that command register set sanely.
    728 	 */
    729 	data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
    730 	data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
    731 
    732 	/*
    733 	 * Not so sure about these- but I think it's important that they get
    734 	 * enabled......
    735 	 */
    736 	data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
    737 	if (IS_2300(isp)) {	/* per QLogic errata */
    738 		data &= ~PCI_COMMAND_INVALIDATE_ENABLE;
    739 	}
    740 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data);
    741 
    742 	/*
    743 	 * Make sure that the latency timer, cache line size,
    744 	 * and ROM is disabled.
    745 	 */
    746 	data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
    747 	data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
    748 	data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
    749 	data |= (PCI_DFLT_LTNCY	<< PCI_LATTIMER_SHIFT);
    750 	data |= (linesz << PCI_CACHELINE_SHIFT);
    751 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
    752 
    753 	data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR);
    754 	data &= ~1;
    755 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data);
    756 
    757 	if (pci_intr_map(pa, &ih)) {
    758 		aprint_error_dev(self, "couldn't map interrupt\n");
    759 		free(isp->isp_param, M_DEVBUF);
    760 		free(isp->isp_osinfo.chan, M_DEVBUF);
    761 		return;
    762 	}
    763 	intrstr = pci_intr_string(pa->pa_pc, ih);
    764 	if (intrstr == NULL)
    765 		intrstr = "<I dunno>";
    766 	pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
    767 	    isp_pci_intr, isp);
    768 	if (pcs->pci_ih == NULL) {
    769 		aprint_error_dev(self, "couldn't establish interrupt at %s\n",
    770 			intrstr);
    771 		free(isp->isp_param, M_DEVBUF);
    772 		free(isp->isp_osinfo.chan, M_DEVBUF);
    773 		return;
    774 	}
    775 
    776 	printf("%s: interrupting at %s\n", device_xname(self), intrstr);
    777 
    778 	isp->isp_confopts = device_cfdata(self)->cf_flags;
    779 	ISP_LOCK(isp);
    780 	isp_reset(isp, 1);
    781 	if (isp->isp_state != ISP_RESETSTATE) {
    782 		ISP_UNLOCK(isp);
    783 		free(isp->isp_param, M_DEVBUF);
    784 		free(isp->isp_osinfo.chan, M_DEVBUF);
    785 		return;
    786 	}
    787 	isp_init(isp);
    788 	if (isp->isp_state != ISP_INITSTATE) {
    789 		isp_uninit(isp);
    790 		ISP_UNLOCK(isp);
    791 		free(isp->isp_param, M_DEVBUF);
    792 		free(isp->isp_osinfo.chan, M_DEVBUF);
    793 		return;
    794 	}
    795 	/*
    796 	 * Do platform attach.
    797 	 */
    798 	ISP_UNLOCK(isp);
    799 	isp_attach(isp);
    800 }
    801 
    802 #define	IspVirt2Off(a, x)	\
    803 	(((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
    804 	_BLK_REG_SHFT] + ((x) & 0xff))
    805 
    806 #define	BXR2(pcs, off)		\
    807 	bus_space_read_2(pcs->pci_st, pcs->pci_sh, off)
    808 #define	BXW2(pcs, off, v)	\
    809 	bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v)
    810 #define	BXR4(pcs, off)		\
    811 	bus_space_read_4(pcs->pci_st, pcs->pci_sh, off)
    812 #define	BXW4(pcs, off, v)	\
    813 	bus_space_write_4(pcs->pci_st, pcs->pci_sh, off, v)
    814 
    815 
    816 static int
    817 isp_pci_rd_debounced(struct ispsoftc *isp, int off, uint16_t *rp)
    818 {
    819 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
    820 	uint16_t val0, val1;
    821 	int i = 0;
    822 
    823 	do {
    824 		val0 = BXR2(pcs, IspVirt2Off(isp, off));
    825 		val1 = BXR2(pcs, IspVirt2Off(isp, off));
    826 	} while (val0 != val1 && ++i < 1000);
    827 	if (val0 != val1) {
    828 		return (1);
    829 	}
    830 	*rp = val0;
    831 	return (0);
    832 }
    833 
    834 #if !defined(ISP_DISABLE_2100_SUPPORT) && \
    835 	 !defined(ISP_DISABLE_2200_SUPPORT) && \
    836 	 !defined(ISP_DISABLE_1020_SUPPORT) && \
    837 	 !defined(ISP_DISABLE_1080_SUPPORT) && \
    838 	 !defined(ISP_DISABLE_12160_SUPPORT)
    839 static int
    840 isp_pci_rd_isr(struct ispsoftc *isp, uint32_t *isrp,
    841     uint16_t *semap, uint16_t *mbp)
    842 {
    843 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
    844 	uint16_t isr, sema;
    845 
    846 	if (IS_2100(isp)) {
    847 		if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
    848 		    return (0);
    849 		}
    850 		if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) {
    851 		    return (0);
    852 		}
    853 	} else {
    854 		isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR));
    855 		sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA));
    856 	}
    857 	isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema);
    858 	isr &= INT_PENDING_MASK(isp);
    859 	sema &= BIU_SEMA_LOCK;
    860 	if (isr == 0 && sema == 0) {
    861 		return (0);
    862 	}
    863 	*isrp = isr;
    864 	if ((*semap = sema) != 0) {
    865 		if (IS_2100(isp)) {
    866 			if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) {
    867 				return (0);
    868 			}
    869 		} else {
    870 			*mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0));
    871 		}
    872 	}
    873 	return (1);
    874 }
    875 #endif
    876 
    877 #if !(defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_2322_SUPPORT))
    878 static int
    879 isp_pci_rd_isr_2300(struct ispsoftc *isp, uint32_t *isrp,
    880     uint16_t *semap, uint16_t *mbox0p)
    881 {
    882 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
    883 	uint32_t r2hisr;
    884 
    885 	if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) {
    886 		*isrp = 0;
    887 		return (0);
    888 	}
    889 	r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh,
    890 	    IspVirt2Off(pcs, BIU_R2HSTSLO));
    891 	isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
    892 	if ((r2hisr & BIU_R2HST_INTR) == 0) {
    893 		*isrp = 0;
    894 		return (0);
    895 	}
    896 	switch (r2hisr & BIU_R2HST_ISTAT_MASK) {
    897 	case ISPR2HST_ROM_MBX_OK:
    898 	case ISPR2HST_ROM_MBX_FAIL:
    899 	case ISPR2HST_MBX_OK:
    900 	case ISPR2HST_MBX_FAIL:
    901 	case ISPR2HST_ASYNC_EVENT:
    902 		*isrp = r2hisr & 0xffff;
    903 		*mbox0p = (r2hisr >> 16);
    904 		*semap = 1;
    905 		return (1);
    906 	case ISPR2HST_RIO_16:
    907 		*isrp = r2hisr & 0xffff;
    908 		*mbox0p = ASYNC_RIO16_1;
    909 		*semap = 1;
    910 		return (1);
    911 	case ISPR2HST_FPOST:
    912 		*isrp = r2hisr & 0xffff;
    913 		*mbox0p = ASYNC_CMD_CMPLT;
    914 		*semap = 1;
    915 		return (1);
    916 	case ISPR2HST_FPOST_CTIO:
    917 		*isrp = r2hisr & 0xffff;
    918 		*mbox0p = ASYNC_CTIO_DONE;
    919 		*semap = 1;
    920 		return (1);
    921 	case ISPR2HST_RSPQ_UPDATE:
    922 		*isrp = r2hisr & 0xffff;
    923 		*mbox0p = 0;
    924 		*semap = 0;
    925 		return (1);
    926 	default:
    927 		return (0);
    928 	}
    929 }
    930 #endif
    931 
    932 #ifndef	ISP_DISABLE_2400_SUPPORT
    933 static int
    934 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp,
    935     uint16_t *semap, uint16_t *mbox0p)
    936 {
    937 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
    938 	uint32_t r2hisr;
    939 
    940 	r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU2400_R2HSTSLO));
    941 	isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
    942 	if ((r2hisr & BIU2400_R2HST_INTR) == 0) {
    943 		*isrp = 0;
    944 		return (0);
    945 	}
    946 	switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) {
    947 	case ISP2400R2HST_ROM_MBX_OK:
    948 	case ISP2400R2HST_ROM_MBX_FAIL:
    949 	case ISP2400R2HST_MBX_OK:
    950 	case ISP2400R2HST_MBX_FAIL:
    951 	case ISP2400R2HST_ASYNC_EVENT:
    952 		*isrp = r2hisr & 0xffff;
    953 		*mbox0p = (r2hisr >> 16);
    954 		*semap = 1;
    955 		return (1);
    956 	case ISP2400R2HST_RSPQ_UPDATE:
    957 	case ISP2400R2HST_ATIO_RSPQ_UPDATE:
    958 	case ISP2400R2HST_ATIO_RQST_UPDATE:
    959 		*isrp = r2hisr & 0xffff;
    960 		*mbox0p = 0;
    961 		*semap = 0;
    962 		return (1);
    963 	default:
    964 		ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
    965 		isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
    966 		return (0);
    967 	}
    968 }
    969 
    970 static uint32_t
    971 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
    972 {
    973 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
    974 	uint32_t rv;
    975 	int block = regoff & _BLK_REG_MASK;
    976 
    977 	switch (block) {
    978 	case BIU_BLOCK:
    979 		break;
    980 	case MBOX_BLOCK:
    981 		return (BXR2(pcs, IspVirt2Off(pcs, regoff)));
    982 	case SXP_BLOCK:
    983 		isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff);
    984 		return (0xffffffff);
    985 	case RISC_BLOCK:
    986 		isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff);
    987 		return (0xffffffff);
    988 	case DMA_BLOCK:
    989 		isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff);
    990 		return (0xffffffff);
    991 	default:
    992 		isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff);
    993 		return (0xffffffff);
    994 	}
    995 
    996 
    997 	switch (regoff) {
    998 	case BIU2400_FLASH_ADDR:
    999 	case BIU2400_FLASH_DATA:
   1000 	case BIU2400_ICR:
   1001 	case BIU2400_ISR:
   1002 	case BIU2400_CSR:
   1003 	case BIU2400_REQINP:
   1004 	case BIU2400_REQOUTP:
   1005 	case BIU2400_RSPINP:
   1006 	case BIU2400_RSPOUTP:
   1007 	case BIU2400_PRI_REQINP:
   1008 	case BIU2400_PRI_REQOUTP:
   1009 	case BIU2400_ATIO_RSPINP:
   1010 	case BIU2400_ATIO_RSPOUTP:
   1011 	case BIU2400_HCCR:
   1012 	case BIU2400_GPIOD:
   1013 	case BIU2400_GPIOE:
   1014 	case BIU2400_HSEMA:
   1015 		rv = BXR4(pcs, IspVirt2Off(pcs, regoff));
   1016 		break;
   1017 	case BIU2400_R2HSTSLO:
   1018 		rv = BXR4(pcs, IspVirt2Off(pcs, regoff));
   1019 		break;
   1020 	case BIU2400_R2HSTSHI:
   1021 		rv = BXR4(pcs, IspVirt2Off(pcs, regoff)) >> 16;
   1022 		break;
   1023 	default:
   1024 		isp_prt(isp, ISP_LOGERR,
   1025 		    "isp_pci_rd_reg_2400: unknown offset %x", regoff);
   1026 		rv = 0xffffffff;
   1027 		break;
   1028 	}
   1029 	return (rv);
   1030 }
   1031 
   1032 static void
   1033 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
   1034 {
   1035 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
   1036 	int block = regoff & _BLK_REG_MASK;
   1037 	volatile int junk;
   1038 
   1039 	switch (block) {
   1040 	case BIU_BLOCK:
   1041 		break;
   1042 	case MBOX_BLOCK:
   1043 		BXW2(pcs, IspVirt2Off(pcs, regoff), val);
   1044 		junk = BXR2(pcs, IspVirt2Off(pcs, regoff));
   1045 		return;
   1046 	case SXP_BLOCK:
   1047 		isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff);
   1048 		return;
   1049 	case RISC_BLOCK:
   1050 		isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff);
   1051 		return;
   1052 	case DMA_BLOCK:
   1053 		isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff);
   1054 		return;
   1055 	default:
   1056 		isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x",
   1057 		    regoff);
   1058 		break;
   1059 	}
   1060 
   1061 	switch (regoff) {
   1062 	case BIU2400_FLASH_ADDR:
   1063 	case BIU2400_FLASH_DATA:
   1064 	case BIU2400_ICR:
   1065 	case BIU2400_ISR:
   1066 	case BIU2400_CSR:
   1067 	case BIU2400_REQINP:
   1068 	case BIU2400_REQOUTP:
   1069 	case BIU2400_RSPINP:
   1070 	case BIU2400_RSPOUTP:
   1071 	case BIU2400_PRI_REQINP:
   1072 	case BIU2400_PRI_REQOUTP:
   1073 	case BIU2400_ATIO_RSPINP:
   1074 	case BIU2400_ATIO_RSPOUTP:
   1075 	case BIU2400_HCCR:
   1076 	case BIU2400_GPIOD:
   1077 	case BIU2400_GPIOE:
   1078 	case BIU2400_HSEMA:
   1079 		BXW4(pcs, IspVirt2Off(pcs, regoff), val);
   1080 		junk = BXR4(pcs, IspVirt2Off(pcs, regoff));
   1081 		break;
   1082 	default:
   1083 		isp_prt(isp, ISP_LOGERR,
   1084 		    "isp_pci_wr_reg_2400: bad offset 0x%x", regoff);
   1085 		break;
   1086 	}
   1087 }
   1088 #endif
   1089 
   1090 static uint32_t
   1091 isp_pci_rd_reg(struct ispsoftc *isp, int regoff)
   1092 {
   1093 	uint32_t rv;
   1094 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
   1095 	int oldconf = 0;
   1096 
   1097 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
   1098 		/*
   1099 		 * We will assume that someone has paused the RISC processor.
   1100 		 */
   1101 		oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
   1102 		BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
   1103 		    oldconf | BIU_PCI_CONF1_SXP);
   1104 	}
   1105 	rv = BXR2(pcs, IspVirt2Off(isp, regoff));
   1106 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
   1107 		BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
   1108 	}
   1109 	return (rv);
   1110 }
   1111 
   1112 static void
   1113 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, uint32_t val)
   1114 {
   1115 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
   1116 	int oldconf = 0;
   1117 
   1118 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
   1119 		/*
   1120 		 * We will assume that someone has paused the RISC processor.
   1121 		 */
   1122 		oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
   1123 		BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
   1124 		    oldconf | BIU_PCI_CONF1_SXP);
   1125 	}
   1126 	BXW2(pcs, IspVirt2Off(isp, regoff), val);
   1127 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
   1128 		BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
   1129 	}
   1130 }
   1131 
   1132 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
   1133 static uint32_t
   1134 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff)
   1135 {
   1136 	uint16_t rv, oc = 0;
   1137 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
   1138 
   1139 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
   1140 	    (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
   1141 		uint16_t tc;
   1142 		/*
   1143 		 * We will assume that someone has paused the RISC processor.
   1144 		 */
   1145 		oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
   1146 		tc = oc & ~BIU_PCI1080_CONF1_DMA;
   1147 		if (regoff & SXP_BANK1_SELECT)
   1148 			tc |= BIU_PCI1080_CONF1_SXP1;
   1149 		else
   1150 			tc |= BIU_PCI1080_CONF1_SXP0;
   1151 		BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
   1152 	} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
   1153 		oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
   1154 		BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
   1155 		    oc | BIU_PCI1080_CONF1_DMA);
   1156 	}
   1157 	rv = BXR2(pcs, IspVirt2Off(isp, regoff));
   1158 	if (oc) {
   1159 		BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
   1160 	}
   1161 	return (rv);
   1162 }
   1163 
   1164 static void
   1165 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, uint32_t val)
   1166 {
   1167 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
   1168 	int oc = 0;
   1169 
   1170 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
   1171 	    (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
   1172 		uint16_t tc;
   1173 		/*
   1174 		 * We will assume that someone has paused the RISC processor.
   1175 		 */
   1176 		oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
   1177 		tc = oc & ~BIU_PCI1080_CONF1_DMA;
   1178 		if (regoff & SXP_BANK1_SELECT)
   1179 			tc |= BIU_PCI1080_CONF1_SXP1;
   1180 		else
   1181 			tc |= BIU_PCI1080_CONF1_SXP0;
   1182 		BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
   1183 	} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
   1184 		oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
   1185 		BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
   1186 		    oc | BIU_PCI1080_CONF1_DMA);
   1187 	}
   1188 	BXW2(pcs, IspVirt2Off(isp, regoff), val);
   1189 	if (oc) {
   1190 		BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
   1191 	}
   1192 }
   1193 #endif
   1194 
   1195 static int
   1196 isp_pci_mbxdma(struct ispsoftc *isp)
   1197 {
   1198 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
   1199 	bus_dma_tag_t dmat = isp->isp_dmatag;
   1200 	bus_dma_segment_t sg;
   1201 	bus_size_t len, dbound;
   1202 	fcparam *fcp;
   1203 	int rs, i;
   1204 
   1205 	if (isp->isp_rquest_dma)	/* been here before? */
   1206 		return (0);
   1207 
   1208 	if (isp->isp_type <= ISP_HA_SCSI_1040B) {
   1209 		dbound = 1 << 24;
   1210 	} else {
   1211 		/*
   1212 		 * For 32-bit PCI DMA, the range is 32 bits or zero :-)
   1213 		 */
   1214 		dbound = 0;
   1215 	}
   1216 	len = isp->isp_maxcmds * sizeof (isp_hdl_t);
   1217 	isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK);
   1218 	if (isp->isp_xflist == NULL) {
   1219 		isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array");
   1220 		return (1);
   1221 	}
   1222 	memset(isp->isp_xflist, 0, len);
   1223 	for (len = 0; len < isp->isp_maxcmds - 1; len++) {
   1224 		isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1];
   1225 	}
   1226 	isp->isp_xffree = isp->isp_xflist;
   1227 	len = isp->isp_maxcmds * sizeof (bus_dmamap_t);
   1228 	pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK);
   1229 	if (pcs->pci_xfer_dmap == NULL) {
   1230 		free(isp->isp_xflist, M_DEVBUF);
   1231 		isp->isp_xflist = NULL;
   1232 		isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array");
   1233 		return (1);
   1234 	}
   1235 	for (i = 0; i < isp->isp_maxcmds; i++) {
   1236 		if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1,
   1237 		    MAXPHYS, dbound, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) {
   1238 			isp_prt(isp, ISP_LOGERR, "cannot create DMA maps");
   1239 			break;
   1240 		}
   1241 	}
   1242 	if (i < isp->isp_maxcmds) {
   1243 		while (--i >= 0) {
   1244 			bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
   1245 		}
   1246 		free(isp->isp_xflist, M_DEVBUF);
   1247 		free(pcs->pci_xfer_dmap, M_DEVBUF);
   1248 		isp->isp_xflist = NULL;
   1249 		pcs->pci_xfer_dmap = NULL;
   1250 		return (1);
   1251 	}
   1252 
   1253 	/*
   1254 	 * Allocate and map the request queue.
   1255 	 */
   1256 	len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
   1257 	if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 0)) {
   1258 		goto dmafail;
   1259 	}
   1260  	if (bus_dmamem_map(isp->isp_dmatag, &sg, rs, len,
   1261 	    (void *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
   1262 		goto dmafail;
   1263 	}
   1264 	if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
   1265 	    &isp->isp_rqdmap)) {
   1266 		goto dmafail;
   1267 	}
   1268 	if (bus_dmamap_load(dmat, isp->isp_rqdmap, isp->isp_rquest, len, NULL,
   1269 	    BUS_DMA_NOWAIT)) {
   1270 		goto dmafail;
   1271 	}
   1272 	isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr;
   1273 
   1274 	/*
   1275 	 * Allocate and map the result queue.
   1276 	 */
   1277 	len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
   1278 	if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs,
   1279 	    BUS_DMA_NOWAIT)) {
   1280 		goto dmafail;
   1281 	}
   1282 	if (bus_dmamem_map(dmat, &sg, rs, len,
   1283 	    (void *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
   1284 		goto dmafail;
   1285 	}
   1286 	if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
   1287 	    &isp->isp_rsdmap)) {
   1288 		goto dmafail;
   1289 	}
   1290 	if (bus_dmamap_load(dmat, isp->isp_rsdmap, isp->isp_result, len, NULL,
   1291 	    BUS_DMA_NOWAIT)) {
   1292 		goto dmafail;
   1293 	}
   1294 	isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr;
   1295 
   1296 	if (IS_SCSI(isp)) {
   1297 		return (0);
   1298 	}
   1299 
   1300 	/*
   1301 	 * Allocate and map an FC scratch area
   1302 	 */
   1303 	fcp = isp->isp_param;
   1304 	len = ISP_FC_SCRLEN;
   1305 	if (bus_dmamem_alloc(dmat, len, sizeof (uint64_t), 0, &sg, 1, &rs,
   1306 	    BUS_DMA_NOWAIT)) {
   1307 		goto dmafail;
   1308 	}
   1309 	if (bus_dmamem_map(dmat, &sg, rs, len,
   1310 	    (void *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
   1311 		goto dmafail;
   1312 	}
   1313 	if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
   1314 	    &isp->isp_scdmap)) {
   1315 		goto dmafail;
   1316 	}
   1317 	if (bus_dmamap_load(dmat, isp->isp_scdmap, fcp->isp_scratch, len, NULL,
   1318 	    BUS_DMA_NOWAIT)) {
   1319 		goto dmafail;
   1320 	}
   1321 	fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr;
   1322 	return (0);
   1323 dmafail:
   1324 	isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure");
   1325 	for (i = 0; i < isp->isp_maxcmds; i++) {
   1326 		bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
   1327 	}
   1328 	free(isp->isp_xflist, M_DEVBUF);
   1329 	free(pcs->pci_xfer_dmap, M_DEVBUF);
   1330 	isp->isp_xflist = NULL;
   1331 	pcs->pci_xfer_dmap = NULL;
   1332 	return (1);
   1333 }
   1334 
   1335 static int
   1336 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, void *arg)
   1337 {
   1338 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
   1339 	ispreq_t *rq = arg;
   1340 	bus_dmamap_t dmap;
   1341 	bus_dma_segment_t *dm_segs;
   1342 	uint32_t nsegs, hidx;
   1343 	isp_ddir_t ddir;
   1344 
   1345 	hidx = isp_handle_index(isp, rq->req_handle);
   1346 	if (hidx == ISP_BAD_HANDLE_INDEX) {
   1347 		XS_SETERR(xs, HBA_BOTCH);
   1348 		return (CMD_COMPLETE);
   1349 	}
   1350 	dmap = pcs->pci_xfer_dmap[hidx];
   1351 	if (xs->datalen == 0) {
   1352 		ddir = ISP_NOXFR;
   1353 		nsegs = 0;
   1354 		dm_segs = NULL;
   1355 	 } else {
   1356 		int error;
   1357 		uint32_t flag, flg2;
   1358 
   1359 		if (sizeof (bus_addr_t) > 4) {
   1360 			if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) {
   1361 				rq->req_header.rqs_entry_type = RQSTYPE_T3RQS;
   1362 			} else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) {
   1363 				rq->req_header.rqs_entry_type = RQSTYPE_A64;
   1364 			}
   1365 		}
   1366 
   1367 		if (xs->xs_control & XS_CTL_DATA_IN) {
   1368 			flg2 = BUS_DMASYNC_PREREAD;
   1369 			flag = BUS_DMA_READ;
   1370 			ddir = ISP_FROM_DEVICE;
   1371 		} else {
   1372 			flg2 = BUS_DMASYNC_PREWRITE;
   1373 			flag = BUS_DMA_WRITE;
   1374 			ddir = ISP_TO_DEVICE;
   1375 		}
   1376 		error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen,
   1377 		    NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | flag);
   1378 		if (error) {
   1379 			isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", error);
   1380 			XS_SETERR(xs, HBA_BOTCH);
   1381 			if (error == EAGAIN || error == ENOMEM) {
   1382 				return (CMD_EAGAIN);
   1383 			} else {
   1384 				return (CMD_COMPLETE);
   1385 			}
   1386 		}
   1387 		dm_segs = dmap->dm_segs;
   1388 		nsegs = dmap->dm_nsegs;
   1389 		bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, flg2);
   1390 	}
   1391 
   1392 	if (isp_send_cmd(isp, rq, dm_segs, nsegs, xs->datalen, ddir) != CMD_QUEUED) {
   1393 		return (CMD_EAGAIN);
   1394 	} else {
   1395 		return (CMD_QUEUED);
   1396 	}
   1397 }
   1398 
   1399 static int
   1400 isp_pci_intr(void *arg)
   1401 {
   1402 	uint32_t isr;
   1403 	uint16_t sema, mbox;
   1404 	struct ispsoftc *isp = arg;
   1405 
   1406 	isp->isp_intcnt++;
   1407 	if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) {
   1408 		isp->isp_intbogus++;
   1409 		return (0);
   1410 	} else {
   1411 		isp->isp_osinfo.onintstack = 1;
   1412 		isp_intr(isp, isr, sema, mbox);
   1413 		isp->isp_osinfo.onintstack = 0;
   1414 		return (1);
   1415 	}
   1416 }
   1417 
   1418 static void
   1419 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, uint32_t handle)
   1420 {
   1421 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
   1422 	uint32_t hidx;
   1423 	bus_dmamap_t dmap;
   1424 
   1425 	hidx = isp_handle_index(isp, handle);
   1426 	if (hidx == ISP_BAD_HANDLE_INDEX) {
   1427 		isp_xs_prt(isp, xs, ISP_LOGERR, "bad handle on teardown");
   1428 		return;
   1429 	}
   1430 	dmap = pcs->pci_xfer_dmap[hidx];
   1431 	bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize,
   1432 	    xs->xs_control & XS_CTL_DATA_IN ?
   1433 	    BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   1434 	bus_dmamap_unload(isp->isp_dmatag, dmap);
   1435 }
   1436 
   1437 static void
   1438 isp_pci_reset0(ispsoftc_t *isp)
   1439 {
   1440 	ISP_DISABLE_INTS(isp);
   1441 }
   1442 
   1443 static void
   1444 isp_pci_reset1(ispsoftc_t *isp)
   1445 {
   1446 	if (!IS_24XX(isp)) {
   1447 		/* Make sure the BIOS is disabled */
   1448 		isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
   1449 	}
   1450 	/* and enable interrupts */
   1451 	ISP_ENABLE_INTS(isp);
   1452 }
   1453 
   1454 static void
   1455 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg)
   1456 {
   1457 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
   1458 	if (msg)
   1459 		printf("%s: %s\n", device_xname(isp->isp_osinfo.dev), msg);
   1460 	if (IS_SCSI(isp))
   1461 		printf("    biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
   1462 	else
   1463 		printf("    biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
   1464 	printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
   1465 	    ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
   1466 	printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
   1467 
   1468 
   1469 	if (IS_SCSI(isp)) {
   1470 		ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
   1471 		printf("    cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
   1472 			ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
   1473 			ISP_READ(isp, CDMA_FIFO_STS));
   1474 		printf("    ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
   1475 			ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
   1476 			ISP_READ(isp, DDMA_FIFO_STS));
   1477 		printf("    sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
   1478 			ISP_READ(isp, SXP_INTERRUPT),
   1479 			ISP_READ(isp, SXP_GROSS_ERR),
   1480 			ISP_READ(isp, SXP_PINS_CTRL));
   1481 		ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
   1482 	}
   1483 	printf("    mbox regs: %x %x %x %x %x\n",
   1484 	    ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
   1485 	    ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
   1486 	    ISP_READ(isp, OUTMAILBOX4));
   1487 	printf("    PCI Status Command/Status=%x\n",
   1488 	    pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG));
   1489 }
   1490