isp_pci.c revision 1.117
1 /* $NetBSD: isp_pci.c,v 1.117 2014/03/29 19:28:25 christos Exp $ */ 2 /* 3 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 4 * All rights reserved. 5 * 6 * Additional Copyright (C) 2000-2007 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 33 */ 34 35 /* 36 * 24XX 4Gb material support provided by MetrumRG Associates. 37 * Many thanks are due to them. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.117 2014/03/29 19:28:25 christos Exp $"); 42 43 #include <dev/ic/isp_netbsd.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 #include <sys/reboot.h> 48 49 static uint32_t isp_pci_rd_reg(struct ispsoftc *, int); 50 static void isp_pci_wr_reg(struct ispsoftc *, int, uint32_t); 51 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 52 static uint32_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 53 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, uint32_t); 54 #endif 55 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 56 !defined(ISP_DISABLE_2200_SUPPORT) && \ 57 !defined(ISP_DISABLE_1020_SUPPORT) && \ 58 !defined(ISP_DISABLE_1080_SUPPORT) && \ 59 !defined(ISP_DISABLE_12160_SUPPORT) 60 static int 61 isp_pci_rd_isr(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 62 #endif 63 #if !(defined(ISP_DISABLE_2300_SUPPORT) && defined(ISP_DISABLE_2322_SUPPORT)) 64 static int 65 isp_pci_rd_isr_2300(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 66 #endif 67 #if !defined(ISP_DISABLE_2400_SUPPORT) 68 static uint32_t isp_pci_rd_reg_2400(struct ispsoftc *, int); 69 static void isp_pci_wr_reg_2400(struct ispsoftc *, int, uint32_t); 70 static int 71 isp_pci_rd_isr_2400(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 72 #endif 73 static int isp_pci_mbxdma(struct ispsoftc *); 74 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, void *); 75 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, uint32_t); 76 static void isp_pci_reset0(struct ispsoftc *); 77 static void isp_pci_reset1(struct ispsoftc *); 78 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 79 static int isp_pci_intr(void *); 80 81 #if defined(ISP_DISABLE_1020_SUPPORT) || defined(ISP_DISABLE_FW) 82 #define ISP_1040_RISC_CODE NULL 83 #else 84 #define ISP_1040_RISC_CODE (const uint16_t *) isp_1040_risc_code 85 #include <dev/microcode/isp/asm_1040.h> 86 #endif 87 88 #if defined(ISP_DISABLE_1080_SUPPORT) || defined(ISP_DISABLE_FW) 89 #define ISP_1080_RISC_CODE NULL 90 #else 91 #define ISP_1080_RISC_CODE (const uint16_t *) isp_1080_risc_code 92 #include <dev/microcode/isp/asm_1080.h> 93 #endif 94 95 #if defined(ISP_DISABLE_12160_SUPPORT) || defined(ISP_DISABLE_FW) 96 #define ISP_12160_RISC_CODE NULL 97 #else 98 #define ISP_12160_RISC_CODE (const uint16_t *) isp_12160_risc_code 99 #include <dev/microcode/isp/asm_12160.h> 100 #endif 101 102 #if defined(ISP_DISABLE_2100_SUPPORT) || defined(ISP_DISABLE_FW) 103 #define ISP_2100_RISC_CODE NULL 104 #else 105 #define ISP_2100_RISC_CODE (const uint16_t *) isp_2100_risc_code 106 #include <dev/microcode/isp/asm_2100.h> 107 #endif 108 109 #if defined(ISP_DISABLE_2200_SUPPORT) || defined(ISP_DISABLE_FW) 110 #define ISP_2200_RISC_CODE NULL 111 #else 112 #define ISP_2200_RISC_CODE (const uint16_t *) isp_2200_risc_code 113 #include <dev/microcode/isp/asm_2200.h> 114 #endif 115 116 #if defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_FW) 117 #define ISP_2300_RISC_CODE NULL 118 #else 119 #define ISP_2300_RISC_CODE (const uint16_t *) isp_2300_risc_code 120 #include <dev/microcode/isp/asm_2300.h> 121 #endif 122 #if defined(ISP_DISABLE_2322_SUPPORT) || defined(ISP_DISABLE_FW) 123 #define ISP_2322_RISC_CODE NULL 124 #else 125 #define ISP_2322_RISC_CODE (const uint16_t *) isp_2322_risc_code 126 #include <dev/microcode/isp/asm_2322.h> 127 #endif 128 129 #if defined(ISP_DISABLE_2400_SUPPORT) || defined(ISP_DISABLE_FW) 130 #define ISP_2400_RISC_CODE NULL 131 #define ISP_2500_RISC_CODE NULL 132 #else 133 #define ISP_2500 134 #define ISP_2400 135 #define ISP_2400_RISC_CODE (const uint32_t *) isp_2400_risc_code 136 #define ISP_2500_RISC_CODE (const uint32_t *) isp_2500_risc_code 137 #include <dev/microcode/isp/asm_2400.h> 138 #include <dev/microcode/isp/asm_2500.h> 139 #endif 140 141 #ifndef ISP_DISABLE_1020_SUPPORT 142 static struct ispmdvec mdvec = { 143 isp_pci_rd_isr, 144 isp_pci_rd_reg, 145 isp_pci_wr_reg, 146 isp_pci_mbxdma, 147 isp_pci_dmasetup, 148 isp_pci_dmateardown, 149 isp_pci_reset0, 150 isp_pci_reset1, 151 isp_pci_dumpregs, 152 ISP_1040_RISC_CODE, 153 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 154 0 155 }; 156 #endif 157 158 #ifndef ISP_DISABLE_1080_SUPPORT 159 static struct ispmdvec mdvec_1080 = { 160 isp_pci_rd_isr, 161 isp_pci_rd_reg_1080, 162 isp_pci_wr_reg_1080, 163 isp_pci_mbxdma, 164 isp_pci_dmasetup, 165 isp_pci_dmateardown, 166 isp_pci_reset0, 167 isp_pci_reset1, 168 isp_pci_dumpregs, 169 ISP_1080_RISC_CODE, 170 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 171 0 172 }; 173 #endif 174 175 #ifndef ISP_DISABLE_12160_SUPPORT 176 static struct ispmdvec mdvec_12160 = { 177 isp_pci_rd_isr, 178 isp_pci_rd_reg_1080, 179 isp_pci_wr_reg_1080, 180 isp_pci_mbxdma, 181 isp_pci_dmasetup, 182 isp_pci_dmateardown, 183 isp_pci_reset0, 184 isp_pci_reset1, 185 isp_pci_dumpregs, 186 ISP_12160_RISC_CODE, 187 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 188 0 189 }; 190 #endif 191 192 #ifndef ISP_DISABLE_2100_SUPPORT 193 static struct ispmdvec mdvec_2100 = { 194 isp_pci_rd_isr, 195 isp_pci_rd_reg, 196 isp_pci_wr_reg, 197 isp_pci_mbxdma, 198 isp_pci_dmasetup, 199 isp_pci_dmateardown, 200 isp_pci_reset0, 201 isp_pci_reset1, 202 isp_pci_dumpregs, 203 ISP_2100_RISC_CODE, 204 0, 205 0 206 }; 207 #endif 208 209 #ifndef ISP_DISABLE_2200_SUPPORT 210 static struct ispmdvec mdvec_2200 = { 211 isp_pci_rd_isr, 212 isp_pci_rd_reg, 213 isp_pci_wr_reg, 214 isp_pci_mbxdma, 215 isp_pci_dmasetup, 216 isp_pci_dmateardown, 217 isp_pci_reset0, 218 isp_pci_reset1, 219 isp_pci_dumpregs, 220 ISP_2200_RISC_CODE, 221 0, 222 0 223 }; 224 #endif 225 226 #ifndef ISP_DISABLE_2300_SUPPORT 227 static struct ispmdvec mdvec_2300 = { 228 isp_pci_rd_isr_2300, 229 isp_pci_rd_reg, 230 isp_pci_wr_reg, 231 isp_pci_mbxdma, 232 isp_pci_dmasetup, 233 isp_pci_dmateardown, 234 isp_pci_reset0, 235 isp_pci_reset1, 236 isp_pci_dumpregs, 237 ISP_2300_RISC_CODE, 238 0, 239 0 240 }; 241 #endif 242 243 #ifndef ISP_DISABLE_2322_SUPPORT 244 static struct ispmdvec mdvec_2322 = { 245 isp_pci_rd_isr_2300, 246 isp_pci_rd_reg, 247 isp_pci_wr_reg, 248 isp_pci_mbxdma, 249 isp_pci_dmasetup, 250 isp_pci_dmateardown, 251 isp_pci_reset0, 252 isp_pci_reset1, 253 isp_pci_dumpregs, 254 ISP_2322_RISC_CODE, 255 0, 256 0 257 }; 258 #endif 259 260 #ifndef ISP_DISABLE_2400_SUPPORT 261 static struct ispmdvec mdvec_2400 = { 262 isp_pci_rd_isr_2400, 263 isp_pci_rd_reg_2400, 264 isp_pci_wr_reg_2400, 265 isp_pci_mbxdma, 266 isp_pci_dmasetup, 267 isp_pci_dmateardown, 268 isp_pci_reset0, 269 isp_pci_reset1, 270 NULL, 271 ISP_2400_RISC_CODE, 272 0, 273 0 274 }; 275 static struct ispmdvec mdvec_2500 = { 276 isp_pci_rd_isr_2400, 277 isp_pci_rd_reg_2400, 278 isp_pci_wr_reg_2400, 279 isp_pci_mbxdma, 280 isp_pci_dmasetup, 281 isp_pci_dmateardown, 282 isp_pci_reset0, 283 isp_pci_reset1, 284 NULL, 285 ISP_2500_RISC_CODE, 286 0, 287 0 288 }; 289 #endif 290 291 #ifndef PCI_VENDOR_QLOGIC 292 #define PCI_VENDOR_QLOGIC 0x1077 293 #endif 294 295 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 296 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 297 #endif 298 299 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 300 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 301 #endif 302 303 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 304 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 305 #endif 306 307 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 308 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 309 #endif 310 311 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 312 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 313 #endif 314 315 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 316 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 317 #endif 318 319 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 320 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 321 #endif 322 323 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 324 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 325 #endif 326 327 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 328 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 329 #endif 330 331 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 332 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 333 #endif 334 335 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 336 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 337 #endif 338 339 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 340 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 341 #endif 342 343 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 344 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 345 #endif 346 347 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 348 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 349 #endif 350 351 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 352 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 353 #endif 354 355 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 356 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 357 #endif 358 359 360 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 361 362 #define PCI_QLOGIC_ISP1080 \ 363 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 364 365 #define PCI_QLOGIC_ISP10160 \ 366 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 367 368 #define PCI_QLOGIC_ISP12160 \ 369 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 370 371 #define PCI_QLOGIC_ISP1240 \ 372 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 373 374 #define PCI_QLOGIC_ISP1280 \ 375 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 376 377 #define PCI_QLOGIC_ISP2100 \ 378 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 379 380 #define PCI_QLOGIC_ISP2200 \ 381 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 382 383 #define PCI_QLOGIC_ISP2300 \ 384 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 385 386 #define PCI_QLOGIC_ISP2312 \ 387 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 388 389 #define PCI_QLOGIC_ISP2322 \ 390 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 391 392 #define PCI_QLOGIC_ISP2422 \ 393 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 394 395 #define PCI_QLOGIC_ISP2432 \ 396 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 397 398 #define PCI_QLOGIC_ISP2532 \ 399 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 400 401 #define PCI_QLOGIC_ISP6312 \ 402 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 403 404 #define PCI_QLOGIC_ISP6322 \ 405 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 406 407 #define IO_MAP_REG 0x10 408 #define MEM_MAP_REG 0x14 409 #define PCIR_ROMADDR 0x30 410 411 #define PCI_DFLT_LTNCY 0x40 412 #define PCI_DFLT_LNSZ 0x10 413 414 static int isp_pci_probe(device_t, cfdata_t, void *); 415 static void isp_pci_attach(device_t, device_t, void *); 416 417 struct isp_pcisoftc { 418 struct ispsoftc pci_isp; 419 pci_chipset_tag_t pci_pc; 420 pcitag_t pci_tag; 421 bus_space_tag_t pci_st; 422 bus_space_handle_t pci_sh; 423 bus_dmamap_t *pci_xfer_dmap; 424 void * pci_ih; 425 int16_t pci_poff[_NREG_BLKS]; 426 }; 427 428 CFATTACH_DECL_NEW(isp_pci, sizeof (struct isp_pcisoftc), 429 isp_pci_probe, isp_pci_attach, NULL, NULL); 430 431 static int 432 isp_pci_probe(device_t parent, cfdata_t match, void *aux) 433 { 434 struct pci_attach_args *pa = aux; 435 switch (pa->pa_id) { 436 #ifndef ISP_DISABLE_1020_SUPPORT 437 case PCI_QLOGIC_ISP: 438 return (1); 439 #endif 440 #ifndef ISP_DISABLE_1080_SUPPORT 441 case PCI_QLOGIC_ISP1080: 442 case PCI_QLOGIC_ISP1240: 443 case PCI_QLOGIC_ISP1280: 444 return (1); 445 #endif 446 #ifndef ISP_DISABLE_12160_SUPPORT 447 case PCI_QLOGIC_ISP10160: 448 case PCI_QLOGIC_ISP12160: 449 return (1); 450 #endif 451 #ifndef ISP_DISABLE_2100_SUPPORT 452 case PCI_QLOGIC_ISP2100: 453 return (1); 454 #endif 455 #ifndef ISP_DISABLE_2200_SUPPORT 456 case PCI_QLOGIC_ISP2200: 457 return (1); 458 #endif 459 #ifndef ISP_DISABLE_2300_SUPPORT 460 case PCI_QLOGIC_ISP2300: 461 case PCI_QLOGIC_ISP2312: 462 case PCI_QLOGIC_ISP6312: 463 #endif 464 #ifndef ISP_DISABLE_2322_SUPPORT 465 case PCI_QLOGIC_ISP2322: 466 case PCI_QLOGIC_ISP6322: 467 return (1); 468 #endif 469 #ifndef ISP_DISABLE_2400_SUPPORT 470 case PCI_QLOGIC_ISP2422: 471 case PCI_QLOGIC_ISP2432: 472 case PCI_QLOGIC_ISP2532: 473 return (1); 474 #endif 475 default: 476 return (0); 477 } 478 } 479 480 static void 481 isp_pci_attach(device_t parent, device_t self, void *aux) 482 { 483 static const char nomem[] = "\n%s: no mem for sdparam table\n"; 484 uint32_t data, rev, linesz = PCI_DFLT_LNSZ; 485 struct pci_attach_args *pa = aux; 486 struct isp_pcisoftc *pcs = device_private(self); 487 struct ispsoftc *isp = &pcs->pci_isp; 488 bus_space_tag_t st, iot, memt; 489 bus_space_handle_t sh, ioh, memh; 490 pci_intr_handle_t ih; 491 pcireg_t mem_type; 492 const char *dstring; 493 const char *intrstr; 494 int ioh_valid, memh_valid; 495 size_t mamt; 496 char intrbuf[PCI_INTRSTR_LEN]; 497 498 isp->isp_osinfo.dev = self; 499 500 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 501 PCI_MAPREG_TYPE_IO, 0, 502 &iot, &ioh, NULL, NULL) == 0); 503 504 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG); 505 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) { 506 memh_valid = 0; 507 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT && 508 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) { 509 memh_valid = 0; 510 } else { 511 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0, 512 &memt, &memh, NULL, NULL) == 0); 513 } 514 if (memh_valid) { 515 st = memt; 516 sh = memh; 517 } else if (ioh_valid) { 518 st = iot; 519 sh = ioh; 520 } else { 521 printf(": unable to map device registers\n"); 522 return; 523 } 524 dstring = "\n"; 525 526 isp->isp_nchan = 1; 527 mamt = 0; 528 529 pcs->pci_st = st; 530 pcs->pci_sh = sh; 531 pcs->pci_pc = pa->pa_pc; 532 pcs->pci_tag = pa->pa_tag; 533 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 534 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 535 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 536 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 537 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 538 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 539 540 541 #ifndef ISP_DISABLE_1020_SUPPORT 542 if (pa->pa_id == PCI_QLOGIC_ISP) { 543 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n"; 544 isp->isp_mdvec = &mdvec; 545 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 546 mamt = sizeof (sdparam); 547 } 548 #endif 549 #ifndef ISP_DISABLE_1080_SUPPORT 550 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 551 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n"; 552 isp->isp_mdvec = &mdvec_1080; 553 isp->isp_type = ISP_HA_SCSI_1080; 554 mamt = sizeof (sdparam); 555 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 556 ISP1080_DMA_REGS_OFF; 557 } 558 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 559 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n"; 560 isp->isp_mdvec = &mdvec_1080; 561 isp->isp_type = ISP_HA_SCSI_1240; 562 isp->isp_nchan++; 563 mamt = sizeof (sdparam) * 2; 564 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 565 ISP1080_DMA_REGS_OFF; 566 } 567 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 568 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n"; 569 isp->isp_mdvec = &mdvec_1080; 570 isp->isp_type = ISP_HA_SCSI_1280; 571 isp->isp_nchan++; 572 mamt = sizeof (sdparam) * 2; 573 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 574 ISP1080_DMA_REGS_OFF; 575 } 576 #endif 577 #ifndef ISP_DISABLE_12160_SUPPORT 578 if (pa->pa_id == PCI_QLOGIC_ISP10160) { 579 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n"; 580 isp->isp_mdvec = &mdvec_12160; 581 isp->isp_type = ISP_HA_SCSI_10160; 582 mamt = sizeof (sdparam); 583 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 584 ISP1080_DMA_REGS_OFF; 585 } 586 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 587 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n"; 588 isp->isp_mdvec = &mdvec_12160; 589 isp->isp_type = ISP_HA_SCSI_12160; 590 isp->isp_nchan++; 591 mamt = sizeof (sdparam) * 2; 592 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 593 ISP1080_DMA_REGS_OFF; 594 } 595 #endif 596 #ifndef ISP_DISABLE_2100_SUPPORT 597 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 598 dstring = ": QLogic FC-AL HBA\n"; 599 isp->isp_mdvec = &mdvec_2100; 600 isp->isp_type = ISP_HA_FC_2100; 601 mamt = sizeof (fcparam); 602 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 603 PCI_MBOX_REGS2100_OFF; 604 if (rev < 3) { 605 /* 606 * XXX: Need to get the actual revision 607 * XXX: number of the 2100 FB. At any rate, 608 * XXX: lower cache line size for early revision 609 * XXX; boards. 610 */ 611 linesz = 1; 612 } 613 } 614 #endif 615 #ifndef ISP_DISABLE_2200_SUPPORT 616 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 617 dstring = ": QLogic FC-AL and Fabric HBA\n"; 618 isp->isp_mdvec = &mdvec_2200; 619 isp->isp_type = ISP_HA_FC_2200; 620 mamt = sizeof (fcparam); 621 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 622 PCI_MBOX_REGS2100_OFF; 623 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 624 } 625 #endif 626 #ifndef ISP_DISABLE_2300_SUPPORT 627 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 628 pa->pa_id == PCI_QLOGIC_ISP2312 || 629 pa->pa_id == PCI_QLOGIC_ISP6312) { 630 isp->isp_mdvec = &mdvec_2300; 631 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 632 pa->pa_id == PCI_QLOGIC_ISP6312) { 633 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n"; 634 isp->isp_type = ISP_HA_FC_2300; 635 } else { 636 dstring = 637 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n"; 638 isp->isp_port = pa->pa_function; 639 } 640 isp->isp_type = ISP_HA_FC_2312; 641 mamt = sizeof (fcparam); 642 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 643 PCI_MBOX_REGS2300_OFF; 644 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 645 } 646 #endif 647 #ifndef ISP_DISABLE_2322_SUPPORT 648 if (pa->pa_id == PCI_QLOGIC_ISP2322 || 649 pa->pa_id == PCI_QLOGIC_ISP6322) { 650 isp->isp_mdvec = &mdvec_2322; 651 dstring = ": QLogic FC-AL and 2Gbps Fabric PCI-E HBA\n"; 652 isp->isp_type = ISP_HA_FC_2322; 653 isp->isp_port = pa->pa_function; 654 mamt = sizeof (fcparam); 655 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 656 PCI_MBOX_REGS2300_OFF; 657 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 658 } 659 #endif 660 #ifndef ISP_DISABLE_2400_SUPPORT 661 if (pa->pa_id == PCI_QLOGIC_ISP2422 || 662 pa->pa_id == PCI_QLOGIC_ISP2432) { 663 isp->isp_mdvec = &mdvec_2400; 664 if (pa->pa_id == PCI_QLOGIC_ISP2422) { 665 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-X HBA\n"; 666 } else { 667 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-E HBA\n"; 668 } 669 isp->isp_type = ISP_HA_FC_2400; 670 isp->isp_port = pa->pa_function; 671 mamt = sizeof (fcparam); 672 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 673 PCI_MBOX_REGS2400_OFF; 674 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 675 } 676 if (pa->pa_id == PCI_QLOGIC_ISP2532) { 677 isp->isp_mdvec = &mdvec_2500; 678 dstring = ": QLogic FC-AL and 8Gbps Fabric PCI-E HBA\n"; 679 isp->isp_type = ISP_HA_FC_2500; 680 isp->isp_port = pa->pa_function; 681 mamt = sizeof (fcparam); 682 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 683 PCI_MBOX_REGS2400_OFF; 684 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 685 } 686 #endif 687 if (mamt == 0) { 688 return; 689 } 690 691 isp->isp_param = malloc(mamt, M_DEVBUF, M_NOWAIT); 692 if (isp->isp_param == NULL) { 693 printf(nomem, device_xname(self)); 694 return; 695 } 696 memset(isp->isp_param, 0, mamt); 697 mamt = sizeof (struct scsipi_channel) * isp->isp_nchan; 698 isp->isp_osinfo.chan = malloc(mamt, M_DEVBUF, M_NOWAIT); 699 if (isp->isp_osinfo.chan == NULL) { 700 free(isp->isp_param, M_DEVBUF); 701 printf(nomem, device_xname(self)); 702 return; 703 } 704 memset(isp->isp_osinfo.chan, 0, mamt); 705 isp->isp_osinfo.adapter.adapt_nchannels = isp->isp_nchan; 706 707 /* 708 * Set up logging levels. 709 */ 710 #ifdef ISP_LOGDEFAULT 711 isp->isp_dblev = ISP_LOGDEFAULT; 712 #else 713 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 714 if (bootverbose) 715 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 716 #ifdef SCSIDEBUG 717 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2; 718 #endif 719 #endif 720 if (isp->isp_dblev & ISP_LOGCONFIG) { 721 printf("\n"); 722 } else { 723 printf("%s", dstring); 724 } 725 726 isp->isp_dmatag = pa->pa_dmat; 727 isp->isp_revision = rev; 728 729 /* 730 * Make sure that command register set sanely. 731 */ 732 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 733 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 734 735 /* 736 * Not so sure about these- but I think it's important that they get 737 * enabled...... 738 */ 739 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 740 if (IS_2300(isp)) { /* per QLogic errata */ 741 data &= ~PCI_COMMAND_INVALIDATE_ENABLE; 742 } 743 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 744 745 /* 746 * Make sure that the latency timer, cache line size, 747 * and ROM is disabled. 748 */ 749 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 750 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 751 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 752 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 753 data |= (linesz << PCI_CACHELINE_SHIFT); 754 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 755 756 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 757 data &= ~1; 758 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 759 760 if (pci_intr_map(pa, &ih)) { 761 aprint_error_dev(self, "couldn't map interrupt\n"); 762 free(isp->isp_param, M_DEVBUF); 763 free(isp->isp_osinfo.chan, M_DEVBUF); 764 return; 765 } 766 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 767 if (intrstr == NULL) 768 intrstr = "<I dunno>"; 769 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 770 isp_pci_intr, isp); 771 if (pcs->pci_ih == NULL) { 772 aprint_error_dev(self, "couldn't establish interrupt at %s\n", 773 intrstr); 774 free(isp->isp_param, M_DEVBUF); 775 free(isp->isp_osinfo.chan, M_DEVBUF); 776 return; 777 } 778 779 printf("%s: interrupting at %s\n", device_xname(self), intrstr); 780 781 isp->isp_confopts = device_cfdata(self)->cf_flags; 782 ISP_LOCK(isp); 783 isp_reset(isp, 1); 784 if (isp->isp_state != ISP_RESETSTATE) { 785 ISP_UNLOCK(isp); 786 free(isp->isp_param, M_DEVBUF); 787 free(isp->isp_osinfo.chan, M_DEVBUF); 788 return; 789 } 790 isp_init(isp); 791 if (isp->isp_state != ISP_INITSTATE) { 792 isp_uninit(isp); 793 ISP_UNLOCK(isp); 794 free(isp->isp_param, M_DEVBUF); 795 free(isp->isp_osinfo.chan, M_DEVBUF); 796 return; 797 } 798 /* 799 * Do platform attach. 800 */ 801 ISP_UNLOCK(isp); 802 isp_attach(isp); 803 } 804 805 #define IspVirt2Off(a, x) \ 806 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 807 _BLK_REG_SHFT] + ((x) & 0xff)) 808 809 #define BXR2(pcs, off) \ 810 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 811 #define BXW2(pcs, off, v) \ 812 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 813 #define BXR4(pcs, off) \ 814 bus_space_read_4(pcs->pci_st, pcs->pci_sh, off) 815 #define BXW4(pcs, off, v) \ 816 bus_space_write_4(pcs->pci_st, pcs->pci_sh, off, v) 817 818 819 static int 820 isp_pci_rd_debounced(struct ispsoftc *isp, int off, uint16_t *rp) 821 { 822 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 823 uint16_t val0, val1; 824 int i = 0; 825 826 do { 827 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 828 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 829 } while (val0 != val1 && ++i < 1000); 830 if (val0 != val1) { 831 return (1); 832 } 833 *rp = val0; 834 return (0); 835 } 836 837 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 838 !defined(ISP_DISABLE_2200_SUPPORT) && \ 839 !defined(ISP_DISABLE_1020_SUPPORT) && \ 840 !defined(ISP_DISABLE_1080_SUPPORT) && \ 841 !defined(ISP_DISABLE_12160_SUPPORT) 842 static int 843 isp_pci_rd_isr(struct ispsoftc *isp, uint32_t *isrp, 844 uint16_t *semap, uint16_t *mbp) 845 { 846 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 847 uint16_t isr, sema; 848 849 if (IS_2100(isp)) { 850 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 851 return (0); 852 } 853 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 854 return (0); 855 } 856 } else { 857 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 858 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 859 } 860 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 861 isr &= INT_PENDING_MASK(isp); 862 sema &= BIU_SEMA_LOCK; 863 if (isr == 0 && sema == 0) { 864 return (0); 865 } 866 *isrp = isr; 867 if ((*semap = sema) != 0) { 868 if (IS_2100(isp)) { 869 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 870 return (0); 871 } 872 } else { 873 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 874 } 875 } 876 return (1); 877 } 878 #endif 879 880 #if !(defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_2322_SUPPORT)) 881 static int 882 isp_pci_rd_isr_2300(struct ispsoftc *isp, uint32_t *isrp, 883 uint16_t *semap, uint16_t *mbox0p) 884 { 885 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 886 uint32_t r2hisr; 887 888 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 889 *isrp = 0; 890 return (0); 891 } 892 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 893 IspVirt2Off(pcs, BIU_R2HSTSLO)); 894 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 895 if ((r2hisr & BIU_R2HST_INTR) == 0) { 896 *isrp = 0; 897 return (0); 898 } 899 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 900 case ISPR2HST_ROM_MBX_OK: 901 case ISPR2HST_ROM_MBX_FAIL: 902 case ISPR2HST_MBX_OK: 903 case ISPR2HST_MBX_FAIL: 904 case ISPR2HST_ASYNC_EVENT: 905 *isrp = r2hisr & 0xffff; 906 *mbox0p = (r2hisr >> 16); 907 *semap = 1; 908 return (1); 909 case ISPR2HST_RIO_16: 910 *isrp = r2hisr & 0xffff; 911 *mbox0p = ASYNC_RIO16_1; 912 *semap = 1; 913 return (1); 914 case ISPR2HST_FPOST: 915 *isrp = r2hisr & 0xffff; 916 *mbox0p = ASYNC_CMD_CMPLT; 917 *semap = 1; 918 return (1); 919 case ISPR2HST_FPOST_CTIO: 920 *isrp = r2hisr & 0xffff; 921 *mbox0p = ASYNC_CTIO_DONE; 922 *semap = 1; 923 return (1); 924 case ISPR2HST_RSPQ_UPDATE: 925 *isrp = r2hisr & 0xffff; 926 *mbox0p = 0; 927 *semap = 0; 928 return (1); 929 default: 930 return (0); 931 } 932 } 933 #endif 934 935 #ifndef ISP_DISABLE_2400_SUPPORT 936 static int 937 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, 938 uint16_t *semap, uint16_t *mbox0p) 939 { 940 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 941 uint32_t r2hisr; 942 943 r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU2400_R2HSTSLO)); 944 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 945 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 946 *isrp = 0; 947 return (0); 948 } 949 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 950 case ISP2400R2HST_ROM_MBX_OK: 951 case ISP2400R2HST_ROM_MBX_FAIL: 952 case ISP2400R2HST_MBX_OK: 953 case ISP2400R2HST_MBX_FAIL: 954 case ISP2400R2HST_ASYNC_EVENT: 955 *isrp = r2hisr & 0xffff; 956 *mbox0p = (r2hisr >> 16); 957 *semap = 1; 958 return (1); 959 case ISP2400R2HST_RSPQ_UPDATE: 960 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 961 case ISP2400R2HST_ATIO_RQST_UPDATE: 962 *isrp = r2hisr & 0xffff; 963 *mbox0p = 0; 964 *semap = 0; 965 return (1); 966 default: 967 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 968 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 969 return (0); 970 } 971 } 972 973 static uint32_t 974 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 975 { 976 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 977 uint32_t rv; 978 int block = regoff & _BLK_REG_MASK; 979 980 switch (block) { 981 case BIU_BLOCK: 982 break; 983 case MBOX_BLOCK: 984 return (BXR2(pcs, IspVirt2Off(pcs, regoff))); 985 case SXP_BLOCK: 986 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 987 return (0xffffffff); 988 case RISC_BLOCK: 989 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 990 return (0xffffffff); 991 case DMA_BLOCK: 992 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 993 return (0xffffffff); 994 default: 995 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 996 return (0xffffffff); 997 } 998 999 1000 switch (regoff) { 1001 case BIU2400_FLASH_ADDR: 1002 case BIU2400_FLASH_DATA: 1003 case BIU2400_ICR: 1004 case BIU2400_ISR: 1005 case BIU2400_CSR: 1006 case BIU2400_REQINP: 1007 case BIU2400_REQOUTP: 1008 case BIU2400_RSPINP: 1009 case BIU2400_RSPOUTP: 1010 case BIU2400_PRI_REQINP: 1011 case BIU2400_PRI_REQOUTP: 1012 case BIU2400_ATIO_RSPINP: 1013 case BIU2400_ATIO_RSPOUTP: 1014 case BIU2400_HCCR: 1015 case BIU2400_GPIOD: 1016 case BIU2400_GPIOE: 1017 case BIU2400_HSEMA: 1018 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1019 break; 1020 case BIU2400_R2HSTSLO: 1021 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1022 break; 1023 case BIU2400_R2HSTSHI: 1024 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)) >> 16; 1025 break; 1026 default: 1027 isp_prt(isp, ISP_LOGERR, 1028 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1029 rv = 0xffffffff; 1030 break; 1031 } 1032 return (rv); 1033 } 1034 1035 static void 1036 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1037 { 1038 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1039 int block = regoff & _BLK_REG_MASK; 1040 1041 switch (block) { 1042 case BIU_BLOCK: 1043 break; 1044 case MBOX_BLOCK: 1045 BXW2(pcs, IspVirt2Off(pcs, regoff), val); 1046 (void)BXR2(pcs, IspVirt2Off(pcs, regoff)); 1047 return; 1048 case SXP_BLOCK: 1049 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1050 return; 1051 case RISC_BLOCK: 1052 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1053 return; 1054 case DMA_BLOCK: 1055 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1056 return; 1057 default: 1058 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1059 regoff); 1060 break; 1061 } 1062 1063 switch (regoff) { 1064 case BIU2400_FLASH_ADDR: 1065 case BIU2400_FLASH_DATA: 1066 case BIU2400_ICR: 1067 case BIU2400_ISR: 1068 case BIU2400_CSR: 1069 case BIU2400_REQINP: 1070 case BIU2400_REQOUTP: 1071 case BIU2400_RSPINP: 1072 case BIU2400_RSPOUTP: 1073 case BIU2400_PRI_REQINP: 1074 case BIU2400_PRI_REQOUTP: 1075 case BIU2400_ATIO_RSPINP: 1076 case BIU2400_ATIO_RSPOUTP: 1077 case BIU2400_HCCR: 1078 case BIU2400_GPIOD: 1079 case BIU2400_GPIOE: 1080 case BIU2400_HSEMA: 1081 BXW4(pcs, IspVirt2Off(pcs, regoff), val); 1082 (void)BXR4(pcs, IspVirt2Off(pcs, regoff)); 1083 break; 1084 default: 1085 isp_prt(isp, ISP_LOGERR, 1086 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1087 break; 1088 } 1089 } 1090 #endif 1091 1092 static uint32_t 1093 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 1094 { 1095 uint32_t rv; 1096 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1097 int oldconf = 0; 1098 1099 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1100 /* 1101 * We will assume that someone has paused the RISC processor. 1102 */ 1103 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1104 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1105 oldconf | BIU_PCI_CONF1_SXP); 1106 } 1107 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1108 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1109 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1110 } 1111 return (rv); 1112 } 1113 1114 static void 1115 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, uint32_t val) 1116 { 1117 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1118 int oldconf = 0; 1119 1120 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1121 /* 1122 * We will assume that someone has paused the RISC processor. 1123 */ 1124 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1125 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1126 oldconf | BIU_PCI_CONF1_SXP); 1127 } 1128 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1129 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1130 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1131 } 1132 } 1133 1134 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 1135 static uint32_t 1136 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 1137 { 1138 uint16_t rv, oc = 0; 1139 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1140 1141 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1142 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1143 uint16_t tc; 1144 /* 1145 * We will assume that someone has paused the RISC processor. 1146 */ 1147 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1148 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1149 if (regoff & SXP_BANK1_SELECT) 1150 tc |= BIU_PCI1080_CONF1_SXP1; 1151 else 1152 tc |= BIU_PCI1080_CONF1_SXP0; 1153 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1154 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1155 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1156 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1157 oc | BIU_PCI1080_CONF1_DMA); 1158 } 1159 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1160 if (oc) { 1161 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1162 } 1163 return (rv); 1164 } 1165 1166 static void 1167 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, uint32_t val) 1168 { 1169 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1170 int oc = 0; 1171 1172 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1173 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1174 uint16_t tc; 1175 /* 1176 * We will assume that someone has paused the RISC processor. 1177 */ 1178 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1179 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1180 if (regoff & SXP_BANK1_SELECT) 1181 tc |= BIU_PCI1080_CONF1_SXP1; 1182 else 1183 tc |= BIU_PCI1080_CONF1_SXP0; 1184 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1185 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1186 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1187 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1188 oc | BIU_PCI1080_CONF1_DMA); 1189 } 1190 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1191 if (oc) { 1192 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1193 } 1194 } 1195 #endif 1196 1197 static int 1198 isp_pci_mbxdma(struct ispsoftc *isp) 1199 { 1200 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1201 bus_dma_tag_t dmat = isp->isp_dmatag; 1202 bus_dma_segment_t sg; 1203 bus_size_t len, dbound; 1204 fcparam *fcp; 1205 int rs, i; 1206 1207 if (isp->isp_rquest_dma) /* been here before? */ 1208 return (0); 1209 1210 if (isp->isp_type <= ISP_HA_SCSI_1040B) { 1211 dbound = 1 << 24; 1212 } else { 1213 /* 1214 * For 32-bit PCI DMA, the range is 32 bits or zero :-) 1215 */ 1216 dbound = 0; 1217 } 1218 len = isp->isp_maxcmds * sizeof (isp_hdl_t); 1219 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK); 1220 if (isp->isp_xflist == NULL) { 1221 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 1222 return (1); 1223 } 1224 memset(isp->isp_xflist, 0, len); 1225 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1226 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1227 } 1228 isp->isp_xffree = isp->isp_xflist; 1229 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 1230 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1231 if (pcs->pci_xfer_dmap == NULL) { 1232 free(isp->isp_xflist, M_DEVBUF); 1233 isp->isp_xflist = NULL; 1234 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array"); 1235 return (1); 1236 } 1237 for (i = 0; i < isp->isp_maxcmds; i++) { 1238 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 1239 MAXPHYS, dbound, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 1240 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps"); 1241 break; 1242 } 1243 } 1244 if (i < isp->isp_maxcmds) { 1245 while (--i >= 0) { 1246 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1247 } 1248 free(isp->isp_xflist, M_DEVBUF); 1249 free(pcs->pci_xfer_dmap, M_DEVBUF); 1250 isp->isp_xflist = NULL; 1251 pcs->pci_xfer_dmap = NULL; 1252 return (1); 1253 } 1254 1255 /* 1256 * Allocate and map the request queue. 1257 */ 1258 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1259 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 0)) { 1260 goto dmafail; 1261 } 1262 if (bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 1263 (void *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1264 goto dmafail; 1265 } 1266 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1267 &isp->isp_rqdmap)) { 1268 goto dmafail; 1269 } 1270 if (bus_dmamap_load(dmat, isp->isp_rqdmap, isp->isp_rquest, len, NULL, 1271 BUS_DMA_NOWAIT)) { 1272 goto dmafail; 1273 } 1274 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 1275 1276 /* 1277 * Allocate and map the result queue. 1278 */ 1279 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1280 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 1281 BUS_DMA_NOWAIT)) { 1282 goto dmafail; 1283 } 1284 if (bus_dmamem_map(dmat, &sg, rs, len, 1285 (void *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1286 goto dmafail; 1287 } 1288 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1289 &isp->isp_rsdmap)) { 1290 goto dmafail; 1291 } 1292 if (bus_dmamap_load(dmat, isp->isp_rsdmap, isp->isp_result, len, NULL, 1293 BUS_DMA_NOWAIT)) { 1294 goto dmafail; 1295 } 1296 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 1297 1298 if (IS_SCSI(isp)) { 1299 return (0); 1300 } 1301 1302 /* 1303 * Allocate and map an FC scratch area 1304 */ 1305 fcp = isp->isp_param; 1306 len = ISP_FC_SCRLEN; 1307 if (bus_dmamem_alloc(dmat, len, sizeof (uint64_t), 0, &sg, 1, &rs, 1308 BUS_DMA_NOWAIT)) { 1309 goto dmafail; 1310 } 1311 if (bus_dmamem_map(dmat, &sg, rs, len, 1312 (void *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1313 goto dmafail; 1314 } 1315 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1316 &isp->isp_scdmap)) { 1317 goto dmafail; 1318 } 1319 if (bus_dmamap_load(dmat, isp->isp_scdmap, fcp->isp_scratch, len, NULL, 1320 BUS_DMA_NOWAIT)) { 1321 goto dmafail; 1322 } 1323 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 1324 return (0); 1325 dmafail: 1326 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure"); 1327 for (i = 0; i < isp->isp_maxcmds; i++) { 1328 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1329 } 1330 free(isp->isp_xflist, M_DEVBUF); 1331 free(pcs->pci_xfer_dmap, M_DEVBUF); 1332 isp->isp_xflist = NULL; 1333 pcs->pci_xfer_dmap = NULL; 1334 return (1); 1335 } 1336 1337 static int 1338 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, void *arg) 1339 { 1340 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1341 ispreq_t *rq = arg; 1342 bus_dmamap_t dmap; 1343 bus_dma_segment_t *dm_segs; 1344 uint32_t nsegs, hidx; 1345 isp_ddir_t ddir; 1346 1347 hidx = isp_handle_index(isp, rq->req_handle); 1348 if (hidx == ISP_BAD_HANDLE_INDEX) { 1349 XS_SETERR(xs, HBA_BOTCH); 1350 return (CMD_COMPLETE); 1351 } 1352 dmap = pcs->pci_xfer_dmap[hidx]; 1353 if (xs->datalen == 0) { 1354 ddir = ISP_NOXFR; 1355 nsegs = 0; 1356 dm_segs = NULL; 1357 } else { 1358 int error; 1359 uint32_t flag, flg2; 1360 1361 if (sizeof (bus_addr_t) > 4) { 1362 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1363 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1364 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1365 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1366 } 1367 } 1368 1369 if (xs->xs_control & XS_CTL_DATA_IN) { 1370 flg2 = BUS_DMASYNC_PREREAD; 1371 flag = BUS_DMA_READ; 1372 ddir = ISP_FROM_DEVICE; 1373 } else { 1374 flg2 = BUS_DMASYNC_PREWRITE; 1375 flag = BUS_DMA_WRITE; 1376 ddir = ISP_TO_DEVICE; 1377 } 1378 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 1379 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | flag); 1380 if (error) { 1381 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", error); 1382 XS_SETERR(xs, HBA_BOTCH); 1383 if (error == EAGAIN || error == ENOMEM) { 1384 return (CMD_EAGAIN); 1385 } else { 1386 return (CMD_COMPLETE); 1387 } 1388 } 1389 dm_segs = dmap->dm_segs; 1390 nsegs = dmap->dm_nsegs; 1391 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, flg2); 1392 } 1393 1394 if (isp_send_cmd(isp, rq, dm_segs, nsegs, xs->datalen, ddir) != CMD_QUEUED) { 1395 return (CMD_EAGAIN); 1396 } else { 1397 return (CMD_QUEUED); 1398 } 1399 } 1400 1401 static int 1402 isp_pci_intr(void *arg) 1403 { 1404 uint32_t isr; 1405 uint16_t sema, mbox; 1406 struct ispsoftc *isp = arg; 1407 1408 isp->isp_intcnt++; 1409 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1410 isp->isp_intbogus++; 1411 return (0); 1412 } else { 1413 isp->isp_osinfo.onintstack = 1; 1414 isp_intr(isp, isr, sema, mbox); 1415 isp->isp_osinfo.onintstack = 0; 1416 return (1); 1417 } 1418 } 1419 1420 static void 1421 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, uint32_t handle) 1422 { 1423 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1424 uint32_t hidx; 1425 bus_dmamap_t dmap; 1426 1427 hidx = isp_handle_index(isp, handle); 1428 if (hidx == ISP_BAD_HANDLE_INDEX) { 1429 isp_xs_prt(isp, xs, ISP_LOGERR, "bad handle on teardown"); 1430 return; 1431 } 1432 dmap = pcs->pci_xfer_dmap[hidx]; 1433 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1434 xs->xs_control & XS_CTL_DATA_IN ? 1435 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1436 bus_dmamap_unload(isp->isp_dmatag, dmap); 1437 } 1438 1439 static void 1440 isp_pci_reset0(ispsoftc_t *isp) 1441 { 1442 ISP_DISABLE_INTS(isp); 1443 } 1444 1445 static void 1446 isp_pci_reset1(ispsoftc_t *isp) 1447 { 1448 if (!IS_24XX(isp)) { 1449 /* Make sure the BIOS is disabled */ 1450 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1451 } 1452 /* and enable interrupts */ 1453 ISP_ENABLE_INTS(isp); 1454 } 1455 1456 static void 1457 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1458 { 1459 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1460 if (msg) 1461 printf("%s: %s\n", device_xname(isp->isp_osinfo.dev), msg); 1462 if (IS_SCSI(isp)) 1463 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1464 else 1465 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1466 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1467 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1468 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1469 1470 1471 if (IS_SCSI(isp)) { 1472 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1473 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1474 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1475 ISP_READ(isp, CDMA_FIFO_STS)); 1476 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1477 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1478 ISP_READ(isp, DDMA_FIFO_STS)); 1479 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1480 ISP_READ(isp, SXP_INTERRUPT), 1481 ISP_READ(isp, SXP_GROSS_ERR), 1482 ISP_READ(isp, SXP_PINS_CTRL)); 1483 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1484 } 1485 printf(" mbox regs: %x %x %x %x %x\n", 1486 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1487 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1488 ISP_READ(isp, OUTMAILBOX4)); 1489 printf(" PCI Status Command/Status=%x\n", 1490 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1491 } 1492
Indexes created Mon Sep 29 03:10:08 GMT 2025