isp_pci.c revision 1.17.2.1 1 /* $NetBSD: isp_pci.c,v 1.17.2.1 1998/11/07 05:55:55 cgd Exp $ */
2 /*
3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
4 *
5 *---------------------------------------
6 * Copyright (c) 1997, 1998 by Matthew Jacob
7 * NASA/Ames Research Center
8 * All rights reserved.
9 *---------------------------------------
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice immediately at the beginning of the file, without modification,
16 * this list of conditions, and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 */
36
37 #include <dev/ic/isp_netbsd.h>
38 #include <dev/microcode/isp/asm_pci.h>
39
40 #include <dev/pci/pcireg.h>
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcidevs.h>
43
44 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int));
45 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t));
46 static int isp_pci_mbxdma __P((struct ispsoftc *));
47 static int isp_pci_dmasetup __P((struct ispsoftc *, struct scsipi_xfer *,
48 ispreq_t *, u_int8_t *, u_int8_t));
49 static void isp_pci_dmateardown __P((struct ispsoftc *, struct scsipi_xfer *,
50 u_int32_t));
51 static void isp_pci_reset1 __P((struct ispsoftc *));
52 static void isp_pci_dumpregs __P((struct ispsoftc *));
53 static int isp_pci_intr __P((void *));
54
55 static struct ispmdvec mdvec = {
56 isp_pci_rd_reg,
57 isp_pci_wr_reg,
58 isp_pci_mbxdma,
59 isp_pci_dmasetup,
60 isp_pci_dmateardown,
61 NULL,
62 isp_pci_reset1,
63 isp_pci_dumpregs,
64 ISP_RISC_CODE,
65 ISP_CODE_LENGTH,
66 ISP_CODE_ORG,
67 ISP_CODE_VERSION,
68 BIU_BURST_ENABLE, /* default to 8 byte burst */
69 0
70 };
71
72 static struct ispmdvec mdvec_2100 = {
73 isp_pci_rd_reg,
74 isp_pci_wr_reg,
75 isp_pci_mbxdma,
76 isp_pci_dmasetup,
77 isp_pci_dmateardown,
78 NULL,
79 isp_pci_reset1,
80 isp_pci_dumpregs,
81 ISP2100_RISC_CODE,
82 ISP2100_CODE_LENGTH,
83 ISP2100_CODE_ORG,
84 ISP2100_CODE_VERSION,
85 BIU_BURST_ENABLE, /* default to 8 byte burst */
86 0 /* Not relevant to the 2100 */
87 };
88
89 #define PCI_QLOGIC_ISP \
90 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
91
92 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
93 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
94 #endif
95 #define PCI_QLOGIC_ISP2100 \
96 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
97
98 #define IO_MAP_REG 0x10
99 #define MEM_MAP_REG 0x14
100
101
102 #ifdef __BROKEN_INDIRECT_CONFIG
103 static int isp_pci_probe __P((struct device *, void *, void *));
104 #else
105 static int isp_pci_probe __P((struct device *, struct cfdata *, void *));
106 #endif
107 static void isp_pci_attach __P((struct device *, struct device *, void *));
108
109 struct isp_pcisoftc {
110 struct ispsoftc pci_isp;
111 pci_chipset_tag_t pci_pc;
112 pcitag_t pci_tag;
113 bus_space_tag_t pci_st;
114 bus_space_handle_t pci_sh;
115 bus_dma_tag_t pci_dmat;
116 bus_dmamap_t pci_scratch_dmap; /* for fcp only */
117 bus_dmamap_t pci_rquest_dmap;
118 bus_dmamap_t pci_result_dmap;
119 bus_dmamap_t pci_xfer_dmap[MAXISPREQUEST];
120 void * pci_ih;
121 };
122
123 struct cfattach isp_pci_ca = {
124 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach
125 };
126
127 static int
128 isp_pci_probe(parent, match, aux)
129 struct device *parent;
130 #ifdef __BROKEN_INDIRECT_CONFIG
131 void *match;
132 #else
133 struct cfdata *match;
134 #endif
135 void *aux;
136 {
137 struct pci_attach_args *pa = aux;
138
139 if (pa->pa_id == PCI_QLOGIC_ISP ||
140 pa->pa_id == PCI_QLOGIC_ISP2100) {
141 return (1);
142 } else {
143 return (0);
144 }
145 }
146
147
148 static void
149 isp_pci_attach(parent, self, aux)
150 struct device *parent, *self;
151 void *aux;
152 {
153 #ifdef DEBUG
154 static char oneshot = 1;
155 #endif
156 struct pci_attach_args *pa = aux;
157 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self;
158 struct ispsoftc *isp = &pcs->pci_isp;
159 bus_space_tag_t st, iot, memt;
160 bus_space_handle_t sh, ioh, memh;
161 pci_intr_handle_t ih;
162 const char *intrstr;
163 int ioh_valid, memh_valid, i;
164 ISP_LOCKVAL_DECL;
165
166 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
167 PCI_MAPREG_TYPE_IO, 0,
168 &iot, &ioh, NULL, NULL) == 0);
169 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG,
170 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
171 &memt, &memh, NULL, NULL) == 0);
172
173 if (memh_valid) {
174 st = memt;
175 sh = memh;
176 } else if (ioh_valid) {
177 st = iot;
178 sh = ioh;
179 } else {
180 printf(": unable to map device registers\n");
181 return;
182 }
183 printf("\n");
184
185 pcs->pci_st = st;
186 pcs->pci_sh = sh;
187 pcs->pci_dmat = pa->pa_dmat;
188 pcs->pci_pc = pa->pa_pc;
189 pcs->pci_tag = pa->pa_tag;
190 if (pa->pa_id == PCI_QLOGIC_ISP) {
191 isp->isp_mdvec = &mdvec;
192 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
193 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT);
194 if (isp->isp_param == NULL) {
195 printf("%s: couldn't allocate sdparam table\n",
196 isp->isp_name);
197 return;
198 }
199 bzero(isp->isp_param, sizeof (sdparam));
200 } else if (pa->pa_id == PCI_QLOGIC_ISP2100) {
201 u_int32_t data;
202 isp->isp_mdvec = &mdvec_2100;
203 if (ioh_valid == 0) {
204 printf("%s: warning, ISP2100 cannot use I/O Space"
205 " Mappings\n", isp->isp_name);
206 } else {
207 pcs->pci_st = iot;
208 pcs->pci_sh = ioh;
209 }
210
211 #if 0
212 printf("%s: PCIREGS cmd=%x bhlc=%x\n", isp->isp_name,
213 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG),
214 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG));
215 #endif
216 isp->isp_type = ISP_HA_FC_2100;
217 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT);
218 if (isp->isp_param == NULL) {
219 printf("%s: couldn't allocate fcparam table\n",
220 isp->isp_name);
221 return;
222 }
223 bzero(isp->isp_param, sizeof (fcparam));
224
225 data = pci_conf_read(pa->pa_pc, pa->pa_tag,
226 PCI_COMMAND_STATUS_REG);
227 data |= PCI_COMMAND_MASTER_ENABLE |
228 PCI_COMMAND_INVALIDATE_ENABLE;
229 pci_conf_write(pa->pa_pc, pa->pa_tag,
230 PCI_COMMAND_STATUS_REG, data);
231 /*
232 * Wierd- we need to clear the lsb in offset 0x30 to take the
233 * chip out of reset state.
234 */
235 data = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x30);
236 data &= ~1;
237 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x30, data);
238 #if 0
239 /*
240 * XXX: Need to get the actual revision number of the 2100 FB
241 */
242 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
243 data &= ~0xffff;
244 data |= 0xf801;
245 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
246 printf("%s: setting latency to %x and cache line size to %x\n",
247 isp->isp_name, (data >> 8) & 0xff,
248 data & 0xff);
249 #endif
250 } else {
251 return;
252 }
253 #ifdef DEBUG
254 if (oneshot) {
255 oneshot = 0;
256 printf("Qlogic ISP Driver, NetBSD (pci) Platform Version "
257 "%d.%d Core Version %d.%d\n",
258 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
259 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
260 }
261 #endif
262 ISP_LOCK(isp);
263 isp_reset(isp);
264 if (isp->isp_state != ISP_RESETSTATE) {
265 ISP_UNLOCK(isp);
266 free(isp->isp_param, M_DEVBUF);
267 return;
268 }
269 isp_init(isp);
270 if (isp->isp_state != ISP_INITSTATE) {
271 isp_uninit(isp);
272 ISP_UNLOCK(isp);
273 free(isp->isp_param, M_DEVBUF);
274 return;
275 }
276
277 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
278 pa->pa_intrline, &ih)) {
279 printf("%s: couldn't map interrupt\n", isp->isp_name);
280 isp_uninit(isp);
281 ISP_UNLOCK(isp);
282 free(isp->isp_param, M_DEVBUF);
283 return;
284 }
285
286 intrstr = pci_intr_string(pa->pa_pc, ih);
287 if (intrstr == NULL)
288 intrstr = "<I dunno>";
289 pcs->pci_ih =
290 pci_intr_establish(pa->pa_pc, ih, IPL_BIO, isp_pci_intr, isp);
291 if (pcs->pci_ih == NULL) {
292 printf("%s: couldn't establish interrupt at %s\n",
293 isp->isp_name, intrstr);
294 isp_uninit(isp);
295 ISP_UNLOCK(isp);
296 free(isp->isp_param, M_DEVBUF);
297 return;
298 }
299 printf("%s: interrupting at %s\n", isp->isp_name, intrstr);
300
301 /*
302 * Create the DMA maps for the data transfers.
303 */
304 for (i = 0; i < RQUEST_QUEUE_LEN; i++) {
305 if (bus_dmamap_create(pcs->pci_dmat, MAXPHYS,
306 (MAXPHYS / NBPG) + 1, MAXPHYS, 0, BUS_DMA_NOWAIT,
307 &pcs->pci_xfer_dmap[i])) {
308 printf("%s: can't create dma maps\n",
309 isp->isp_name);
310 isp_uninit(isp);
311 ISP_UNLOCK(isp);
312 return;
313 }
314 }
315 /*
316 * Do Generic attach now.
317 */
318 isp_attach(isp);
319 if (isp->isp_state != ISP_RUNSTATE) {
320 isp_uninit(isp);
321 free(isp->isp_param, M_DEVBUF);
322 }
323 ISP_UNLOCK(isp);
324 }
325
326 #define PCI_BIU_REGS_OFF BIU_REGS_OFF
327
328 static u_int16_t
329 isp_pci_rd_reg(isp, regoff)
330 struct ispsoftc *isp;
331 int regoff;
332 {
333 u_int16_t rv;
334 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
335 int offset, oldsxp = 0;
336
337 if ((regoff & BIU_BLOCK) != 0) {
338 offset = PCI_BIU_REGS_OFF;
339 } else if ((regoff & MBOX_BLOCK) != 0) {
340 if (isp->isp_type & ISP_HA_SCSI)
341 offset = PCI_MBOX_REGS_OFF;
342 else
343 offset = PCI_MBOX_REGS2100_OFF;
344 } else if ((regoff & SXP_BLOCK) != 0) {
345 offset = PCI_SXP_REGS_OFF;
346 /*
347 * We will assume that someone has paused the RISC processor.
348 */
349 oldsxp = isp_pci_rd_reg(isp, BIU_CONF1);
350 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP);
351 } else {
352 offset = PCI_RISC_REGS_OFF;
353 }
354 regoff &= 0xff;
355 offset += regoff;
356 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
357 if ((regoff & SXP_BLOCK) != 0) {
358 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp);
359 }
360 return (rv);
361 }
362
363 static void
364 isp_pci_wr_reg(isp, regoff, val)
365 struct ispsoftc *isp;
366 int regoff;
367 u_int16_t val;
368 {
369 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
370 int offset, oldsxp = 0;
371 if ((regoff & BIU_BLOCK) != 0) {
372 offset = PCI_BIU_REGS_OFF;
373 } else if ((regoff & MBOX_BLOCK) != 0) {
374 if (isp->isp_type & ISP_HA_SCSI)
375 offset = PCI_MBOX_REGS_OFF;
376 else
377 offset = PCI_MBOX_REGS2100_OFF;
378 } else if ((regoff & SXP_BLOCK) != 0) {
379 offset = PCI_SXP_REGS_OFF;
380 /*
381 * We will assume that someone has paused the RISC processor.
382 */
383 oldsxp = isp_pci_rd_reg(isp, BIU_CONF1);
384 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP);
385 } else {
386 offset = PCI_RISC_REGS_OFF;
387 }
388 regoff &= 0xff;
389 offset += regoff;
390 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
391 if ((regoff & SXP_BLOCK) != 0) {
392 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp);
393 }
394 }
395
396 static int
397 isp_pci_mbxdma(isp)
398 struct ispsoftc *isp;
399 {
400 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
401 bus_dma_segment_t seg;
402 bus_size_t len;
403 fcparam *fcp;
404 int rseg;
405
406 /*
407 * Allocate and map the request queue.
408 */
409 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN);
410 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
411 BUS_DMA_NOWAIT) ||
412 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
413 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMAMEM_NOSYNC))
414 return (1);
415 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
416 &pci->pci_rquest_dmap) ||
417 bus_dmamap_load(pci->pci_dmat, pci->pci_rquest_dmap,
418 (caddr_t)isp->isp_rquest, len, NULL, BUS_DMA_NOWAIT))
419 return (1);
420
421 isp->isp_rquest_dma = pci->pci_rquest_dmap->dm_segs[0].ds_addr;
422
423 /*
424 * Allocate and map the result queue.
425 */
426 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN);
427 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
428 BUS_DMA_NOWAIT) ||
429 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
430 (caddr_t *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMAMEM_NOSYNC))
431 return (1);
432 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
433 &pci->pci_result_dmap) ||
434 bus_dmamap_load(pci->pci_dmat, pci->pci_result_dmap,
435 (caddr_t)isp->isp_result, len, NULL, BUS_DMA_NOWAIT))
436 return (1);
437 isp->isp_result_dma = pci->pci_result_dmap->dm_segs[0].ds_addr;
438
439 if (isp->isp_type & ISP_HA_SCSI) {
440 return (0);
441 }
442
443 fcp = isp->isp_param;
444 len = ISP2100_SCRLEN;
445 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
446 BUS_DMA_NOWAIT) ||
447 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
448 (caddr_t *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMAMEM_NOSYNC))
449 return (1);
450 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
451 &pci->pci_scratch_dmap) ||
452 bus_dmamap_load(pci->pci_dmat, pci->pci_scratch_dmap,
453 (caddr_t)fcp->isp_scratch, len, NULL, BUS_DMA_NOWAIT))
454 return (1);
455 fcp->isp_scdma = pci->pci_scratch_dmap->dm_segs[0].ds_addr;
456 return (0);
457 }
458
459 static int
460 isp_pci_dmasetup(isp, xs, rq, iptrp, optr)
461 struct ispsoftc *isp;
462 struct scsipi_xfer *xs;
463 ispreq_t *rq;
464 u_int8_t *iptrp;
465 u_int8_t optr;
466 {
467 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
468 bus_dmamap_t dmap = pci->pci_xfer_dmap[rq->req_handle - 1];
469 ispcontreq_t *crq;
470 int segcnt, seg, error, ovseg, seglim, drq;
471
472 if (xs->datalen == 0) {
473 rq->req_seg_count = 1;
474 goto mbxsync;
475 }
476
477 if (rq->req_handle > RQUEST_QUEUE_LEN || rq->req_handle < 1) {
478 panic("%s: bad handle (%d) in isp_pci_dmasetup\n",
479 isp->isp_name, rq->req_handle);
480 /* NOTREACHED */
481 }
482
483 if (xs->flags & SCSI_DATA_IN) {
484 drq = REQFLAG_DATA_IN;
485 } else {
486 drq = REQFLAG_DATA_OUT;
487 }
488
489 if (isp->isp_type & ISP_HA_FC) {
490 seglim = ISP_RQDSEG_T2;
491 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen;
492 ((ispreqt2_t *)rq)->req_flags |= drq;
493 } else {
494 seglim = ISP_RQDSEG;
495 rq->req_flags |= drq;
496 }
497 error = bus_dmamap_load(pci->pci_dmat, dmap, xs->data, xs->datalen,
498 NULL, xs->flags & SCSI_NOSLEEP ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
499 if (error) {
500 XS_SETERR(xs, HBA_BOTCH);
501 return (CMD_COMPLETE);
502 }
503
504 segcnt = dmap->dm_nsegs;
505
506 for (seg = 0, rq->req_seg_count = 0;
507 seg < segcnt && rq->req_seg_count < seglim;
508 seg++, rq->req_seg_count++) {
509 if (isp->isp_type & ISP_HA_FC) {
510 ispreqt2_t *rq2 = (ispreqt2_t *)rq;
511 rq2->req_dataseg[rq2->req_seg_count].ds_count =
512 dmap->dm_segs[seg].ds_len;
513 rq2->req_dataseg[rq2->req_seg_count].ds_base =
514 dmap->dm_segs[seg].ds_addr;
515 } else {
516 rq->req_dataseg[rq->req_seg_count].ds_count =
517 dmap->dm_segs[seg].ds_len;
518 rq->req_dataseg[rq->req_seg_count].ds_base =
519 dmap->dm_segs[seg].ds_addr;
520 }
521 }
522
523 if (seg == segcnt)
524 goto dmasync;
525
526 do {
527 crq = (ispcontreq_t *)
528 ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp);
529 *iptrp = (*iptrp + 1) & (RQUEST_QUEUE_LEN - 1);
530 if (*iptrp == optr) {
531 printf("%s: Request Queue Overflow++\n",
532 isp->isp_name);
533 bus_dmamap_unload(pci->pci_dmat, dmap);
534 XS_SETERR(xs, HBA_BOTCH);
535 return (CMD_COMPLETE);
536 }
537 rq->req_header.rqs_entry_count++;
538 bzero((void *)crq, sizeof (*crq));
539 crq->req_header.rqs_entry_count = 1;
540 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG;
541
542 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG;
543 rq->req_seg_count++, seg++, ovseg++) {
544 crq->req_dataseg[ovseg].ds_count =
545 dmap->dm_segs[seg].ds_len;
546 crq->req_dataseg[ovseg].ds_base =
547 dmap->dm_segs[seg].ds_addr;
548 }
549 } while (seg < segcnt);
550
551 dmasync:
552 bus_dmamap_sync(pci->pci_dmat, dmap,
553 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD :
554 BUS_DMASYNC_PREWRITE);
555
556 mbxsync:
557
558 bus_dmamap_sync(pci->pci_dmat, pci->pci_rquest_dmap,
559 BUS_DMASYNC_PREWRITE);
560 return (CMD_QUEUED);
561 }
562
563 static int
564 isp_pci_intr(arg)
565 void *arg;
566 {
567 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)arg;
568 bus_dmamap_sync(pci->pci_dmat, pci->pci_result_dmap,
569 BUS_DMASYNC_POSTREAD);
570 return (isp_intr(arg));
571 }
572
573 static void
574 isp_pci_dmateardown(isp, xs, handle)
575 struct ispsoftc *isp;
576 struct scsipi_xfer *xs;
577 u_int32_t handle;
578 {
579 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
580 bus_dmamap_t dmap = pci->pci_xfer_dmap[handle];
581
582 bus_dmamap_sync(pci->pci_dmat, dmap,
583 xs->flags & SCSI_DATA_IN ?
584 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
585 bus_dmamap_unload(pci->pci_dmat, dmap);
586 }
587
588 static void
589 isp_pci_reset1(isp)
590 struct ispsoftc *isp;
591 {
592 /* Make sure the BIOS is disabled */
593 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
594 }
595
596 static void
597 isp_pci_dumpregs(isp)
598 struct ispsoftc *isp;
599 {
600 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
601 printf("%s: PCI Status Command/Status=%x\n", pci->pci_isp.isp_name,
602 pci_conf_read(pci->pci_pc, pci->pci_tag, PCI_COMMAND_STATUS_REG));
603 }
604