isp_pci.c revision 1.20 1 /* $NetBSD: isp_pci.c,v 1.20 1998/06/08 06:55:57 thorpej Exp $ */
2
3 /*
4 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
5 *
6 * Copyright (c) 1997 by Matthew Jacob
7 * NASA AMES Research Center
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice immediately at the beginning of the file, without modification,
15 * this list of conditions, and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/queue.h>
40 #include <sys/device.h>
41 #include <machine/bus.h>
42 #include <machine/intr.h>
43 #include <dev/scsipi/scsi_all.h>
44 #include <dev/scsipi/scsipi_all.h>
45 #include <dev/scsipi/scsiconf.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcidevs.h>
49 #include <vm/vm.h>
50
51 #include <dev/ic/ispreg.h>
52 #include <dev/ic/ispvar.h>
53 #include <dev/ic/ispmbox.h>
54 #include <dev/microcode/isp/asm_pci.h>
55
56 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int));
57 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t));
58 static int isp_pci_mbxdma __P((struct ispsoftc *));
59 static int isp_pci_dmasetup __P((struct ispsoftc *, struct scsipi_xfer *,
60 ispreq_t *, u_int8_t *, u_int8_t));
61 static void isp_pci_dmateardown __P((struct ispsoftc *, struct scsipi_xfer *,
62 u_int32_t));
63
64 static void isp_pci_reset1 __P((struct ispsoftc *));
65 static void isp_pci_dumpregs __P((struct ispsoftc *));
66
67 static struct ispmdvec mdvec = {
68 isp_pci_rd_reg,
69 isp_pci_wr_reg,
70 isp_pci_mbxdma,
71 isp_pci_dmasetup,
72 isp_pci_dmateardown,
73 NULL,
74 isp_pci_reset1,
75 isp_pci_dumpregs,
76 ISP_RISC_CODE,
77 ISP_CODE_LENGTH,
78 ISP_CODE_ORG,
79 ISP_CODE_VERSION,
80 BIU_PCI_CONF1_FIFO_64 | BIU_BURST_ENABLE,
81 60 /* MAGIC- all known PCI card implementations are 60MHz */
82 };
83
84 static struct ispmdvec mdvec_2100 = {
85 isp_pci_rd_reg,
86 isp_pci_wr_reg,
87 isp_pci_mbxdma,
88 isp_pci_dmasetup,
89 isp_pci_dmateardown,
90 NULL,
91 isp_pci_reset1,
92 isp_pci_dumpregs,
93 ISP2100_RISC_CODE,
94 ISP2100_CODE_LENGTH,
95 ISP2100_CODE_ORG,
96 ISP2100_CODE_VERSION,
97 BIU_PCI_CONF1_FIFO_64 | BIU_BURST_ENABLE,
98 60 /* MAGIC- all known PCI card implementations are 60MHz */
99 };
100
101 #define PCI_QLOGIC_ISP \
102 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
103
104 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
105 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
106 #endif
107 #define PCI_QLOGIC_ISP2100 \
108 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
109
110 #define IO_MAP_REG 0x10
111 #define MEM_MAP_REG 0x14
112
113
114 static int isp_pci_probe __P((struct device *, struct cfdata *, void *));
115 static void isp_pci_attach __P((struct device *, struct device *, void *));
116
117 struct isp_pcisoftc {
118 struct ispsoftc pci_isp;
119 pci_chipset_tag_t pci_pc;
120 pcitag_t pci_tag;
121 bus_space_tag_t pci_st;
122 bus_space_handle_t pci_sh;
123 bus_dma_tag_t pci_dmat;
124 bus_dmamap_t pci_scratch_dmap; /* for fcp only */
125 bus_dmamap_t pci_rquest_dmap;
126 bus_dmamap_t pci_result_dmap;
127 bus_dmamap_t pci_xfer_dmap[MAXISPREQUEST];
128 void * pci_ih;
129 };
130
131 struct cfattach isp_pci_ca = {
132 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach
133 };
134
135 static int
136 isp_pci_probe(parent, match, aux)
137 struct device *parent;
138 struct cfdata *match;
139 void *aux;
140 {
141 struct pci_attach_args *pa = aux;
142
143 if (pa->pa_id == PCI_QLOGIC_ISP ||
144 pa->pa_id == PCI_QLOGIC_ISP2100) {
145 return (1);
146 } else {
147 return (0);
148 }
149 }
150
151
152 static void
153 isp_pci_attach(parent, self, aux)
154 struct device *parent, *self;
155 void *aux;
156 {
157 struct pci_attach_args *pa = aux;
158 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self;
159 bus_space_tag_t st, iot, memt;
160 bus_space_handle_t sh, ioh, memh;
161 pci_intr_handle_t ih;
162 const char *intrstr;
163 int ioh_valid, memh_valid, i;
164
165 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
166 PCI_MAPREG_TYPE_IO, 0,
167 &iot, &ioh, NULL, NULL) == 0);
168 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG,
169 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
170 &memt, &memh, NULL, NULL) == 0);
171
172 if (memh_valid) {
173 st = memt;
174 sh = memh;
175 } else if (ioh_valid) {
176 st = iot;
177 sh = ioh;
178 } else {
179 printf(": unable to map device registers\n");
180 return;
181 }
182 printf("\n");
183
184 pcs->pci_st = st;
185 pcs->pci_sh = sh;
186 pcs->pci_dmat = pa->pa_dmat;
187 pcs->pci_pc = pa->pa_pc;
188 pcs->pci_tag = pa->pa_tag;
189 if (pa->pa_id == PCI_QLOGIC_ISP) {
190 pcs->pci_isp.isp_mdvec = &mdvec;
191 pcs->pci_isp.isp_type = ISP_HA_SCSI_UNKNOWN;
192 pcs->pci_isp.isp_param =
193 malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT);
194 if (pcs->pci_isp.isp_param == NULL) {
195 printf("%s: couldn't allocate sdparam table\n",
196 pcs->pci_isp.isp_name);
197 }
198 bzero(pcs->pci_isp.isp_param, sizeof (sdparam));
199 } else if (pa->pa_id == PCI_QLOGIC_ISP2100) {
200 u_int32_t data;
201 pcs->pci_isp.isp_mdvec = &mdvec_2100;
202 if (ioh_valid == 0) {
203 printf("%s: warning, ISP2100 cannot use I/O Space"
204 " Mappings\n", pcs->pci_isp.isp_name);
205 } else {
206 pcs->pci_st = iot;
207 pcs->pci_sh = ioh;
208 }
209
210 #if 0
211 printf("%s: PCIREGS cmd=%x bhlc=%x\n", pcs->pci_isp.isp_name,
212 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG),
213 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG));
214 #endif
215 pcs->pci_isp.isp_type = ISP_HA_FC_2100;
216 pcs->pci_isp.isp_param =
217 malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT);
218 if (pcs->pci_isp.isp_param == NULL) {
219 printf("%s: couldn't allocate fcparam table\n",
220 pcs->pci_isp.isp_name);
221 }
222 bzero(pcs->pci_isp.isp_param, sizeof (fcparam));
223
224 data = pci_conf_read(pa->pa_pc, pa->pa_tag,
225 PCI_COMMAND_STATUS_REG);
226 data |= PCI_COMMAND_MASTER_ENABLE |
227 PCI_COMMAND_INVALIDATE_ENABLE;
228 pci_conf_write(pa->pa_pc, pa->pa_tag,
229 PCI_COMMAND_STATUS_REG, data);
230 /*
231 * Wierd- we need to clear the lsb in offset 0x30 to take the
232 * chip out of reset state.
233 */
234 data = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x30);
235 data &= ~1;
236 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x30, data);
237 #if 0
238 /*
239 * XXX: Need to get the actual revision number of the 2100 FB
240 */
241 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
242 data &= ~0xffff;
243 data |= 0xf801;
244 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
245 printf("%s: setting latency to %x and cache line size to %x\n",
246 pcs->pci_isp.isp_name, (data >> 8) & 0xff,
247 data & 0xff);
248 #endif
249 } else {
250 return;
251 }
252 isp_reset(&pcs->pci_isp);
253 if (pcs->pci_isp.isp_state != ISP_RESETSTATE) {
254 free(pcs->pci_isp.isp_param, M_DEVBUF);
255 return;
256 }
257 isp_init(&pcs->pci_isp);
258 if (pcs->pci_isp.isp_state != ISP_INITSTATE) {
259 isp_uninit(&pcs->pci_isp);
260 free(pcs->pci_isp.isp_param, M_DEVBUF);
261 return;
262 }
263
264 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
265 pa->pa_intrline, &ih)) {
266 printf("%s: couldn't map interrupt\n", pcs->pci_isp.isp_name);
267 isp_uninit(&pcs->pci_isp);
268 free(pcs->pci_isp.isp_param, M_DEVBUF);
269 return;
270 }
271
272 intrstr = pci_intr_string(pa->pa_pc, ih);
273 if (intrstr == NULL)
274 intrstr = "<I dunno>";
275 pcs->pci_ih =
276 pci_intr_establish(pa->pa_pc, ih, IPL_BIO, isp_intr, &pcs->pci_isp);
277 if (pcs->pci_ih == NULL) {
278 printf("%s: couldn't establish interrupt at %s\n",
279 pcs->pci_isp.isp_name, intrstr);
280 isp_uninit(&pcs->pci_isp);
281 free(pcs->pci_isp.isp_param, M_DEVBUF);
282 return;
283 }
284 printf("%s: interrupting at %s\n", pcs->pci_isp.isp_name, intrstr);
285
286 /*
287 * Create the DMA maps for the data transfers.
288 */
289 for (i = 0; i < RQUEST_QUEUE_LEN(&pcs->pci_isp); i++) {
290 if (bus_dmamap_create(pcs->pci_dmat, MAXPHYS,
291 (MAXPHYS / NBPG) + 1, MAXPHYS, 0, BUS_DMA_NOWAIT,
292 &pcs->pci_xfer_dmap[i])) {
293 printf("%s: can't create dma maps\n",
294 pcs->pci_isp.isp_name);
295 isp_uninit(&pcs->pci_isp);
296 return;
297 }
298 }
299 /*
300 * Do Generic attach now.
301 */
302 isp_attach(&pcs->pci_isp);
303 if (pcs->pci_isp.isp_state != ISP_RUNSTATE) {
304 isp_uninit(&pcs->pci_isp);
305 free(pcs->pci_isp.isp_param, M_DEVBUF);
306 }
307 }
308
309 #define PCI_BIU_REGS_OFF BIU_REGS_OFF
310
311 static u_int16_t
312 isp_pci_rd_reg(isp, regoff)
313 struct ispsoftc *isp;
314 int regoff;
315 {
316 u_int16_t rv;
317 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
318 int offset, oldsxp = 0;
319
320 if ((regoff & BIU_BLOCK) != 0) {
321 offset = PCI_BIU_REGS_OFF;
322 } else if ((regoff & MBOX_BLOCK) != 0) {
323 if (isp->isp_type & ISP_HA_SCSI)
324 offset = PCI_MBOX_REGS_OFF;
325 else
326 offset = PCI_MBOX_REGS2100_OFF;
327 } else if ((regoff & SXP_BLOCK) != 0) {
328 offset = PCI_SXP_REGS_OFF;
329 /*
330 * We will assume that someone has paused the RISC processor.
331 */
332 oldsxp = isp_pci_rd_reg(isp, BIU_CONF1);
333 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP);
334 } else {
335 offset = PCI_RISC_REGS_OFF;
336 }
337 regoff &= 0xff;
338 offset += regoff;
339 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
340 if ((regoff & SXP_BLOCK) != 0) {
341 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp);
342 }
343 return (rv);
344 }
345
346 static void
347 isp_pci_wr_reg(isp, regoff, val)
348 struct ispsoftc *isp;
349 int regoff;
350 u_int16_t val;
351 {
352 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
353 int offset, oldsxp = 0;
354 if ((regoff & BIU_BLOCK) != 0) {
355 offset = PCI_BIU_REGS_OFF;
356 } else if ((regoff & MBOX_BLOCK) != 0) {
357 if (isp->isp_type & ISP_HA_SCSI)
358 offset = PCI_MBOX_REGS_OFF;
359 else
360 offset = PCI_MBOX_REGS2100_OFF;
361 } else if ((regoff & SXP_BLOCK) != 0) {
362 offset = PCI_SXP_REGS_OFF;
363 /*
364 * We will assume that someone has paused the RISC processor.
365 */
366 oldsxp = isp_pci_rd_reg(isp, BIU_CONF1);
367 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP);
368 } else {
369 offset = PCI_RISC_REGS_OFF;
370 }
371 regoff &= 0xff;
372 offset += regoff;
373 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
374 if ((regoff & SXP_BLOCK) != 0) {
375 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp);
376 }
377 }
378
379 static int
380 isp_pci_mbxdma(isp)
381 struct ispsoftc *isp;
382 {
383 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
384 bus_dma_segment_t seg;
385 bus_size_t len;
386 fcparam *fcp;
387 int rseg;
388
389 /*
390 * Allocate and map the request queue.
391 */
392 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
393 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
394 BUS_DMA_NOWAIT) ||
395 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
396 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT))
397 return (1);
398 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
399 &pci->pci_rquest_dmap) ||
400 bus_dmamap_load(pci->pci_dmat, pci->pci_rquest_dmap,
401 (caddr_t)isp->isp_rquest, len, NULL, BUS_DMA_NOWAIT))
402 return (1);
403
404 isp->isp_rquest_dma = pci->pci_rquest_dmap->dm_segs[0].ds_addr;
405
406 /*
407 * Allocate and map the result queue.
408 */
409 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
410 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
411 BUS_DMA_NOWAIT) ||
412 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
413 (caddr_t *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT))
414 return (1);
415 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
416 &pci->pci_result_dmap) ||
417 bus_dmamap_load(pci->pci_dmat, pci->pci_result_dmap,
418 (caddr_t)isp->isp_result, len, NULL, BUS_DMA_NOWAIT))
419 return (1);
420 isp->isp_result_dma = pci->pci_result_dmap->dm_segs[0].ds_addr;
421
422 if (isp->isp_type & ISP_HA_SCSI) {
423 return (0);
424 }
425
426 fcp = isp->isp_param;
427 len = ISP2100_SCRLEN;
428 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
429 BUS_DMA_NOWAIT) ||
430 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
431 (caddr_t *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT))
432 return (1);
433 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
434 &pci->pci_scratch_dmap) ||
435 bus_dmamap_load(pci->pci_dmat, pci->pci_scratch_dmap,
436 (caddr_t)fcp->isp_scratch, len, NULL, BUS_DMA_NOWAIT))
437 return (1);
438 fcp->isp_scdma = pci->pci_scratch_dmap->dm_segs[0].ds_addr;
439 return (0);
440 }
441
442 static int
443 isp_pci_dmasetup(isp, xs, rq, iptrp, optr)
444 struct ispsoftc *isp;
445 struct scsipi_xfer *xs;
446 ispreq_t *rq;
447 u_int8_t *iptrp;
448 u_int8_t optr;
449 {
450 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
451 bus_dmamap_t dmap = pci->pci_xfer_dmap[rq->req_handle - 1];
452 ispcontreq_t *crq;
453 int segcnt, seg, error, ovseg, seglim, drq;
454
455 if (xs->datalen == 0) {
456 rq->req_seg_count = 1;
457 return (0);
458 }
459
460 if (rq->req_handle > RQUEST_QUEUE_LEN(isp) || rq->req_handle < 1) {
461 panic("%s: bad handle (%d) in isp_pci_dmasetup\n",
462 isp->isp_name, rq->req_handle);
463 /* NOTREACHED */
464 }
465
466 if (xs->flags & SCSI_DATA_IN) {
467 drq = REQFLAG_DATA_IN;
468 } else {
469 drq = REQFLAG_DATA_OUT;
470 }
471
472 if (isp->isp_type & ISP_HA_FC) {
473 seglim = ISP_RQDSEG_T2;
474 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen;
475 ((ispreqt2_t *)rq)->req_flags |= drq;
476 } else {
477 seglim = ISP_RQDSEG;
478 rq->req_flags |= drq;
479 }
480 error = bus_dmamap_load(pci->pci_dmat, dmap, xs->data, xs->datalen,
481 NULL, xs->flags & SCSI_NOSLEEP ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
482 if (error)
483 return (error);
484
485 segcnt = dmap->dm_nsegs;
486
487 for (seg = 0, rq->req_seg_count = 0;
488 seg < segcnt && rq->req_seg_count < seglim;
489 seg++, rq->req_seg_count++) {
490 if (isp->isp_type & ISP_HA_FC) {
491 ispreqt2_t *rq2 = (ispreqt2_t *)rq;
492 rq2->req_dataseg[rq2->req_seg_count].ds_count =
493 dmap->dm_segs[seg].ds_len;
494 rq2->req_dataseg[rq2->req_seg_count].ds_base =
495 dmap->dm_segs[seg].ds_addr;
496 } else {
497 rq->req_dataseg[rq->req_seg_count].ds_count =
498 dmap->dm_segs[seg].ds_len;
499 rq->req_dataseg[rq->req_seg_count].ds_base =
500 dmap->dm_segs[seg].ds_addr;
501 }
502 }
503
504 if (seg == segcnt)
505 goto mapsync;
506
507 do {
508 crq = (ispcontreq_t *)
509 ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp);
510 *iptrp = (*iptrp + 1) & (RQUEST_QUEUE_LEN(isp) - 1);
511 if (*iptrp == optr) {
512 printf("%s: Request Queue Overflow++\n",
513 isp->isp_name);
514 bus_dmamap_unload(pci->pci_dmat, dmap);
515 return (EFBIG);
516 }
517 rq->req_header.rqs_entry_count++;
518 bzero((void *)crq, sizeof (*crq));
519 crq->req_header.rqs_entry_count = 1;
520 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG;
521
522 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG;
523 rq->req_seg_count++, seg++, ovseg++) {
524 crq->req_dataseg[ovseg].ds_count =
525 dmap->dm_segs[seg].ds_len;
526 crq->req_dataseg[ovseg].ds_base =
527 dmap->dm_segs[seg].ds_addr;
528 }
529 } while (seg < segcnt);
530
531 mapsync:
532 bus_dmamap_sync(pci->pci_dmat, dmap, 0, dmap->dm_mapsize,
533 xs->flags & SCSI_DATA_IN ?
534 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
535 return (0);
536 }
537
538 static void
539 isp_pci_dmateardown(isp, xs, handle)
540 struct ispsoftc *isp;
541 struct scsipi_xfer *xs;
542 u_int32_t handle;
543 {
544 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
545 bus_dmamap_t dmap = pci->pci_xfer_dmap[handle];
546
547 bus_dmamap_sync(pci->pci_dmat, dmap, 0, dmap->dm_mapsize,
548 xs->flags & SCSI_DATA_IN ?
549 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
550 bus_dmamap_unload(pci->pci_dmat, dmap);
551 }
552
553 static void
554 isp_pci_reset1(isp)
555 struct ispsoftc *isp;
556 {
557 /* Make sure the BIOS is disabled */
558 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
559 }
560
561 static void
562 isp_pci_dumpregs(isp)
563 struct ispsoftc *isp;
564 {
565 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
566 printf("%s: PCI Status Command/Status=%x\n", pci->pci_isp.isp_name,
567 pci_conf_read(pci->pci_pc, pci->pci_tag, PCI_COMMAND_STATUS_REG));
568 }
569