isp_pci.c revision 1.22
1 /* $NetBSD: isp_pci.c,v 1.22 1998/07/18 21:02:42 mjacob Exp $ */ 2 /* 3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 4 * 5 *--------------------------------------- 6 * Copyright (c) 1997, 1998 by Matthew Jacob 7 * NASA/Ames Research Center 8 * All rights reserved. 9 *--------------------------------------- 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 #include <dev/ic/isp_netbsd.h> 38 #include <dev/microcode/isp/asm_pci.h> 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcidevs.h> 43 44 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int)); 45 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t)); 46 static int isp_pci_mbxdma __P((struct ispsoftc *)); 47 static int isp_pci_dmasetup __P((struct ispsoftc *, struct scsipi_xfer *, 48 ispreq_t *, u_int8_t *, u_int8_t)); 49 static void isp_pci_dmateardown __P((struct ispsoftc *, struct scsipi_xfer *, 50 u_int32_t)); 51 52 static void isp_pci_reset1 __P((struct ispsoftc *)); 53 static void isp_pci_dumpregs __P((struct ispsoftc *)); 54 55 static struct ispmdvec mdvec = { 56 isp_pci_rd_reg, 57 isp_pci_wr_reg, 58 isp_pci_mbxdma, 59 isp_pci_dmasetup, 60 isp_pci_dmateardown, 61 NULL, 62 isp_pci_reset1, 63 isp_pci_dumpregs, 64 ISP_RISC_CODE, 65 ISP_CODE_LENGTH, 66 ISP_CODE_ORG, 67 ISP_CODE_VERSION, 68 BIU_PCI_CONF1_FIFO_64 | BIU_BURST_ENABLE, 69 60 /* MAGIC- all known PCI card implementations are 60MHz */ 70 }; 71 72 static struct ispmdvec mdvec_2100 = { 73 isp_pci_rd_reg, 74 isp_pci_wr_reg, 75 isp_pci_mbxdma, 76 isp_pci_dmasetup, 77 isp_pci_dmateardown, 78 NULL, 79 isp_pci_reset1, 80 isp_pci_dumpregs, 81 ISP2100_RISC_CODE, 82 ISP2100_CODE_LENGTH, 83 ISP2100_CODE_ORG, 84 ISP2100_CODE_VERSION, 85 BIU_PCI_CONF1_FIFO_64 | BIU_BURST_ENABLE, 86 60 /* MAGIC- all known PCI card implementations are 60MHz */ 87 }; 88 89 #define PCI_QLOGIC_ISP \ 90 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 91 92 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 93 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 94 #endif 95 #define PCI_QLOGIC_ISP2100 \ 96 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 97 98 #define IO_MAP_REG 0x10 99 #define MEM_MAP_REG 0x14 100 101 102 static int isp_pci_probe __P((struct device *, struct cfdata *, void *)); 103 static void isp_pci_attach __P((struct device *, struct device *, void *)); 104 105 struct isp_pcisoftc { 106 struct ispsoftc pci_isp; 107 pci_chipset_tag_t pci_pc; 108 pcitag_t pci_tag; 109 bus_space_tag_t pci_st; 110 bus_space_handle_t pci_sh; 111 bus_dma_tag_t pci_dmat; 112 bus_dmamap_t pci_scratch_dmap; /* for fcp only */ 113 bus_dmamap_t pci_rquest_dmap; 114 bus_dmamap_t pci_result_dmap; 115 bus_dmamap_t pci_xfer_dmap[MAXISPREQUEST]; 116 void * pci_ih; 117 }; 118 119 struct cfattach isp_pci_ca = { 120 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach 121 }; 122 123 static int 124 isp_pci_probe(parent, match, aux) 125 struct device *parent; 126 struct cfdata *match; 127 void *aux; 128 { 129 struct pci_attach_args *pa = aux; 130 131 if (pa->pa_id == PCI_QLOGIC_ISP || 132 pa->pa_id == PCI_QLOGIC_ISP2100) { 133 return (1); 134 } else { 135 return (0); 136 } 137 } 138 139 140 static void 141 isp_pci_attach(parent, self, aux) 142 struct device *parent, *self; 143 void *aux; 144 { 145 static char oneshot = 0; 146 struct pci_attach_args *pa = aux; 147 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 148 struct ispsoftc *isp = &pcs->pci_isp; 149 bus_space_tag_t st, iot, memt; 150 bus_space_handle_t sh, ioh, memh; 151 pci_intr_handle_t ih; 152 const char *intrstr; 153 int ioh_valid, memh_valid, i; 154 ISP_LOCKVAL_DECL; 155 156 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 157 PCI_MAPREG_TYPE_IO, 0, 158 &iot, &ioh, NULL, NULL) == 0); 159 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 160 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 161 &memt, &memh, NULL, NULL) == 0); 162 163 if (memh_valid) { 164 st = memt; 165 sh = memh; 166 } else if (ioh_valid) { 167 st = iot; 168 sh = ioh; 169 } else { 170 printf(": unable to map device registers\n"); 171 return; 172 } 173 printf("\n"); 174 175 pcs->pci_st = st; 176 pcs->pci_sh = sh; 177 pcs->pci_dmat = pa->pa_dmat; 178 pcs->pci_pc = pa->pa_pc; 179 pcs->pci_tag = pa->pa_tag; 180 if (pa->pa_id == PCI_QLOGIC_ISP) { 181 isp->isp_mdvec = &mdvec; 182 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 183 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 184 if (isp->isp_param == NULL) { 185 printf("%s: couldn't allocate sdparam table\n", 186 isp->isp_name); 187 return; 188 } 189 bzero(isp->isp_param, sizeof (sdparam)); 190 } else if (pa->pa_id == PCI_QLOGIC_ISP2100) { 191 u_int32_t data; 192 isp->isp_mdvec = &mdvec_2100; 193 if (ioh_valid == 0) { 194 printf("%s: warning, ISP2100 cannot use I/O Space" 195 " Mappings\n", isp->isp_name); 196 } else { 197 pcs->pci_st = iot; 198 pcs->pci_sh = ioh; 199 } 200 201 #if 0 202 printf("%s: PCIREGS cmd=%x bhlc=%x\n", isp->isp_name, 203 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG), 204 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG)); 205 #endif 206 isp->isp_type = ISP_HA_FC_2100; 207 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 208 if (isp->isp_param == NULL) { 209 printf("%s: couldn't allocate fcparam table\n", 210 isp->isp_name); 211 return; 212 } 213 bzero(isp->isp_param, sizeof (fcparam)); 214 215 data = pci_conf_read(pa->pa_pc, pa->pa_tag, 216 PCI_COMMAND_STATUS_REG); 217 data |= PCI_COMMAND_MASTER_ENABLE | 218 PCI_COMMAND_INVALIDATE_ENABLE; 219 pci_conf_write(pa->pa_pc, pa->pa_tag, 220 PCI_COMMAND_STATUS_REG, data); 221 /* 222 * Wierd- we need to clear the lsb in offset 0x30 to take the 223 * chip out of reset state. 224 */ 225 data = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x30); 226 data &= ~1; 227 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x30, data); 228 #if 0 229 /* 230 * XXX: Need to get the actual revision number of the 2100 FB 231 */ 232 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 233 data &= ~0xffff; 234 data |= 0xf801; 235 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 236 printf("%s: setting latency to %x and cache line size to %x\n", 237 isp->isp_name, (data >> 8) & 0xff, 238 data & 0xff); 239 #endif 240 } else { 241 return; 242 } 243 244 if (oneshot) { 245 oneshot = 0; 246 printf("***Qlogic ISP Driver, NetBSD (pci) Platform Version " 247 "%d.%d Core Version %d.%d\n", 248 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 249 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 250 } 251 252 ISP_LOCK(isp); 253 isp_reset(isp); 254 if (isp->isp_state != ISP_RESETSTATE) { 255 ISP_UNLOCK(isp); 256 free(isp->isp_param, M_DEVBUF); 257 return; 258 } 259 isp_init(isp); 260 if (isp->isp_state != ISP_INITSTATE) { 261 isp_uninit(isp); 262 ISP_UNLOCK(isp); 263 free(isp->isp_param, M_DEVBUF); 264 return; 265 } 266 267 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 268 pa->pa_intrline, &ih)) { 269 printf("%s: couldn't map interrupt\n", isp->isp_name); 270 isp_uninit(isp); 271 ISP_UNLOCK(isp); 272 free(isp->isp_param, M_DEVBUF); 273 return; 274 } 275 276 intrstr = pci_intr_string(pa->pa_pc, ih); 277 if (intrstr == NULL) 278 intrstr = "<I dunno>"; 279 pcs->pci_ih = 280 pci_intr_establish(pa->pa_pc, ih, IPL_BIO, isp_intr, isp); 281 if (pcs->pci_ih == NULL) { 282 printf("%s: couldn't establish interrupt at %s\n", 283 isp->isp_name, intrstr); 284 isp_uninit(isp); 285 ISP_UNLOCK(isp); 286 free(isp->isp_param, M_DEVBUF); 287 return; 288 } 289 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 290 291 /* 292 * Create the DMA maps for the data transfers. 293 */ 294 for (i = 0; i < RQUEST_QUEUE_LEN; i++) { 295 if (bus_dmamap_create(pcs->pci_dmat, MAXPHYS, 296 (MAXPHYS / NBPG) + 1, MAXPHYS, 0, BUS_DMA_NOWAIT, 297 &pcs->pci_xfer_dmap[i])) { 298 printf("%s: can't create dma maps\n", 299 isp->isp_name); 300 isp_uninit(isp); 301 ISP_UNLOCK(isp); 302 return; 303 } 304 } 305 /* 306 * Do Generic attach now. 307 */ 308 isp_attach(isp); 309 if (isp->isp_state != ISP_RUNSTATE) { 310 isp_uninit(isp); 311 free(isp->isp_param, M_DEVBUF); 312 } 313 ISP_UNLOCK(isp); 314 } 315 316 #define PCI_BIU_REGS_OFF BIU_REGS_OFF 317 318 static u_int16_t 319 isp_pci_rd_reg(isp, regoff) 320 struct ispsoftc *isp; 321 int regoff; 322 { 323 u_int16_t rv; 324 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 325 int offset, oldsxp = 0; 326 327 if ((regoff & BIU_BLOCK) != 0) { 328 offset = PCI_BIU_REGS_OFF; 329 } else if ((regoff & MBOX_BLOCK) != 0) { 330 if (isp->isp_type & ISP_HA_SCSI) 331 offset = PCI_MBOX_REGS_OFF; 332 else 333 offset = PCI_MBOX_REGS2100_OFF; 334 } else if ((regoff & SXP_BLOCK) != 0) { 335 offset = PCI_SXP_REGS_OFF; 336 /* 337 * We will assume that someone has paused the RISC processor. 338 */ 339 oldsxp = isp_pci_rd_reg(isp, BIU_CONF1); 340 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP); 341 } else { 342 offset = PCI_RISC_REGS_OFF; 343 } 344 regoff &= 0xff; 345 offset += regoff; 346 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 347 if ((regoff & SXP_BLOCK) != 0) { 348 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp); 349 } 350 return (rv); 351 } 352 353 static void 354 isp_pci_wr_reg(isp, regoff, val) 355 struct ispsoftc *isp; 356 int regoff; 357 u_int16_t val; 358 { 359 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 360 int offset, oldsxp = 0; 361 if ((regoff & BIU_BLOCK) != 0) { 362 offset = PCI_BIU_REGS_OFF; 363 } else if ((regoff & MBOX_BLOCK) != 0) { 364 if (isp->isp_type & ISP_HA_SCSI) 365 offset = PCI_MBOX_REGS_OFF; 366 else 367 offset = PCI_MBOX_REGS2100_OFF; 368 } else if ((regoff & SXP_BLOCK) != 0) { 369 offset = PCI_SXP_REGS_OFF; 370 /* 371 * We will assume that someone has paused the RISC processor. 372 */ 373 oldsxp = isp_pci_rd_reg(isp, BIU_CONF1); 374 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP); 375 } else { 376 offset = PCI_RISC_REGS_OFF; 377 } 378 regoff &= 0xff; 379 offset += regoff; 380 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 381 if ((regoff & SXP_BLOCK) != 0) { 382 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp); 383 } 384 } 385 386 static int 387 isp_pci_mbxdma(isp) 388 struct ispsoftc *isp; 389 { 390 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 391 bus_dma_segment_t seg; 392 bus_size_t len; 393 fcparam *fcp; 394 int rseg; 395 396 /* 397 * Allocate and map the request queue. 398 */ 399 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN); 400 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg, 401 BUS_DMA_NOWAIT) || 402 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len, 403 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) 404 return (1); 405 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 406 &pci->pci_rquest_dmap) || 407 bus_dmamap_load(pci->pci_dmat, pci->pci_rquest_dmap, 408 (caddr_t)isp->isp_rquest, len, NULL, BUS_DMA_NOWAIT)) 409 return (1); 410 411 isp->isp_rquest_dma = pci->pci_rquest_dmap->dm_segs[0].ds_addr; 412 413 /* 414 * Allocate and map the result queue. 415 */ 416 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN); 417 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg, 418 BUS_DMA_NOWAIT) || 419 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len, 420 (caddr_t *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) 421 return (1); 422 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 423 &pci->pci_result_dmap) || 424 bus_dmamap_load(pci->pci_dmat, pci->pci_result_dmap, 425 (caddr_t)isp->isp_result, len, NULL, BUS_DMA_NOWAIT)) 426 return (1); 427 isp->isp_result_dma = pci->pci_result_dmap->dm_segs[0].ds_addr; 428 429 if (isp->isp_type & ISP_HA_SCSI) { 430 return (0); 431 } 432 433 fcp = isp->isp_param; 434 len = ISP2100_SCRLEN; 435 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg, 436 BUS_DMA_NOWAIT) || 437 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len, 438 (caddr_t *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) 439 return (1); 440 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 441 &pci->pci_scratch_dmap) || 442 bus_dmamap_load(pci->pci_dmat, pci->pci_scratch_dmap, 443 (caddr_t)fcp->isp_scratch, len, NULL, BUS_DMA_NOWAIT)) 444 return (1); 445 fcp->isp_scdma = pci->pci_scratch_dmap->dm_segs[0].ds_addr; 446 return (0); 447 } 448 449 static int 450 isp_pci_dmasetup(isp, xs, rq, iptrp, optr) 451 struct ispsoftc *isp; 452 struct scsipi_xfer *xs; 453 ispreq_t *rq; 454 u_int8_t *iptrp; 455 u_int8_t optr; 456 { 457 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 458 bus_dmamap_t dmap = pci->pci_xfer_dmap[rq->req_handle - 1]; 459 ispcontreq_t *crq; 460 int segcnt, seg, error, ovseg, seglim, drq; 461 462 if (xs->datalen == 0) { 463 rq->req_seg_count = 1; 464 return (0); 465 } 466 467 if (rq->req_handle > RQUEST_QUEUE_LEN || rq->req_handle < 1) { 468 panic("%s: bad handle (%d) in isp_pci_dmasetup\n", 469 isp->isp_name, rq->req_handle); 470 /* NOTREACHED */ 471 } 472 473 if (xs->flags & SCSI_DATA_IN) { 474 drq = REQFLAG_DATA_IN; 475 } else { 476 drq = REQFLAG_DATA_OUT; 477 } 478 479 if (isp->isp_type & ISP_HA_FC) { 480 seglim = ISP_RQDSEG_T2; 481 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 482 ((ispreqt2_t *)rq)->req_flags |= drq; 483 } else { 484 seglim = ISP_RQDSEG; 485 rq->req_flags |= drq; 486 } 487 error = bus_dmamap_load(pci->pci_dmat, dmap, xs->data, xs->datalen, 488 NULL, xs->flags & SCSI_NOSLEEP ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 489 if (error) { 490 XS_SETERR(xs, HBA_BOTCH); 491 return (error); 492 } 493 494 segcnt = dmap->dm_nsegs; 495 496 for (seg = 0, rq->req_seg_count = 0; 497 seg < segcnt && rq->req_seg_count < seglim; 498 seg++, rq->req_seg_count++) { 499 if (isp->isp_type & ISP_HA_FC) { 500 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 501 rq2->req_dataseg[rq2->req_seg_count].ds_count = 502 dmap->dm_segs[seg].ds_len; 503 rq2->req_dataseg[rq2->req_seg_count].ds_base = 504 dmap->dm_segs[seg].ds_addr; 505 } else { 506 rq->req_dataseg[rq->req_seg_count].ds_count = 507 dmap->dm_segs[seg].ds_len; 508 rq->req_dataseg[rq->req_seg_count].ds_base = 509 dmap->dm_segs[seg].ds_addr; 510 } 511 } 512 513 if (seg == segcnt) 514 goto mapsync; 515 516 do { 517 crq = (ispcontreq_t *) 518 ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp); 519 *iptrp = (*iptrp + 1) & (RQUEST_QUEUE_LEN - 1); 520 if (*iptrp == optr) { 521 printf("%s: Request Queue Overflow++\n", 522 isp->isp_name); 523 bus_dmamap_unload(pci->pci_dmat, dmap); 524 XS_SETERR(xs, HBA_BOTCH); 525 return (EFBIG); 526 } 527 rq->req_header.rqs_entry_count++; 528 bzero((void *)crq, sizeof (*crq)); 529 crq->req_header.rqs_entry_count = 1; 530 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 531 532 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 533 rq->req_seg_count++, seg++, ovseg++) { 534 crq->req_dataseg[ovseg].ds_count = 535 dmap->dm_segs[seg].ds_len; 536 crq->req_dataseg[ovseg].ds_base = 537 dmap->dm_segs[seg].ds_addr; 538 } 539 } while (seg < segcnt); 540 541 mapsync: 542 bus_dmamap_sync(pci->pci_dmat, dmap, 0, dmap->dm_mapsize, 543 xs->flags & SCSI_DATA_IN ? 544 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 545 return (0); 546 } 547 548 static void 549 isp_pci_dmateardown(isp, xs, handle) 550 struct ispsoftc *isp; 551 struct scsipi_xfer *xs; 552 u_int32_t handle; 553 { 554 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 555 bus_dmamap_t dmap = pci->pci_xfer_dmap[handle]; 556 557 bus_dmamap_sync(pci->pci_dmat, dmap, 0, dmap->dm_mapsize, 558 xs->flags & SCSI_DATA_IN ? 559 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 560 bus_dmamap_unload(pci->pci_dmat, dmap); 561 } 562 563 static void 564 isp_pci_reset1(isp) 565 struct ispsoftc *isp; 566 { 567 /* Make sure the BIOS is disabled */ 568 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 569 } 570 571 static void 572 isp_pci_dumpregs(isp) 573 struct ispsoftc *isp; 574 { 575 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 576 printf("%s: PCI Status Command/Status=%x\n", pci->pci_isp.isp_name, 577 pci_conf_read(pci->pci_pc, pci->pci_tag, PCI_COMMAND_STATUS_REG)); 578 } 579
Indexes created Sat Sep 27 14:09:57 GMT 2025