isp_pci.c revision 1.25 1 /* $NetBSD: isp_pci.c,v 1.25 1998/07/20 21:17:30 thorpej Exp $ */
2 /*
3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
4 *
5 *---------------------------------------
6 * Copyright (c) 1997, 1998 by Matthew Jacob
7 * NASA/Ames Research Center
8 * All rights reserved.
9 *---------------------------------------
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice immediately at the beginning of the file, without modification,
16 * this list of conditions, and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 */
36
37 #include <dev/ic/isp_netbsd.h>
38 #include <dev/microcode/isp/asm_pci.h>
39
40 #include <dev/pci/pcireg.h>
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcidevs.h>
43
44 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int));
45 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t));
46 static int isp_pci_mbxdma __P((struct ispsoftc *));
47 static int isp_pci_dmasetup __P((struct ispsoftc *, struct scsipi_xfer *,
48 ispreq_t *, u_int8_t *, u_int8_t));
49 static void isp_pci_dmateardown __P((struct ispsoftc *, struct scsipi_xfer *,
50 u_int32_t));
51
52 static void isp_pci_reset1 __P((struct ispsoftc *));
53 static void isp_pci_dumpregs __P((struct ispsoftc *));
54
55 static struct ispmdvec mdvec = {
56 isp_pci_rd_reg,
57 isp_pci_wr_reg,
58 isp_pci_mbxdma,
59 isp_pci_dmasetup,
60 isp_pci_dmateardown,
61 NULL,
62 isp_pci_reset1,
63 isp_pci_dumpregs,
64 ISP_RISC_CODE,
65 ISP_CODE_LENGTH,
66 ISP_CODE_ORG,
67 ISP_CODE_VERSION,
68 BIU_PCI_CONF1_FIFO_64 | BIU_BURST_ENABLE,
69 60 /* MAGIC- all known PCI card implementations are 60MHz */
70 };
71
72 static struct ispmdvec mdvec_2100 = {
73 isp_pci_rd_reg,
74 isp_pci_wr_reg,
75 isp_pci_mbxdma,
76 isp_pci_dmasetup,
77 isp_pci_dmateardown,
78 NULL,
79 isp_pci_reset1,
80 isp_pci_dumpregs,
81 ISP2100_RISC_CODE,
82 ISP2100_CODE_LENGTH,
83 ISP2100_CODE_ORG,
84 ISP2100_CODE_VERSION,
85 BIU_PCI_CONF1_FIFO_64 | BIU_BURST_ENABLE,
86 60 /* MAGIC- all known PCI card implementations are 60MHz */
87 };
88
89 #define PCI_QLOGIC_ISP \
90 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
91
92 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
93 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
94 #endif
95 #define PCI_QLOGIC_ISP2100 \
96 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
97
98 #define IO_MAP_REG 0x10
99 #define MEM_MAP_REG 0x14
100
101
102 static int isp_pci_probe __P((struct device *, struct cfdata *, void *));
103 static void isp_pci_attach __P((struct device *, struct device *, void *));
104
105 struct isp_pcisoftc {
106 struct ispsoftc pci_isp;
107 pci_chipset_tag_t pci_pc;
108 pcitag_t pci_tag;
109 bus_space_tag_t pci_st;
110 bus_space_handle_t pci_sh;
111 bus_dma_tag_t pci_dmat;
112 bus_dmamap_t pci_scratch_dmap; /* for fcp only */
113 bus_dmamap_t pci_rquest_dmap;
114 bus_dmamap_t pci_result_dmap;
115 bus_dmamap_t pci_xfer_dmap[MAXISPREQUEST];
116 void * pci_ih;
117 };
118
119 struct cfattach isp_pci_ca = {
120 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach
121 };
122
123 static int
124 isp_pci_probe(parent, match, aux)
125 struct device *parent;
126 struct cfdata *match;
127 void *aux;
128 {
129 struct pci_attach_args *pa = aux;
130
131 if (pa->pa_id == PCI_QLOGIC_ISP ||
132 pa->pa_id == PCI_QLOGIC_ISP2100) {
133 return (1);
134 } else {
135 return (0);
136 }
137 }
138
139
140 static void
141 isp_pci_attach(parent, self, aux)
142 struct device *parent, *self;
143 void *aux;
144 {
145 #ifdef DEBUG
146 static char oneshot = 1;
147 #endif
148 struct pci_attach_args *pa = aux;
149 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self;
150 struct ispsoftc *isp = &pcs->pci_isp;
151 bus_space_tag_t st, iot, memt;
152 bus_space_handle_t sh, ioh, memh;
153 pci_intr_handle_t ih;
154 const char *intrstr;
155 int ioh_valid, memh_valid, i;
156 ISP_LOCKVAL_DECL;
157
158 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
159 PCI_MAPREG_TYPE_IO, 0,
160 &iot, &ioh, NULL, NULL) == 0);
161 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG,
162 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
163 &memt, &memh, NULL, NULL) == 0);
164
165 if (memh_valid) {
166 st = memt;
167 sh = memh;
168 } else if (ioh_valid) {
169 st = iot;
170 sh = ioh;
171 } else {
172 printf(": unable to map device registers\n");
173 return;
174 }
175 printf("\n");
176
177 pcs->pci_st = st;
178 pcs->pci_sh = sh;
179 pcs->pci_dmat = pa->pa_dmat;
180 pcs->pci_pc = pa->pa_pc;
181 pcs->pci_tag = pa->pa_tag;
182 if (pa->pa_id == PCI_QLOGIC_ISP) {
183 isp->isp_mdvec = &mdvec;
184 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
185 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT);
186 if (isp->isp_param == NULL) {
187 printf("%s: couldn't allocate sdparam table\n",
188 isp->isp_name);
189 return;
190 }
191 bzero(isp->isp_param, sizeof (sdparam));
192 } else if (pa->pa_id == PCI_QLOGIC_ISP2100) {
193 u_int32_t data;
194 isp->isp_mdvec = &mdvec_2100;
195 if (ioh_valid == 0) {
196 printf("%s: warning, ISP2100 cannot use I/O Space"
197 " Mappings\n", isp->isp_name);
198 } else {
199 pcs->pci_st = iot;
200 pcs->pci_sh = ioh;
201 }
202
203 #if 0
204 printf("%s: PCIREGS cmd=%x bhlc=%x\n", isp->isp_name,
205 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG),
206 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG));
207 #endif
208 isp->isp_type = ISP_HA_FC_2100;
209 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT);
210 if (isp->isp_param == NULL) {
211 printf("%s: couldn't allocate fcparam table\n",
212 isp->isp_name);
213 return;
214 }
215 bzero(isp->isp_param, sizeof (fcparam));
216
217 data = pci_conf_read(pa->pa_pc, pa->pa_tag,
218 PCI_COMMAND_STATUS_REG);
219 data |= PCI_COMMAND_MASTER_ENABLE |
220 PCI_COMMAND_INVALIDATE_ENABLE;
221 pci_conf_write(pa->pa_pc, pa->pa_tag,
222 PCI_COMMAND_STATUS_REG, data);
223 /*
224 * Wierd- we need to clear the lsb in offset 0x30 to take the
225 * chip out of reset state.
226 */
227 data = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x30);
228 data &= ~1;
229 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x30, data);
230 #if 0
231 /*
232 * XXX: Need to get the actual revision number of the 2100 FB
233 */
234 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
235 data &= ~0xffff;
236 data |= 0xf801;
237 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
238 printf("%s: setting latency to %x and cache line size to %x\n",
239 isp->isp_name, (data >> 8) & 0xff,
240 data & 0xff);
241 #endif
242 } else {
243 return;
244 }
245
246 #ifdef DEBUG
247 if (oneshot) {
248 oneshot = 0;
249 printf("***Qlogic ISP Driver, NetBSD (pci) Platform Version "
250 "%d.%d Core Version %d.%d\n",
251 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
252 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
253 }
254 #endif
255
256 ISP_LOCK(isp);
257 isp_reset(isp);
258 if (isp->isp_state != ISP_RESETSTATE) {
259 ISP_UNLOCK(isp);
260 free(isp->isp_param, M_DEVBUF);
261 return;
262 }
263 isp_init(isp);
264 if (isp->isp_state != ISP_INITSTATE) {
265 isp_uninit(isp);
266 ISP_UNLOCK(isp);
267 free(isp->isp_param, M_DEVBUF);
268 return;
269 }
270
271 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
272 pa->pa_intrline, &ih)) {
273 printf("%s: couldn't map interrupt\n", isp->isp_name);
274 isp_uninit(isp);
275 ISP_UNLOCK(isp);
276 free(isp->isp_param, M_DEVBUF);
277 return;
278 }
279
280 intrstr = pci_intr_string(pa->pa_pc, ih);
281 if (intrstr == NULL)
282 intrstr = "<I dunno>";
283 pcs->pci_ih =
284 pci_intr_establish(pa->pa_pc, ih, IPL_BIO, isp_intr, isp);
285 if (pcs->pci_ih == NULL) {
286 printf("%s: couldn't establish interrupt at %s\n",
287 isp->isp_name, intrstr);
288 isp_uninit(isp);
289 ISP_UNLOCK(isp);
290 free(isp->isp_param, M_DEVBUF);
291 return;
292 }
293 printf("%s: interrupting at %s\n", isp->isp_name, intrstr);
294
295 /*
296 * Create the DMA maps for the data transfers.
297 */
298 for (i = 0; i < RQUEST_QUEUE_LEN; i++) {
299 if (bus_dmamap_create(pcs->pci_dmat, MAXPHYS,
300 (MAXPHYS / NBPG) + 1, MAXPHYS, 0, BUS_DMA_NOWAIT,
301 &pcs->pci_xfer_dmap[i])) {
302 printf("%s: can't create dma maps\n",
303 isp->isp_name);
304 isp_uninit(isp);
305 ISP_UNLOCK(isp);
306 return;
307 }
308 }
309 /*
310 * Do Generic attach now.
311 */
312 isp_attach(isp);
313 if (isp->isp_state != ISP_RUNSTATE) {
314 isp_uninit(isp);
315 free(isp->isp_param, M_DEVBUF);
316 }
317 ISP_UNLOCK(isp);
318 }
319
320 #define PCI_BIU_REGS_OFF BIU_REGS_OFF
321
322 static u_int16_t
323 isp_pci_rd_reg(isp, regoff)
324 struct ispsoftc *isp;
325 int regoff;
326 {
327 u_int16_t rv;
328 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
329 int offset, oldsxp = 0;
330
331 if ((regoff & BIU_BLOCK) != 0) {
332 offset = PCI_BIU_REGS_OFF;
333 } else if ((regoff & MBOX_BLOCK) != 0) {
334 if (isp->isp_type & ISP_HA_SCSI)
335 offset = PCI_MBOX_REGS_OFF;
336 else
337 offset = PCI_MBOX_REGS2100_OFF;
338 } else if ((regoff & SXP_BLOCK) != 0) {
339 offset = PCI_SXP_REGS_OFF;
340 /*
341 * We will assume that someone has paused the RISC processor.
342 */
343 oldsxp = isp_pci_rd_reg(isp, BIU_CONF1);
344 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP);
345 } else {
346 offset = PCI_RISC_REGS_OFF;
347 }
348 regoff &= 0xff;
349 offset += regoff;
350 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
351 if ((regoff & SXP_BLOCK) != 0) {
352 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp);
353 }
354 return (rv);
355 }
356
357 static void
358 isp_pci_wr_reg(isp, regoff, val)
359 struct ispsoftc *isp;
360 int regoff;
361 u_int16_t val;
362 {
363 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
364 int offset, oldsxp = 0;
365 if ((regoff & BIU_BLOCK) != 0) {
366 offset = PCI_BIU_REGS_OFF;
367 } else if ((regoff & MBOX_BLOCK) != 0) {
368 if (isp->isp_type & ISP_HA_SCSI)
369 offset = PCI_MBOX_REGS_OFF;
370 else
371 offset = PCI_MBOX_REGS2100_OFF;
372 } else if ((regoff & SXP_BLOCK) != 0) {
373 offset = PCI_SXP_REGS_OFF;
374 /*
375 * We will assume that someone has paused the RISC processor.
376 */
377 oldsxp = isp_pci_rd_reg(isp, BIU_CONF1);
378 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP);
379 } else {
380 offset = PCI_RISC_REGS_OFF;
381 }
382 regoff &= 0xff;
383 offset += regoff;
384 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
385 if ((regoff & SXP_BLOCK) != 0) {
386 isp_pci_wr_reg(isp, BIU_CONF1, oldsxp);
387 }
388 }
389
390 static int
391 isp_pci_mbxdma(isp)
392 struct ispsoftc *isp;
393 {
394 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
395 bus_dma_segment_t seg;
396 bus_size_t len;
397 fcparam *fcp;
398 int rseg;
399
400 /*
401 * Allocate and map the request queue.
402 */
403 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN);
404 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
405 BUS_DMA_NOWAIT) ||
406 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
407 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT))
408 return (1);
409 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
410 &pci->pci_rquest_dmap) ||
411 bus_dmamap_load(pci->pci_dmat, pci->pci_rquest_dmap,
412 (caddr_t)isp->isp_rquest, len, NULL, BUS_DMA_NOWAIT))
413 return (1);
414
415 isp->isp_rquest_dma = pci->pci_rquest_dmap->dm_segs[0].ds_addr;
416
417 /*
418 * Allocate and map the result queue.
419 */
420 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN);
421 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
422 BUS_DMA_NOWAIT) ||
423 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
424 (caddr_t *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT))
425 return (1);
426 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
427 &pci->pci_result_dmap) ||
428 bus_dmamap_load(pci->pci_dmat, pci->pci_result_dmap,
429 (caddr_t)isp->isp_result, len, NULL, BUS_DMA_NOWAIT))
430 return (1);
431 isp->isp_result_dma = pci->pci_result_dmap->dm_segs[0].ds_addr;
432
433 if (isp->isp_type & ISP_HA_SCSI) {
434 return (0);
435 }
436
437 fcp = isp->isp_param;
438 len = ISP2100_SCRLEN;
439 if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
440 BUS_DMA_NOWAIT) ||
441 bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
442 (caddr_t *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT))
443 return (1);
444 if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
445 &pci->pci_scratch_dmap) ||
446 bus_dmamap_load(pci->pci_dmat, pci->pci_scratch_dmap,
447 (caddr_t)fcp->isp_scratch, len, NULL, BUS_DMA_NOWAIT))
448 return (1);
449 fcp->isp_scdma = pci->pci_scratch_dmap->dm_segs[0].ds_addr;
450 return (0);
451 }
452
453 static int
454 isp_pci_dmasetup(isp, xs, rq, iptrp, optr)
455 struct ispsoftc *isp;
456 struct scsipi_xfer *xs;
457 ispreq_t *rq;
458 u_int8_t *iptrp;
459 u_int8_t optr;
460 {
461 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
462 bus_dmamap_t dmap = pci->pci_xfer_dmap[rq->req_handle - 1];
463 ispcontreq_t *crq;
464 int segcnt, seg, error, ovseg, seglim, drq;
465
466 if (xs->datalen == 0) {
467 rq->req_seg_count = 1;
468 return (0);
469 }
470
471 if (rq->req_handle > RQUEST_QUEUE_LEN || rq->req_handle < 1) {
472 panic("%s: bad handle (%d) in isp_pci_dmasetup\n",
473 isp->isp_name, rq->req_handle);
474 /* NOTREACHED */
475 }
476
477 if (xs->flags & SCSI_DATA_IN) {
478 drq = REQFLAG_DATA_IN;
479 } else {
480 drq = REQFLAG_DATA_OUT;
481 }
482
483 if (isp->isp_type & ISP_HA_FC) {
484 seglim = ISP_RQDSEG_T2;
485 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen;
486 ((ispreqt2_t *)rq)->req_flags |= drq;
487 } else {
488 seglim = ISP_RQDSEG;
489 rq->req_flags |= drq;
490 }
491 error = bus_dmamap_load(pci->pci_dmat, dmap, xs->data, xs->datalen,
492 NULL, xs->flags & SCSI_NOSLEEP ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
493 if (error) {
494 XS_SETERR(xs, HBA_BOTCH);
495 return (error);
496 }
497
498 segcnt = dmap->dm_nsegs;
499
500 for (seg = 0, rq->req_seg_count = 0;
501 seg < segcnt && rq->req_seg_count < seglim;
502 seg++, rq->req_seg_count++) {
503 if (isp->isp_type & ISP_HA_FC) {
504 ispreqt2_t *rq2 = (ispreqt2_t *)rq;
505 rq2->req_dataseg[rq2->req_seg_count].ds_count =
506 dmap->dm_segs[seg].ds_len;
507 rq2->req_dataseg[rq2->req_seg_count].ds_base =
508 dmap->dm_segs[seg].ds_addr;
509 } else {
510 rq->req_dataseg[rq->req_seg_count].ds_count =
511 dmap->dm_segs[seg].ds_len;
512 rq->req_dataseg[rq->req_seg_count].ds_base =
513 dmap->dm_segs[seg].ds_addr;
514 }
515 }
516
517 if (seg == segcnt)
518 goto mapsync;
519
520 do {
521 crq = (ispcontreq_t *)
522 ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp);
523 *iptrp = (*iptrp + 1) & (RQUEST_QUEUE_LEN - 1);
524 if (*iptrp == optr) {
525 printf("%s: Request Queue Overflow++\n",
526 isp->isp_name);
527 bus_dmamap_unload(pci->pci_dmat, dmap);
528 XS_SETERR(xs, HBA_BOTCH);
529 return (EFBIG);
530 }
531 rq->req_header.rqs_entry_count++;
532 bzero((void *)crq, sizeof (*crq));
533 crq->req_header.rqs_entry_count = 1;
534 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG;
535
536 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG;
537 rq->req_seg_count++, seg++, ovseg++) {
538 crq->req_dataseg[ovseg].ds_count =
539 dmap->dm_segs[seg].ds_len;
540 crq->req_dataseg[ovseg].ds_base =
541 dmap->dm_segs[seg].ds_addr;
542 }
543 } while (seg < segcnt);
544
545 mapsync:
546 bus_dmamap_sync(pci->pci_dmat, dmap, 0, dmap->dm_mapsize,
547 xs->flags & SCSI_DATA_IN ?
548 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
549 return (0);
550 }
551
552 static void
553 isp_pci_dmateardown(isp, xs, handle)
554 struct ispsoftc *isp;
555 struct scsipi_xfer *xs;
556 u_int32_t handle;
557 {
558 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
559 bus_dmamap_t dmap = pci->pci_xfer_dmap[handle];
560
561 bus_dmamap_sync(pci->pci_dmat, dmap, 0, dmap->dm_mapsize,
562 xs->flags & SCSI_DATA_IN ?
563 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
564 bus_dmamap_unload(pci->pci_dmat, dmap);
565 }
566
567 static void
568 isp_pci_reset1(isp)
569 struct ispsoftc *isp;
570 {
571 /* Make sure the BIOS is disabled */
572 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
573 }
574
575 static void
576 isp_pci_dumpregs(isp)
577 struct ispsoftc *isp;
578 {
579 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
580 printf("%s: PCI Status Command/Status=%x\n", pci->pci_isp.isp_name,
581 pci_conf_read(pci->pci_pc, pci->pci_tag, PCI_COMMAND_STATUS_REG));
582 }
583