isp_pci.c revision 1.51.4.4 1 /* $NetBSD: isp_pci.c,v 1.51.4.4 2001/03/16 19:08:42 he Exp $ */
2 /*
3 * This driver, which is contained in NetBSD in the files:
4 *
5 * sys/dev/ic/isp.c
6 * sys/dev/ic/isp_inline.h
7 * sys/dev/ic/isp_netbsd.c
8 * sys/dev/ic/isp_netbsd.h
9 * sys/dev/ic/isp_target.c
10 * sys/dev/ic/isp_target.h
11 * sys/dev/ic/isp_tpublic.h
12 * sys/dev/ic/ispmbox.h
13 * sys/dev/ic/ispreg.h
14 * sys/dev/ic/ispvar.h
15 * sys/microcode/isp/asm_sbus.h
16 * sys/microcode/isp/asm_1040.h
17 * sys/microcode/isp/asm_1080.h
18 * sys/microcode/isp/asm_12160.h
19 * sys/microcode/isp/asm_2100.h
20 * sys/microcode/isp/asm_2200.h
21 * sys/pci/isp_pci.c
22 * sys/sbus/isp_sbus.c
23 *
24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org).
25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris,
26 * Linux versions. This tends to be an interesting maintenance problem.
27 *
28 * Please coordinate with Matthew Jacob on changes you wish to make here.
29 */
30 /*
31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
32 */
33 /*
34 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration
35 * All rights reserved.
36 *
37 * Additional Copyright (C) 2000, 2001 by Matthew Jacob
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * 2. The name of the author may not be used to endorse or promote products
45 * derived from this software without specific prior written permission
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 #include <dev/ic/isp_netbsd.h>
60 #include <dev/pci/pcireg.h>
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcidevs.h>
63
64 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int);
65 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t);
66 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
67 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int);
68 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t);
69 #endif
70 static int isp_pci_mbxdma(struct ispsoftc *);
71 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *,
72 u_int16_t *, u_int16_t);
73 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t);
74 static void isp_pci_reset1(struct ispsoftc *);
75 static void isp_pci_dumpregs(struct ispsoftc *, const char *);
76 static int isp_pci_intr(void *);
77
78 #if defined(ISP_DISABLE_1020_SUPPORT)
79 #define ISP_1040_RISC_CODE NULL
80 #else
81 #define ISP_1040_RISC_CODE isp_1040_risc_code
82 #include <dev/microcode/isp/asm_1040.h>
83 #endif
84
85 #if defined(ISP_DISABLE_1080_SUPPORT)
86 #define ISP_1080_RISC_CODE NULL
87 #else
88 #define ISP_1080_RISC_CODE isp_1080_risc_code
89 #include <dev/microcode/isp/asm_1080.h>
90 #endif
91
92 #if defined(ISP_DISABLE_12160_SUPPORT)
93 #define ISP_12160_RISC_CODE NULL
94 #else
95 #define ISP_12160_RISC_CODE isp_12160_risc_code
96 #include <dev/microcode/isp/asm_12160.h>
97 #endif
98
99 #if defined(ISP_DISABLE_2100_SUPPORT)
100 #define ISP_2100_RISC_CODE NULL
101 #else
102 #define ISP_2100_RISC_CODE isp_2100_risc_code
103 #include <dev/microcode/isp/asm_2100.h>
104 #endif
105
106 #if defined(ISP_DISABLE_2200_SUPPORT)
107 #define ISP_2200_RISC_CODE NULL
108 #else
109 #define ISP_2200_RISC_CODE isp_2200_risc_code
110 #include <dev/microcode/isp/asm_2200.h>
111 #endif
112
113 #ifndef ISP_DISABLE_1020_SUPPORT
114 static struct ispmdvec mdvec = {
115 isp_pci_rd_reg,
116 isp_pci_wr_reg,
117 isp_pci_mbxdma,
118 isp_pci_dmasetup,
119 isp_pci_dmateardown,
120 NULL,
121 isp_pci_reset1,
122 isp_pci_dumpregs,
123 ISP_1040_RISC_CODE,
124 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
125 };
126 #endif
127
128 #ifndef ISP_DISABLE_1080_SUPPORT
129 static struct ispmdvec mdvec_1080 = {
130 isp_pci_rd_reg_1080,
131 isp_pci_wr_reg_1080,
132 isp_pci_mbxdma,
133 isp_pci_dmasetup,
134 isp_pci_dmateardown,
135 NULL,
136 isp_pci_reset1,
137 isp_pci_dumpregs,
138 ISP_1080_RISC_CODE,
139 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
140 };
141 #endif
142
143 #ifndef ISP_DISABLE_12160_SUPPORT
144 static struct ispmdvec mdvec_12160 = {
145 isp_pci_rd_reg_1080,
146 isp_pci_wr_reg_1080,
147 isp_pci_mbxdma,
148 isp_pci_dmasetup,
149 isp_pci_dmateardown,
150 NULL,
151 isp_pci_reset1,
152 isp_pci_dumpregs,
153 ISP_12160_RISC_CODE,
154 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
155 };
156 #endif
157
158 #ifndef ISP_DISABLE_2100_SUPPORT
159 static struct ispmdvec mdvec_2100 = {
160 isp_pci_rd_reg,
161 isp_pci_wr_reg,
162 isp_pci_mbxdma,
163 isp_pci_dmasetup,
164 isp_pci_dmateardown,
165 NULL,
166 isp_pci_reset1,
167 isp_pci_dumpregs,
168 ISP_2100_RISC_CODE
169 };
170 #endif
171
172 #ifndef ISP_DISABLE_2200_SUPPORT
173 static struct ispmdvec mdvec_2200 = {
174 isp_pci_rd_reg,
175 isp_pci_wr_reg,
176 isp_pci_mbxdma,
177 isp_pci_dmasetup,
178 isp_pci_dmateardown,
179 NULL,
180 isp_pci_reset1,
181 isp_pci_dumpregs,
182 ISP_2200_RISC_CODE
183 };
184 #endif
185
186 #ifndef PCI_VENDOR_QLOGIC
187 #define PCI_VENDOR_QLOGIC 0x1077
188 #endif
189
190 #ifndef PCI_PRODUCT_QLOGIC_ISP1020
191 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
192 #endif
193
194 #ifndef PCI_PRODUCT_QLOGIC_ISP1080
195 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080
196 #endif
197
198 #ifndef PCI_PRODUCT_QLOGIC_ISP1240
199 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
200 #endif
201
202 #ifndef PCI_PRODUCT_QLOGIC_ISP1280
203 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
204 #endif
205
206 #ifndef PCI_PRODUCT_QLOGIC_ISP12160
207 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216
208 #endif
209
210 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
211 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
212 #endif
213
214 #ifndef PCI_PRODUCT_QLOGIC_ISP2200
215 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200
216 #endif
217
218 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
219
220 #define PCI_QLOGIC_ISP1080 \
221 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
222
223 #define PCI_QLOGIC_ISP1240 \
224 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
225
226 #define PCI_QLOGIC_ISP1280 \
227 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
228
229 #define PCI_QLOGIC_ISP12160 \
230 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
231
232 #define PCI_QLOGIC_ISP2100 \
233 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
234
235 #define PCI_QLOGIC_ISP2200 \
236 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
237
238 #define IO_MAP_REG 0x10
239 #define MEM_MAP_REG 0x14
240 #define PCIR_ROMADDR 0x30
241
242 #define PCI_DFLT_LTNCY 0x40
243 #define PCI_DFLT_LNSZ 0x10
244
245
246 static int isp_pci_probe(struct device *, struct cfdata *, void *);
247 static void isp_pci_attach(struct device *, struct device *, void *);
248
249 struct isp_pcisoftc {
250 struct ispsoftc pci_isp;
251 pci_chipset_tag_t pci_pc;
252 pcitag_t pci_tag;
253 bus_space_tag_t pci_st;
254 bus_space_handle_t pci_sh;
255 bus_dma_tag_t pci_dmat;
256 bus_dmamap_t pci_scratch_dmap; /* for fcp only */
257 bus_dmamap_t pci_rquest_dmap;
258 bus_dmamap_t pci_result_dmap;
259 bus_dmamap_t *pci_xfer_dmap;
260 void * pci_ih;
261 int16_t pci_poff[_NREG_BLKS];
262 };
263
264 struct cfattach isp_pci_ca = {
265 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach
266 };
267
268 #ifdef DEBUG
269 const char vstring[] =
270 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d";
271 #endif
272
273 static int
274 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux)
275 {
276 struct pci_attach_args *pa = aux;
277 switch (pa->pa_id) {
278 #ifndef ISP_DISABLE_1020_SUPPORT
279 case PCI_QLOGIC_ISP:
280 return (1);
281 #endif
282 #ifndef ISP_DISABLE_1080_SUPPORT
283 case PCI_QLOGIC_ISP1080:
284 case PCI_QLOGIC_ISP1240:
285 case PCI_QLOGIC_ISP1280:
286 return (1);
287 #endif
288 #ifndef ISP_DISABLE_12160_SUPPORT
289 case PCI_QLOGIC_ISP12160:
290 return (1);
291 #endif
292 #ifndef ISP_DISABLE_2100_SUPPORT
293 case PCI_QLOGIC_ISP2100:
294 return (1);
295 #endif
296 #ifndef ISP_DISABLE_2200_SUPPORT
297 case PCI_QLOGIC_ISP2200:
298 return (1);
299 #endif
300 default:
301 return (0);
302 }
303 }
304
305
306 static void
307 isp_pci_attach(struct device *parent, struct device *self, void *aux)
308 {
309 #ifdef DEBUG
310 static char oneshot = 1;
311 #endif
312 static const char nomem[] = "%s: no mem for sdparam table\n";
313 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ;
314 struct pci_attach_args *pa = aux;
315 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self;
316 struct ispsoftc *isp = &pcs->pci_isp;
317 bus_space_tag_t st, iot, memt;
318 bus_space_handle_t sh, ioh, memh;
319 pci_intr_handle_t ih;
320 const char *intrstr;
321 int ioh_valid, memh_valid;
322
323 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
324 PCI_MAPREG_TYPE_IO, 0,
325 &iot, &ioh, NULL, NULL) == 0);
326 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG,
327 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
328 &memt, &memh, NULL, NULL) == 0);
329
330 if (memh_valid) {
331 st = memt;
332 sh = memh;
333 } else if (ioh_valid) {
334 st = iot;
335 sh = ioh;
336 } else {
337 printf(": unable to map device registers\n");
338 return;
339 }
340 printf("\n");
341
342 pcs->pci_st = st;
343 pcs->pci_sh = sh;
344 pcs->pci_dmat = pa->pa_dmat;
345 pcs->pci_pc = pa->pa_pc;
346 pcs->pci_tag = pa->pa_tag;
347 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
348 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
349 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
350 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
351 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
352 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff;
353
354 #ifndef ISP_DISABLE_1020_SUPPORT
355 if (pa->pa_id == PCI_QLOGIC_ISP) {
356 isp->isp_mdvec = &mdvec;
357 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
358 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT);
359 if (isp->isp_param == NULL) {
360 printf(nomem, isp->isp_name);
361 return;
362 }
363 bzero(isp->isp_param, sizeof (sdparam));
364 }
365 #endif
366 #ifndef ISP_DISABLE_1080_SUPPORT
367 if (pa->pa_id == PCI_QLOGIC_ISP1080) {
368 isp->isp_mdvec = &mdvec_1080;
369 isp->isp_type = ISP_HA_SCSI_1080;
370 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT);
371 if (isp->isp_param == NULL) {
372 printf(nomem, isp->isp_name);
373 return;
374 }
375 bzero(isp->isp_param, sizeof (sdparam));
376 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
377 ISP1080_DMA_REGS_OFF;
378 }
379 if (pa->pa_id == PCI_QLOGIC_ISP1240) {
380 isp->isp_mdvec = &mdvec_1080;
381 isp->isp_type = ISP_HA_SCSI_1240;
382 isp->isp_param =
383 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT);
384 if (isp->isp_param == NULL) {
385 printf(nomem, isp->isp_name);
386 return;
387 }
388 bzero(isp->isp_param, 2 * sizeof (sdparam));
389 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
390 ISP1080_DMA_REGS_OFF;
391 }
392 if (pa->pa_id == PCI_QLOGIC_ISP1280) {
393 isp->isp_mdvec = &mdvec_1080;
394 isp->isp_type = ISP_HA_SCSI_1280;
395 isp->isp_param =
396 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT);
397 if (isp->isp_param == NULL) {
398 printf(nomem, isp->isp_name);
399 return;
400 }
401 bzero(isp->isp_param, 2 * sizeof (sdparam));
402 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
403 ISP1080_DMA_REGS_OFF;
404 }
405 #endif
406 #ifndef ISP_DISABLE_12160_SUPPORT
407 if (pa->pa_id == PCI_QLOGIC_ISP12160) {
408 isp->isp_mdvec = &mdvec_12160;
409 isp->isp_type = ISP_HA_SCSI_12160;
410 isp->isp_param =
411 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT);
412 if (isp->isp_param == NULL) {
413 printf(nomem, isp->isp_name);
414 return;
415 }
416 bzero(isp->isp_param, 2 * sizeof (sdparam));
417 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
418 ISP1080_DMA_REGS_OFF;
419 }
420 #endif
421 #ifndef ISP_DISABLE_2100_SUPPORT
422 if (pa->pa_id == PCI_QLOGIC_ISP2100) {
423 isp->isp_mdvec = &mdvec_2100;
424 isp->isp_type = ISP_HA_FC_2100;
425 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT);
426 if (isp->isp_param == NULL) {
427 printf(nomem, isp->isp_name);
428 return;
429 }
430 bzero(isp->isp_param, sizeof (fcparam));
431 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
432 PCI_MBOX_REGS2100_OFF;
433 if (rev < 3) {
434 /*
435 * XXX: Need to get the actual revision
436 * XXX: number of the 2100 FB. At any rate,
437 * XXX: lower cache line size for early revision
438 * XXX; boards.
439 */
440 linesz = 1;
441 }
442 }
443 #endif
444 #ifndef ISP_DISABLE_2200_SUPPORT
445 if (pa->pa_id == PCI_QLOGIC_ISP2200) {
446 isp->isp_mdvec = &mdvec_2200;
447 isp->isp_type = ISP_HA_FC_2200;
448 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT);
449 if (isp->isp_param == NULL) {
450 printf(nomem, isp->isp_name);
451 return;
452 }
453 bzero(isp->isp_param, sizeof (fcparam));
454 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
455 PCI_MBOX_REGS2100_OFF;
456 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
457 }
458 #endif
459 /*
460 * Set up logging levels.
461 */
462 #ifdef ISP_LOGDEFAULT
463 isp->isp_dblev = ISP_LOGDEFAULT;
464 #else
465 isp->isp_dblev = ISP_LOGCONFIG|ISP_LOGWARN|ISP_LOGERR;
466 #ifdef SCSIDEBUG
467 isp->isp_dblev |= ISP_LOGDEBUG1|ISP_LOGDEBUG2;
468 #endif
469 #ifdef DEBUG
470 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGINFO;
471 #endif
472 #endif
473
474 #ifdef DEBUG
475 if (oneshot) {
476 oneshot = 0;
477 isp_prt(isp, ISP_LOGCONFIG, vstring,
478 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
479 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
480 }
481 #endif
482
483 isp->isp_revision = rev;
484
485 /*
486 * Make sure that command register set sanely.
487 */
488 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
489 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
490
491 /*
492 * Not so sure about these- but I think it's important that they get
493 * enabled......
494 */
495 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
496 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data);
497
498 /*
499 * Make sure that the latency timer, cache line size,
500 * and ROM is disabled.
501 */
502 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
503 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
504 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
505 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT);
506 data |= (linesz << PCI_CACHELINE_SHIFT);
507 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
508
509 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR);
510 data &= ~1;
511 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data);
512
513 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
514 pa->pa_intrline, &ih)) {
515 printf("%s: couldn't map interrupt\n", isp->isp_name);
516 free(isp->isp_param, M_DEVBUF);
517 return;
518 }
519 intrstr = pci_intr_string(pa->pa_pc, ih);
520 if (intrstr == NULL)
521 intrstr = "<I dunno>";
522 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
523 isp_pci_intr, isp);
524 if (pcs->pci_ih == NULL) {
525 printf("%s: couldn't establish interrupt at %s\n",
526 isp->isp_name, intrstr);
527 free(isp->isp_param, M_DEVBUF);
528 return;
529 }
530
531 printf("%s: interrupting at %s\n", isp->isp_name, intrstr);
532
533 if (IS_FC(isp)) {
534 DEFAULT_NODEWWN(isp) = 0x400000007F000002;
535 DEFAULT_PORTWWN(isp) = 0x400000007F000002;
536 }
537
538 isp->isp_confopts = self->dv_cfdata->cf_flags;
539 isp->isp_role = ISP_DEFAULT_ROLES;
540 ISP_LOCK(isp);
541 isp->isp_osinfo.no_mbox_ints = 1;
542 isp_reset(isp);
543 if (isp->isp_state != ISP_RESETSTATE) {
544 ISP_UNLOCK(isp);
545 free(isp->isp_param, M_DEVBUF);
546 return;
547 }
548 ENABLE_INTS(isp);
549 isp_init(isp);
550 if (isp->isp_state != ISP_INITSTATE) {
551 isp_uninit(isp);
552 ISP_UNLOCK(isp);
553 free(isp->isp_param, M_DEVBUF);
554 return;
555 }
556 /*
557 * Do platform attach.
558 */
559 ISP_UNLOCK(isp);
560 isp_attach(isp);
561 if (isp->isp_state != ISP_RUNSTATE) {
562 ISP_LOCK(isp);
563 isp_uninit(isp);
564 free(isp->isp_param, M_DEVBUF);
565 ISP_UNLOCK(isp);
566 }
567 }
568
569 static u_int16_t
570 isp_pci_rd_reg(struct ispsoftc *isp, int regoff)
571 {
572 u_int16_t rv;
573 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
574 int offset, oldconf = 0;
575
576 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
577 /*
578 * We will assume that someone has paused the RISC processor.
579 */
580 oldconf = isp_pci_rd_reg(isp, BIU_CONF1);
581 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP);
582 delay(250);
583 }
584 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
585 offset += (regoff & 0xff);
586 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
587 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
588 isp_pci_wr_reg(isp, BIU_CONF1, oldconf);
589 delay(250);
590 }
591 return (rv);
592 }
593
594 static void
595 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val)
596 {
597 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
598 int offset, oldconf = 0;
599
600 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
601 /*
602 * We will assume that someone has paused the RISC processor.
603 */
604 oldconf = isp_pci_rd_reg(isp, BIU_CONF1);
605 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP);
606 delay(250);
607 }
608 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
609 offset += (regoff & 0xff);
610 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
611 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
612 isp_pci_wr_reg(isp, BIU_CONF1, oldconf);
613 delay(250);
614 }
615 }
616
617 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
618 static u_int16_t
619 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff)
620 {
621 u_int16_t rv, oc = 0;
622 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
623 int offset;
624
625 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
626 u_int16_t tc;
627 /*
628 * We will assume that someone has paused the RISC processor.
629 */
630 oc = isp_pci_rd_reg(isp, BIU_CONF1);
631 tc = oc & ~BIU_PCI1080_CONF1_DMA;
632 if (IS_1280(isp)) {
633 if (regoff & SXP_BANK1_SELECT)
634 tc |= BIU_PCI1080_CONF1_SXP0;
635 else
636 tc |= BIU_PCI1080_CONF1_SXP1;
637 } else {
638 tc |= BIU_PCI1080_CONF1_SXP0;
639 }
640 isp_pci_wr_reg(isp, BIU_CONF1, tc);
641 delay(250);
642 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
643 oc = isp_pci_rd_reg(isp, BIU_CONF1);
644 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA);
645 delay(250);
646 }
647 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
648 offset += (regoff & 0xff);
649 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
650 /*
651 * Okay, because BIU_CONF1 is always nonzero
652 */
653 if (oc) {
654 isp_pci_wr_reg(isp, BIU_CONF1, oc);
655 delay(250);
656 }
657 return (rv);
658 }
659
660 static void
661 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val)
662 {
663 u_int16_t oc = 0;
664 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
665 int offset;
666
667 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
668 u_int16_t tc;
669 /*
670 * We will assume that someone has paused the RISC processor.
671 */
672 oc = isp_pci_rd_reg(isp, BIU_CONF1);
673 tc = oc & ~BIU_PCI1080_CONF1_DMA;
674 if (IS_1280(isp)) {
675 if (regoff & SXP_BANK1_SELECT)
676 tc |= BIU_PCI1080_CONF1_SXP0;
677 else
678 tc |= BIU_PCI1080_CONF1_SXP1;
679 } else {
680 tc |= BIU_PCI1080_CONF1_SXP0;
681 }
682 isp_pci_wr_reg(isp, BIU_CONF1, tc);
683 delay(250);
684 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
685 oc = isp_pci_rd_reg(isp, BIU_CONF1);
686 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA);
687 delay(250);
688 }
689 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
690 offset += (regoff & 0xff);
691 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
692 /*
693 * Okay, because BIU_CONF1 is always nonzero
694 */
695 if (oc) {
696 isp_pci_wr_reg(isp, BIU_CONF1, oc);
697 delay(250);
698 }
699 }
700 #endif
701
702 static int
703 isp_pci_mbxdma(struct ispsoftc *isp)
704 {
705 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
706 bus_dma_tag_t dmat = pcs->pci_dmat;
707 bus_dma_segment_t sg;
708 bus_size_t len;
709 fcparam *fcp;
710 int rs, i;
711
712 if (isp->isp_rquest_dma) /* been here before? */
713 return (0);
714
715 len = isp->isp_maxcmds * sizeof (XS_T);
716 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK);
717 if (isp->isp_xflist == NULL) {
718 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array");
719 return (1);
720 }
721 bzero(isp->isp_xflist, len);
722 len = isp->isp_maxcmds * sizeof (bus_dmamap_t);
723 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK);
724 if (pcs->pci_xfer_dmap == NULL) {
725 free(isp->isp_xflist, M_DEVBUF);
726 isp->isp_xflist = NULL;
727 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array");
728 return (1);
729 }
730 for (i = 0; i < isp->isp_maxcmds; i++) {
731 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / NBPG) + 1,
732 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) {
733 isp_prt(isp, ISP_LOGERR, "cannot create dma maps");
734 break;
735 }
736 }
737 if (i < isp->isp_maxcmds) {
738 while (--i >= 0) {
739 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
740 }
741 free(isp->isp_xflist, M_DEVBUF);
742 free(pcs->pci_xfer_dmap, M_DEVBUF);
743 isp->isp_xflist = NULL;
744 pcs->pci_xfer_dmap = NULL;
745 return (1);
746 }
747
748 /*
749 * Allocate and map the request queue.
750 */
751 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
752 if (bus_dmamem_alloc(dmat, len, NBPG, 0, &sg, 1, &rs, BUS_DMA_NOWAIT) ||
753 bus_dmamem_map(pcs->pci_dmat, &sg, rs, len,
754 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
755 goto dmafail;
756 }
757
758 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
759 &pcs->pci_rquest_dmap) || bus_dmamap_load(dmat,
760 pcs->pci_rquest_dmap, (caddr_t)isp->isp_rquest, len, NULL,
761 BUS_DMA_NOWAIT)) {
762 goto dmafail;
763 }
764
765 isp->isp_rquest_dma = pcs->pci_rquest_dmap->dm_segs[0].ds_addr;
766
767 /*
768 * Allocate and map the result queue.
769 */
770 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
771 if (bus_dmamem_alloc(dmat, len, NBPG, 0, &sg, 1, &rs, BUS_DMA_NOWAIT) ||
772 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result,
773 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
774 goto dmafail;
775 }
776 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
777 &pcs->pci_result_dmap) || bus_dmamap_load(pcs->pci_dmat,
778 pcs->pci_result_dmap, (caddr_t)isp->isp_result, len, NULL,
779 BUS_DMA_NOWAIT)) {
780 goto dmafail;
781 }
782 isp->isp_result_dma = pcs->pci_result_dmap->dm_segs[0].ds_addr;
783
784 if (IS_SCSI(isp)) {
785 return (0);
786 }
787
788 fcp = isp->isp_param;
789 len = ISP2100_SCRLEN;
790 if (bus_dmamem_alloc(dmat, len, NBPG, 0, &sg, 1, &rs, BUS_DMA_NOWAIT) ||
791 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch,
792 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
793 goto dmafail;
794 }
795 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
796 &pcs->pci_scratch_dmap) || bus_dmamap_load(dmat,
797 pcs->pci_scratch_dmap, (caddr_t)fcp->isp_scratch, len, NULL,
798 BUS_DMA_NOWAIT)) {
799 goto dmafail;
800 }
801 fcp->isp_scdma = pcs->pci_scratch_dmap->dm_segs[0].ds_addr;
802 return (0);
803 dmafail:
804 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure");
805 for (i = 0; i < isp->isp_maxcmds; i++) {
806 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
807 }
808 free(isp->isp_xflist, M_DEVBUF);
809 free(pcs->pci_xfer_dmap, M_DEVBUF);
810 isp->isp_xflist = NULL;
811 pcs->pci_xfer_dmap = NULL;
812 return (1);
813 }
814
815 static int
816 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq,
817 u_int16_t *iptrp, u_int16_t optr)
818 {
819 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
820 bus_dmamap_t dmap;
821 ispcontreq_t *crq;
822 int segcnt, seg, error, ovseg, seglim, drq;
823
824 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)];
825
826 if (xs->datalen == 0) {
827 rq->req_seg_count = 1;
828 goto mbxsync;
829 }
830 if (xs->xs_control & XS_CTL_DATA_IN) {
831 drq = REQFLAG_DATA_IN;
832 } else {
833 drq = REQFLAG_DATA_OUT;
834 }
835
836 if (IS_FC(isp)) {
837 seglim = ISP_RQDSEG_T2;
838 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen;
839 ((ispreqt2_t *)rq)->req_flags |= drq;
840 } else {
841 rq->req_flags |= drq;
842 if (XS_CDBLEN(xs) > 12) {
843 seglim = 0;
844 } else {
845 seglim = ISP_RQDSEG;
846 }
847 }
848 error = bus_dmamap_load(pcs->pci_dmat, dmap, xs->data, xs->datalen,
849 NULL, xs->xs_control & XS_CTL_NOSLEEP ?
850 BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
851 if (error) {
852 XS_SETERR(xs, HBA_BOTCH);
853 return (CMD_COMPLETE);
854 }
855
856 segcnt = dmap->dm_nsegs;
857
858 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs",
859 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" :
860 "write from", xs->data, segcnt);
861
862 for (seg = 0, rq->req_seg_count = 0;
863 seglim && seg < segcnt && rq->req_seg_count < seglim;
864 seg++, rq->req_seg_count++) {
865 if (IS_FC(isp)) {
866 ispreqt2_t *rq2 = (ispreqt2_t *)rq;
867 #if _BYTE_ORDER == _BIG_ENDIAN
868 rq2->req_dataseg[rq2->req_seg_count].ds_count =
869 bswap32(dmap->dm_segs[seg].ds_len);
870 rq2->req_dataseg[rq2->req_seg_count].ds_base =
871 bswap32(dmap->dm_segs[seg].ds_addr);
872 #else
873 rq2->req_dataseg[rq2->req_seg_count].ds_count =
874 dmap->dm_segs[seg].ds_len;
875 rq2->req_dataseg[rq2->req_seg_count].ds_base =
876 dmap->dm_segs[seg].ds_addr;
877 #endif
878 } else {
879 #if _BYTE_ORDER == _BIG_ENDIAN
880 rq->req_dataseg[rq->req_seg_count].ds_count =
881 bswap32(dmap->dm_segs[seg].ds_len);
882 rq->req_dataseg[rq->req_seg_count].ds_base =
883 bswap32(dmap->dm_segs[seg].ds_addr);
884 #else
885 rq->req_dataseg[rq->req_seg_count].ds_count =
886 dmap->dm_segs[seg].ds_len;
887 rq->req_dataseg[rq->req_seg_count].ds_base =
888 dmap->dm_segs[seg].ds_addr;
889 #endif
890 }
891 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}",
892 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr,
893 (unsigned long) dmap->dm_segs[seg].ds_len);
894 }
895
896 if (seg == segcnt)
897 goto dmasync;
898
899 do {
900 crq = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp);
901 *iptrp = ISP_NXT_QENTRY(*iptrp, RQUEST_QUEUE_LEN(isp));
902 if (*iptrp == optr) {
903 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++");
904 bus_dmamap_unload(pcs->pci_dmat, dmap);
905 XS_SETERR(xs, HBA_BOTCH);
906 return (CMD_EAGAIN);
907 }
908 rq->req_header.rqs_entry_count++;
909 bzero((void *)crq, sizeof (*crq));
910 crq->req_header.rqs_entry_count = 1;
911 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG;
912
913 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG;
914 rq->req_seg_count++, seg++, ovseg++) {
915 #if _BYTE_ORDER == _BIG_ENDIAN
916 crq->req_dataseg[ovseg].ds_count =
917 bswap32(dmap->dm_segs[seg].ds_len);
918 crq->req_dataseg[ovseg].ds_base =
919 bswap32(dmap->dm_segs[seg].ds_addr);
920 #else
921 crq->req_dataseg[ovseg].ds_count =
922 dmap->dm_segs[seg].ds_len;
923 crq->req_dataseg[ovseg].ds_base =
924 dmap->dm_segs[seg].ds_addr;
925 #endif
926 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}",
927 rq->req_header.rqs_entry_count - 1,
928 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr,
929 (unsigned long) dmap->dm_segs[seg].ds_len);
930 }
931 } while (seg < segcnt);
932
933
934 dmasync:
935 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize,
936 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD :
937 BUS_DMASYNC_PREWRITE);
938
939 mbxsync:
940 ISP_SWIZZLE_REQUEST(isp, rq);
941 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_rquest_dmap, 0,
942 pcs->pci_rquest_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
943 return (CMD_QUEUED);
944 }
945
946 static int
947 isp_pci_intr(void *arg)
948 {
949 int rv;
950 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)arg;
951 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_result_dmap, 0,
952 pcs->pci_result_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
953 pcs->pci_isp.isp_osinfo.onintstack = 1;
954 rv = isp_intr(arg);
955 pcs->pci_isp.isp_osinfo.onintstack = 0;
956 return (rv);
957 }
958
959 static void
960 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle)
961 {
962 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
963 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)];
964 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize,
965 xs->xs_control & XS_CTL_DATA_IN ?
966 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
967 bus_dmamap_unload(pcs->pci_dmat, dmap);
968 }
969
970 static void
971 isp_pci_reset1(struct ispsoftc *isp)
972 {
973 /* Make sure the BIOS is disabled */
974 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
975 }
976
977 static void
978 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg)
979 {
980 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
981 if (msg)
982 printf("%s: %s\n", isp->isp_name, msg);
983 if (IS_SCSI(isp))
984 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
985 else
986 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
987 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
988 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
989 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
990
991
992 if (IS_SCSI(isp)) {
993 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
994 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
995 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
996 ISP_READ(isp, CDMA_FIFO_STS));
997 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
998 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
999 ISP_READ(isp, DDMA_FIFO_STS));
1000 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
1001 ISP_READ(isp, SXP_INTERRUPT),
1002 ISP_READ(isp, SXP_GROSS_ERR),
1003 ISP_READ(isp, SXP_PINS_CTRL));
1004 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
1005 }
1006 printf(" mbox regs: %x %x %x %x %x\n",
1007 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
1008 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
1009 ISP_READ(isp, OUTMAILBOX4));
1010 printf(" PCI Status Command/Status=%x\n",
1011 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG));
1012 }
1013