isp_pci.c revision 1.55
1 /* $NetBSD: isp_pci.c,v 1.55 2000/08/03 03:00:04 mjacob Exp $ */ 2 /* 3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 4 * Matthew Jacob (mjacob (at) nas.nasa.gov) 5 */ 6 /* 7 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <dev/ic/isp_netbsd.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 38 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int)); 39 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t)); 40 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 41 static u_int16_t isp_pci_rd_reg_1080 __P((struct ispsoftc *, int)); 42 static void isp_pci_wr_reg_1080 __P((struct ispsoftc *, int, u_int16_t)); 43 #endif 44 static int isp_pci_mbxdma __P((struct ispsoftc *)); 45 static int isp_pci_dmasetup __P((struct ispsoftc *, struct scsipi_xfer *, 46 ispreq_t *, u_int16_t *, u_int16_t)); 47 static void isp_pci_dmateardown __P((struct ispsoftc *, struct scsipi_xfer *, 48 u_int32_t)); 49 static void isp_pci_reset1 __P((struct ispsoftc *)); 50 static void isp_pci_dumpregs __P((struct ispsoftc *, const char *)); 51 static int isp_pci_intr __P((void *)); 52 53 #if defined(ISP_DISABLE_1020_SUPPORT) 54 #define ISP_1040_RISC_CODE NULL 55 #else 56 #define ISP_1040_RISC_CODE isp_1040_risc_code 57 #include <dev/microcode/isp/asm_1040.h> 58 #endif 59 60 #if defined(ISP_DISABLE_1080_SUPPORT) 61 #define ISP_1080_RISC_CODE NULL 62 #else 63 #define ISP_1080_RISC_CODE isp_1080_risc_code 64 #include <dev/microcode/isp/asm_1080.h> 65 #endif 66 67 #if defined(ISP_DISABLE_12160_SUPPORT) 68 #define ISP_12160_RISC_CODE NULL 69 #else 70 #define ISP_12160_RISC_CODE isp_12160_risc_code 71 #include <dev/microcode/isp/asm_12160.h> 72 #endif 73 74 #if defined(ISP_DISABLE_2100_SUPPORT) 75 #define ISP_2100_RISC_CODE NULL 76 #else 77 #define ISP_2100_RISC_CODE isp_2100_risc_code 78 #include <dev/microcode/isp/asm_2100.h> 79 #endif 80 81 #if defined(ISP_DISABLE_2200_SUPPORT) 82 #define ISP_2200_RISC_CODE NULL 83 #else 84 #define ISP_2200_RISC_CODE isp_2200_risc_code 85 #include <dev/microcode/isp/asm_2200.h> 86 #endif 87 88 #ifndef ISP_DISABLE_1020_SUPPORT 89 static struct ispmdvec mdvec = { 90 isp_pci_rd_reg, 91 isp_pci_wr_reg, 92 isp_pci_mbxdma, 93 isp_pci_dmasetup, 94 isp_pci_dmateardown, 95 NULL, 96 isp_pci_reset1, 97 isp_pci_dumpregs, 98 ISP_1040_RISC_CODE, 99 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 100 }; 101 #endif 102 103 #ifndef ISP_DISABLE_1080_SUPPORT 104 static struct ispmdvec mdvec_1080 = { 105 isp_pci_rd_reg_1080, 106 isp_pci_wr_reg_1080, 107 isp_pci_mbxdma, 108 isp_pci_dmasetup, 109 isp_pci_dmateardown, 110 NULL, 111 isp_pci_reset1, 112 isp_pci_dumpregs, 113 ISP_1080_RISC_CODE, 114 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 115 }; 116 #endif 117 118 #ifndef ISP_DISABLE_12160_SUPPORT 119 static struct ispmdvec mdvec_12160 = { 120 isp_pci_rd_reg_1080, 121 isp_pci_wr_reg_1080, 122 isp_pci_mbxdma, 123 isp_pci_dmasetup, 124 isp_pci_dmateardown, 125 NULL, 126 isp_pci_reset1, 127 isp_pci_dumpregs, 128 ISP_12160_RISC_CODE, 129 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 130 }; 131 #endif 132 133 #ifndef ISP_DISABLE_2100_SUPPORT 134 static struct ispmdvec mdvec_2100 = { 135 isp_pci_rd_reg, 136 isp_pci_wr_reg, 137 isp_pci_mbxdma, 138 isp_pci_dmasetup, 139 isp_pci_dmateardown, 140 NULL, 141 isp_pci_reset1, 142 isp_pci_dumpregs, 143 ISP_2100_RISC_CODE 144 }; 145 #endif 146 147 #ifndef ISP_DISABLE_2200_SUPPORT 148 static struct ispmdvec mdvec_2200 = { 149 isp_pci_rd_reg, 150 isp_pci_wr_reg, 151 isp_pci_mbxdma, 152 isp_pci_dmasetup, 153 isp_pci_dmateardown, 154 NULL, 155 isp_pci_reset1, 156 isp_pci_dumpregs, 157 ISP_2200_RISC_CODE 158 }; 159 #endif 160 161 #ifndef PCI_VENDOR_QLOGIC 162 #define PCI_VENDOR_QLOGIC 0x1077 163 #endif 164 165 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 166 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 167 #endif 168 169 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 170 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 171 #endif 172 173 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 174 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 175 #endif 176 177 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 178 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 179 #endif 180 181 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 182 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 183 #endif 184 185 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 186 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 187 #endif 188 189 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 190 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 191 #endif 192 193 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 194 195 #define PCI_QLOGIC_ISP1080 \ 196 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 197 198 #define PCI_QLOGIC_ISP1240 \ 199 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 200 201 #define PCI_QLOGIC_ISP1280 \ 202 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 203 204 #define PCI_QLOGIC_ISP12160 \ 205 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 206 207 #define PCI_QLOGIC_ISP2100 \ 208 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 209 210 #define PCI_QLOGIC_ISP2200 \ 211 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 212 213 #define IO_MAP_REG 0x10 214 #define MEM_MAP_REG 0x14 215 #define PCIR_ROMADDR 0x30 216 217 #define PCI_DFLT_LTNCY 0x40 218 #define PCI_DFLT_LNSZ 0x10 219 220 221 static int isp_pci_probe __P((struct device *, struct cfdata *, void *)); 222 static void isp_pci_attach __P((struct device *, struct device *, void *)); 223 224 struct isp_pcisoftc { 225 struct ispsoftc pci_isp; 226 pci_chipset_tag_t pci_pc; 227 pcitag_t pci_tag; 228 bus_space_tag_t pci_st; 229 bus_space_handle_t pci_sh; 230 bus_dma_tag_t pci_dmat; 231 bus_dmamap_t pci_scratch_dmap; /* for fcp only */ 232 bus_dmamap_t pci_rquest_dmap; 233 bus_dmamap_t pci_result_dmap; 234 bus_dmamap_t *pci_xfer_dmap; 235 void * pci_ih; 236 int16_t pci_poff[_NREG_BLKS]; 237 }; 238 239 struct cfattach isp_pci_ca = { 240 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach 241 }; 242 243 #ifdef DEBUG 244 static char *vstring = 245 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 246 #endif 247 248 static int 249 isp_pci_probe(parent, match, aux) 250 struct device *parent; 251 struct cfdata *match; 252 void *aux; 253 { 254 struct pci_attach_args *pa = aux; 255 switch (pa->pa_id) { 256 #ifndef ISP_DISABLE_1020_SUPPORT 257 case PCI_QLOGIC_ISP: 258 return (1); 259 #endif 260 #ifndef ISP_DISABLE_1080_SUPPORT 261 case PCI_QLOGIC_ISP1080: 262 case PCI_QLOGIC_ISP1240: 263 case PCI_QLOGIC_ISP1280: 264 return (1); 265 #endif 266 #ifndef ISP_DISABLE_12160_SUPPORT 267 case PCI_QLOGIC_ISP12160: 268 return (1); 269 #endif 270 #ifndef ISP_DISABLE_2100_SUPPORT 271 case PCI_QLOGIC_ISP2100: 272 return (1); 273 #endif 274 #ifndef ISP_DISABLE_2200_SUPPORT 275 case PCI_QLOGIC_ISP2200: 276 return (1); 277 #endif 278 default: 279 return (0); 280 } 281 } 282 283 284 static void 285 isp_pci_attach(parent, self, aux) 286 struct device *parent, *self; 287 void *aux; 288 { 289 #ifdef DEBUG 290 static char oneshot = 1; 291 #endif 292 static char *nomem = "%s: no mem for sdparam table\n"; 293 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 294 struct pci_attach_args *pa = aux; 295 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 296 struct ispsoftc *isp = &pcs->pci_isp; 297 bus_space_tag_t st, iot, memt; 298 bus_space_handle_t sh, ioh, memh; 299 pci_intr_handle_t ih; 300 const char *intrstr; 301 int ioh_valid, memh_valid; 302 303 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 304 PCI_MAPREG_TYPE_IO, 0, 305 &iot, &ioh, NULL, NULL) == 0); 306 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 307 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 308 &memt, &memh, NULL, NULL) == 0); 309 310 if (memh_valid) { 311 st = memt; 312 sh = memh; 313 } else if (ioh_valid) { 314 st = iot; 315 sh = ioh; 316 } else { 317 printf(": unable to map device registers\n"); 318 return; 319 } 320 printf("\n"); 321 322 pcs->pci_st = st; 323 pcs->pci_sh = sh; 324 pcs->pci_dmat = pa->pa_dmat; 325 pcs->pci_pc = pa->pa_pc; 326 pcs->pci_tag = pa->pa_tag; 327 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 328 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 329 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 330 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 331 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 332 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 333 334 #ifndef ISP_DISABLE_1020_SUPPORT 335 if (pa->pa_id == PCI_QLOGIC_ISP) { 336 isp->isp_mdvec = &mdvec; 337 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 338 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 339 if (isp->isp_param == NULL) { 340 printf(nomem, isp->isp_name); 341 return; 342 } 343 bzero(isp->isp_param, sizeof (sdparam)); 344 } 345 #endif 346 #ifndef ISP_DISABLE_1080_SUPPORT 347 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 348 isp->isp_mdvec = &mdvec_1080; 349 isp->isp_type = ISP_HA_SCSI_1080; 350 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 351 if (isp->isp_param == NULL) { 352 printf(nomem, isp->isp_name); 353 return; 354 } 355 bzero(isp->isp_param, sizeof (sdparam)); 356 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 357 ISP1080_DMA_REGS_OFF; 358 } 359 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 360 isp->isp_mdvec = &mdvec_1080; 361 isp->isp_type = ISP_HA_SCSI_1240; 362 isp->isp_param = 363 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 364 if (isp->isp_param == NULL) { 365 printf(nomem, isp->isp_name); 366 return; 367 } 368 bzero(isp->isp_param, 2 * sizeof (sdparam)); 369 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 370 ISP1080_DMA_REGS_OFF; 371 } 372 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 373 isp->isp_mdvec = &mdvec_1080; 374 isp->isp_type = ISP_HA_SCSI_1280; 375 isp->isp_param = 376 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 377 if (isp->isp_param == NULL) { 378 printf(nomem, isp->isp_name); 379 return; 380 } 381 bzero(isp->isp_param, 2 * sizeof (sdparam)); 382 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 383 ISP1080_DMA_REGS_OFF; 384 } 385 #endif 386 #ifndef ISP_DISABLE_12160_SUPPORT 387 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 388 isp->isp_mdvec = &mdvec_12160; 389 isp->isp_type = ISP_HA_SCSI_12160; 390 isp->isp_param = 391 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 392 if (isp->isp_param == NULL) { 393 printf(nomem, isp->isp_name); 394 return; 395 } 396 bzero(isp->isp_param, 2 * sizeof (sdparam)); 397 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 398 ISP1080_DMA_REGS_OFF; 399 } 400 #endif 401 #ifndef ISP_DISABLE_2100_SUPPORT 402 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 403 isp->isp_mdvec = &mdvec_2100; 404 isp->isp_type = ISP_HA_FC_2100; 405 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 406 if (isp->isp_param == NULL) { 407 printf(nomem, isp->isp_name); 408 return; 409 } 410 bzero(isp->isp_param, sizeof (fcparam)); 411 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 412 PCI_MBOX_REGS2100_OFF; 413 if (rev < 3) { 414 /* 415 * XXX: Need to get the actual revision 416 * XXX: number of the 2100 FB. At any rate, 417 * XXX: lower cache line size for early revision 418 * XXX; boards. 419 */ 420 linesz = 1; 421 } 422 } 423 #endif 424 #ifndef ISP_DISABLE_2200_SUPPORT 425 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 426 isp->isp_mdvec = &mdvec_2200; 427 isp->isp_type = ISP_HA_FC_2200; 428 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 429 if (isp->isp_param == NULL) { 430 printf(nomem, isp->isp_name); 431 return; 432 } 433 bzero(isp->isp_param, sizeof (fcparam)); 434 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 435 PCI_MBOX_REGS2100_OFF; 436 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 437 } 438 #endif 439 /* 440 * Set up logging levels. 441 */ 442 #ifdef ISP_LOGDEFAULT 443 isp->isp_dblev = ISP_LOGDEFAULT; 444 #else 445 isp->isp_dblev = ISP_LOGCONFIG|ISP_LOGWARN|ISP_LOGERR; 446 #ifdef SCSIDEBUG 447 isp->isp_dblev |= ISP_LOGDEBUG1|ISP_LOGDEBUG2; 448 #endif 449 #ifdef DEBUG 450 isp->isp_dblev |= ISP_LOGDEBUG0; 451 #endif 452 #ifdef DIAGNOSTIC 453 isp->isp_dblev |= ISP_LOGINFO; 454 #endif 455 #endif 456 #ifdef DEBUG 457 if (oneshot) { 458 oneshot = 0; 459 isp_prt(isp, ISP_LOGCONFIG, vstring, 460 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 461 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 462 } 463 #endif 464 465 isp->isp_revision = rev; 466 467 /* 468 * Make sure that command register set sanely. 469 */ 470 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 471 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 472 473 /* 474 * Not so sure about these- but I think it's important that they get 475 * enabled...... 476 */ 477 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 478 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 479 480 /* 481 * Make sure that the latency timer, cache line size, 482 * and ROM is disabled. 483 */ 484 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 485 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 486 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 487 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 488 data |= (linesz << PCI_CACHELINE_SHIFT); 489 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 490 491 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 492 data &= ~1; 493 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 494 495 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 496 pa->pa_intrline, &ih)) { 497 printf("%s: couldn't map interrupt\n", isp->isp_name); 498 free(isp->isp_param, M_DEVBUF); 499 return; 500 } 501 intrstr = pci_intr_string(pa->pa_pc, ih); 502 if (intrstr == NULL) 503 intrstr = "<I dunno>"; 504 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 505 isp_pci_intr, isp); 506 if (pcs->pci_ih == NULL) { 507 printf("%s: couldn't establish interrupt at %s\n", 508 isp->isp_name, intrstr); 509 free(isp->isp_param, M_DEVBUF); 510 return; 511 } 512 513 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 514 515 if (IS_FC(isp)) { 516 DEFAULT_NODEWWN(isp) = 0x400000007F000002; 517 } 518 519 isp->isp_confopts = self->dv_cfdata->cf_flags; 520 ISP_LOCK(isp); 521 isp->isp_osinfo.no_mbox_ints = 1; 522 isp_reset(isp); 523 if (isp->isp_state != ISP_RESETSTATE) { 524 ISP_UNLOCK(isp); 525 free(isp->isp_param, M_DEVBUF); 526 return; 527 } 528 ENABLE_INTS(isp); 529 isp_init(isp); 530 if (isp->isp_state != ISP_INITSTATE) { 531 isp_uninit(isp); 532 ISP_UNLOCK(isp); 533 free(isp->isp_param, M_DEVBUF); 534 return; 535 } 536 /* 537 * Do platform attach. 538 */ 539 ISP_UNLOCK(isp); 540 isp_attach(isp); 541 if (isp->isp_state != ISP_RUNSTATE) { 542 ISP_LOCK(isp); 543 isp_uninit(isp); 544 free(isp->isp_param, M_DEVBUF); 545 ISP_UNLOCK(isp); 546 } 547 } 548 549 static u_int16_t 550 isp_pci_rd_reg(isp, regoff) 551 struct ispsoftc *isp; 552 int regoff; 553 { 554 u_int16_t rv; 555 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 556 int offset, oldconf = 0; 557 558 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 559 /* 560 * We will assume that someone has paused the RISC processor. 561 */ 562 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 563 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 564 delay(250); 565 } 566 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 567 offset += (regoff & 0xff); 568 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 569 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 570 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 571 delay(250); 572 } 573 return (rv); 574 } 575 576 static void 577 isp_pci_wr_reg(isp, regoff, val) 578 struct ispsoftc *isp; 579 int regoff; 580 u_int16_t val; 581 { 582 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 583 int offset, oldconf = 0; 584 585 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 586 /* 587 * We will assume that someone has paused the RISC processor. 588 */ 589 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 590 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 591 delay(250); 592 } 593 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 594 offset += (regoff & 0xff); 595 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 596 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 597 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 598 delay(250); 599 } 600 } 601 602 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 603 static u_int16_t 604 isp_pci_rd_reg_1080(isp, regoff) 605 struct ispsoftc *isp; 606 int regoff; 607 { 608 u_int16_t rv, oc = 0; 609 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 610 int offset; 611 612 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 613 u_int16_t tc; 614 /* 615 * We will assume that someone has paused the RISC processor. 616 */ 617 oc = isp_pci_rd_reg(isp, BIU_CONF1); 618 tc = oc & ~BIU_PCI1080_CONF1_DMA; 619 if (IS_1280(isp)) { 620 if (regoff & SXP_BANK1_SELECT) 621 tc |= BIU_PCI1080_CONF1_SXP0; 622 else 623 tc |= BIU_PCI1080_CONF1_SXP1; 624 } else { 625 tc |= BIU_PCI1080_CONF1_SXP0; 626 } 627 isp_pci_wr_reg(isp, BIU_CONF1, tc); 628 delay(250); 629 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 630 oc = isp_pci_rd_reg(isp, BIU_CONF1); 631 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 632 delay(250); 633 } 634 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 635 offset += (regoff & 0xff); 636 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 637 /* 638 * Okay, because BIU_CONF1 is always nonzero 639 */ 640 if (oc) { 641 isp_pci_wr_reg(isp, BIU_CONF1, oc); 642 delay(250); 643 } 644 return (rv); 645 } 646 647 static void 648 isp_pci_wr_reg_1080(isp, regoff, val) 649 struct ispsoftc *isp; 650 int regoff; 651 u_int16_t val; 652 { 653 u_int16_t oc = 0; 654 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 655 int offset; 656 657 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 658 u_int16_t tc; 659 /* 660 * We will assume that someone has paused the RISC processor. 661 */ 662 oc = isp_pci_rd_reg(isp, BIU_CONF1); 663 tc = oc & ~BIU_PCI1080_CONF1_DMA; 664 if (IS_1280(isp)) { 665 if (regoff & SXP_BANK1_SELECT) 666 tc |= BIU_PCI1080_CONF1_SXP0; 667 else 668 tc |= BIU_PCI1080_CONF1_SXP1; 669 } else { 670 tc |= BIU_PCI1080_CONF1_SXP0; 671 } 672 isp_pci_wr_reg(isp, BIU_CONF1, tc); 673 delay(250); 674 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 675 oc = isp_pci_rd_reg(isp, BIU_CONF1); 676 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 677 delay(250); 678 } 679 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 680 offset += (regoff & 0xff); 681 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 682 /* 683 * Okay, because BIU_CONF1 is always nonzero 684 */ 685 if (oc) { 686 isp_pci_wr_reg(isp, BIU_CONF1, oc); 687 delay(250); 688 } 689 } 690 #endif 691 692 static int 693 isp_pci_mbxdma(isp) 694 struct ispsoftc *isp; 695 { 696 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 697 bus_dma_tag_t dmat = pcs->pci_dmat; 698 bus_dma_segment_t sg; 699 bus_size_t len; 700 fcparam *fcp; 701 int rs, i; 702 703 if (isp->isp_rquest_dma) /* been here before? */ 704 return (0); 705 706 len = isp->isp_maxcmds * sizeof (XS_T); 707 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 708 if (isp->isp_xflist == NULL) { 709 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 710 return (1); 711 } 712 bzero(isp->isp_xflist, len); 713 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 714 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 715 if (pcs->pci_xfer_dmap == NULL) { 716 free(isp->isp_xflist, M_DEVBUF); 717 isp->isp_xflist = NULL; 718 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array"); 719 return (1); 720 } 721 for (i = 0; i < isp->isp_maxcmds; i++) { 722 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / NBPG) + 1, 723 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 724 isp_prt(isp, ISP_LOGERR, "cannot create dma maps"); 725 break; 726 } 727 } 728 if (i < isp->isp_maxcmds) { 729 while (--i >= 0) { 730 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 731 } 732 free(isp->isp_xflist, M_DEVBUF); 733 free(pcs->pci_xfer_dmap, M_DEVBUF); 734 isp->isp_xflist = NULL; 735 pcs->pci_xfer_dmap = NULL; 736 return (1); 737 } 738 739 /* 740 * Allocate and map the request queue. 741 */ 742 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 743 if (bus_dmamem_alloc(dmat, len, NBPG, 0, &sg, 1, &rs, BUS_DMA_NOWAIT) || 744 bus_dmamem_map(pcs->pci_dmat, &sg, rs, len, 745 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 746 goto dmafail; 747 } 748 749 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 750 &pcs->pci_rquest_dmap) || bus_dmamap_load(dmat, 751 pcs->pci_rquest_dmap, (caddr_t)isp->isp_rquest, len, NULL, 752 BUS_DMA_NOWAIT)) { 753 goto dmafail; 754 } 755 756 isp->isp_rquest_dma = pcs->pci_rquest_dmap->dm_segs[0].ds_addr; 757 758 /* 759 * Allocate and map the result queue. 760 */ 761 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 762 if (bus_dmamem_alloc(dmat, len, NBPG, 0, &sg, 1, &rs, BUS_DMA_NOWAIT) || 763 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 764 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 765 goto dmafail; 766 } 767 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 768 &pcs->pci_result_dmap) || bus_dmamap_load(pcs->pci_dmat, 769 pcs->pci_result_dmap, (caddr_t)isp->isp_result, len, NULL, 770 BUS_DMA_NOWAIT)) { 771 goto dmafail; 772 } 773 isp->isp_result_dma = pcs->pci_result_dmap->dm_segs[0].ds_addr; 774 775 if (IS_SCSI(isp)) { 776 return (0); 777 } 778 779 fcp = isp->isp_param; 780 len = ISP2100_SCRLEN; 781 if (bus_dmamem_alloc(dmat, len, NBPG, 0, &sg, 1, &rs, BUS_DMA_NOWAIT) || 782 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 783 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 784 goto dmafail; 785 } 786 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 787 &pcs->pci_scratch_dmap) || bus_dmamap_load(dmat, 788 pcs->pci_scratch_dmap, (caddr_t)fcp->isp_scratch, len, NULL, 789 BUS_DMA_NOWAIT)) { 790 goto dmafail; 791 } 792 fcp->isp_scdma = pcs->pci_scratch_dmap->dm_segs[0].ds_addr; 793 return (0); 794 dmafail: 795 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure"); 796 for (i = 0; i < isp->isp_maxcmds; i++) { 797 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 798 } 799 free(isp->isp_xflist, M_DEVBUF); 800 free(pcs->pci_xfer_dmap, M_DEVBUF); 801 isp->isp_xflist = NULL; 802 pcs->pci_xfer_dmap = NULL; 803 return (1); 804 } 805 806 static int 807 isp_pci_dmasetup(isp, xs, rq, iptrp, optr) 808 struct ispsoftc *isp; 809 struct scsipi_xfer *xs; 810 ispreq_t *rq; 811 u_int16_t *iptrp; 812 u_int16_t optr; 813 { 814 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 815 bus_dmamap_t dmap; 816 ispcontreq_t *crq; 817 int segcnt, seg, error, ovseg, seglim, drq; 818 819 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 820 821 if (xs->datalen == 0) { 822 rq->req_seg_count = 1; 823 goto mbxsync; 824 } 825 if (xs->xs_control & XS_CTL_DATA_IN) { 826 drq = REQFLAG_DATA_IN; 827 } else { 828 drq = REQFLAG_DATA_OUT; 829 } 830 831 if (IS_FC(isp)) { 832 seglim = ISP_RQDSEG_T2; 833 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 834 ((ispreqt2_t *)rq)->req_flags |= drq; 835 } else { 836 rq->req_flags |= drq; 837 if (XS_CDBLEN(xs) > 12) { 838 seglim = 0; 839 } else { 840 seglim = ISP_RQDSEG; 841 } 842 } 843 error = bus_dmamap_load(pcs->pci_dmat, dmap, xs->data, xs->datalen, 844 NULL, xs->xs_control & XS_CTL_NOSLEEP ? 845 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 846 if (error) { 847 XS_SETERR(xs, HBA_BOTCH); 848 return (CMD_COMPLETE); 849 } 850 851 segcnt = dmap->dm_nsegs; 852 853 for (seg = 0, rq->req_seg_count = 0; 854 seg < segcnt && rq->req_seg_count < seglim; 855 seg++, rq->req_seg_count++) { 856 if (IS_FC(isp)) { 857 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 858 rq2->req_dataseg[rq2->req_seg_count].ds_count = 859 dmap->dm_segs[seg].ds_len; 860 rq2->req_dataseg[rq2->req_seg_count].ds_base = 861 dmap->dm_segs[seg].ds_addr; 862 } else { 863 rq->req_dataseg[rq->req_seg_count].ds_count = 864 dmap->dm_segs[seg].ds_len; 865 rq->req_dataseg[rq->req_seg_count].ds_base = 866 dmap->dm_segs[seg].ds_addr; 867 } 868 } 869 870 if (seg == segcnt) 871 goto dmasync; 872 873 do { 874 crq = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp); 875 *iptrp = ISP_NXT_QENTRY(*iptrp, RQUEST_QUEUE_LEN(isp)); 876 if (*iptrp == optr) { 877 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 878 bus_dmamap_unload(pcs->pci_dmat, dmap); 879 XS_SETERR(xs, HBA_BOTCH); 880 return (CMD_EAGAIN); 881 } 882 rq->req_header.rqs_entry_count++; 883 bzero((void *)crq, sizeof (*crq)); 884 crq->req_header.rqs_entry_count = 1; 885 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 886 887 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 888 rq->req_seg_count++, seg++, ovseg++) { 889 crq->req_dataseg[ovseg].ds_count = 890 dmap->dm_segs[seg].ds_len; 891 crq->req_dataseg[ovseg].ds_base = 892 dmap->dm_segs[seg].ds_addr; 893 } 894 } while (seg < segcnt); 895 896 dmasync: 897 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 898 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 899 BUS_DMASYNC_PREWRITE); 900 901 mbxsync: 902 ISP_SWIZZLE_REQUEST(isp, rq); 903 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_rquest_dmap, 0, 904 pcs->pci_rquest_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 905 return (CMD_QUEUED); 906 } 907 908 static int 909 isp_pci_intr(arg) 910 void *arg; 911 { 912 int rv; 913 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)arg; 914 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_result_dmap, 0, 915 pcs->pci_result_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 916 pcs->pci_isp.isp_osinfo.onintstack = 1; 917 rv = isp_intr(arg); 918 pcs->pci_isp.isp_osinfo.onintstack = 0; 919 return (rv); 920 } 921 922 static void 923 isp_pci_dmateardown(isp, xs, handle) 924 struct ispsoftc *isp; 925 struct scsipi_xfer *xs; 926 u_int32_t handle; 927 { 928 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 929 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 930 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 931 xs->xs_control & XS_CTL_DATA_IN ? 932 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 933 bus_dmamap_unload(pcs->pci_dmat, dmap); 934 } 935 936 static void 937 isp_pci_reset1(isp) 938 struct ispsoftc *isp; 939 { 940 /* Make sure the BIOS is disabled */ 941 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 942 } 943 944 static void 945 isp_pci_dumpregs(isp, msg) 946 struct ispsoftc *isp; 947 const char *msg; 948 { 949 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 950 if (msg) 951 printf("%s: %s\n", isp->isp_name, msg); 952 if (IS_SCSI(isp)) 953 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 954 else 955 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 956 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 957 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 958 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 959 960 961 if (IS_SCSI(isp)) { 962 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 963 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 964 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 965 ISP_READ(isp, CDMA_FIFO_STS)); 966 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 967 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 968 ISP_READ(isp, DDMA_FIFO_STS)); 969 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 970 ISP_READ(isp, SXP_INTERRUPT), 971 ISP_READ(isp, SXP_GROSS_ERR), 972 ISP_READ(isp, SXP_PINS_CTRL)); 973 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 974 } 975 printf(" mbox regs: %x %x %x %x %x\n", 976 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 977 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 978 ISP_READ(isp, OUTMAILBOX4)); 979 printf(" PCI Status Command/Status=%x\n", 980 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 981 } 982
Indexes created Sat Sep 27 14:09:57 GMT 2025