isp_pci.c revision 1.64
1 /* $NetBSD: isp_pci.c,v 1.64 2000/12/28 22:59:14 sommerfeld Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 * Matthew Jacob (mjacob (at) nas.nasa.gov) 33 */ 34 /* 35 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 #include <dev/ic/isp_netbsd.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 #include <uvm/uvm_extern.h> 66 67 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int)); 68 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t)); 69 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 70 static u_int16_t isp_pci_rd_reg_1080 __P((struct ispsoftc *, int)); 71 static void isp_pci_wr_reg_1080 __P((struct ispsoftc *, int, u_int16_t)); 72 #endif 73 static int isp_pci_mbxdma __P((struct ispsoftc *)); 74 static int isp_pci_dmasetup __P((struct ispsoftc *, struct scsipi_xfer *, 75 ispreq_t *, u_int16_t *, u_int16_t)); 76 static void isp_pci_dmateardown __P((struct ispsoftc *, struct scsipi_xfer *, 77 u_int32_t)); 78 static void isp_pci_reset1 __P((struct ispsoftc *)); 79 static void isp_pci_dumpregs __P((struct ispsoftc *, const char *)); 80 static int isp_pci_intr __P((void *)); 81 82 #if defined(ISP_DISABLE_1020_SUPPORT) 83 #define ISP_1040_RISC_CODE NULL 84 #else 85 #define ISP_1040_RISC_CODE isp_1040_risc_code 86 #include <dev/microcode/isp/asm_1040.h> 87 #endif 88 89 #if defined(ISP_DISABLE_1080_SUPPORT) 90 #define ISP_1080_RISC_CODE NULL 91 #else 92 #define ISP_1080_RISC_CODE isp_1080_risc_code 93 #include <dev/microcode/isp/asm_1080.h> 94 #endif 95 96 #if defined(ISP_DISABLE_12160_SUPPORT) 97 #define ISP_12160_RISC_CODE NULL 98 #else 99 #define ISP_12160_RISC_CODE isp_12160_risc_code 100 #include <dev/microcode/isp/asm_12160.h> 101 #endif 102 103 #if defined(ISP_DISABLE_2100_SUPPORT) 104 #define ISP_2100_RISC_CODE NULL 105 #else 106 #define ISP_2100_RISC_CODE isp_2100_risc_code 107 #include <dev/microcode/isp/asm_2100.h> 108 #endif 109 110 #if defined(ISP_DISABLE_2200_SUPPORT) 111 #define ISP_2200_RISC_CODE NULL 112 #else 113 #define ISP_2200_RISC_CODE isp_2200_risc_code 114 #include <dev/microcode/isp/asm_2200.h> 115 #endif 116 117 #ifndef ISP_DISABLE_1020_SUPPORT 118 static struct ispmdvec mdvec = { 119 isp_pci_rd_reg, 120 isp_pci_wr_reg, 121 isp_pci_mbxdma, 122 isp_pci_dmasetup, 123 isp_pci_dmateardown, 124 NULL, 125 isp_pci_reset1, 126 isp_pci_dumpregs, 127 ISP_1040_RISC_CODE, 128 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 129 }; 130 #endif 131 132 #ifndef ISP_DISABLE_1080_SUPPORT 133 static struct ispmdvec mdvec_1080 = { 134 isp_pci_rd_reg_1080, 135 isp_pci_wr_reg_1080, 136 isp_pci_mbxdma, 137 isp_pci_dmasetup, 138 isp_pci_dmateardown, 139 NULL, 140 isp_pci_reset1, 141 isp_pci_dumpregs, 142 ISP_1080_RISC_CODE, 143 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 144 }; 145 #endif 146 147 #ifndef ISP_DISABLE_12160_SUPPORT 148 static struct ispmdvec mdvec_12160 = { 149 isp_pci_rd_reg_1080, 150 isp_pci_wr_reg_1080, 151 isp_pci_mbxdma, 152 isp_pci_dmasetup, 153 isp_pci_dmateardown, 154 NULL, 155 isp_pci_reset1, 156 isp_pci_dumpregs, 157 ISP_12160_RISC_CODE, 158 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 159 }; 160 #endif 161 162 #ifndef ISP_DISABLE_2100_SUPPORT 163 static struct ispmdvec mdvec_2100 = { 164 isp_pci_rd_reg, 165 isp_pci_wr_reg, 166 isp_pci_mbxdma, 167 isp_pci_dmasetup, 168 isp_pci_dmateardown, 169 NULL, 170 isp_pci_reset1, 171 isp_pci_dumpregs, 172 ISP_2100_RISC_CODE 173 }; 174 #endif 175 176 #ifndef ISP_DISABLE_2200_SUPPORT 177 static struct ispmdvec mdvec_2200 = { 178 isp_pci_rd_reg, 179 isp_pci_wr_reg, 180 isp_pci_mbxdma, 181 isp_pci_dmasetup, 182 isp_pci_dmateardown, 183 NULL, 184 isp_pci_reset1, 185 isp_pci_dumpregs, 186 ISP_2200_RISC_CODE 187 }; 188 #endif 189 190 #ifndef PCI_VENDOR_QLOGIC 191 #define PCI_VENDOR_QLOGIC 0x1077 192 #endif 193 194 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 195 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 196 #endif 197 198 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 199 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 200 #endif 201 202 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 203 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 204 #endif 205 206 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 207 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 208 #endif 209 210 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 211 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 212 #endif 213 214 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 215 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 216 #endif 217 218 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 219 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 220 #endif 221 222 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 223 224 #define PCI_QLOGIC_ISP1080 \ 225 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 226 227 #define PCI_QLOGIC_ISP1240 \ 228 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 229 230 #define PCI_QLOGIC_ISP1280 \ 231 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 232 233 #define PCI_QLOGIC_ISP12160 \ 234 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 235 236 #define PCI_QLOGIC_ISP2100 \ 237 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 238 239 #define PCI_QLOGIC_ISP2200 \ 240 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 241 242 #define IO_MAP_REG 0x10 243 #define MEM_MAP_REG 0x14 244 #define PCIR_ROMADDR 0x30 245 246 #define PCI_DFLT_LTNCY 0x40 247 #define PCI_DFLT_LNSZ 0x10 248 249 250 static int isp_pci_probe __P((struct device *, struct cfdata *, void *)); 251 static void isp_pci_attach __P((struct device *, struct device *, void *)); 252 253 struct isp_pcisoftc { 254 struct ispsoftc pci_isp; 255 pci_chipset_tag_t pci_pc; 256 pcitag_t pci_tag; 257 bus_space_tag_t pci_st; 258 bus_space_handle_t pci_sh; 259 bus_dma_tag_t pci_dmat; 260 bus_dmamap_t pci_scratch_dmap; /* for fcp only */ 261 bus_dmamap_t pci_rquest_dmap; 262 bus_dmamap_t pci_result_dmap; 263 bus_dmamap_t *pci_xfer_dmap; 264 void * pci_ih; 265 int16_t pci_poff[_NREG_BLKS]; 266 }; 267 268 struct cfattach isp_pci_ca = { 269 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach 270 }; 271 272 #ifdef DEBUG 273 const char vstring[] = 274 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 275 #endif 276 277 static int 278 isp_pci_probe(parent, match, aux) 279 struct device *parent; 280 struct cfdata *match; 281 void *aux; 282 { 283 struct pci_attach_args *pa = aux; 284 switch (pa->pa_id) { 285 #ifndef ISP_DISABLE_1020_SUPPORT 286 case PCI_QLOGIC_ISP: 287 return (1); 288 #endif 289 #ifndef ISP_DISABLE_1080_SUPPORT 290 case PCI_QLOGIC_ISP1080: 291 case PCI_QLOGIC_ISP1240: 292 case PCI_QLOGIC_ISP1280: 293 return (1); 294 #endif 295 #ifndef ISP_DISABLE_12160_SUPPORT 296 case PCI_QLOGIC_ISP12160: 297 return (1); 298 #endif 299 #ifndef ISP_DISABLE_2100_SUPPORT 300 case PCI_QLOGIC_ISP2100: 301 return (1); 302 #endif 303 #ifndef ISP_DISABLE_2200_SUPPORT 304 case PCI_QLOGIC_ISP2200: 305 return (1); 306 #endif 307 default: 308 return (0); 309 } 310 } 311 312 313 static void 314 isp_pci_attach(parent, self, aux) 315 struct device *parent, *self; 316 void *aux; 317 { 318 #ifdef DEBUG 319 static char oneshot = 1; 320 #endif 321 static const char nomem[] = "%s: no mem for sdparam table\n"; 322 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 323 struct pci_attach_args *pa = aux; 324 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 325 struct ispsoftc *isp = &pcs->pci_isp; 326 bus_space_tag_t st, iot, memt; 327 bus_space_handle_t sh, ioh, memh; 328 pci_intr_handle_t ih; 329 const char *intrstr; 330 int ioh_valid, memh_valid; 331 332 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 333 PCI_MAPREG_TYPE_IO, 0, 334 &iot, &ioh, NULL, NULL) == 0); 335 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 336 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 337 &memt, &memh, NULL, NULL) == 0); 338 339 if (memh_valid) { 340 st = memt; 341 sh = memh; 342 } else if (ioh_valid) { 343 st = iot; 344 sh = ioh; 345 } else { 346 printf(": unable to map device registers\n"); 347 return; 348 } 349 printf("\n"); 350 351 pcs->pci_st = st; 352 pcs->pci_sh = sh; 353 pcs->pci_dmat = pa->pa_dmat; 354 pcs->pci_pc = pa->pa_pc; 355 pcs->pci_tag = pa->pa_tag; 356 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 357 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 358 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 359 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 360 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 361 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 362 363 #ifndef ISP_DISABLE_1020_SUPPORT 364 if (pa->pa_id == PCI_QLOGIC_ISP) { 365 isp->isp_mdvec = &mdvec; 366 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 367 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 368 if (isp->isp_param == NULL) { 369 printf(nomem, isp->isp_name); 370 return; 371 } 372 bzero(isp->isp_param, sizeof (sdparam)); 373 } 374 #endif 375 #ifndef ISP_DISABLE_1080_SUPPORT 376 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 377 isp->isp_mdvec = &mdvec_1080; 378 isp->isp_type = ISP_HA_SCSI_1080; 379 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 380 if (isp->isp_param == NULL) { 381 printf(nomem, isp->isp_name); 382 return; 383 } 384 bzero(isp->isp_param, sizeof (sdparam)); 385 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 386 ISP1080_DMA_REGS_OFF; 387 } 388 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 389 isp->isp_mdvec = &mdvec_1080; 390 isp->isp_type = ISP_HA_SCSI_1240; 391 isp->isp_param = 392 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 393 if (isp->isp_param == NULL) { 394 printf(nomem, isp->isp_name); 395 return; 396 } 397 bzero(isp->isp_param, 2 * sizeof (sdparam)); 398 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 399 ISP1080_DMA_REGS_OFF; 400 } 401 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 402 isp->isp_mdvec = &mdvec_1080; 403 isp->isp_type = ISP_HA_SCSI_1280; 404 isp->isp_param = 405 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 406 if (isp->isp_param == NULL) { 407 printf(nomem, isp->isp_name); 408 return; 409 } 410 bzero(isp->isp_param, 2 * sizeof (sdparam)); 411 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 412 ISP1080_DMA_REGS_OFF; 413 } 414 #endif 415 #ifndef ISP_DISABLE_12160_SUPPORT 416 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 417 isp->isp_mdvec = &mdvec_12160; 418 isp->isp_type = ISP_HA_SCSI_12160; 419 isp->isp_param = 420 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 421 if (isp->isp_param == NULL) { 422 printf(nomem, isp->isp_name); 423 return; 424 } 425 bzero(isp->isp_param, 2 * sizeof (sdparam)); 426 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 427 ISP1080_DMA_REGS_OFF; 428 } 429 #endif 430 #ifndef ISP_DISABLE_2100_SUPPORT 431 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 432 isp->isp_mdvec = &mdvec_2100; 433 isp->isp_type = ISP_HA_FC_2100; 434 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 435 if (isp->isp_param == NULL) { 436 printf(nomem, isp->isp_name); 437 return; 438 } 439 bzero(isp->isp_param, sizeof (fcparam)); 440 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 441 PCI_MBOX_REGS2100_OFF; 442 if (rev < 3) { 443 /* 444 * XXX: Need to get the actual revision 445 * XXX: number of the 2100 FB. At any rate, 446 * XXX: lower cache line size for early revision 447 * XXX; boards. 448 */ 449 linesz = 1; 450 } 451 } 452 #endif 453 #ifndef ISP_DISABLE_2200_SUPPORT 454 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 455 isp->isp_mdvec = &mdvec_2200; 456 isp->isp_type = ISP_HA_FC_2200; 457 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 458 if (isp->isp_param == NULL) { 459 printf(nomem, isp->isp_name); 460 return; 461 } 462 bzero(isp->isp_param, sizeof (fcparam)); 463 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 464 PCI_MBOX_REGS2100_OFF; 465 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 466 } 467 #endif 468 /* 469 * Set up logging levels. 470 */ 471 #ifdef ISP_LOGDEFAULT 472 isp->isp_dblev = ISP_LOGDEFAULT; 473 #else 474 isp->isp_dblev = ISP_LOGCONFIG|ISP_LOGWARN|ISP_LOGERR; 475 #ifdef SCSIDEBUG 476 isp->isp_dblev |= ISP_LOGDEBUG1|ISP_LOGDEBUG2; 477 #endif 478 #ifdef DEBUG 479 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGINFO; 480 #endif 481 #endif 482 483 #ifdef DEBUG 484 if (oneshot) { 485 oneshot = 0; 486 isp_prt(isp, ISP_LOGCONFIG, vstring, 487 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 488 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 489 } 490 #endif 491 492 isp->isp_revision = rev; 493 494 /* 495 * Make sure that command register set sanely. 496 */ 497 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 498 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 499 500 /* 501 * Not so sure about these- but I think it's important that they get 502 * enabled...... 503 */ 504 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 505 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 506 507 /* 508 * Make sure that the latency timer, cache line size, 509 * and ROM is disabled. 510 */ 511 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 512 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 513 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 514 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 515 data |= (linesz << PCI_CACHELINE_SHIFT); 516 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 517 518 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 519 data &= ~1; 520 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 521 522 if (pci_intr_map(pa, &ih)) { 523 printf("%s: couldn't map interrupt\n", isp->isp_name); 524 free(isp->isp_param, M_DEVBUF); 525 return; 526 } 527 intrstr = pci_intr_string(pa->pa_pc, ih); 528 if (intrstr == NULL) 529 intrstr = "<I dunno>"; 530 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 531 isp_pci_intr, isp); 532 if (pcs->pci_ih == NULL) { 533 printf("%s: couldn't establish interrupt at %s\n", 534 isp->isp_name, intrstr); 535 free(isp->isp_param, M_DEVBUF); 536 return; 537 } 538 539 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 540 541 if (IS_FC(isp)) { 542 DEFAULT_NODEWWN(isp) = 0x400000007F000002; 543 DEFAULT_PORTWWN(isp) = 0x400000007F000002; 544 } 545 546 isp->isp_confopts = self->dv_cfdata->cf_flags; 547 ISP_LOCK(isp); 548 isp->isp_osinfo.no_mbox_ints = 1; 549 isp_reset(isp); 550 if (isp->isp_state != ISP_RESETSTATE) { 551 ISP_UNLOCK(isp); 552 free(isp->isp_param, M_DEVBUF); 553 return; 554 } 555 ENABLE_INTS(isp); 556 isp_init(isp); 557 if (isp->isp_state != ISP_INITSTATE) { 558 isp_uninit(isp); 559 ISP_UNLOCK(isp); 560 free(isp->isp_param, M_DEVBUF); 561 return; 562 } 563 /* 564 * Do platform attach. 565 */ 566 ISP_UNLOCK(isp); 567 isp_attach(isp); 568 if (isp->isp_state != ISP_RUNSTATE) { 569 ISP_LOCK(isp); 570 isp_uninit(isp); 571 free(isp->isp_param, M_DEVBUF); 572 ISP_UNLOCK(isp); 573 } 574 } 575 576 static u_int16_t 577 isp_pci_rd_reg(isp, regoff) 578 struct ispsoftc *isp; 579 int regoff; 580 { 581 u_int16_t rv; 582 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 583 int offset, oldconf = 0; 584 585 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 586 /* 587 * We will assume that someone has paused the RISC processor. 588 */ 589 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 590 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 591 delay(250); 592 } 593 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 594 offset += (regoff & 0xff); 595 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 596 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 597 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 598 delay(250); 599 } 600 return (rv); 601 } 602 603 static void 604 isp_pci_wr_reg(isp, regoff, val) 605 struct ispsoftc *isp; 606 int regoff; 607 u_int16_t val; 608 { 609 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 610 int offset, oldconf = 0; 611 612 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 613 /* 614 * We will assume that someone has paused the RISC processor. 615 */ 616 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 617 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 618 delay(250); 619 } 620 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 621 offset += (regoff & 0xff); 622 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 623 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 624 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 625 delay(250); 626 } 627 } 628 629 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 630 static u_int16_t 631 isp_pci_rd_reg_1080(isp, regoff) 632 struct ispsoftc *isp; 633 int regoff; 634 { 635 u_int16_t rv, oc = 0; 636 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 637 int offset; 638 639 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 640 u_int16_t tc; 641 /* 642 * We will assume that someone has paused the RISC processor. 643 */ 644 oc = isp_pci_rd_reg(isp, BIU_CONF1); 645 tc = oc & ~BIU_PCI1080_CONF1_DMA; 646 if (IS_1280(isp)) { 647 if (regoff & SXP_BANK1_SELECT) 648 tc |= BIU_PCI1080_CONF1_SXP0; 649 else 650 tc |= BIU_PCI1080_CONF1_SXP1; 651 } else { 652 tc |= BIU_PCI1080_CONF1_SXP0; 653 } 654 isp_pci_wr_reg(isp, BIU_CONF1, tc); 655 delay(250); 656 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 657 oc = isp_pci_rd_reg(isp, BIU_CONF1); 658 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 659 delay(250); 660 } 661 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 662 offset += (regoff & 0xff); 663 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 664 /* 665 * Okay, because BIU_CONF1 is always nonzero 666 */ 667 if (oc) { 668 isp_pci_wr_reg(isp, BIU_CONF1, oc); 669 delay(250); 670 } 671 return (rv); 672 } 673 674 static void 675 isp_pci_wr_reg_1080(isp, regoff, val) 676 struct ispsoftc *isp; 677 int regoff; 678 u_int16_t val; 679 { 680 u_int16_t oc = 0; 681 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 682 int offset; 683 684 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 685 u_int16_t tc; 686 /* 687 * We will assume that someone has paused the RISC processor. 688 */ 689 oc = isp_pci_rd_reg(isp, BIU_CONF1); 690 tc = oc & ~BIU_PCI1080_CONF1_DMA; 691 if (IS_1280(isp)) { 692 if (regoff & SXP_BANK1_SELECT) 693 tc |= BIU_PCI1080_CONF1_SXP0; 694 else 695 tc |= BIU_PCI1080_CONF1_SXP1; 696 } else { 697 tc |= BIU_PCI1080_CONF1_SXP0; 698 } 699 isp_pci_wr_reg(isp, BIU_CONF1, tc); 700 delay(250); 701 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 702 oc = isp_pci_rd_reg(isp, BIU_CONF1); 703 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 704 delay(250); 705 } 706 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 707 offset += (regoff & 0xff); 708 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 709 /* 710 * Okay, because BIU_CONF1 is always nonzero 711 */ 712 if (oc) { 713 isp_pci_wr_reg(isp, BIU_CONF1, oc); 714 delay(250); 715 } 716 } 717 #endif 718 719 static int 720 isp_pci_mbxdma(isp) 721 struct ispsoftc *isp; 722 { 723 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 724 bus_dma_tag_t dmat = pcs->pci_dmat; 725 bus_dma_segment_t sg; 726 bus_size_t len; 727 fcparam *fcp; 728 int rs, i; 729 730 if (isp->isp_rquest_dma) /* been here before? */ 731 return (0); 732 733 len = isp->isp_maxcmds * sizeof (XS_T); 734 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 735 if (isp->isp_xflist == NULL) { 736 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 737 return (1); 738 } 739 bzero(isp->isp_xflist, len); 740 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 741 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 742 if (pcs->pci_xfer_dmap == NULL) { 743 free(isp->isp_xflist, M_DEVBUF); 744 isp->isp_xflist = NULL; 745 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array"); 746 return (1); 747 } 748 for (i = 0; i < isp->isp_maxcmds; i++) { 749 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 750 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 751 isp_prt(isp, ISP_LOGERR, "cannot create dma maps"); 752 break; 753 } 754 } 755 if (i < isp->isp_maxcmds) { 756 while (--i >= 0) { 757 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 758 } 759 free(isp->isp_xflist, M_DEVBUF); 760 free(pcs->pci_xfer_dmap, M_DEVBUF); 761 isp->isp_xflist = NULL; 762 pcs->pci_xfer_dmap = NULL; 763 return (1); 764 } 765 766 /* 767 * Allocate and map the request queue. 768 */ 769 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 770 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 771 BUS_DMA_NOWAIT) || 772 bus_dmamem_map(pcs->pci_dmat, &sg, rs, len, 773 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 774 goto dmafail; 775 } 776 777 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 778 &pcs->pci_rquest_dmap) || bus_dmamap_load(dmat, 779 pcs->pci_rquest_dmap, (caddr_t)isp->isp_rquest, len, NULL, 780 BUS_DMA_NOWAIT)) { 781 goto dmafail; 782 } 783 784 isp->isp_rquest_dma = pcs->pci_rquest_dmap->dm_segs[0].ds_addr; 785 786 /* 787 * Allocate and map the result queue. 788 */ 789 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 790 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 791 BUS_DMA_NOWAIT) || 792 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 793 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 794 goto dmafail; 795 } 796 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 797 &pcs->pci_result_dmap) || bus_dmamap_load(pcs->pci_dmat, 798 pcs->pci_result_dmap, (caddr_t)isp->isp_result, len, NULL, 799 BUS_DMA_NOWAIT)) { 800 goto dmafail; 801 } 802 isp->isp_result_dma = pcs->pci_result_dmap->dm_segs[0].ds_addr; 803 804 if (IS_SCSI(isp)) { 805 return (0); 806 } 807 808 fcp = isp->isp_param; 809 len = ISP2100_SCRLEN; 810 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 811 BUS_DMA_NOWAIT) || 812 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 813 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 814 goto dmafail; 815 } 816 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 817 &pcs->pci_scratch_dmap) || bus_dmamap_load(dmat, 818 pcs->pci_scratch_dmap, (caddr_t)fcp->isp_scratch, len, NULL, 819 BUS_DMA_NOWAIT)) { 820 goto dmafail; 821 } 822 fcp->isp_scdma = pcs->pci_scratch_dmap->dm_segs[0].ds_addr; 823 return (0); 824 dmafail: 825 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure"); 826 for (i = 0; i < isp->isp_maxcmds; i++) { 827 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 828 } 829 free(isp->isp_xflist, M_DEVBUF); 830 free(pcs->pci_xfer_dmap, M_DEVBUF); 831 isp->isp_xflist = NULL; 832 pcs->pci_xfer_dmap = NULL; 833 return (1); 834 } 835 836 static int 837 isp_pci_dmasetup(isp, xs, rq, iptrp, optr) 838 struct ispsoftc *isp; 839 struct scsipi_xfer *xs; 840 ispreq_t *rq; 841 u_int16_t *iptrp; 842 u_int16_t optr; 843 { 844 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 845 bus_dmamap_t dmap; 846 ispcontreq_t *crq; 847 int segcnt, seg, error, ovseg, seglim, drq; 848 849 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 850 851 if (xs->datalen == 0) { 852 rq->req_seg_count = 1; 853 goto mbxsync; 854 } 855 if (xs->xs_control & XS_CTL_DATA_IN) { 856 drq = REQFLAG_DATA_IN; 857 } else { 858 drq = REQFLAG_DATA_OUT; 859 } 860 861 if (IS_FC(isp)) { 862 seglim = ISP_RQDSEG_T2; 863 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 864 ((ispreqt2_t *)rq)->req_flags |= drq; 865 } else { 866 rq->req_flags |= drq; 867 if (XS_CDBLEN(xs) > 12) { 868 seglim = 0; 869 } else { 870 seglim = ISP_RQDSEG; 871 } 872 } 873 error = bus_dmamap_load(pcs->pci_dmat, dmap, xs->data, xs->datalen, 874 NULL, xs->xs_control & XS_CTL_NOSLEEP ? 875 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 876 if (error) { 877 XS_SETERR(xs, HBA_BOTCH); 878 return (CMD_COMPLETE); 879 } 880 881 segcnt = dmap->dm_nsegs; 882 883 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 884 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 885 "write from", xs->data, segcnt); 886 887 for (seg = 0, rq->req_seg_count = 0; 888 seglim && seg < segcnt && rq->req_seg_count < seglim; 889 seg++, rq->req_seg_count++) { 890 if (IS_FC(isp)) { 891 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 892 #if _BYTE_ORDER == _BIG_ENDIAN 893 rq2->req_dataseg[rq2->req_seg_count].ds_count = 894 bswap32(dmap->dm_segs[seg].ds_len); 895 rq2->req_dataseg[rq2->req_seg_count].ds_base = 896 bswap32(dmap->dm_segs[seg].ds_addr); 897 #else 898 rq2->req_dataseg[rq2->req_seg_count].ds_count = 899 dmap->dm_segs[seg].ds_len; 900 rq2->req_dataseg[rq2->req_seg_count].ds_base = 901 dmap->dm_segs[seg].ds_addr; 902 #endif 903 } else { 904 #if _BYTE_ORDER == _BIG_ENDIAN 905 rq->req_dataseg[rq->req_seg_count].ds_count = 906 bswap32(dmap->dm_segs[seg].ds_len); 907 rq->req_dataseg[rq->req_seg_count].ds_base = 908 bswap32(dmap->dm_segs[seg].ds_addr); 909 #else 910 rq->req_dataseg[rq->req_seg_count].ds_count = 911 dmap->dm_segs[seg].ds_len; 912 rq->req_dataseg[rq->req_seg_count].ds_base = 913 dmap->dm_segs[seg].ds_addr; 914 #endif 915 } 916 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 917 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 918 (unsigned long) dmap->dm_segs[seg].ds_len); 919 } 920 921 if (seg == segcnt) 922 goto dmasync; 923 924 do { 925 crq = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp); 926 *iptrp = ISP_NXT_QENTRY(*iptrp, RQUEST_QUEUE_LEN(isp)); 927 if (*iptrp == optr) { 928 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 929 bus_dmamap_unload(pcs->pci_dmat, dmap); 930 XS_SETERR(xs, HBA_BOTCH); 931 return (CMD_EAGAIN); 932 } 933 rq->req_header.rqs_entry_count++; 934 bzero((void *)crq, sizeof (*crq)); 935 crq->req_header.rqs_entry_count = 1; 936 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 937 938 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 939 rq->req_seg_count++, seg++, ovseg++) { 940 #if _BYTE_ORDER == _BIG_ENDIAN 941 crq->req_dataseg[ovseg].ds_count = 942 bswap32(dmap->dm_segs[seg].ds_len); 943 crq->req_dataseg[ovseg].ds_base = 944 bswap32(dmap->dm_segs[seg].ds_addr); 945 #else 946 crq->req_dataseg[ovseg].ds_count = 947 dmap->dm_segs[seg].ds_len; 948 crq->req_dataseg[ovseg].ds_base = 949 dmap->dm_segs[seg].ds_addr; 950 #endif 951 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 952 rq->req_header.rqs_entry_count - 1, 953 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 954 (unsigned long) dmap->dm_segs[seg].ds_len); 955 } 956 } while (seg < segcnt); 957 958 959 dmasync: 960 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 961 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 962 BUS_DMASYNC_PREWRITE); 963 964 mbxsync: 965 ISP_SWIZZLE_REQUEST(isp, rq); 966 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_rquest_dmap, 0, 967 pcs->pci_rquest_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 968 return (CMD_QUEUED); 969 } 970 971 static int 972 isp_pci_intr(arg) 973 void *arg; 974 { 975 int rv; 976 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)arg; 977 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_result_dmap, 0, 978 pcs->pci_result_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 979 pcs->pci_isp.isp_osinfo.onintstack = 1; 980 rv = isp_intr(arg); 981 pcs->pci_isp.isp_osinfo.onintstack = 0; 982 return (rv); 983 } 984 985 static void 986 isp_pci_dmateardown(isp, xs, handle) 987 struct ispsoftc *isp; 988 struct scsipi_xfer *xs; 989 u_int32_t handle; 990 { 991 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 992 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 993 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 994 xs->xs_control & XS_CTL_DATA_IN ? 995 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 996 bus_dmamap_unload(pcs->pci_dmat, dmap); 997 } 998 999 static void 1000 isp_pci_reset1(isp) 1001 struct ispsoftc *isp; 1002 { 1003 /* Make sure the BIOS is disabled */ 1004 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1005 } 1006 1007 static void 1008 isp_pci_dumpregs(isp, msg) 1009 struct ispsoftc *isp; 1010 const char *msg; 1011 { 1012 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1013 if (msg) 1014 printf("%s: %s\n", isp->isp_name, msg); 1015 if (IS_SCSI(isp)) 1016 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1017 else 1018 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1019 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1020 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1021 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1022 1023 1024 if (IS_SCSI(isp)) { 1025 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1026 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1027 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1028 ISP_READ(isp, CDMA_FIFO_STS)); 1029 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1030 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1031 ISP_READ(isp, DDMA_FIFO_STS)); 1032 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1033 ISP_READ(isp, SXP_INTERRUPT), 1034 ISP_READ(isp, SXP_GROSS_ERR), 1035 ISP_READ(isp, SXP_PINS_CTRL)); 1036 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1037 } 1038 printf(" mbox regs: %x %x %x %x %x\n", 1039 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1040 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1041 ISP_READ(isp, OUTMAILBOX4)); 1042 printf(" PCI Status Command/Status=%x\n", 1043 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1044 } 1045
Indexes created Sat Sep 27 14:09:57 GMT 2025