isp_pci.c revision 1.65
1 /* $NetBSD: isp_pci.c,v 1.65 2000/12/30 08:49:11 mjacob Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 * Matthew Jacob (mjacob (at) nas.nasa.gov) 33 */ 34 /* 35 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 #include <dev/ic/isp_netbsd.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 #include <uvm/uvm_extern.h> 66 #include <sys/reboot.h> 67 68 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int)); 69 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t)); 70 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 71 static u_int16_t isp_pci_rd_reg_1080 __P((struct ispsoftc *, int)); 72 static void isp_pci_wr_reg_1080 __P((struct ispsoftc *, int, u_int16_t)); 73 #endif 74 static int isp_pci_mbxdma __P((struct ispsoftc *)); 75 static int isp_pci_dmasetup __P((struct ispsoftc *, struct scsipi_xfer *, 76 ispreq_t *, u_int16_t *, u_int16_t)); 77 static void isp_pci_dmateardown __P((struct ispsoftc *, struct scsipi_xfer *, 78 u_int32_t)); 79 static void isp_pci_reset1 __P((struct ispsoftc *)); 80 static void isp_pci_dumpregs __P((struct ispsoftc *, const char *)); 81 static int isp_pci_intr __P((void *)); 82 83 #if defined(ISP_DISABLE_1020_SUPPORT) 84 #define ISP_1040_RISC_CODE NULL 85 #else 86 #define ISP_1040_RISC_CODE isp_1040_risc_code 87 #include <dev/microcode/isp/asm_1040.h> 88 #endif 89 90 #if defined(ISP_DISABLE_1080_SUPPORT) 91 #define ISP_1080_RISC_CODE NULL 92 #else 93 #define ISP_1080_RISC_CODE isp_1080_risc_code 94 #include <dev/microcode/isp/asm_1080.h> 95 #endif 96 97 #if defined(ISP_DISABLE_12160_SUPPORT) 98 #define ISP_12160_RISC_CODE NULL 99 #else 100 #define ISP_12160_RISC_CODE isp_12160_risc_code 101 #include <dev/microcode/isp/asm_12160.h> 102 #endif 103 104 #if defined(ISP_DISABLE_2100_SUPPORT) 105 #define ISP_2100_RISC_CODE NULL 106 #else 107 #define ISP_2100_RISC_CODE isp_2100_risc_code 108 #include <dev/microcode/isp/asm_2100.h> 109 #endif 110 111 #if defined(ISP_DISABLE_2200_SUPPORT) 112 #define ISP_2200_RISC_CODE NULL 113 #else 114 #define ISP_2200_RISC_CODE isp_2200_risc_code 115 #include <dev/microcode/isp/asm_2200.h> 116 #endif 117 118 #ifndef ISP_DISABLE_1020_SUPPORT 119 static struct ispmdvec mdvec = { 120 isp_pci_rd_reg, 121 isp_pci_wr_reg, 122 isp_pci_mbxdma, 123 isp_pci_dmasetup, 124 isp_pci_dmateardown, 125 NULL, 126 isp_pci_reset1, 127 isp_pci_dumpregs, 128 ISP_1040_RISC_CODE, 129 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 130 }; 131 #endif 132 133 #ifndef ISP_DISABLE_1080_SUPPORT 134 static struct ispmdvec mdvec_1080 = { 135 isp_pci_rd_reg_1080, 136 isp_pci_wr_reg_1080, 137 isp_pci_mbxdma, 138 isp_pci_dmasetup, 139 isp_pci_dmateardown, 140 NULL, 141 isp_pci_reset1, 142 isp_pci_dumpregs, 143 ISP_1080_RISC_CODE, 144 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 145 }; 146 #endif 147 148 #ifndef ISP_DISABLE_12160_SUPPORT 149 static struct ispmdvec mdvec_12160 = { 150 isp_pci_rd_reg_1080, 151 isp_pci_wr_reg_1080, 152 isp_pci_mbxdma, 153 isp_pci_dmasetup, 154 isp_pci_dmateardown, 155 NULL, 156 isp_pci_reset1, 157 isp_pci_dumpregs, 158 ISP_12160_RISC_CODE, 159 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 160 }; 161 #endif 162 163 #ifndef ISP_DISABLE_2100_SUPPORT 164 static struct ispmdvec mdvec_2100 = { 165 isp_pci_rd_reg, 166 isp_pci_wr_reg, 167 isp_pci_mbxdma, 168 isp_pci_dmasetup, 169 isp_pci_dmateardown, 170 NULL, 171 isp_pci_reset1, 172 isp_pci_dumpregs, 173 ISP_2100_RISC_CODE 174 }; 175 #endif 176 177 #ifndef ISP_DISABLE_2200_SUPPORT 178 static struct ispmdvec mdvec_2200 = { 179 isp_pci_rd_reg, 180 isp_pci_wr_reg, 181 isp_pci_mbxdma, 182 isp_pci_dmasetup, 183 isp_pci_dmateardown, 184 NULL, 185 isp_pci_reset1, 186 isp_pci_dumpregs, 187 ISP_2200_RISC_CODE 188 }; 189 #endif 190 191 #ifndef PCI_VENDOR_QLOGIC 192 #define PCI_VENDOR_QLOGIC 0x1077 193 #endif 194 195 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 196 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 197 #endif 198 199 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 200 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 201 #endif 202 203 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 204 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 205 #endif 206 207 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 208 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 209 #endif 210 211 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 212 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 213 #endif 214 215 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 216 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 217 #endif 218 219 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 220 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 221 #endif 222 223 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 224 225 #define PCI_QLOGIC_ISP1080 \ 226 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 227 228 #define PCI_QLOGIC_ISP1240 \ 229 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 230 231 #define PCI_QLOGIC_ISP1280 \ 232 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 233 234 #define PCI_QLOGIC_ISP12160 \ 235 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 236 237 #define PCI_QLOGIC_ISP2100 \ 238 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 239 240 #define PCI_QLOGIC_ISP2200 \ 241 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 242 243 #define IO_MAP_REG 0x10 244 #define MEM_MAP_REG 0x14 245 #define PCIR_ROMADDR 0x30 246 247 #define PCI_DFLT_LTNCY 0x40 248 #define PCI_DFLT_LNSZ 0x10 249 250 251 static int isp_pci_probe __P((struct device *, struct cfdata *, void *)); 252 static void isp_pci_attach __P((struct device *, struct device *, void *)); 253 254 struct isp_pcisoftc { 255 struct ispsoftc pci_isp; 256 pci_chipset_tag_t pci_pc; 257 pcitag_t pci_tag; 258 bus_space_tag_t pci_st; 259 bus_space_handle_t pci_sh; 260 bus_dma_tag_t pci_dmat; 261 bus_dmamap_t pci_scratch_dmap; /* for fcp only */ 262 bus_dmamap_t pci_rquest_dmap; 263 bus_dmamap_t pci_result_dmap; 264 bus_dmamap_t *pci_xfer_dmap; 265 void * pci_ih; 266 int16_t pci_poff[_NREG_BLKS]; 267 }; 268 269 struct cfattach isp_pci_ca = { 270 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach 271 }; 272 273 #ifdef DEBUG 274 const char vstring[] = 275 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 276 #endif 277 278 static int 279 isp_pci_probe(parent, match, aux) 280 struct device *parent; 281 struct cfdata *match; 282 void *aux; 283 { 284 struct pci_attach_args *pa = aux; 285 switch (pa->pa_id) { 286 #ifndef ISP_DISABLE_1020_SUPPORT 287 case PCI_QLOGIC_ISP: 288 return (1); 289 #endif 290 #ifndef ISP_DISABLE_1080_SUPPORT 291 case PCI_QLOGIC_ISP1080: 292 case PCI_QLOGIC_ISP1240: 293 case PCI_QLOGIC_ISP1280: 294 return (1); 295 #endif 296 #ifndef ISP_DISABLE_12160_SUPPORT 297 case PCI_QLOGIC_ISP12160: 298 return (1); 299 #endif 300 #ifndef ISP_DISABLE_2100_SUPPORT 301 case PCI_QLOGIC_ISP2100: 302 return (1); 303 #endif 304 #ifndef ISP_DISABLE_2200_SUPPORT 305 case PCI_QLOGIC_ISP2200: 306 return (1); 307 #endif 308 default: 309 return (0); 310 } 311 } 312 313 314 static void 315 isp_pci_attach(parent, self, aux) 316 struct device *parent, *self; 317 void *aux; 318 { 319 #ifdef DEBUG 320 static char oneshot = 1; 321 #endif 322 static const char nomem[] = "%s: no mem for sdparam table\n"; 323 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 324 struct pci_attach_args *pa = aux; 325 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 326 struct ispsoftc *isp = &pcs->pci_isp; 327 bus_space_tag_t st, iot, memt; 328 bus_space_handle_t sh, ioh, memh; 329 pci_intr_handle_t ih; 330 const char *intrstr; 331 int ioh_valid, memh_valid; 332 333 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 334 PCI_MAPREG_TYPE_IO, 0, 335 &iot, &ioh, NULL, NULL) == 0); 336 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 337 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 338 &memt, &memh, NULL, NULL) == 0); 339 if (memh_valid) { 340 st = memt; 341 sh = memh; 342 } else if (ioh_valid) { 343 st = iot; 344 sh = ioh; 345 } else { 346 printf(": unable to map device registers\n"); 347 return; 348 } 349 printf("\n"); 350 351 pcs->pci_st = st; 352 pcs->pci_sh = sh; 353 pcs->pci_dmat = pa->pa_dmat; 354 pcs->pci_pc = pa->pa_pc; 355 pcs->pci_tag = pa->pa_tag; 356 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 357 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 358 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 359 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 360 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 361 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 362 363 #ifndef ISP_DISABLE_1020_SUPPORT 364 if (pa->pa_id == PCI_QLOGIC_ISP) { 365 isp->isp_mdvec = &mdvec; 366 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 367 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 368 if (isp->isp_param == NULL) { 369 printf(nomem, isp->isp_name); 370 return; 371 } 372 bzero(isp->isp_param, sizeof (sdparam)); 373 } 374 #endif 375 #ifndef ISP_DISABLE_1080_SUPPORT 376 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 377 isp->isp_mdvec = &mdvec_1080; 378 isp->isp_type = ISP_HA_SCSI_1080; 379 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 380 if (isp->isp_param == NULL) { 381 printf(nomem, isp->isp_name); 382 return; 383 } 384 bzero(isp->isp_param, sizeof (sdparam)); 385 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 386 ISP1080_DMA_REGS_OFF; 387 } 388 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 389 isp->isp_mdvec = &mdvec_1080; 390 isp->isp_type = ISP_HA_SCSI_1240; 391 isp->isp_param = 392 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 393 if (isp->isp_param == NULL) { 394 printf(nomem, isp->isp_name); 395 return; 396 } 397 bzero(isp->isp_param, 2 * sizeof (sdparam)); 398 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 399 ISP1080_DMA_REGS_OFF; 400 } 401 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 402 isp->isp_mdvec = &mdvec_1080; 403 isp->isp_type = ISP_HA_SCSI_1280; 404 isp->isp_param = 405 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 406 if (isp->isp_param == NULL) { 407 printf(nomem, isp->isp_name); 408 return; 409 } 410 bzero(isp->isp_param, 2 * sizeof (sdparam)); 411 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 412 ISP1080_DMA_REGS_OFF; 413 } 414 #endif 415 #ifndef ISP_DISABLE_12160_SUPPORT 416 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 417 isp->isp_mdvec = &mdvec_12160; 418 isp->isp_type = ISP_HA_SCSI_12160; 419 isp->isp_param = 420 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 421 if (isp->isp_param == NULL) { 422 printf(nomem, isp->isp_name); 423 return; 424 } 425 bzero(isp->isp_param, 2 * sizeof (sdparam)); 426 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 427 ISP1080_DMA_REGS_OFF; 428 } 429 #endif 430 #ifndef ISP_DISABLE_2100_SUPPORT 431 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 432 isp->isp_mdvec = &mdvec_2100; 433 isp->isp_type = ISP_HA_FC_2100; 434 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 435 if (isp->isp_param == NULL) { 436 printf(nomem, isp->isp_name); 437 return; 438 } 439 bzero(isp->isp_param, sizeof (fcparam)); 440 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 441 PCI_MBOX_REGS2100_OFF; 442 if (rev < 3) { 443 /* 444 * XXX: Need to get the actual revision 445 * XXX: number of the 2100 FB. At any rate, 446 * XXX: lower cache line size for early revision 447 * XXX; boards. 448 */ 449 linesz = 1; 450 } 451 } 452 #endif 453 #ifndef ISP_DISABLE_2200_SUPPORT 454 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 455 isp->isp_mdvec = &mdvec_2200; 456 isp->isp_type = ISP_HA_FC_2200; 457 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 458 if (isp->isp_param == NULL) { 459 printf(nomem, isp->isp_name); 460 return; 461 } 462 bzero(isp->isp_param, sizeof (fcparam)); 463 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 464 PCI_MBOX_REGS2100_OFF; 465 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 466 } 467 #endif 468 /* 469 * Set up logging levels. 470 */ 471 #ifdef ISP_LOGDEFAULT 472 isp->isp_dblev = ISP_LOGDEFAULT; 473 #else 474 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 475 if (bootverbose) 476 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 477 #ifdef SCSIDEBUG 478 isp->isp_dblev |= ISP_LOGDEBUG1|ISP_LOGDEBUG2; 479 #endif 480 #ifdef DEBUG 481 isp->isp_dblev |= ISP_LOGDEBUG0; 482 #endif 483 #endif 484 485 #ifdef DEBUG 486 if (oneshot) { 487 oneshot = 0; 488 isp_prt(isp, ISP_LOGCONFIG, vstring, 489 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 490 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 491 } 492 #endif 493 494 isp->isp_revision = rev; 495 496 /* 497 * Make sure that command register set sanely. 498 */ 499 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 500 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 501 502 /* 503 * Not so sure about these- but I think it's important that they get 504 * enabled...... 505 */ 506 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 507 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 508 509 /* 510 * Make sure that the latency timer, cache line size, 511 * and ROM is disabled. 512 */ 513 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 514 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 515 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 516 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 517 data |= (linesz << PCI_CACHELINE_SHIFT); 518 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 519 520 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 521 data &= ~1; 522 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 523 524 if (pci_intr_map(pa, &ih)) { 525 printf("%s: couldn't map interrupt\n", isp->isp_name); 526 free(isp->isp_param, M_DEVBUF); 527 return; 528 } 529 intrstr = pci_intr_string(pa->pa_pc, ih); 530 if (intrstr == NULL) 531 intrstr = "<I dunno>"; 532 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 533 isp_pci_intr, isp); 534 if (pcs->pci_ih == NULL) { 535 printf("%s: couldn't establish interrupt at %s\n", 536 isp->isp_name, intrstr); 537 free(isp->isp_param, M_DEVBUF); 538 return; 539 } 540 541 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 542 543 if (IS_FC(isp)) { 544 DEFAULT_NODEWWN(isp) = 0x400000007F000002; 545 DEFAULT_PORTWWN(isp) = 0x400000007F000002; 546 } 547 548 isp->isp_confopts = self->dv_cfdata->cf_flags; 549 ISP_LOCK(isp); 550 isp->isp_osinfo.no_mbox_ints = 1; 551 isp_reset(isp); 552 if (isp->isp_state != ISP_RESETSTATE) { 553 ISP_UNLOCK(isp); 554 free(isp->isp_param, M_DEVBUF); 555 return; 556 } 557 ENABLE_INTS(isp); 558 isp_init(isp); 559 if (isp->isp_state != ISP_INITSTATE) { 560 isp_uninit(isp); 561 ISP_UNLOCK(isp); 562 free(isp->isp_param, M_DEVBUF); 563 return; 564 } 565 /* 566 * Do platform attach. 567 */ 568 ISP_UNLOCK(isp); 569 isp_attach(isp); 570 if (isp->isp_state != ISP_RUNSTATE) { 571 ISP_LOCK(isp); 572 isp_uninit(isp); 573 free(isp->isp_param, M_DEVBUF); 574 ISP_UNLOCK(isp); 575 } 576 } 577 578 static u_int16_t 579 isp_pci_rd_reg(isp, regoff) 580 struct ispsoftc *isp; 581 int regoff; 582 { 583 u_int16_t rv; 584 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 585 int offset, oldconf = 0; 586 587 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 588 /* 589 * We will assume that someone has paused the RISC processor. 590 */ 591 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 592 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 593 delay(250); 594 } 595 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 596 offset += (regoff & 0xff); 597 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 598 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 599 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 600 delay(250); 601 } 602 return (rv); 603 } 604 605 static void 606 isp_pci_wr_reg(isp, regoff, val) 607 struct ispsoftc *isp; 608 int regoff; 609 u_int16_t val; 610 { 611 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 612 int offset, oldconf = 0; 613 614 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 615 /* 616 * We will assume that someone has paused the RISC processor. 617 */ 618 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 619 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 620 delay(250); 621 } 622 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 623 offset += (regoff & 0xff); 624 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 625 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 626 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 627 delay(250); 628 } 629 } 630 631 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 632 static u_int16_t 633 isp_pci_rd_reg_1080(isp, regoff) 634 struct ispsoftc *isp; 635 int regoff; 636 { 637 u_int16_t rv, oc = 0; 638 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 639 int offset; 640 641 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 642 u_int16_t tc; 643 /* 644 * We will assume that someone has paused the RISC processor. 645 */ 646 oc = isp_pci_rd_reg(isp, BIU_CONF1); 647 tc = oc & ~BIU_PCI1080_CONF1_DMA; 648 if (IS_1280(isp)) { 649 if (regoff & SXP_BANK1_SELECT) 650 tc |= BIU_PCI1080_CONF1_SXP0; 651 else 652 tc |= BIU_PCI1080_CONF1_SXP1; 653 } else { 654 tc |= BIU_PCI1080_CONF1_SXP0; 655 } 656 isp_pci_wr_reg(isp, BIU_CONF1, tc); 657 delay(250); 658 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 659 oc = isp_pci_rd_reg(isp, BIU_CONF1); 660 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 661 delay(250); 662 } 663 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 664 offset += (regoff & 0xff); 665 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 666 /* 667 * Okay, because BIU_CONF1 is always nonzero 668 */ 669 if (oc) { 670 isp_pci_wr_reg(isp, BIU_CONF1, oc); 671 delay(250); 672 } 673 return (rv); 674 } 675 676 static void 677 isp_pci_wr_reg_1080(isp, regoff, val) 678 struct ispsoftc *isp; 679 int regoff; 680 u_int16_t val; 681 { 682 u_int16_t oc = 0; 683 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 684 int offset; 685 686 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 687 u_int16_t tc; 688 /* 689 * We will assume that someone has paused the RISC processor. 690 */ 691 oc = isp_pci_rd_reg(isp, BIU_CONF1); 692 tc = oc & ~BIU_PCI1080_CONF1_DMA; 693 if (IS_1280(isp)) { 694 if (regoff & SXP_BANK1_SELECT) 695 tc |= BIU_PCI1080_CONF1_SXP0; 696 else 697 tc |= BIU_PCI1080_CONF1_SXP1; 698 } else { 699 tc |= BIU_PCI1080_CONF1_SXP0; 700 } 701 isp_pci_wr_reg(isp, BIU_CONF1, tc); 702 delay(250); 703 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 704 oc = isp_pci_rd_reg(isp, BIU_CONF1); 705 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 706 delay(250); 707 } 708 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 709 offset += (regoff & 0xff); 710 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 711 /* 712 * Okay, because BIU_CONF1 is always nonzero 713 */ 714 if (oc) { 715 isp_pci_wr_reg(isp, BIU_CONF1, oc); 716 delay(250); 717 } 718 } 719 #endif 720 721 static int 722 isp_pci_mbxdma(isp) 723 struct ispsoftc *isp; 724 { 725 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 726 bus_dma_tag_t dmat = pcs->pci_dmat; 727 bus_dma_segment_t sg; 728 bus_size_t len; 729 fcparam *fcp; 730 int rs, i; 731 732 if (isp->isp_rquest_dma) /* been here before? */ 733 return (0); 734 735 len = isp->isp_maxcmds * sizeof (XS_T); 736 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 737 if (isp->isp_xflist == NULL) { 738 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 739 return (1); 740 } 741 bzero(isp->isp_xflist, len); 742 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 743 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 744 if (pcs->pci_xfer_dmap == NULL) { 745 free(isp->isp_xflist, M_DEVBUF); 746 isp->isp_xflist = NULL; 747 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array"); 748 return (1); 749 } 750 for (i = 0; i < isp->isp_maxcmds; i++) { 751 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 752 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 753 isp_prt(isp, ISP_LOGERR, "cannot create dma maps"); 754 break; 755 } 756 } 757 if (i < isp->isp_maxcmds) { 758 while (--i >= 0) { 759 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 760 } 761 free(isp->isp_xflist, M_DEVBUF); 762 free(pcs->pci_xfer_dmap, M_DEVBUF); 763 isp->isp_xflist = NULL; 764 pcs->pci_xfer_dmap = NULL; 765 return (1); 766 } 767 768 /* 769 * Allocate and map the request queue. 770 */ 771 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 772 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 773 BUS_DMA_NOWAIT) || 774 bus_dmamem_map(pcs->pci_dmat, &sg, rs, len, 775 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 776 goto dmafail; 777 } 778 779 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 780 &pcs->pci_rquest_dmap) || bus_dmamap_load(dmat, 781 pcs->pci_rquest_dmap, (caddr_t)isp->isp_rquest, len, NULL, 782 BUS_DMA_NOWAIT)) { 783 goto dmafail; 784 } 785 786 isp->isp_rquest_dma = pcs->pci_rquest_dmap->dm_segs[0].ds_addr; 787 788 /* 789 * Allocate and map the result queue. 790 */ 791 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 792 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 793 BUS_DMA_NOWAIT) || 794 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 795 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 796 goto dmafail; 797 } 798 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 799 &pcs->pci_result_dmap) || bus_dmamap_load(pcs->pci_dmat, 800 pcs->pci_result_dmap, (caddr_t)isp->isp_result, len, NULL, 801 BUS_DMA_NOWAIT)) { 802 goto dmafail; 803 } 804 isp->isp_result_dma = pcs->pci_result_dmap->dm_segs[0].ds_addr; 805 806 if (IS_SCSI(isp)) { 807 return (0); 808 } 809 810 fcp = isp->isp_param; 811 len = ISP2100_SCRLEN; 812 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 813 BUS_DMA_NOWAIT) || 814 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 815 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 816 goto dmafail; 817 } 818 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 819 &pcs->pci_scratch_dmap) || bus_dmamap_load(dmat, 820 pcs->pci_scratch_dmap, (caddr_t)fcp->isp_scratch, len, NULL, 821 BUS_DMA_NOWAIT)) { 822 goto dmafail; 823 } 824 fcp->isp_scdma = pcs->pci_scratch_dmap->dm_segs[0].ds_addr; 825 return (0); 826 dmafail: 827 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure"); 828 for (i = 0; i < isp->isp_maxcmds; i++) { 829 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 830 } 831 free(isp->isp_xflist, M_DEVBUF); 832 free(pcs->pci_xfer_dmap, M_DEVBUF); 833 isp->isp_xflist = NULL; 834 pcs->pci_xfer_dmap = NULL; 835 return (1); 836 } 837 838 static int 839 isp_pci_dmasetup(isp, xs, rq, iptrp, optr) 840 struct ispsoftc *isp; 841 struct scsipi_xfer *xs; 842 ispreq_t *rq; 843 u_int16_t *iptrp; 844 u_int16_t optr; 845 { 846 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 847 bus_dmamap_t dmap; 848 ispcontreq_t *crq; 849 int segcnt, seg, error, ovseg, seglim, drq; 850 851 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 852 853 if (xs->datalen == 0) { 854 rq->req_seg_count = 1; 855 goto mbxsync; 856 } 857 if (xs->xs_control & XS_CTL_DATA_IN) { 858 drq = REQFLAG_DATA_IN; 859 } else { 860 drq = REQFLAG_DATA_OUT; 861 } 862 863 if (IS_FC(isp)) { 864 seglim = ISP_RQDSEG_T2; 865 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 866 ((ispreqt2_t *)rq)->req_flags |= drq; 867 } else { 868 rq->req_flags |= drq; 869 if (XS_CDBLEN(xs) > 12) { 870 seglim = 0; 871 } else { 872 seglim = ISP_RQDSEG; 873 } 874 } 875 error = bus_dmamap_load(pcs->pci_dmat, dmap, xs->data, xs->datalen, 876 NULL, xs->xs_control & XS_CTL_NOSLEEP ? 877 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 878 if (error) { 879 XS_SETERR(xs, HBA_BOTCH); 880 return (CMD_COMPLETE); 881 } 882 883 segcnt = dmap->dm_nsegs; 884 885 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 886 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 887 "write from", xs->data, segcnt); 888 889 for (seg = 0, rq->req_seg_count = 0; 890 seglim && seg < segcnt && rq->req_seg_count < seglim; 891 seg++, rq->req_seg_count++) { 892 if (IS_FC(isp)) { 893 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 894 #if _BYTE_ORDER == _BIG_ENDIAN 895 rq2->req_dataseg[rq2->req_seg_count].ds_count = 896 bswap32(dmap->dm_segs[seg].ds_len); 897 rq2->req_dataseg[rq2->req_seg_count].ds_base = 898 bswap32(dmap->dm_segs[seg].ds_addr); 899 #else 900 rq2->req_dataseg[rq2->req_seg_count].ds_count = 901 dmap->dm_segs[seg].ds_len; 902 rq2->req_dataseg[rq2->req_seg_count].ds_base = 903 dmap->dm_segs[seg].ds_addr; 904 #endif 905 } else { 906 #if _BYTE_ORDER == _BIG_ENDIAN 907 rq->req_dataseg[rq->req_seg_count].ds_count = 908 bswap32(dmap->dm_segs[seg].ds_len); 909 rq->req_dataseg[rq->req_seg_count].ds_base = 910 bswap32(dmap->dm_segs[seg].ds_addr); 911 #else 912 rq->req_dataseg[rq->req_seg_count].ds_count = 913 dmap->dm_segs[seg].ds_len; 914 rq->req_dataseg[rq->req_seg_count].ds_base = 915 dmap->dm_segs[seg].ds_addr; 916 #endif 917 } 918 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 919 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 920 (unsigned long) dmap->dm_segs[seg].ds_len); 921 } 922 923 if (seg == segcnt) 924 goto dmasync; 925 926 do { 927 crq = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp); 928 *iptrp = ISP_NXT_QENTRY(*iptrp, RQUEST_QUEUE_LEN(isp)); 929 if (*iptrp == optr) { 930 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 931 bus_dmamap_unload(pcs->pci_dmat, dmap); 932 XS_SETERR(xs, HBA_BOTCH); 933 return (CMD_EAGAIN); 934 } 935 rq->req_header.rqs_entry_count++; 936 bzero((void *)crq, sizeof (*crq)); 937 crq->req_header.rqs_entry_count = 1; 938 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 939 940 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 941 rq->req_seg_count++, seg++, ovseg++) { 942 #if _BYTE_ORDER == _BIG_ENDIAN 943 crq->req_dataseg[ovseg].ds_count = 944 bswap32(dmap->dm_segs[seg].ds_len); 945 crq->req_dataseg[ovseg].ds_base = 946 bswap32(dmap->dm_segs[seg].ds_addr); 947 #else 948 crq->req_dataseg[ovseg].ds_count = 949 dmap->dm_segs[seg].ds_len; 950 crq->req_dataseg[ovseg].ds_base = 951 dmap->dm_segs[seg].ds_addr; 952 #endif 953 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 954 rq->req_header.rqs_entry_count - 1, 955 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 956 (unsigned long) dmap->dm_segs[seg].ds_len); 957 } 958 } while (seg < segcnt); 959 960 961 dmasync: 962 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 963 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 964 BUS_DMASYNC_PREWRITE); 965 966 mbxsync: 967 ISP_SWIZZLE_REQUEST(isp, rq); 968 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_rquest_dmap, 0, 969 pcs->pci_rquest_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 970 return (CMD_QUEUED); 971 } 972 973 static int 974 isp_pci_intr(arg) 975 void *arg; 976 { 977 int rv; 978 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)arg; 979 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_result_dmap, 0, 980 pcs->pci_result_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 981 pcs->pci_isp.isp_osinfo.onintstack = 1; 982 rv = isp_intr(arg); 983 pcs->pci_isp.isp_osinfo.onintstack = 0; 984 return (rv); 985 } 986 987 static void 988 isp_pci_dmateardown(isp, xs, handle) 989 struct ispsoftc *isp; 990 struct scsipi_xfer *xs; 991 u_int32_t handle; 992 { 993 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 994 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 995 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 996 xs->xs_control & XS_CTL_DATA_IN ? 997 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 998 bus_dmamap_unload(pcs->pci_dmat, dmap); 999 } 1000 1001 static void 1002 isp_pci_reset1(isp) 1003 struct ispsoftc *isp; 1004 { 1005 /* Make sure the BIOS is disabled */ 1006 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1007 } 1008 1009 static void 1010 isp_pci_dumpregs(isp, msg) 1011 struct ispsoftc *isp; 1012 const char *msg; 1013 { 1014 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1015 if (msg) 1016 printf("%s: %s\n", isp->isp_name, msg); 1017 if (IS_SCSI(isp)) 1018 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1019 else 1020 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1021 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1022 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1023 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1024 1025 1026 if (IS_SCSI(isp)) { 1027 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1028 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1029 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1030 ISP_READ(isp, CDMA_FIFO_STS)); 1031 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1032 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1033 ISP_READ(isp, DDMA_FIFO_STS)); 1034 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1035 ISP_READ(isp, SXP_INTERRUPT), 1036 ISP_READ(isp, SXP_GROSS_ERR), 1037 ISP_READ(isp, SXP_PINS_CTRL)); 1038 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1039 } 1040 printf(" mbox regs: %x %x %x %x %x\n", 1041 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1042 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1043 ISP_READ(isp, OUTMAILBOX4)); 1044 printf(" PCI Status Command/Status=%x\n", 1045 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1046 } 1047
Indexes created Sat Sep 27 14:09:57 GMT 2025