isp_pci.c revision 1.67
1 /* $NetBSD: isp_pci.c,v 1.67 2001/03/07 23:07:16 thorpej Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 * Matthew Jacob (mjacob (at) nas.nasa.gov) 33 */ 34 /* 35 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 #include <dev/ic/isp_netbsd.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 #include <uvm/uvm_extern.h> 66 #include <sys/reboot.h> 67 68 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int)); 69 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t)); 70 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 71 static u_int16_t isp_pci_rd_reg_1080 __P((struct ispsoftc *, int)); 72 static void isp_pci_wr_reg_1080 __P((struct ispsoftc *, int, u_int16_t)); 73 #endif 74 static int isp_pci_mbxdma __P((struct ispsoftc *)); 75 static int isp_pci_dmasetup __P((struct ispsoftc *, struct scsipi_xfer *, 76 ispreq_t *, u_int16_t *, u_int16_t)); 77 static void isp_pci_dmateardown __P((struct ispsoftc *, struct scsipi_xfer *, 78 u_int32_t)); 79 static void isp_pci_reset1 __P((struct ispsoftc *)); 80 static void isp_pci_dumpregs __P((struct ispsoftc *, const char *)); 81 static int isp_pci_intr __P((void *)); 82 83 #if defined(ISP_DISABLE_1020_SUPPORT) 84 #define ISP_1040_RISC_CODE NULL 85 #else 86 #define ISP_1040_RISC_CODE isp_1040_risc_code 87 #include <dev/microcode/isp/asm_1040.h> 88 #endif 89 90 #if defined(ISP_DISABLE_1080_SUPPORT) 91 #define ISP_1080_RISC_CODE NULL 92 #else 93 #define ISP_1080_RISC_CODE isp_1080_risc_code 94 #include <dev/microcode/isp/asm_1080.h> 95 #endif 96 97 #if defined(ISP_DISABLE_12160_SUPPORT) 98 #define ISP_12160_RISC_CODE NULL 99 #else 100 #define ISP_12160_RISC_CODE isp_12160_risc_code 101 #include <dev/microcode/isp/asm_12160.h> 102 #endif 103 104 #if defined(ISP_DISABLE_2100_SUPPORT) 105 #define ISP_2100_RISC_CODE NULL 106 #else 107 #define ISP_2100_RISC_CODE isp_2100_risc_code 108 #include <dev/microcode/isp/asm_2100.h> 109 #endif 110 111 #if defined(ISP_DISABLE_2200_SUPPORT) 112 #define ISP_2200_RISC_CODE NULL 113 #else 114 #define ISP_2200_RISC_CODE isp_2200_risc_code 115 #include <dev/microcode/isp/asm_2200.h> 116 #endif 117 118 #ifndef ISP_DISABLE_1020_SUPPORT 119 static struct ispmdvec mdvec = { 120 isp_pci_rd_reg, 121 isp_pci_wr_reg, 122 isp_pci_mbxdma, 123 isp_pci_dmasetup, 124 isp_pci_dmateardown, 125 NULL, 126 isp_pci_reset1, 127 isp_pci_dumpregs, 128 ISP_1040_RISC_CODE, 129 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 130 }; 131 #endif 132 133 #ifndef ISP_DISABLE_1080_SUPPORT 134 static struct ispmdvec mdvec_1080 = { 135 isp_pci_rd_reg_1080, 136 isp_pci_wr_reg_1080, 137 isp_pci_mbxdma, 138 isp_pci_dmasetup, 139 isp_pci_dmateardown, 140 NULL, 141 isp_pci_reset1, 142 isp_pci_dumpregs, 143 ISP_1080_RISC_CODE, 144 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 145 }; 146 #endif 147 148 #ifndef ISP_DISABLE_12160_SUPPORT 149 static struct ispmdvec mdvec_12160 = { 150 isp_pci_rd_reg_1080, 151 isp_pci_wr_reg_1080, 152 isp_pci_mbxdma, 153 isp_pci_dmasetup, 154 isp_pci_dmateardown, 155 NULL, 156 isp_pci_reset1, 157 isp_pci_dumpregs, 158 ISP_12160_RISC_CODE, 159 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 160 }; 161 #endif 162 163 #ifndef ISP_DISABLE_2100_SUPPORT 164 static struct ispmdvec mdvec_2100 = { 165 isp_pci_rd_reg, 166 isp_pci_wr_reg, 167 isp_pci_mbxdma, 168 isp_pci_dmasetup, 169 isp_pci_dmateardown, 170 NULL, 171 isp_pci_reset1, 172 isp_pci_dumpregs, 173 ISP_2100_RISC_CODE 174 }; 175 #endif 176 177 #ifndef ISP_DISABLE_2200_SUPPORT 178 static struct ispmdvec mdvec_2200 = { 179 isp_pci_rd_reg, 180 isp_pci_wr_reg, 181 isp_pci_mbxdma, 182 isp_pci_dmasetup, 183 isp_pci_dmateardown, 184 NULL, 185 isp_pci_reset1, 186 isp_pci_dumpregs, 187 ISP_2200_RISC_CODE 188 }; 189 #endif 190 191 #ifndef PCI_VENDOR_QLOGIC 192 #define PCI_VENDOR_QLOGIC 0x1077 193 #endif 194 195 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 196 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 197 #endif 198 199 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 200 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 201 #endif 202 203 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 204 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 205 #endif 206 207 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 208 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 209 #endif 210 211 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 212 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 213 #endif 214 215 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 216 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 217 #endif 218 219 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 220 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 221 #endif 222 223 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 224 225 #define PCI_QLOGIC_ISP1080 \ 226 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 227 228 #define PCI_QLOGIC_ISP1240 \ 229 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 230 231 #define PCI_QLOGIC_ISP1280 \ 232 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 233 234 #define PCI_QLOGIC_ISP12160 \ 235 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 236 237 #define PCI_QLOGIC_ISP2100 \ 238 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 239 240 #define PCI_QLOGIC_ISP2200 \ 241 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 242 243 #define IO_MAP_REG 0x10 244 #define MEM_MAP_REG 0x14 245 #define PCIR_ROMADDR 0x30 246 247 #define PCI_DFLT_LTNCY 0x40 248 #define PCI_DFLT_LNSZ 0x10 249 250 251 static int isp_pci_probe __P((struct device *, struct cfdata *, void *)); 252 static void isp_pci_attach __P((struct device *, struct device *, void *)); 253 254 struct isp_pcisoftc { 255 struct ispsoftc pci_isp; 256 pci_chipset_tag_t pci_pc; 257 pcitag_t pci_tag; 258 bus_space_tag_t pci_st; 259 bus_space_handle_t pci_sh; 260 bus_dma_tag_t pci_dmat; 261 bus_dmamap_t pci_scratch_dmap; /* for fcp only */ 262 bus_dmamap_t pci_rquest_dmap; 263 bus_dmamap_t pci_result_dmap; 264 bus_dmamap_t *pci_xfer_dmap; 265 void * pci_ih; 266 int16_t pci_poff[_NREG_BLKS]; 267 }; 268 269 struct cfattach isp_pci_ca = { 270 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach 271 }; 272 273 #ifdef DEBUG 274 const char vstring[] = 275 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 276 #endif 277 278 static int 279 isp_pci_probe(parent, match, aux) 280 struct device *parent; 281 struct cfdata *match; 282 void *aux; 283 { 284 struct pci_attach_args *pa = aux; 285 switch (pa->pa_id) { 286 #ifndef ISP_DISABLE_1020_SUPPORT 287 case PCI_QLOGIC_ISP: 288 return (1); 289 #endif 290 #ifndef ISP_DISABLE_1080_SUPPORT 291 case PCI_QLOGIC_ISP1080: 292 case PCI_QLOGIC_ISP1240: 293 case PCI_QLOGIC_ISP1280: 294 return (1); 295 #endif 296 #ifndef ISP_DISABLE_12160_SUPPORT 297 case PCI_QLOGIC_ISP12160: 298 return (1); 299 #endif 300 #ifndef ISP_DISABLE_2100_SUPPORT 301 case PCI_QLOGIC_ISP2100: 302 return (1); 303 #endif 304 #ifndef ISP_DISABLE_2200_SUPPORT 305 case PCI_QLOGIC_ISP2200: 306 return (1); 307 #endif 308 default: 309 return (0); 310 } 311 } 312 313 314 static void 315 isp_pci_attach(parent, self, aux) 316 struct device *parent, *self; 317 void *aux; 318 { 319 #ifdef DEBUG 320 static char oneshot = 1; 321 #endif 322 static const char nomem[] = "%s: no mem for sdparam table\n"; 323 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 324 struct pci_attach_args *pa = aux; 325 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 326 struct ispsoftc *isp = &pcs->pci_isp; 327 bus_space_tag_t st, iot, memt; 328 bus_space_handle_t sh, ioh, memh; 329 pci_intr_handle_t ih; 330 const char *intrstr; 331 int ioh_valid, memh_valid; 332 333 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 334 PCI_MAPREG_TYPE_IO, 0, 335 &iot, &ioh, NULL, NULL) == 0); 336 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 337 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 338 &memt, &memh, NULL, NULL) == 0); 339 if (memh_valid) { 340 st = memt; 341 sh = memh; 342 } else if (ioh_valid) { 343 st = iot; 344 sh = ioh; 345 } else { 346 printf(": unable to map device registers\n"); 347 return; 348 } 349 printf("\n"); 350 351 pcs->pci_st = st; 352 pcs->pci_sh = sh; 353 pcs->pci_dmat = pa->pa_dmat; 354 pcs->pci_pc = pa->pa_pc; 355 pcs->pci_tag = pa->pa_tag; 356 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 357 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 358 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 359 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 360 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 361 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 362 363 #ifndef ISP_DISABLE_1020_SUPPORT 364 if (pa->pa_id == PCI_QLOGIC_ISP) { 365 isp->isp_mdvec = &mdvec; 366 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 367 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 368 if (isp->isp_param == NULL) { 369 printf(nomem, isp->isp_name); 370 return; 371 } 372 bzero(isp->isp_param, sizeof (sdparam)); 373 } 374 #endif 375 #ifndef ISP_DISABLE_1080_SUPPORT 376 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 377 isp->isp_mdvec = &mdvec_1080; 378 isp->isp_type = ISP_HA_SCSI_1080; 379 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 380 if (isp->isp_param == NULL) { 381 printf(nomem, isp->isp_name); 382 return; 383 } 384 bzero(isp->isp_param, sizeof (sdparam)); 385 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 386 ISP1080_DMA_REGS_OFF; 387 } 388 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 389 isp->isp_mdvec = &mdvec_1080; 390 isp->isp_type = ISP_HA_SCSI_1240; 391 isp->isp_param = 392 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 393 if (isp->isp_param == NULL) { 394 printf(nomem, isp->isp_name); 395 return; 396 } 397 bzero(isp->isp_param, 2 * sizeof (sdparam)); 398 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 399 ISP1080_DMA_REGS_OFF; 400 } 401 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 402 isp->isp_mdvec = &mdvec_1080; 403 isp->isp_type = ISP_HA_SCSI_1280; 404 isp->isp_param = 405 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 406 if (isp->isp_param == NULL) { 407 printf(nomem, isp->isp_name); 408 return; 409 } 410 bzero(isp->isp_param, 2 * sizeof (sdparam)); 411 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 412 ISP1080_DMA_REGS_OFF; 413 } 414 #endif 415 #ifndef ISP_DISABLE_12160_SUPPORT 416 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 417 isp->isp_mdvec = &mdvec_12160; 418 isp->isp_type = ISP_HA_SCSI_12160; 419 isp->isp_param = 420 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 421 if (isp->isp_param == NULL) { 422 printf(nomem, isp->isp_name); 423 return; 424 } 425 bzero(isp->isp_param, 2 * sizeof (sdparam)); 426 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 427 ISP1080_DMA_REGS_OFF; 428 } 429 #endif 430 #ifndef ISP_DISABLE_2100_SUPPORT 431 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 432 isp->isp_mdvec = &mdvec_2100; 433 isp->isp_type = ISP_HA_FC_2100; 434 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 435 if (isp->isp_param == NULL) { 436 printf(nomem, isp->isp_name); 437 return; 438 } 439 bzero(isp->isp_param, sizeof (fcparam)); 440 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 441 PCI_MBOX_REGS2100_OFF; 442 if (rev < 3) { 443 /* 444 * XXX: Need to get the actual revision 445 * XXX: number of the 2100 FB. At any rate, 446 * XXX: lower cache line size for early revision 447 * XXX; boards. 448 */ 449 linesz = 1; 450 } 451 } 452 #endif 453 #ifndef ISP_DISABLE_2200_SUPPORT 454 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 455 isp->isp_mdvec = &mdvec_2200; 456 isp->isp_type = ISP_HA_FC_2200; 457 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 458 if (isp->isp_param == NULL) { 459 printf(nomem, isp->isp_name); 460 return; 461 } 462 bzero(isp->isp_param, sizeof (fcparam)); 463 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 464 PCI_MBOX_REGS2100_OFF; 465 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 466 } 467 #endif 468 /* 469 * Set up logging levels. 470 */ 471 #ifdef ISP_LOGDEFAULT 472 isp->isp_dblev = ISP_LOGDEFAULT; 473 #else 474 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 475 if (bootverbose) 476 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 477 #ifdef SCSIDEBUG 478 isp->isp_dblev |= ISP_LOGDEBUG1|ISP_LOGDEBUG2; 479 #endif 480 #ifdef DEBUG 481 isp->isp_dblev |= ISP_LOGDEBUG0; 482 #endif 483 #endif 484 485 #ifdef DEBUG 486 if (oneshot) { 487 oneshot = 0; 488 isp_prt(isp, ISP_LOGCONFIG, vstring, 489 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 490 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 491 } 492 #endif 493 494 isp->isp_revision = rev; 495 496 /* 497 * Make sure that command register set sanely. 498 */ 499 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 500 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 501 502 /* 503 * Not so sure about these- but I think it's important that they get 504 * enabled...... 505 */ 506 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 507 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 508 509 /* 510 * Make sure that the latency timer, cache line size, 511 * and ROM is disabled. 512 */ 513 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 514 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 515 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 516 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 517 data |= (linesz << PCI_CACHELINE_SHIFT); 518 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 519 520 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 521 data &= ~1; 522 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 523 524 if (pci_intr_map(pa, &ih)) { 525 printf("%s: couldn't map interrupt\n", isp->isp_name); 526 free(isp->isp_param, M_DEVBUF); 527 return; 528 } 529 intrstr = pci_intr_string(pa->pa_pc, ih); 530 if (intrstr == NULL) 531 intrstr = "<I dunno>"; 532 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 533 isp_pci_intr, isp); 534 if (pcs->pci_ih == NULL) { 535 printf("%s: couldn't establish interrupt at %s\n", 536 isp->isp_name, intrstr); 537 free(isp->isp_param, M_DEVBUF); 538 return; 539 } 540 541 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 542 543 if (IS_FC(isp)) { 544 DEFAULT_NODEWWN(isp) = 0x400000007F000002; 545 DEFAULT_PORTWWN(isp) = 0x400000007F000002; 546 } 547 548 isp->isp_confopts = self->dv_cfdata->cf_flags; 549 isp->isp_role = ISP_DEFAULT_ROLES; 550 ISP_LOCK(isp); 551 isp->isp_osinfo.no_mbox_ints = 1; 552 isp_reset(isp); 553 if (isp->isp_state != ISP_RESETSTATE) { 554 ISP_UNLOCK(isp); 555 free(isp->isp_param, M_DEVBUF); 556 return; 557 } 558 ENABLE_INTS(isp); 559 isp_init(isp); 560 if (isp->isp_state != ISP_INITSTATE) { 561 isp_uninit(isp); 562 ISP_UNLOCK(isp); 563 free(isp->isp_param, M_DEVBUF); 564 return; 565 } 566 /* 567 * Do platform attach. 568 */ 569 ISP_UNLOCK(isp); 570 isp_attach(isp); 571 if (isp->isp_state != ISP_RUNSTATE) { 572 ISP_LOCK(isp); 573 isp_uninit(isp); 574 free(isp->isp_param, M_DEVBUF); 575 ISP_UNLOCK(isp); 576 } 577 } 578 579 static u_int16_t 580 isp_pci_rd_reg(isp, regoff) 581 struct ispsoftc *isp; 582 int regoff; 583 { 584 u_int16_t rv; 585 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 586 int offset, oldconf = 0; 587 588 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 589 /* 590 * We will assume that someone has paused the RISC processor. 591 */ 592 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 593 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 594 delay(250); 595 } 596 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 597 offset += (regoff & 0xff); 598 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 599 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 600 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 601 delay(250); 602 } 603 return (rv); 604 } 605 606 static void 607 isp_pci_wr_reg(isp, regoff, val) 608 struct ispsoftc *isp; 609 int regoff; 610 u_int16_t val; 611 { 612 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 613 int offset, oldconf = 0; 614 615 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 616 /* 617 * We will assume that someone has paused the RISC processor. 618 */ 619 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 620 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 621 delay(250); 622 } 623 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 624 offset += (regoff & 0xff); 625 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 626 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 627 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 628 delay(250); 629 } 630 } 631 632 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 633 static u_int16_t 634 isp_pci_rd_reg_1080(isp, regoff) 635 struct ispsoftc *isp; 636 int regoff; 637 { 638 u_int16_t rv, oc = 0; 639 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 640 int offset; 641 642 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 643 u_int16_t tc; 644 /* 645 * We will assume that someone has paused the RISC processor. 646 */ 647 oc = isp_pci_rd_reg(isp, BIU_CONF1); 648 tc = oc & ~BIU_PCI1080_CONF1_DMA; 649 if (IS_1280(isp)) { 650 if (regoff & SXP_BANK1_SELECT) 651 tc |= BIU_PCI1080_CONF1_SXP0; 652 else 653 tc |= BIU_PCI1080_CONF1_SXP1; 654 } else { 655 tc |= BIU_PCI1080_CONF1_SXP0; 656 } 657 isp_pci_wr_reg(isp, BIU_CONF1, tc); 658 delay(250); 659 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 660 oc = isp_pci_rd_reg(isp, BIU_CONF1); 661 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 662 delay(250); 663 } 664 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 665 offset += (regoff & 0xff); 666 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 667 /* 668 * Okay, because BIU_CONF1 is always nonzero 669 */ 670 if (oc) { 671 isp_pci_wr_reg(isp, BIU_CONF1, oc); 672 delay(250); 673 } 674 return (rv); 675 } 676 677 static void 678 isp_pci_wr_reg_1080(isp, regoff, val) 679 struct ispsoftc *isp; 680 int regoff; 681 u_int16_t val; 682 { 683 u_int16_t oc = 0; 684 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 685 int offset; 686 687 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 688 u_int16_t tc; 689 /* 690 * We will assume that someone has paused the RISC processor. 691 */ 692 oc = isp_pci_rd_reg(isp, BIU_CONF1); 693 tc = oc & ~BIU_PCI1080_CONF1_DMA; 694 if (IS_1280(isp)) { 695 if (regoff & SXP_BANK1_SELECT) 696 tc |= BIU_PCI1080_CONF1_SXP0; 697 else 698 tc |= BIU_PCI1080_CONF1_SXP1; 699 } else { 700 tc |= BIU_PCI1080_CONF1_SXP0; 701 } 702 isp_pci_wr_reg(isp, BIU_CONF1, tc); 703 delay(250); 704 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 705 oc = isp_pci_rd_reg(isp, BIU_CONF1); 706 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 707 delay(250); 708 } 709 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 710 offset += (regoff & 0xff); 711 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 712 /* 713 * Okay, because BIU_CONF1 is always nonzero 714 */ 715 if (oc) { 716 isp_pci_wr_reg(isp, BIU_CONF1, oc); 717 delay(250); 718 } 719 } 720 #endif 721 722 static int 723 isp_pci_mbxdma(isp) 724 struct ispsoftc *isp; 725 { 726 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 727 bus_dma_tag_t dmat = pcs->pci_dmat; 728 bus_dma_segment_t sg; 729 bus_size_t len; 730 fcparam *fcp; 731 int rs, i; 732 733 if (isp->isp_rquest_dma) /* been here before? */ 734 return (0); 735 736 len = isp->isp_maxcmds * sizeof (XS_T); 737 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 738 if (isp->isp_xflist == NULL) { 739 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 740 return (1); 741 } 742 bzero(isp->isp_xflist, len); 743 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 744 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 745 if (pcs->pci_xfer_dmap == NULL) { 746 free(isp->isp_xflist, M_DEVBUF); 747 isp->isp_xflist = NULL; 748 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array"); 749 return (1); 750 } 751 for (i = 0; i < isp->isp_maxcmds; i++) { 752 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 753 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 754 isp_prt(isp, ISP_LOGERR, "cannot create dma maps"); 755 break; 756 } 757 } 758 if (i < isp->isp_maxcmds) { 759 while (--i >= 0) { 760 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 761 } 762 free(isp->isp_xflist, M_DEVBUF); 763 free(pcs->pci_xfer_dmap, M_DEVBUF); 764 isp->isp_xflist = NULL; 765 pcs->pci_xfer_dmap = NULL; 766 return (1); 767 } 768 769 /* 770 * Allocate and map the request queue. 771 */ 772 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 773 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 774 BUS_DMA_NOWAIT) || 775 bus_dmamem_map(pcs->pci_dmat, &sg, rs, len, 776 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 777 goto dmafail; 778 } 779 780 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 781 &pcs->pci_rquest_dmap) || bus_dmamap_load(dmat, 782 pcs->pci_rquest_dmap, (caddr_t)isp->isp_rquest, len, NULL, 783 BUS_DMA_NOWAIT)) { 784 goto dmafail; 785 } 786 787 isp->isp_rquest_dma = pcs->pci_rquest_dmap->dm_segs[0].ds_addr; 788 789 /* 790 * Allocate and map the result queue. 791 */ 792 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 793 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 794 BUS_DMA_NOWAIT) || 795 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 796 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 797 goto dmafail; 798 } 799 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 800 &pcs->pci_result_dmap) || bus_dmamap_load(pcs->pci_dmat, 801 pcs->pci_result_dmap, (caddr_t)isp->isp_result, len, NULL, 802 BUS_DMA_NOWAIT)) { 803 goto dmafail; 804 } 805 isp->isp_result_dma = pcs->pci_result_dmap->dm_segs[0].ds_addr; 806 807 if (IS_SCSI(isp)) { 808 return (0); 809 } 810 811 fcp = isp->isp_param; 812 len = ISP2100_SCRLEN; 813 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 814 BUS_DMA_NOWAIT) || 815 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 816 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 817 goto dmafail; 818 } 819 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 820 &pcs->pci_scratch_dmap) || bus_dmamap_load(dmat, 821 pcs->pci_scratch_dmap, (caddr_t)fcp->isp_scratch, len, NULL, 822 BUS_DMA_NOWAIT)) { 823 goto dmafail; 824 } 825 fcp->isp_scdma = pcs->pci_scratch_dmap->dm_segs[0].ds_addr; 826 return (0); 827 dmafail: 828 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure"); 829 for (i = 0; i < isp->isp_maxcmds; i++) { 830 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 831 } 832 free(isp->isp_xflist, M_DEVBUF); 833 free(pcs->pci_xfer_dmap, M_DEVBUF); 834 isp->isp_xflist = NULL; 835 pcs->pci_xfer_dmap = NULL; 836 return (1); 837 } 838 839 static int 840 isp_pci_dmasetup(isp, xs, rq, iptrp, optr) 841 struct ispsoftc *isp; 842 struct scsipi_xfer *xs; 843 ispreq_t *rq; 844 u_int16_t *iptrp; 845 u_int16_t optr; 846 { 847 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 848 bus_dmamap_t dmap; 849 ispcontreq_t *crq; 850 int segcnt, seg, error, ovseg, seglim, drq; 851 852 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 853 854 if (xs->datalen == 0) { 855 rq->req_seg_count = 1; 856 goto mbxsync; 857 } 858 if (xs->xs_control & XS_CTL_DATA_IN) { 859 drq = REQFLAG_DATA_IN; 860 } else { 861 drq = REQFLAG_DATA_OUT; 862 } 863 864 if (IS_FC(isp)) { 865 seglim = ISP_RQDSEG_T2; 866 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 867 ((ispreqt2_t *)rq)->req_flags |= drq; 868 } else { 869 rq->req_flags |= drq; 870 if (XS_CDBLEN(xs) > 12) { 871 seglim = 0; 872 } else { 873 seglim = ISP_RQDSEG; 874 } 875 } 876 error = bus_dmamap_load(pcs->pci_dmat, dmap, xs->data, xs->datalen, 877 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 878 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING); 879 if (error) { 880 XS_SETERR(xs, HBA_BOTCH); 881 return (CMD_COMPLETE); 882 } 883 884 segcnt = dmap->dm_nsegs; 885 886 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 887 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 888 "write from", xs->data, segcnt); 889 890 for (seg = 0, rq->req_seg_count = 0; 891 seglim && seg < segcnt && rq->req_seg_count < seglim; 892 seg++, rq->req_seg_count++) { 893 if (IS_FC(isp)) { 894 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 895 #if _BYTE_ORDER == _BIG_ENDIAN 896 rq2->req_dataseg[rq2->req_seg_count].ds_count = 897 bswap32(dmap->dm_segs[seg].ds_len); 898 rq2->req_dataseg[rq2->req_seg_count].ds_base = 899 bswap32(dmap->dm_segs[seg].ds_addr); 900 #else 901 rq2->req_dataseg[rq2->req_seg_count].ds_count = 902 dmap->dm_segs[seg].ds_len; 903 rq2->req_dataseg[rq2->req_seg_count].ds_base = 904 dmap->dm_segs[seg].ds_addr; 905 #endif 906 } else { 907 #if _BYTE_ORDER == _BIG_ENDIAN 908 rq->req_dataseg[rq->req_seg_count].ds_count = 909 bswap32(dmap->dm_segs[seg].ds_len); 910 rq->req_dataseg[rq->req_seg_count].ds_base = 911 bswap32(dmap->dm_segs[seg].ds_addr); 912 #else 913 rq->req_dataseg[rq->req_seg_count].ds_count = 914 dmap->dm_segs[seg].ds_len; 915 rq->req_dataseg[rq->req_seg_count].ds_base = 916 dmap->dm_segs[seg].ds_addr; 917 #endif 918 } 919 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 920 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 921 (unsigned long) dmap->dm_segs[seg].ds_len); 922 } 923 924 if (seg == segcnt) 925 goto dmasync; 926 927 do { 928 crq = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp); 929 *iptrp = ISP_NXT_QENTRY(*iptrp, RQUEST_QUEUE_LEN(isp)); 930 if (*iptrp == optr) { 931 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 932 bus_dmamap_unload(pcs->pci_dmat, dmap); 933 XS_SETERR(xs, HBA_BOTCH); 934 return (CMD_EAGAIN); 935 } 936 rq->req_header.rqs_entry_count++; 937 bzero((void *)crq, sizeof (*crq)); 938 crq->req_header.rqs_entry_count = 1; 939 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 940 941 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 942 rq->req_seg_count++, seg++, ovseg++) { 943 #if _BYTE_ORDER == _BIG_ENDIAN 944 crq->req_dataseg[ovseg].ds_count = 945 bswap32(dmap->dm_segs[seg].ds_len); 946 crq->req_dataseg[ovseg].ds_base = 947 bswap32(dmap->dm_segs[seg].ds_addr); 948 #else 949 crq->req_dataseg[ovseg].ds_count = 950 dmap->dm_segs[seg].ds_len; 951 crq->req_dataseg[ovseg].ds_base = 952 dmap->dm_segs[seg].ds_addr; 953 #endif 954 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 955 rq->req_header.rqs_entry_count - 1, 956 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 957 (unsigned long) dmap->dm_segs[seg].ds_len); 958 } 959 } while (seg < segcnt); 960 961 962 dmasync: 963 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 964 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 965 BUS_DMASYNC_PREWRITE); 966 967 mbxsync: 968 ISP_SWIZZLE_REQUEST(isp, rq); 969 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_rquest_dmap, 0, 970 pcs->pci_rquest_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 971 return (CMD_QUEUED); 972 } 973 974 static int 975 isp_pci_intr(arg) 976 void *arg; 977 { 978 int rv; 979 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)arg; 980 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_result_dmap, 0, 981 pcs->pci_result_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 982 pcs->pci_isp.isp_osinfo.onintstack = 1; 983 rv = isp_intr(arg); 984 pcs->pci_isp.isp_osinfo.onintstack = 0; 985 return (rv); 986 } 987 988 static void 989 isp_pci_dmateardown(isp, xs, handle) 990 struct ispsoftc *isp; 991 struct scsipi_xfer *xs; 992 u_int32_t handle; 993 { 994 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 995 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 996 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 997 xs->xs_control & XS_CTL_DATA_IN ? 998 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 999 bus_dmamap_unload(pcs->pci_dmat, dmap); 1000 } 1001 1002 static void 1003 isp_pci_reset1(isp) 1004 struct ispsoftc *isp; 1005 { 1006 /* Make sure the BIOS is disabled */ 1007 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1008 } 1009 1010 static void 1011 isp_pci_dumpregs(isp, msg) 1012 struct ispsoftc *isp; 1013 const char *msg; 1014 { 1015 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1016 if (msg) 1017 printf("%s: %s\n", isp->isp_name, msg); 1018 if (IS_SCSI(isp)) 1019 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1020 else 1021 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1022 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1023 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1024 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1025 1026 1027 if (IS_SCSI(isp)) { 1028 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1029 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1030 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1031 ISP_READ(isp, CDMA_FIFO_STS)); 1032 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1033 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1034 ISP_READ(isp, DDMA_FIFO_STS)); 1035 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1036 ISP_READ(isp, SXP_INTERRUPT), 1037 ISP_READ(isp, SXP_GROSS_ERR), 1038 ISP_READ(isp, SXP_PINS_CTRL)); 1039 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1040 } 1041 printf(" mbox regs: %x %x %x %x %x\n", 1042 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1043 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1044 ISP_READ(isp, OUTMAILBOX4)); 1045 printf(" PCI Status Command/Status=%x\n", 1046 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1047 } 1048
Indexes created Fri Sep 26 20:09:58 GMT 2025