isp_pci.c revision 1.72
1 /* $NetBSD: isp_pci.c,v 1.72 2001/09/01 07:12:25 mjacob Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 */ 33 /* 34 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 35 * All rights reserved. 36 * 37 * Additional Copyright (C) 2000, 2001 by Matthew Jacob 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <dev/ic/isp_netbsd.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 #include <uvm/uvm_extern.h> 64 #include <sys/reboot.h> 65 66 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 67 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 68 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 69 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 70 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 71 #endif 72 static int 73 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 74 static int 75 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 76 static int isp_pci_mbxdma(struct ispsoftc *); 77 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, 78 u_int16_t *, u_int16_t); 79 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 80 static void isp_pci_reset1(struct ispsoftc *); 81 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 82 static int isp_pci_intr(void *); 83 84 #if defined(ISP_DISABLE_1020_SUPPORT) 85 #define ISP_1040_RISC_CODE NULL 86 #else 87 #define ISP_1040_RISC_CODE isp_1040_risc_code 88 #include <dev/microcode/isp/asm_1040.h> 89 #endif 90 91 #if defined(ISP_DISABLE_1080_SUPPORT) 92 #define ISP_1080_RISC_CODE NULL 93 #else 94 #define ISP_1080_RISC_CODE isp_1080_risc_code 95 #include <dev/microcode/isp/asm_1080.h> 96 #endif 97 98 #if defined(ISP_DISABLE_12160_SUPPORT) 99 #define ISP_12160_RISC_CODE NULL 100 #else 101 #define ISP_12160_RISC_CODE isp_12160_risc_code 102 #include <dev/microcode/isp/asm_12160.h> 103 #endif 104 105 #if defined(ISP_DISABLE_2100_SUPPORT) 106 #define ISP_2100_RISC_CODE NULL 107 #else 108 #define ISP_2100_RISC_CODE isp_2100_risc_code 109 #include <dev/microcode/isp/asm_2100.h> 110 #endif 111 112 #if defined(ISP_DISABLE_2200_SUPPORT) 113 #define ISP_2200_RISC_CODE NULL 114 #else 115 #define ISP_2200_RISC_CODE isp_2200_risc_code 116 #include <dev/microcode/isp/asm_2200.h> 117 #endif 118 119 #if defined(ISP_DISABLE_2300_SUPPORT) 120 #define ISP_2300_RISC_CODE NULL 121 #else 122 #define ISP_2300_RISC_CODE isp_2300_risc_code 123 #include <dev/microcode/isp/asm_2300.h> 124 #endif 125 126 #ifndef ISP_DISABLE_1020_SUPPORT 127 static struct ispmdvec mdvec = { 128 isp_pci_rd_isr, 129 isp_pci_rd_reg, 130 isp_pci_wr_reg, 131 isp_pci_mbxdma, 132 isp_pci_dmasetup, 133 isp_pci_dmateardown, 134 NULL, 135 isp_pci_reset1, 136 isp_pci_dumpregs, 137 ISP_1040_RISC_CODE, 138 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 139 }; 140 #endif 141 142 #ifndef ISP_DISABLE_1080_SUPPORT 143 static struct ispmdvec mdvec_1080 = { 144 isp_pci_rd_isr, 145 isp_pci_rd_reg_1080, 146 isp_pci_wr_reg_1080, 147 isp_pci_mbxdma, 148 isp_pci_dmasetup, 149 isp_pci_dmateardown, 150 NULL, 151 isp_pci_reset1, 152 isp_pci_dumpregs, 153 ISP_1080_RISC_CODE, 154 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 155 }; 156 #endif 157 158 #ifndef ISP_DISABLE_12160_SUPPORT 159 static struct ispmdvec mdvec_12160 = { 160 isp_pci_rd_isr, 161 isp_pci_rd_reg_1080, 162 isp_pci_wr_reg_1080, 163 isp_pci_mbxdma, 164 isp_pci_dmasetup, 165 isp_pci_dmateardown, 166 NULL, 167 isp_pci_reset1, 168 isp_pci_dumpregs, 169 ISP_12160_RISC_CODE, 170 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 171 }; 172 #endif 173 174 #ifndef ISP_DISABLE_2100_SUPPORT 175 static struct ispmdvec mdvec_2100 = { 176 isp_pci_rd_isr, 177 isp_pci_rd_reg, 178 isp_pci_wr_reg, 179 isp_pci_mbxdma, 180 isp_pci_dmasetup, 181 isp_pci_dmateardown, 182 NULL, 183 isp_pci_reset1, 184 isp_pci_dumpregs, 185 ISP_2100_RISC_CODE 186 }; 187 #endif 188 189 #ifndef ISP_DISABLE_2200_SUPPORT 190 static struct ispmdvec mdvec_2200 = { 191 isp_pci_rd_isr, 192 isp_pci_rd_reg, 193 isp_pci_wr_reg, 194 isp_pci_mbxdma, 195 isp_pci_dmasetup, 196 isp_pci_dmateardown, 197 NULL, 198 isp_pci_reset1, 199 isp_pci_dumpregs, 200 ISP_2200_RISC_CODE 201 }; 202 #endif 203 204 #ifndef ISP_DISABLE_2300_SUPPORT 205 static struct ispmdvec mdvec_2300 = { 206 isp_pci_rd_isr_2300, 207 isp_pci_rd_reg, 208 isp_pci_wr_reg, 209 isp_pci_mbxdma, 210 isp_pci_dmasetup, 211 isp_pci_dmateardown, 212 NULL, 213 isp_pci_reset1, 214 isp_pci_dumpregs, 215 ISP_2300_RISC_CODE 216 }; 217 #endif 218 219 #ifndef PCI_VENDOR_QLOGIC 220 #define PCI_VENDOR_QLOGIC 0x1077 221 #endif 222 223 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 224 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 225 #endif 226 227 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 228 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 229 #endif 230 231 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 232 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 233 #endif 234 235 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 236 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 237 #endif 238 239 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 240 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 241 #endif 242 243 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 244 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 245 #endif 246 247 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 248 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 249 #endif 250 251 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 252 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 253 #endif 254 255 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 256 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 257 #endif 258 259 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 260 261 #define PCI_QLOGIC_ISP1080 \ 262 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 263 264 #define PCI_QLOGIC_ISP1240 \ 265 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 266 267 #define PCI_QLOGIC_ISP1280 \ 268 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 269 270 #define PCI_QLOGIC_ISP12160 \ 271 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 272 273 #define PCI_QLOGIC_ISP2100 \ 274 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 275 276 #define PCI_QLOGIC_ISP2200 \ 277 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 278 279 #define PCI_QLOGIC_ISP2300 \ 280 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP2312 \ 283 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define IO_MAP_REG 0x10 286 #define MEM_MAP_REG 0x14 287 #define PCIR_ROMADDR 0x30 288 289 #define PCI_DFLT_LTNCY 0x40 290 #define PCI_DFLT_LNSZ 0x10 291 292 293 static int isp_pci_probe(struct device *, struct cfdata *, void *); 294 static void isp_pci_attach(struct device *, struct device *, void *); 295 296 struct isp_pcisoftc { 297 struct ispsoftc pci_isp; 298 pci_chipset_tag_t pci_pc; 299 pcitag_t pci_tag; 300 bus_space_tag_t pci_st; 301 bus_space_handle_t pci_sh; 302 bus_dma_tag_t pci_dmat; 303 bus_dmamap_t pci_scratch_dmap; /* for fcp only */ 304 bus_dmamap_t pci_rquest_dmap; 305 bus_dmamap_t pci_result_dmap; 306 bus_dmamap_t *pci_xfer_dmap; 307 void * pci_ih; 308 int16_t pci_poff[_NREG_BLKS]; 309 }; 310 311 struct cfattach isp_pci_ca = { 312 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach 313 }; 314 315 #ifdef DEBUG 316 const char vstring[] = 317 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 318 #endif 319 320 static int 321 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux) 322 { 323 struct pci_attach_args *pa = aux; 324 switch (pa->pa_id) { 325 #ifndef ISP_DISABLE_1020_SUPPORT 326 case PCI_QLOGIC_ISP: 327 return (1); 328 #endif 329 #ifndef ISP_DISABLE_1080_SUPPORT 330 case PCI_QLOGIC_ISP1080: 331 case PCI_QLOGIC_ISP1240: 332 case PCI_QLOGIC_ISP1280: 333 return (1); 334 #endif 335 #ifndef ISP_DISABLE_12160_SUPPORT 336 case PCI_QLOGIC_ISP12160: 337 return (1); 338 #endif 339 #ifndef ISP_DISABLE_2100_SUPPORT 340 case PCI_QLOGIC_ISP2100: 341 return (1); 342 #endif 343 #ifndef ISP_DISABLE_2200_SUPPORT 344 case PCI_QLOGIC_ISP2200: 345 return (1); 346 #endif 347 #ifndef ISP_DISABLE_2300_SUPPORT 348 case PCI_QLOGIC_ISP2300: 349 case PCI_QLOGIC_ISP2312: 350 return (1); 351 #endif 352 default: 353 return (0); 354 } 355 } 356 357 358 static void 359 isp_pci_attach(struct device *parent, struct device *self, void *aux) 360 { 361 #ifdef DEBUG 362 static char oneshot = 1; 363 #endif 364 static const char nomem[] = "%s: no mem for sdparam table\n"; 365 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 366 struct pci_attach_args *pa = aux; 367 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 368 struct ispsoftc *isp = &pcs->pci_isp; 369 bus_space_tag_t st, iot, memt; 370 bus_space_handle_t sh, ioh, memh; 371 pci_intr_handle_t ih; 372 const char *intrstr; 373 int ioh_valid, memh_valid; 374 375 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 376 PCI_MAPREG_TYPE_IO, 0, 377 &iot, &ioh, NULL, NULL) == 0); 378 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 379 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 380 &memt, &memh, NULL, NULL) == 0); 381 if (memh_valid) { 382 st = memt; 383 sh = memh; 384 } else if (ioh_valid) { 385 st = iot; 386 sh = ioh; 387 } else { 388 printf(": unable to map device registers\n"); 389 return; 390 } 391 printf("\n"); 392 393 pcs->pci_st = st; 394 pcs->pci_sh = sh; 395 pcs->pci_dmat = pa->pa_dmat; 396 pcs->pci_pc = pa->pa_pc; 397 pcs->pci_tag = pa->pa_tag; 398 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 399 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 400 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 401 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 402 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 403 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 404 405 #ifndef ISP_DISABLE_1020_SUPPORT 406 if (pa->pa_id == PCI_QLOGIC_ISP) { 407 isp->isp_mdvec = &mdvec; 408 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 409 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 410 if (isp->isp_param == NULL) { 411 printf(nomem, isp->isp_name); 412 return; 413 } 414 memset(isp->isp_param, 0, sizeof (sdparam)); 415 } 416 #endif 417 #ifndef ISP_DISABLE_1080_SUPPORT 418 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 419 isp->isp_mdvec = &mdvec_1080; 420 isp->isp_type = ISP_HA_SCSI_1080; 421 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 422 if (isp->isp_param == NULL) { 423 printf(nomem, isp->isp_name); 424 return; 425 } 426 memset(isp->isp_param, 0, sizeof (sdparam)); 427 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 428 ISP1080_DMA_REGS_OFF; 429 } 430 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 431 isp->isp_mdvec = &mdvec_1080; 432 isp->isp_type = ISP_HA_SCSI_1240; 433 isp->isp_param = 434 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 435 if (isp->isp_param == NULL) { 436 printf(nomem, isp->isp_name); 437 return; 438 } 439 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 440 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 441 ISP1080_DMA_REGS_OFF; 442 } 443 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 444 isp->isp_mdvec = &mdvec_1080; 445 isp->isp_type = ISP_HA_SCSI_1280; 446 isp->isp_param = 447 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 448 if (isp->isp_param == NULL) { 449 printf(nomem, isp->isp_name); 450 return; 451 } 452 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 453 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 454 ISP1080_DMA_REGS_OFF; 455 } 456 #endif 457 #ifndef ISP_DISABLE_12160_SUPPORT 458 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 459 isp->isp_mdvec = &mdvec_12160; 460 isp->isp_type = ISP_HA_SCSI_12160; 461 isp->isp_param = 462 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 463 if (isp->isp_param == NULL) { 464 printf(nomem, isp->isp_name); 465 return; 466 } 467 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 468 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 469 ISP1080_DMA_REGS_OFF; 470 } 471 #endif 472 #ifndef ISP_DISABLE_2100_SUPPORT 473 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 474 isp->isp_mdvec = &mdvec_2100; 475 isp->isp_type = ISP_HA_FC_2100; 476 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 477 if (isp->isp_param == NULL) { 478 printf(nomem, isp->isp_name); 479 return; 480 } 481 memset(isp->isp_param, 0, sizeof (fcparam)); 482 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 483 PCI_MBOX_REGS2100_OFF; 484 if (rev < 3) { 485 /* 486 * XXX: Need to get the actual revision 487 * XXX: number of the 2100 FB. At any rate, 488 * XXX: lower cache line size for early revision 489 * XXX; boards. 490 */ 491 linesz = 1; 492 } 493 } 494 #endif 495 #ifndef ISP_DISABLE_2200_SUPPORT 496 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 497 isp->isp_mdvec = &mdvec_2200; 498 isp->isp_type = ISP_HA_FC_2200; 499 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 500 if (isp->isp_param == NULL) { 501 printf(nomem, isp->isp_name); 502 return; 503 } 504 memset(isp->isp_param, 0, sizeof (fcparam)); 505 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 506 PCI_MBOX_REGS2100_OFF; 507 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 508 } 509 #endif 510 #ifndef ISP_DISABLE_2300_SUPPORT 511 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 512 pa->pa_id == PCI_QLOGIC_ISP2312) { 513 isp->isp_mdvec = &mdvec_2300; 514 isp->isp_type = ISP_HA_FC_2300; 515 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 516 if (isp->isp_param == NULL) { 517 printf(nomem, isp->isp_name); 518 return; 519 } 520 memset(isp->isp_param, 0, sizeof (fcparam)); 521 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 522 PCI_MBOX_REGS2300_OFF; 523 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 524 } 525 #endif 526 /* 527 * Set up logging levels. 528 */ 529 #ifdef ISP_LOGDEFAULT 530 isp->isp_dblev = ISP_LOGDEFAULT; 531 #else 532 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 533 if (bootverbose) 534 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 535 #ifdef SCSIDEBUG 536 isp->isp_dblev |= ISP_LOGDEBUG1|ISP_LOGDEBUG2; 537 #endif 538 #ifdef DEBUG 539 isp->isp_dblev |= ISP_LOGDEBUG0; 540 #endif 541 #endif 542 543 #ifdef DEBUG 544 if (oneshot) { 545 oneshot = 0; 546 isp_prt(isp, ISP_LOGCONFIG, vstring, 547 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 548 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 549 } 550 #endif 551 552 isp->isp_revision = rev; 553 554 /* 555 * Make sure that command register set sanely. 556 */ 557 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 558 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 559 560 /* 561 * Not so sure about these- but I think it's important that they get 562 * enabled...... 563 */ 564 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 565 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 566 567 /* 568 * Make sure that the latency timer, cache line size, 569 * and ROM is disabled. 570 */ 571 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 572 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 573 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 574 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 575 data |= (linesz << PCI_CACHELINE_SHIFT); 576 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 577 578 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 579 data &= ~1; 580 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 581 582 if (pci_intr_map(pa, &ih)) { 583 printf("%s: couldn't map interrupt\n", isp->isp_name); 584 free(isp->isp_param, M_DEVBUF); 585 return; 586 } 587 intrstr = pci_intr_string(pa->pa_pc, ih); 588 if (intrstr == NULL) 589 intrstr = "<I dunno>"; 590 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 591 isp_pci_intr, isp); 592 if (pcs->pci_ih == NULL) { 593 printf("%s: couldn't establish interrupt at %s\n", 594 isp->isp_name, intrstr); 595 free(isp->isp_param, M_DEVBUF); 596 return; 597 } 598 599 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 600 601 if (IS_FC(isp)) { 602 DEFAULT_NODEWWN(isp) = 0x400000007F000002; 603 DEFAULT_PORTWWN(isp) = 0x400000007F000002; 604 } 605 606 isp->isp_confopts = self->dv_cfdata->cf_flags; 607 isp->isp_role = ISP_DEFAULT_ROLES; 608 ISP_LOCK(isp); 609 isp->isp_osinfo.no_mbox_ints = 1; 610 isp_reset(isp); 611 if (isp->isp_state != ISP_RESETSTATE) { 612 ISP_UNLOCK(isp); 613 free(isp->isp_param, M_DEVBUF); 614 return; 615 } 616 ENABLE_INTS(isp); 617 isp_init(isp); 618 if (isp->isp_state != ISP_INITSTATE) { 619 isp_uninit(isp); 620 ISP_UNLOCK(isp); 621 free(isp->isp_param, M_DEVBUF); 622 return; 623 } 624 /* 625 * Do platform attach. 626 */ 627 ISP_UNLOCK(isp); 628 isp_attach(isp); 629 if (isp->isp_state != ISP_RUNSTATE) { 630 ISP_LOCK(isp); 631 isp_uninit(isp); 632 free(isp->isp_param, M_DEVBUF); 633 ISP_UNLOCK(isp); 634 } 635 } 636 637 #define IspVirt2Off(a, x) \ 638 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 639 _BLK_REG_SHFT] + ((x) & 0xff)) 640 641 #define BXR2(pcs, off) \ 642 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 643 #define BXW2(pcs, off, v) \ 644 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 645 646 647 static INLINE int 648 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 649 { 650 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 651 u_int16_t val0, val1; 652 int i = 0; 653 654 do { 655 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 656 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 657 } while (val0 != val1 && ++i < 1000); 658 if (val0 != val1) { 659 return (1); 660 } 661 *rp = val0; 662 return (0); 663 } 664 665 static int 666 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 667 u_int16_t *semap, u_int16_t *mbp) 668 { 669 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 670 u_int16_t isr, sema; 671 672 if (IS_2100(isp)) { 673 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 674 return (0); 675 } 676 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 677 return (0); 678 } 679 } else { 680 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 681 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 682 } 683 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 684 isr &= INT_PENDING_MASK(isp); 685 sema &= BIU_SEMA_LOCK; 686 if (isr == 0 && sema == 0) { 687 return (0); 688 } 689 *isrp = isr; 690 if ((*semap = sema) != 0) { 691 if (IS_2100(isp)) { 692 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 693 return (0); 694 } 695 } else { 696 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 697 } 698 } 699 return (1); 700 } 701 702 #ifndef ISP_DISABLE_2300_SUPPORT 703 static int 704 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 705 u_int16_t *semap, u_int16_t *mbox0p) 706 { 707 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 708 u_int32_t r2hisr; 709 710 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 711 IspVirt2Off(pcs, BIU_R2HSTSLO)); 712 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 713 if ((r2hisr & BIU_R2HST_INTR) == 0) { 714 *isrp = 0; 715 return (0); 716 } 717 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 718 case ISPR2HST_ROM_MBX_OK: 719 case ISPR2HST_ROM_MBX_FAIL: 720 case ISPR2HST_MBX_OK: 721 case ISPR2HST_MBX_FAIL: 722 case ISPR2HST_ASYNC_EVENT: 723 case ISPR2HST_FPOST: 724 case ISPR2HST_FPOST_CTIO: 725 *isrp = r2hisr & 0xffff; 726 *mbox0p = (r2hisr >> 16); 727 *semap = 1; 728 return (1); 729 case ISPR2HST_RSPQ_UPDATE: 730 *isrp = r2hisr & 0xffff; 731 *mbox0p = 0; 732 *semap = 0; 733 return (1); 734 default: 735 return (0); 736 } 737 } 738 #endif 739 740 static u_int16_t 741 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 742 { 743 u_int16_t rv; 744 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 745 int oldconf = 0; 746 747 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 748 /* 749 * We will assume that someone has paused the RISC processor. 750 */ 751 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 752 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 753 oldconf | BIU_PCI_CONF1_SXP); 754 } 755 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 756 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 757 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 758 } 759 return (rv); 760 } 761 762 static void 763 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 764 { 765 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 766 int oldconf = 0; 767 768 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 769 /* 770 * We will assume that someone has paused the RISC processor. 771 */ 772 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 773 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 774 oldconf | BIU_PCI_CONF1_SXP); 775 } 776 BXW2(pcs, IspVirt2Off(isp, regoff), val); 777 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 778 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 779 } 780 } 781 782 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 783 static u_int16_t 784 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 785 { 786 u_int16_t rv, oc = 0; 787 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 788 789 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 790 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 791 u_int16_t tc; 792 /* 793 * We will assume that someone has paused the RISC processor. 794 */ 795 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 796 tc = oc & ~BIU_PCI1080_CONF1_DMA; 797 if (regoff & SXP_BANK1_SELECT) 798 tc |= BIU_PCI1080_CONF1_SXP1; 799 else 800 tc |= BIU_PCI1080_CONF1_SXP0; 801 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 802 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 803 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 804 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 805 oc | BIU_PCI1080_CONF1_DMA); 806 } 807 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 808 if (oc) { 809 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 810 } 811 return (rv); 812 } 813 814 static void 815 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 816 { 817 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 818 int oc = 0; 819 820 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 821 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 822 u_int16_t tc; 823 /* 824 * We will assume that someone has paused the RISC processor. 825 */ 826 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 827 tc = oc & ~BIU_PCI1080_CONF1_DMA; 828 if (regoff & SXP_BANK1_SELECT) 829 tc |= BIU_PCI1080_CONF1_SXP1; 830 else 831 tc |= BIU_PCI1080_CONF1_SXP0; 832 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 833 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 834 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 835 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 836 oc | BIU_PCI1080_CONF1_DMA); 837 } 838 BXW2(pcs, IspVirt2Off(isp, regoff), val); 839 if (oc) { 840 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 841 } 842 } 843 #endif 844 845 static int 846 isp_pci_mbxdma(struct ispsoftc *isp) 847 { 848 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 849 bus_dma_tag_t dmat = pcs->pci_dmat; 850 bus_dma_segment_t sg; 851 bus_size_t len; 852 fcparam *fcp; 853 int rs, i; 854 855 if (isp->isp_rquest_dma) /* been here before? */ 856 return (0); 857 858 len = isp->isp_maxcmds * sizeof (XS_T *); 859 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 860 if (isp->isp_xflist == NULL) { 861 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 862 return (1); 863 } 864 memset(isp->isp_xflist, 0, len); 865 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 866 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 867 if (pcs->pci_xfer_dmap == NULL) { 868 free(isp->isp_xflist, M_DEVBUF); 869 isp->isp_xflist = NULL; 870 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array"); 871 return (1); 872 } 873 for (i = 0; i < isp->isp_maxcmds; i++) { 874 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 875 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 876 isp_prt(isp, ISP_LOGERR, "cannot create dma maps"); 877 break; 878 } 879 } 880 if (i < isp->isp_maxcmds) { 881 while (--i >= 0) { 882 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 883 } 884 free(isp->isp_xflist, M_DEVBUF); 885 free(pcs->pci_xfer_dmap, M_DEVBUF); 886 isp->isp_xflist = NULL; 887 pcs->pci_xfer_dmap = NULL; 888 return (1); 889 } 890 891 /* 892 * Allocate and map the request queue. 893 */ 894 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 895 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 896 BUS_DMA_NOWAIT) || 897 bus_dmamem_map(pcs->pci_dmat, &sg, rs, len, 898 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 899 goto dmafail; 900 } 901 902 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 903 &pcs->pci_rquest_dmap) || bus_dmamap_load(dmat, 904 pcs->pci_rquest_dmap, (caddr_t)isp->isp_rquest, len, NULL, 905 BUS_DMA_NOWAIT)) { 906 goto dmafail; 907 } 908 909 isp->isp_rquest_dma = pcs->pci_rquest_dmap->dm_segs[0].ds_addr; 910 911 /* 912 * Allocate and map the result queue. 913 */ 914 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 915 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 916 BUS_DMA_NOWAIT) || 917 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 918 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 919 goto dmafail; 920 } 921 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 922 &pcs->pci_result_dmap) || bus_dmamap_load(pcs->pci_dmat, 923 pcs->pci_result_dmap, (caddr_t)isp->isp_result, len, NULL, 924 BUS_DMA_NOWAIT)) { 925 goto dmafail; 926 } 927 isp->isp_result_dma = pcs->pci_result_dmap->dm_segs[0].ds_addr; 928 929 if (IS_SCSI(isp)) { 930 return (0); 931 } 932 933 fcp = isp->isp_param; 934 len = ISP2100_SCRLEN; 935 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 936 BUS_DMA_NOWAIT) || 937 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 938 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 939 goto dmafail; 940 } 941 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 942 &pcs->pci_scratch_dmap) || bus_dmamap_load(dmat, 943 pcs->pci_scratch_dmap, (caddr_t)fcp->isp_scratch, len, NULL, 944 BUS_DMA_NOWAIT)) { 945 goto dmafail; 946 } 947 fcp->isp_scdma = pcs->pci_scratch_dmap->dm_segs[0].ds_addr; 948 return (0); 949 dmafail: 950 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure"); 951 for (i = 0; i < isp->isp_maxcmds; i++) { 952 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 953 } 954 free(isp->isp_xflist, M_DEVBUF); 955 free(pcs->pci_xfer_dmap, M_DEVBUF); 956 isp->isp_xflist = NULL; 957 pcs->pci_xfer_dmap = NULL; 958 return (1); 959 } 960 961 static int 962 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq, 963 u_int16_t *iptrp, u_int16_t optr) 964 { 965 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 966 bus_dmamap_t dmap; 967 ispcontreq_t *crq; 968 int segcnt, seg, error, ovseg, seglim, drq; 969 970 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 971 972 if (xs->datalen == 0) { 973 rq->req_seg_count = 1; 974 goto mbxsync; 975 } 976 if (xs->xs_control & XS_CTL_DATA_IN) { 977 drq = REQFLAG_DATA_IN; 978 } else { 979 drq = REQFLAG_DATA_OUT; 980 } 981 982 if (IS_FC(isp)) { 983 seglim = ISP_RQDSEG_T2; 984 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 985 ((ispreqt2_t *)rq)->req_flags |= drq; 986 } else { 987 rq->req_flags |= drq; 988 if (XS_CDBLEN(xs) > 12) { 989 seglim = 0; 990 } else { 991 seglim = ISP_RQDSEG; 992 } 993 } 994 error = bus_dmamap_load(pcs->pci_dmat, dmap, xs->data, xs->datalen, 995 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 996 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 997 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE)); 998 if (error) { 999 XS_SETERR(xs, HBA_BOTCH); 1000 return (CMD_COMPLETE); 1001 } 1002 1003 segcnt = dmap->dm_nsegs; 1004 1005 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 1006 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 1007 "write from", xs->data, segcnt); 1008 1009 for (seg = 0, rq->req_seg_count = 0; 1010 seglim && seg < segcnt && rq->req_seg_count < seglim; 1011 seg++, rq->req_seg_count++) { 1012 if (IS_FC(isp)) { 1013 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1014 #if _BYTE_ORDER == _BIG_ENDIAN 1015 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1016 bswap32(dmap->dm_segs[seg].ds_len); 1017 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1018 bswap32(dmap->dm_segs[seg].ds_addr); 1019 #else 1020 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1021 dmap->dm_segs[seg].ds_len; 1022 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1023 dmap->dm_segs[seg].ds_addr; 1024 #endif 1025 } else { 1026 #if _BYTE_ORDER == _BIG_ENDIAN 1027 rq->req_dataseg[rq->req_seg_count].ds_count = 1028 bswap32(dmap->dm_segs[seg].ds_len); 1029 rq->req_dataseg[rq->req_seg_count].ds_base = 1030 bswap32(dmap->dm_segs[seg].ds_addr); 1031 #else 1032 rq->req_dataseg[rq->req_seg_count].ds_count = 1033 dmap->dm_segs[seg].ds_len; 1034 rq->req_dataseg[rq->req_seg_count].ds_base = 1035 dmap->dm_segs[seg].ds_addr; 1036 #endif 1037 } 1038 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 1039 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 1040 (unsigned long) dmap->dm_segs[seg].ds_len); 1041 } 1042 1043 if (seg == segcnt) 1044 goto dmasync; 1045 1046 do { 1047 crq = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp); 1048 *iptrp = ISP_NXT_QENTRY(*iptrp, RQUEST_QUEUE_LEN(isp)); 1049 if (*iptrp == optr) { 1050 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1051 bus_dmamap_unload(pcs->pci_dmat, dmap); 1052 XS_SETERR(xs, HBA_BOTCH); 1053 return (CMD_EAGAIN); 1054 } 1055 rq->req_header.rqs_entry_count++; 1056 memset((void *)crq, 0, sizeof (*crq)); 1057 crq->req_header.rqs_entry_count = 1; 1058 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1059 1060 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 1061 rq->req_seg_count++, seg++, ovseg++) { 1062 #if _BYTE_ORDER == _BIG_ENDIAN 1063 crq->req_dataseg[ovseg].ds_count = 1064 bswap32(dmap->dm_segs[seg].ds_len); 1065 crq->req_dataseg[ovseg].ds_base = 1066 bswap32(dmap->dm_segs[seg].ds_addr); 1067 #else 1068 crq->req_dataseg[ovseg].ds_count = 1069 dmap->dm_segs[seg].ds_len; 1070 crq->req_dataseg[ovseg].ds_base = 1071 dmap->dm_segs[seg].ds_addr; 1072 #endif 1073 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 1074 rq->req_header.rqs_entry_count - 1, 1075 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 1076 (unsigned long) dmap->dm_segs[seg].ds_len); 1077 } 1078 } while (seg < segcnt); 1079 1080 1081 dmasync: 1082 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 1083 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 1084 BUS_DMASYNC_PREWRITE); 1085 1086 mbxsync: 1087 ISP_SWIZZLE_REQUEST(isp, rq); 1088 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_rquest_dmap, 0, 1089 pcs->pci_rquest_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1090 return (CMD_QUEUED); 1091 } 1092 1093 static int 1094 isp_pci_intr(void *arg) 1095 { 1096 u_int16_t isr, sema, mbox; 1097 struct ispsoftc *isp = arg; 1098 1099 isp->isp_intcnt++; 1100 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1101 isp->isp_intbogus++; 1102 return (0); 1103 } else { 1104 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)arg; 1105 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_result_dmap, 0, 1106 pcs->pci_result_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1107 isp->isp_osinfo.onintstack = 1; 1108 isp_intr(isp, isr, sema, mbox); 1109 isp->isp_osinfo.onintstack = 0; 1110 return (1); 1111 } 1112 } 1113 1114 static void 1115 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1116 { 1117 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1118 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 1119 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 1120 xs->xs_control & XS_CTL_DATA_IN ? 1121 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1122 bus_dmamap_unload(pcs->pci_dmat, dmap); 1123 } 1124 1125 static void 1126 isp_pci_reset1(struct ispsoftc *isp) 1127 { 1128 /* Make sure the BIOS is disabled */ 1129 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1130 } 1131 1132 static void 1133 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1134 { 1135 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1136 if (msg) 1137 printf("%s: %s\n", isp->isp_name, msg); 1138 if (IS_SCSI(isp)) 1139 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1140 else 1141 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1142 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1143 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1144 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1145 1146 1147 if (IS_SCSI(isp)) { 1148 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1149 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1150 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1151 ISP_READ(isp, CDMA_FIFO_STS)); 1152 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1153 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1154 ISP_READ(isp, DDMA_FIFO_STS)); 1155 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1156 ISP_READ(isp, SXP_INTERRUPT), 1157 ISP_READ(isp, SXP_GROSS_ERR), 1158 ISP_READ(isp, SXP_PINS_CTRL)); 1159 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1160 } 1161 printf(" mbox regs: %x %x %x %x %x\n", 1162 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1163 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1164 ISP_READ(isp, OUTMAILBOX4)); 1165 printf(" PCI Status Command/Status=%x\n", 1166 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1167 } 1168
Indexes created Thu Sep 25 16:09:42 GMT 2025