isp_pci.c revision 1.72.2.1 1 /* $NetBSD: isp_pci.c,v 1.72.2.1 2001/10/11 00:02:10 fvdl Exp $ */
2 /*
3 * This driver, which is contained in NetBSD in the files:
4 *
5 * sys/dev/ic/isp.c
6 * sys/dev/ic/isp_inline.h
7 * sys/dev/ic/isp_netbsd.c
8 * sys/dev/ic/isp_netbsd.h
9 * sys/dev/ic/isp_target.c
10 * sys/dev/ic/isp_target.h
11 * sys/dev/ic/isp_tpublic.h
12 * sys/dev/ic/ispmbox.h
13 * sys/dev/ic/ispreg.h
14 * sys/dev/ic/ispvar.h
15 * sys/microcode/isp/asm_sbus.h
16 * sys/microcode/isp/asm_1040.h
17 * sys/microcode/isp/asm_1080.h
18 * sys/microcode/isp/asm_12160.h
19 * sys/microcode/isp/asm_2100.h
20 * sys/microcode/isp/asm_2200.h
21 * sys/pci/isp_pci.c
22 * sys/sbus/isp_sbus.c
23 *
24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org).
25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris,
26 * Linux versions. This tends to be an interesting maintenance problem.
27 *
28 * Please coordinate with Matthew Jacob on changes you wish to make here.
29 */
30 /*
31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
32 */
33 /*
34 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration
35 * All rights reserved.
36 *
37 * Additional Copyright (C) 2000, 2001 by Matthew Jacob
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * 2. The name of the author may not be used to endorse or promote products
45 * derived from this software without specific prior written permission
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 #include <dev/ic/isp_netbsd.h>
60 #include <dev/pci/pcireg.h>
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcidevs.h>
63 #include <uvm/uvm_extern.h>
64 #include <sys/reboot.h>
65
66 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int);
67 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t);
68 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
69 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int);
70 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t);
71 #endif
72 static int
73 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *);
74 static int
75 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *);
76 static int isp_pci_mbxdma(struct ispsoftc *);
77 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *,
78 u_int16_t *, u_int16_t);
79 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t);
80 static void isp_pci_reset1(struct ispsoftc *);
81 static void isp_pci_dumpregs(struct ispsoftc *, const char *);
82 static int isp_pci_intr(void *);
83
84 #if defined(ISP_DISABLE_1020_SUPPORT)
85 #define ISP_1040_RISC_CODE NULL
86 #else
87 #define ISP_1040_RISC_CODE isp_1040_risc_code
88 #include <dev/microcode/isp/asm_1040.h>
89 #endif
90
91 #if defined(ISP_DISABLE_1080_SUPPORT)
92 #define ISP_1080_RISC_CODE NULL
93 #else
94 #define ISP_1080_RISC_CODE isp_1080_risc_code
95 #include <dev/microcode/isp/asm_1080.h>
96 #endif
97
98 #if defined(ISP_DISABLE_12160_SUPPORT)
99 #define ISP_12160_RISC_CODE NULL
100 #else
101 #define ISP_12160_RISC_CODE isp_12160_risc_code
102 #include <dev/microcode/isp/asm_12160.h>
103 #endif
104
105 #if defined(ISP_DISABLE_2100_SUPPORT)
106 #define ISP_2100_RISC_CODE NULL
107 #else
108 #define ISP_2100_RISC_CODE isp_2100_risc_code
109 #include <dev/microcode/isp/asm_2100.h>
110 #endif
111
112 #if defined(ISP_DISABLE_2200_SUPPORT)
113 #define ISP_2200_RISC_CODE NULL
114 #else
115 #define ISP_2200_RISC_CODE isp_2200_risc_code
116 #include <dev/microcode/isp/asm_2200.h>
117 #endif
118
119 #if defined(ISP_DISABLE_2300_SUPPORT)
120 #define ISP_2300_RISC_CODE NULL
121 #else
122 #define ISP_2300_RISC_CODE isp_2300_risc_code
123 #include <dev/microcode/isp/asm_2300.h>
124 #endif
125
126 #ifndef ISP_DISABLE_1020_SUPPORT
127 static struct ispmdvec mdvec = {
128 isp_pci_rd_isr,
129 isp_pci_rd_reg,
130 isp_pci_wr_reg,
131 isp_pci_mbxdma,
132 isp_pci_dmasetup,
133 isp_pci_dmateardown,
134 NULL,
135 isp_pci_reset1,
136 isp_pci_dumpregs,
137 ISP_1040_RISC_CODE,
138 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
139 };
140 #endif
141
142 #ifndef ISP_DISABLE_1080_SUPPORT
143 static struct ispmdvec mdvec_1080 = {
144 isp_pci_rd_isr,
145 isp_pci_rd_reg_1080,
146 isp_pci_wr_reg_1080,
147 isp_pci_mbxdma,
148 isp_pci_dmasetup,
149 isp_pci_dmateardown,
150 NULL,
151 isp_pci_reset1,
152 isp_pci_dumpregs,
153 ISP_1080_RISC_CODE,
154 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
155 };
156 #endif
157
158 #ifndef ISP_DISABLE_12160_SUPPORT
159 static struct ispmdvec mdvec_12160 = {
160 isp_pci_rd_isr,
161 isp_pci_rd_reg_1080,
162 isp_pci_wr_reg_1080,
163 isp_pci_mbxdma,
164 isp_pci_dmasetup,
165 isp_pci_dmateardown,
166 NULL,
167 isp_pci_reset1,
168 isp_pci_dumpregs,
169 ISP_12160_RISC_CODE,
170 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
171 };
172 #endif
173
174 #ifndef ISP_DISABLE_2100_SUPPORT
175 static struct ispmdvec mdvec_2100 = {
176 isp_pci_rd_isr,
177 isp_pci_rd_reg,
178 isp_pci_wr_reg,
179 isp_pci_mbxdma,
180 isp_pci_dmasetup,
181 isp_pci_dmateardown,
182 NULL,
183 isp_pci_reset1,
184 isp_pci_dumpregs,
185 ISP_2100_RISC_CODE
186 };
187 #endif
188
189 #ifndef ISP_DISABLE_2200_SUPPORT
190 static struct ispmdvec mdvec_2200 = {
191 isp_pci_rd_isr,
192 isp_pci_rd_reg,
193 isp_pci_wr_reg,
194 isp_pci_mbxdma,
195 isp_pci_dmasetup,
196 isp_pci_dmateardown,
197 NULL,
198 isp_pci_reset1,
199 isp_pci_dumpregs,
200 ISP_2200_RISC_CODE
201 };
202 #endif
203
204 #ifndef ISP_DISABLE_2300_SUPPORT
205 static struct ispmdvec mdvec_2300 = {
206 isp_pci_rd_isr_2300,
207 isp_pci_rd_reg,
208 isp_pci_wr_reg,
209 isp_pci_mbxdma,
210 isp_pci_dmasetup,
211 isp_pci_dmateardown,
212 NULL,
213 isp_pci_reset1,
214 isp_pci_dumpregs,
215 ISP_2300_RISC_CODE
216 };
217 #endif
218
219 #ifndef PCI_VENDOR_QLOGIC
220 #define PCI_VENDOR_QLOGIC 0x1077
221 #endif
222
223 #ifndef PCI_PRODUCT_QLOGIC_ISP1020
224 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
225 #endif
226
227 #ifndef PCI_PRODUCT_QLOGIC_ISP1080
228 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080
229 #endif
230
231 #ifndef PCI_PRODUCT_QLOGIC_ISP1240
232 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
233 #endif
234
235 #ifndef PCI_PRODUCT_QLOGIC_ISP1280
236 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
237 #endif
238
239 #ifndef PCI_PRODUCT_QLOGIC_ISP12160
240 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216
241 #endif
242
243 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
244 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
245 #endif
246
247 #ifndef PCI_PRODUCT_QLOGIC_ISP2200
248 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200
249 #endif
250
251 #ifndef PCI_PRODUCT_QLOGIC_ISP2300
252 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300
253 #endif
254
255 #ifndef PCI_PRODUCT_QLOGIC_ISP2312
256 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312
257 #endif
258
259 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
260
261 #define PCI_QLOGIC_ISP1080 \
262 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
263
264 #define PCI_QLOGIC_ISP1240 \
265 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
266
267 #define PCI_QLOGIC_ISP1280 \
268 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
269
270 #define PCI_QLOGIC_ISP12160 \
271 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
272
273 #define PCI_QLOGIC_ISP2100 \
274 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
275
276 #define PCI_QLOGIC_ISP2200 \
277 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
278
279 #define PCI_QLOGIC_ISP2300 \
280 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC)
281
282 #define PCI_QLOGIC_ISP2312 \
283 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC)
284
285 #define IO_MAP_REG 0x10
286 #define MEM_MAP_REG 0x14
287 #define PCIR_ROMADDR 0x30
288
289 #define PCI_DFLT_LTNCY 0x40
290 #define PCI_DFLT_LNSZ 0x10
291
292
293 static int isp_pci_probe(struct device *, struct cfdata *, void *);
294 static void isp_pci_attach(struct device *, struct device *, void *);
295
296 struct isp_pcisoftc {
297 struct ispsoftc pci_isp;
298 pci_chipset_tag_t pci_pc;
299 pcitag_t pci_tag;
300 bus_space_tag_t pci_st;
301 bus_space_handle_t pci_sh;
302 bus_dma_tag_t pci_dmat;
303 bus_dmamap_t pci_scratch_dmap; /* for fcp only */
304 bus_dmamap_t pci_rquest_dmap;
305 bus_dmamap_t pci_result_dmap;
306 bus_dmamap_t *pci_xfer_dmap;
307 void * pci_ih;
308 int16_t pci_poff[_NREG_BLKS];
309 };
310
311 struct cfattach isp_pci_ca = {
312 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach
313 };
314
315 #ifdef DEBUG
316 const char vstring[] =
317 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d";
318 #endif
319
320 static int
321 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux)
322 {
323 struct pci_attach_args *pa = aux;
324 switch (pa->pa_id) {
325 #ifndef ISP_DISABLE_1020_SUPPORT
326 case PCI_QLOGIC_ISP:
327 return (1);
328 #endif
329 #ifndef ISP_DISABLE_1080_SUPPORT
330 case PCI_QLOGIC_ISP1080:
331 case PCI_QLOGIC_ISP1240:
332 case PCI_QLOGIC_ISP1280:
333 return (1);
334 #endif
335 #ifndef ISP_DISABLE_12160_SUPPORT
336 case PCI_QLOGIC_ISP12160:
337 return (1);
338 #endif
339 #ifndef ISP_DISABLE_2100_SUPPORT
340 case PCI_QLOGIC_ISP2100:
341 return (1);
342 #endif
343 #ifndef ISP_DISABLE_2200_SUPPORT
344 case PCI_QLOGIC_ISP2200:
345 return (1);
346 #endif
347 #ifndef ISP_DISABLE_2300_SUPPORT
348 case PCI_QLOGIC_ISP2300:
349 case PCI_QLOGIC_ISP2312:
350 return (1);
351 #endif
352 default:
353 return (0);
354 }
355 }
356
357
358 static void
359 isp_pci_attach(struct device *parent, struct device *self, void *aux)
360 {
361 #ifdef DEBUG
362 static char oneshot = 1;
363 #endif
364 static const char nomem[] = "%s: no mem for sdparam table\n";
365 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ;
366 struct pci_attach_args *pa = aux;
367 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self;
368 struct ispsoftc *isp = &pcs->pci_isp;
369 bus_space_tag_t st, iot, memt;
370 bus_space_handle_t sh, ioh, memh;
371 pci_intr_handle_t ih;
372 const char *intrstr;
373 int ioh_valid, memh_valid;
374
375 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
376 PCI_MAPREG_TYPE_IO, 0,
377 &iot, &ioh, NULL, NULL) == 0);
378 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG,
379 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
380 &memt, &memh, NULL, NULL) == 0);
381 if (memh_valid) {
382 st = memt;
383 sh = memh;
384 } else if (ioh_valid) {
385 st = iot;
386 sh = ioh;
387 } else {
388 printf(": unable to map device registers\n");
389 return;
390 }
391 printf("\n");
392
393 pcs->pci_st = st;
394 pcs->pci_sh = sh;
395 pcs->pci_dmat = pa->pa_dmat;
396 pcs->pci_pc = pa->pa_pc;
397 pcs->pci_tag = pa->pa_tag;
398 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
399 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
400 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
401 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
402 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
403 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff;
404
405 #ifndef ISP_DISABLE_1020_SUPPORT
406 if (pa->pa_id == PCI_QLOGIC_ISP) {
407 isp->isp_mdvec = &mdvec;
408 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
409 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT);
410 if (isp->isp_param == NULL) {
411 printf(nomem, isp->isp_name);
412 return;
413 }
414 memset(isp->isp_param, 0, sizeof (sdparam));
415 }
416 #endif
417 #ifndef ISP_DISABLE_1080_SUPPORT
418 if (pa->pa_id == PCI_QLOGIC_ISP1080) {
419 isp->isp_mdvec = &mdvec_1080;
420 isp->isp_type = ISP_HA_SCSI_1080;
421 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT);
422 if (isp->isp_param == NULL) {
423 printf(nomem, isp->isp_name);
424 return;
425 }
426 memset(isp->isp_param, 0, sizeof (sdparam));
427 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
428 ISP1080_DMA_REGS_OFF;
429 }
430 if (pa->pa_id == PCI_QLOGIC_ISP1240) {
431 isp->isp_mdvec = &mdvec_1080;
432 isp->isp_type = ISP_HA_SCSI_1240;
433 isp->isp_param =
434 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT);
435 if (isp->isp_param == NULL) {
436 printf(nomem, isp->isp_name);
437 return;
438 }
439 memset(isp->isp_param, 0, 2 * sizeof (sdparam));
440 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
441 ISP1080_DMA_REGS_OFF;
442 }
443 if (pa->pa_id == PCI_QLOGIC_ISP1280) {
444 isp->isp_mdvec = &mdvec_1080;
445 isp->isp_type = ISP_HA_SCSI_1280;
446 isp->isp_param =
447 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT);
448 if (isp->isp_param == NULL) {
449 printf(nomem, isp->isp_name);
450 return;
451 }
452 memset(isp->isp_param, 0, 2 * sizeof (sdparam));
453 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
454 ISP1080_DMA_REGS_OFF;
455 }
456 #endif
457 #ifndef ISP_DISABLE_12160_SUPPORT
458 if (pa->pa_id == PCI_QLOGIC_ISP12160) {
459 isp->isp_mdvec = &mdvec_12160;
460 isp->isp_type = ISP_HA_SCSI_12160;
461 isp->isp_param =
462 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT);
463 if (isp->isp_param == NULL) {
464 printf(nomem, isp->isp_name);
465 return;
466 }
467 memset(isp->isp_param, 0, 2 * sizeof (sdparam));
468 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
469 ISP1080_DMA_REGS_OFF;
470 }
471 #endif
472 #ifndef ISP_DISABLE_2100_SUPPORT
473 if (pa->pa_id == PCI_QLOGIC_ISP2100) {
474 isp->isp_mdvec = &mdvec_2100;
475 isp->isp_type = ISP_HA_FC_2100;
476 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT);
477 if (isp->isp_param == NULL) {
478 printf(nomem, isp->isp_name);
479 return;
480 }
481 memset(isp->isp_param, 0, sizeof (fcparam));
482 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
483 PCI_MBOX_REGS2100_OFF;
484 if (rev < 3) {
485 /*
486 * XXX: Need to get the actual revision
487 * XXX: number of the 2100 FB. At any rate,
488 * XXX: lower cache line size for early revision
489 * XXX; boards.
490 */
491 linesz = 1;
492 }
493 }
494 #endif
495 #ifndef ISP_DISABLE_2200_SUPPORT
496 if (pa->pa_id == PCI_QLOGIC_ISP2200) {
497 isp->isp_mdvec = &mdvec_2200;
498 isp->isp_type = ISP_HA_FC_2200;
499 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT);
500 if (isp->isp_param == NULL) {
501 printf(nomem, isp->isp_name);
502 return;
503 }
504 memset(isp->isp_param, 0, sizeof (fcparam));
505 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
506 PCI_MBOX_REGS2100_OFF;
507 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
508 }
509 #endif
510 #ifndef ISP_DISABLE_2300_SUPPORT
511 if (pa->pa_id == PCI_QLOGIC_ISP2300 ||
512 pa->pa_id == PCI_QLOGIC_ISP2312) {
513 isp->isp_mdvec = &mdvec_2300;
514 isp->isp_type = ISP_HA_FC_2300;
515 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT);
516 if (isp->isp_param == NULL) {
517 printf(nomem, isp->isp_name);
518 return;
519 }
520 memset(isp->isp_param, 0, sizeof (fcparam));
521 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
522 PCI_MBOX_REGS2300_OFF;
523 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
524 }
525 #endif
526 /*
527 * Set up logging levels.
528 */
529 #ifdef ISP_LOGDEFAULT
530 isp->isp_dblev = ISP_LOGDEFAULT;
531 #else
532 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
533 if (bootverbose)
534 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
535 #ifdef SCSIDEBUG
536 isp->isp_dblev |= ISP_LOGDEBUG1|ISP_LOGDEBUG2;
537 #endif
538 #ifdef DEBUG
539 isp->isp_dblev |= ISP_LOGDEBUG0;
540 #endif
541 #endif
542
543 #ifdef DEBUG
544 if (oneshot) {
545 oneshot = 0;
546 isp_prt(isp, ISP_LOGCONFIG, vstring,
547 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
548 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
549 }
550 #endif
551
552 isp->isp_revision = rev;
553
554 /*
555 * Make sure that command register set sanely.
556 */
557 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
558 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
559
560 /*
561 * Not so sure about these- but I think it's important that they get
562 * enabled......
563 */
564 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
565 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data);
566
567 /*
568 * Make sure that the latency timer, cache line size,
569 * and ROM is disabled.
570 */
571 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
572 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
573 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
574 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT);
575 data |= (linesz << PCI_CACHELINE_SHIFT);
576 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
577
578 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR);
579 data &= ~1;
580 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data);
581
582 if (pci_intr_map(pa, &ih)) {
583 printf("%s: couldn't map interrupt\n", isp->isp_name);
584 free(isp->isp_param, M_DEVBUF);
585 return;
586 }
587 intrstr = pci_intr_string(pa->pa_pc, ih);
588 if (intrstr == NULL)
589 intrstr = "<I dunno>";
590 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
591 isp_pci_intr, isp);
592 if (pcs->pci_ih == NULL) {
593 printf("%s: couldn't establish interrupt at %s\n",
594 isp->isp_name, intrstr);
595 free(isp->isp_param, M_DEVBUF);
596 return;
597 }
598
599 printf("%s: interrupting at %s\n", isp->isp_name, intrstr);
600
601 if (IS_FC(isp)) {
602 DEFAULT_NODEWWN(isp) = 0x400000007F000002;
603 DEFAULT_PORTWWN(isp) = 0x400000007F000002;
604 }
605
606 isp->isp_confopts = self->dv_cfdata->cf_flags;
607 isp->isp_role = ISP_DEFAULT_ROLES;
608 ISP_LOCK(isp);
609 isp->isp_osinfo.no_mbox_ints = 1;
610 isp_reset(isp);
611 if (isp->isp_state != ISP_RESETSTATE) {
612 ISP_UNLOCK(isp);
613 free(isp->isp_param, M_DEVBUF);
614 return;
615 }
616 ENABLE_INTS(isp);
617 isp_init(isp);
618 if (isp->isp_state != ISP_INITSTATE) {
619 isp_uninit(isp);
620 ISP_UNLOCK(isp);
621 free(isp->isp_param, M_DEVBUF);
622 return;
623 }
624 /*
625 * Do platform attach.
626 */
627 ISP_UNLOCK(isp);
628 isp_attach(isp);
629 if (isp->isp_state != ISP_RUNSTATE) {
630 ISP_LOCK(isp);
631 isp_uninit(isp);
632 free(isp->isp_param, M_DEVBUF);
633 ISP_UNLOCK(isp);
634 }
635 }
636
637 #define IspVirt2Off(a, x) \
638 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
639 _BLK_REG_SHFT] + ((x) & 0xff))
640
641 #define BXR2(pcs, off) \
642 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off)
643 #define BXW2(pcs, off, v) \
644 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v)
645
646
647 static INLINE int
648 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp)
649 {
650 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
651 u_int16_t val0, val1;
652 int i = 0;
653
654 do {
655 val0 = BXR2(pcs, IspVirt2Off(isp, off));
656 val1 = BXR2(pcs, IspVirt2Off(isp, off));
657 } while (val0 != val1 && ++i < 1000);
658 if (val0 != val1) {
659 return (1);
660 }
661 *rp = val0;
662 return (0);
663 }
664
665 static int
666 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp,
667 u_int16_t *semap, u_int16_t *mbp)
668 {
669 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
670 u_int16_t isr, sema;
671
672 if (IS_2100(isp)) {
673 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
674 return (0);
675 }
676 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) {
677 return (0);
678 }
679 } else {
680 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR));
681 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA));
682 }
683 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema);
684 isr &= INT_PENDING_MASK(isp);
685 sema &= BIU_SEMA_LOCK;
686 if (isr == 0 && sema == 0) {
687 return (0);
688 }
689 *isrp = isr;
690 if ((*semap = sema) != 0) {
691 if (IS_2100(isp)) {
692 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) {
693 return (0);
694 }
695 } else {
696 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0));
697 }
698 }
699 return (1);
700 }
701
702 #ifndef ISP_DISABLE_2300_SUPPORT
703 static int
704 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp,
705 u_int16_t *semap, u_int16_t *mbox0p)
706 {
707 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
708 u_int32_t r2hisr;
709
710 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) {
711 *isrp = 0;
712 return (0);
713 }
714 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh,
715 IspVirt2Off(pcs, BIU_R2HSTSLO));
716 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
717 if ((r2hisr & BIU_R2HST_INTR) == 0) {
718 *isrp = 0;
719 return (0);
720 }
721 switch (r2hisr & BIU_R2HST_ISTAT_MASK) {
722 case ISPR2HST_ROM_MBX_OK:
723 case ISPR2HST_ROM_MBX_FAIL:
724 case ISPR2HST_MBX_OK:
725 case ISPR2HST_MBX_FAIL:
726 case ISPR2HST_ASYNC_EVENT:
727 case ISPR2HST_FPOST:
728 case ISPR2HST_FPOST_CTIO:
729 *isrp = r2hisr & 0xffff;
730 *mbox0p = (r2hisr >> 16);
731 *semap = 1;
732 return (1);
733 case ISPR2HST_RSPQ_UPDATE:
734 *isrp = r2hisr & 0xffff;
735 *mbox0p = 0;
736 *semap = 0;
737 return (1);
738 default:
739 return (0);
740 }
741 }
742 #endif
743
744 static u_int16_t
745 isp_pci_rd_reg(struct ispsoftc *isp, int regoff)
746 {
747 u_int16_t rv;
748 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
749 int oldconf = 0;
750
751 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
752 /*
753 * We will assume that someone has paused the RISC processor.
754 */
755 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
756 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
757 oldconf | BIU_PCI_CONF1_SXP);
758 }
759 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
760 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
761 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
762 }
763 return (rv);
764 }
765
766 static void
767 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val)
768 {
769 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
770 int oldconf = 0;
771
772 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
773 /*
774 * We will assume that someone has paused the RISC processor.
775 */
776 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
777 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
778 oldconf | BIU_PCI_CONF1_SXP);
779 }
780 BXW2(pcs, IspVirt2Off(isp, regoff), val);
781 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
782 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
783 }
784 }
785
786 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
787 static u_int16_t
788 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff)
789 {
790 u_int16_t rv, oc = 0;
791 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
792
793 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
794 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
795 u_int16_t tc;
796 /*
797 * We will assume that someone has paused the RISC processor.
798 */
799 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
800 tc = oc & ~BIU_PCI1080_CONF1_DMA;
801 if (regoff & SXP_BANK1_SELECT)
802 tc |= BIU_PCI1080_CONF1_SXP1;
803 else
804 tc |= BIU_PCI1080_CONF1_SXP0;
805 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
806 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
807 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
808 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
809 oc | BIU_PCI1080_CONF1_DMA);
810 }
811 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
812 if (oc) {
813 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
814 }
815 return (rv);
816 }
817
818 static void
819 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val)
820 {
821 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
822 int oc = 0;
823
824 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
825 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
826 u_int16_t tc;
827 /*
828 * We will assume that someone has paused the RISC processor.
829 */
830 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
831 tc = oc & ~BIU_PCI1080_CONF1_DMA;
832 if (regoff & SXP_BANK1_SELECT)
833 tc |= BIU_PCI1080_CONF1_SXP1;
834 else
835 tc |= BIU_PCI1080_CONF1_SXP0;
836 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
837 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
838 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
839 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
840 oc | BIU_PCI1080_CONF1_DMA);
841 }
842 BXW2(pcs, IspVirt2Off(isp, regoff), val);
843 if (oc) {
844 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
845 }
846 }
847 #endif
848
849 static int
850 isp_pci_mbxdma(struct ispsoftc *isp)
851 {
852 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
853 bus_dma_tag_t dmat = pcs->pci_dmat;
854 bus_dma_segment_t sg;
855 bus_size_t len;
856 fcparam *fcp;
857 int rs, i;
858
859 if (isp->isp_rquest_dma) /* been here before? */
860 return (0);
861
862 len = isp->isp_maxcmds * sizeof (XS_T *);
863 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK);
864 if (isp->isp_xflist == NULL) {
865 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array");
866 return (1);
867 }
868 memset(isp->isp_xflist, 0, len);
869 len = isp->isp_maxcmds * sizeof (bus_dmamap_t);
870 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK);
871 if (pcs->pci_xfer_dmap == NULL) {
872 free(isp->isp_xflist, M_DEVBUF);
873 isp->isp_xflist = NULL;
874 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array");
875 return (1);
876 }
877 for (i = 0; i < isp->isp_maxcmds; i++) {
878 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1,
879 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) {
880 isp_prt(isp, ISP_LOGERR, "cannot create dma maps");
881 break;
882 }
883 }
884 if (i < isp->isp_maxcmds) {
885 while (--i >= 0) {
886 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
887 }
888 free(isp->isp_xflist, M_DEVBUF);
889 free(pcs->pci_xfer_dmap, M_DEVBUF);
890 isp->isp_xflist = NULL;
891 pcs->pci_xfer_dmap = NULL;
892 return (1);
893 }
894
895 /*
896 * Allocate and map the request queue.
897 */
898 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
899 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs,
900 BUS_DMA_NOWAIT) ||
901 bus_dmamem_map(pcs->pci_dmat, &sg, rs, len,
902 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
903 goto dmafail;
904 }
905
906 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
907 &pcs->pci_rquest_dmap) || bus_dmamap_load(dmat,
908 pcs->pci_rquest_dmap, (caddr_t)isp->isp_rquest, len, NULL,
909 BUS_DMA_NOWAIT)) {
910 goto dmafail;
911 }
912
913 isp->isp_rquest_dma = pcs->pci_rquest_dmap->dm_segs[0].ds_addr;
914
915 /*
916 * Allocate and map the result queue.
917 */
918 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
919 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs,
920 BUS_DMA_NOWAIT) ||
921 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result,
922 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
923 goto dmafail;
924 }
925 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
926 &pcs->pci_result_dmap) || bus_dmamap_load(pcs->pci_dmat,
927 pcs->pci_result_dmap, (caddr_t)isp->isp_result, len, NULL,
928 BUS_DMA_NOWAIT)) {
929 goto dmafail;
930 }
931 isp->isp_result_dma = pcs->pci_result_dmap->dm_segs[0].ds_addr;
932
933 if (IS_SCSI(isp)) {
934 return (0);
935 }
936
937 fcp = isp->isp_param;
938 len = ISP2100_SCRLEN;
939 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs,
940 BUS_DMA_NOWAIT) ||
941 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch,
942 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
943 goto dmafail;
944 }
945 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
946 &pcs->pci_scratch_dmap) || bus_dmamap_load(dmat,
947 pcs->pci_scratch_dmap, (caddr_t)fcp->isp_scratch, len, NULL,
948 BUS_DMA_NOWAIT)) {
949 goto dmafail;
950 }
951 fcp->isp_scdma = pcs->pci_scratch_dmap->dm_segs[0].ds_addr;
952 return (0);
953 dmafail:
954 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure");
955 for (i = 0; i < isp->isp_maxcmds; i++) {
956 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
957 }
958 free(isp->isp_xflist, M_DEVBUF);
959 free(pcs->pci_xfer_dmap, M_DEVBUF);
960 isp->isp_xflist = NULL;
961 pcs->pci_xfer_dmap = NULL;
962 return (1);
963 }
964
965 static int
966 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq,
967 u_int16_t *iptrp, u_int16_t optr)
968 {
969 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
970 bus_dmamap_t dmap;
971 ispcontreq_t *crq;
972 int segcnt, seg, error, ovseg, seglim, drq;
973
974 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)];
975
976 if (xs->datalen == 0) {
977 rq->req_seg_count = 1;
978 goto mbxsync;
979 }
980 if (xs->xs_control & XS_CTL_DATA_IN) {
981 drq = REQFLAG_DATA_IN;
982 } else {
983 drq = REQFLAG_DATA_OUT;
984 }
985
986 if (IS_FC(isp)) {
987 seglim = ISP_RQDSEG_T2;
988 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen;
989 ((ispreqt2_t *)rq)->req_flags |= drq;
990 } else {
991 rq->req_flags |= drq;
992 if (XS_CDBLEN(xs) > 12) {
993 seglim = 0;
994 } else {
995 seglim = ISP_RQDSEG;
996 }
997 }
998 error = bus_dmamap_load(pcs->pci_dmat, dmap, xs->data, xs->datalen,
999 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ?
1000 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING |
1001 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE));
1002 if (error) {
1003 XS_SETERR(xs, HBA_BOTCH);
1004 return (CMD_COMPLETE);
1005 }
1006
1007 segcnt = dmap->dm_nsegs;
1008
1009 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs",
1010 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" :
1011 "write from", xs->data, segcnt);
1012
1013 for (seg = 0, rq->req_seg_count = 0;
1014 seglim && seg < segcnt && rq->req_seg_count < seglim;
1015 seg++, rq->req_seg_count++) {
1016 if (IS_FC(isp)) {
1017 ispreqt2_t *rq2 = (ispreqt2_t *)rq;
1018 #if _BYTE_ORDER == _BIG_ENDIAN
1019 rq2->req_dataseg[rq2->req_seg_count].ds_count =
1020 bswap32(dmap->dm_segs[seg].ds_len);
1021 rq2->req_dataseg[rq2->req_seg_count].ds_base =
1022 bswap32(dmap->dm_segs[seg].ds_addr);
1023 #else
1024 rq2->req_dataseg[rq2->req_seg_count].ds_count =
1025 dmap->dm_segs[seg].ds_len;
1026 rq2->req_dataseg[rq2->req_seg_count].ds_base =
1027 dmap->dm_segs[seg].ds_addr;
1028 #endif
1029 } else {
1030 #if _BYTE_ORDER == _BIG_ENDIAN
1031 rq->req_dataseg[rq->req_seg_count].ds_count =
1032 bswap32(dmap->dm_segs[seg].ds_len);
1033 rq->req_dataseg[rq->req_seg_count].ds_base =
1034 bswap32(dmap->dm_segs[seg].ds_addr);
1035 #else
1036 rq->req_dataseg[rq->req_seg_count].ds_count =
1037 dmap->dm_segs[seg].ds_len;
1038 rq->req_dataseg[rq->req_seg_count].ds_base =
1039 dmap->dm_segs[seg].ds_addr;
1040 #endif
1041 }
1042 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}",
1043 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr,
1044 (unsigned long) dmap->dm_segs[seg].ds_len);
1045 }
1046
1047 if (seg == segcnt)
1048 goto dmasync;
1049
1050 do {
1051 crq = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp);
1052 *iptrp = ISP_NXT_QENTRY(*iptrp, RQUEST_QUEUE_LEN(isp));
1053 if (*iptrp == optr) {
1054 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++");
1055 bus_dmamap_unload(pcs->pci_dmat, dmap);
1056 XS_SETERR(xs, HBA_BOTCH);
1057 return (CMD_EAGAIN);
1058 }
1059 rq->req_header.rqs_entry_count++;
1060 memset((void *)crq, 0, sizeof (*crq));
1061 crq->req_header.rqs_entry_count = 1;
1062 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG;
1063
1064 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG;
1065 rq->req_seg_count++, seg++, ovseg++) {
1066 #if _BYTE_ORDER == _BIG_ENDIAN
1067 crq->req_dataseg[ovseg].ds_count =
1068 bswap32(dmap->dm_segs[seg].ds_len);
1069 crq->req_dataseg[ovseg].ds_base =
1070 bswap32(dmap->dm_segs[seg].ds_addr);
1071 #else
1072 crq->req_dataseg[ovseg].ds_count =
1073 dmap->dm_segs[seg].ds_len;
1074 crq->req_dataseg[ovseg].ds_base =
1075 dmap->dm_segs[seg].ds_addr;
1076 #endif
1077 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}",
1078 rq->req_header.rqs_entry_count - 1,
1079 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr,
1080 (unsigned long) dmap->dm_segs[seg].ds_len);
1081 }
1082 } while (seg < segcnt);
1083
1084
1085 dmasync:
1086 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize,
1087 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD :
1088 BUS_DMASYNC_PREWRITE);
1089
1090 mbxsync:
1091 ISP_SWIZZLE_REQUEST(isp, rq);
1092 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_rquest_dmap, 0,
1093 pcs->pci_rquest_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
1094 return (CMD_QUEUED);
1095 }
1096
1097 static int
1098 isp_pci_intr(void *arg)
1099 {
1100 u_int16_t isr, sema, mbox;
1101 struct ispsoftc *isp = arg;
1102
1103 isp->isp_intcnt++;
1104 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) {
1105 isp->isp_intbogus++;
1106 return (0);
1107 } else {
1108 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)arg;
1109 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_result_dmap, 0,
1110 pcs->pci_result_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1111 isp->isp_osinfo.onintstack = 1;
1112 isp_intr(isp, isr, sema, mbox);
1113 isp->isp_osinfo.onintstack = 0;
1114 return (1);
1115 }
1116 }
1117
1118 static void
1119 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle)
1120 {
1121 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1122 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)];
1123 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize,
1124 xs->xs_control & XS_CTL_DATA_IN ?
1125 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1126 bus_dmamap_unload(pcs->pci_dmat, dmap);
1127 }
1128
1129 static void
1130 isp_pci_reset1(struct ispsoftc *isp)
1131 {
1132 /* Make sure the BIOS is disabled */
1133 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
1134 }
1135
1136 static void
1137 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg)
1138 {
1139 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1140 if (msg)
1141 printf("%s: %s\n", isp->isp_name, msg);
1142 if (IS_SCSI(isp))
1143 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
1144 else
1145 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
1146 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
1147 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
1148 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
1149
1150
1151 if (IS_SCSI(isp)) {
1152 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
1153 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
1154 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
1155 ISP_READ(isp, CDMA_FIFO_STS));
1156 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
1157 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
1158 ISP_READ(isp, DDMA_FIFO_STS));
1159 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
1160 ISP_READ(isp, SXP_INTERRUPT),
1161 ISP_READ(isp, SXP_GROSS_ERR),
1162 ISP_READ(isp, SXP_PINS_CTRL));
1163 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
1164 }
1165 printf(" mbox regs: %x %x %x %x %x\n",
1166 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
1167 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
1168 ISP_READ(isp, OUTMAILBOX4));
1169 printf(" PCI Status Command/Status=%x\n",
1170 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG));
1171 }
1172