isp_pci.c revision 1.74
1 /* $NetBSD: isp_pci.c,v 1.74 2001/11/13 07:48:45 lukem Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 */ 33 /* 34 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 35 * All rights reserved. 36 * 37 * Additional Copyright (C) 2000, 2001 by Matthew Jacob 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.74 2001/11/13 07:48:45 lukem Exp $"); 61 62 #include <dev/ic/isp_netbsd.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 #include <uvm/uvm_extern.h> 67 #include <sys/reboot.h> 68 69 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 70 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 71 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 72 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 73 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 74 #endif 75 static int 76 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 77 static int 78 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 79 static int isp_pci_mbxdma(struct ispsoftc *); 80 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, 81 u_int16_t *, u_int16_t); 82 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 83 static void isp_pci_reset1(struct ispsoftc *); 84 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 85 static int isp_pci_intr(void *); 86 87 #if defined(ISP_DISABLE_1020_SUPPORT) 88 #define ISP_1040_RISC_CODE NULL 89 #else 90 #define ISP_1040_RISC_CODE isp_1040_risc_code 91 #include <dev/microcode/isp/asm_1040.h> 92 #endif 93 94 #if defined(ISP_DISABLE_1080_SUPPORT) 95 #define ISP_1080_RISC_CODE NULL 96 #else 97 #define ISP_1080_RISC_CODE isp_1080_risc_code 98 #include <dev/microcode/isp/asm_1080.h> 99 #endif 100 101 #if defined(ISP_DISABLE_12160_SUPPORT) 102 #define ISP_12160_RISC_CODE NULL 103 #else 104 #define ISP_12160_RISC_CODE isp_12160_risc_code 105 #include <dev/microcode/isp/asm_12160.h> 106 #endif 107 108 #if defined(ISP_DISABLE_2100_SUPPORT) 109 #define ISP_2100_RISC_CODE NULL 110 #else 111 #define ISP_2100_RISC_CODE isp_2100_risc_code 112 #include <dev/microcode/isp/asm_2100.h> 113 #endif 114 115 #if defined(ISP_DISABLE_2200_SUPPORT) 116 #define ISP_2200_RISC_CODE NULL 117 #else 118 #define ISP_2200_RISC_CODE isp_2200_risc_code 119 #include <dev/microcode/isp/asm_2200.h> 120 #endif 121 122 #if defined(ISP_DISABLE_2300_SUPPORT) 123 #define ISP_2300_RISC_CODE NULL 124 #else 125 #define ISP_2300_RISC_CODE isp_2300_risc_code 126 #include <dev/microcode/isp/asm_2300.h> 127 #endif 128 129 #ifndef ISP_DISABLE_1020_SUPPORT 130 static struct ispmdvec mdvec = { 131 isp_pci_rd_isr, 132 isp_pci_rd_reg, 133 isp_pci_wr_reg, 134 isp_pci_mbxdma, 135 isp_pci_dmasetup, 136 isp_pci_dmateardown, 137 NULL, 138 isp_pci_reset1, 139 isp_pci_dumpregs, 140 ISP_1040_RISC_CODE, 141 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 142 }; 143 #endif 144 145 #ifndef ISP_DISABLE_1080_SUPPORT 146 static struct ispmdvec mdvec_1080 = { 147 isp_pci_rd_isr, 148 isp_pci_rd_reg_1080, 149 isp_pci_wr_reg_1080, 150 isp_pci_mbxdma, 151 isp_pci_dmasetup, 152 isp_pci_dmateardown, 153 NULL, 154 isp_pci_reset1, 155 isp_pci_dumpregs, 156 ISP_1080_RISC_CODE, 157 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 158 }; 159 #endif 160 161 #ifndef ISP_DISABLE_12160_SUPPORT 162 static struct ispmdvec mdvec_12160 = { 163 isp_pci_rd_isr, 164 isp_pci_rd_reg_1080, 165 isp_pci_wr_reg_1080, 166 isp_pci_mbxdma, 167 isp_pci_dmasetup, 168 isp_pci_dmateardown, 169 NULL, 170 isp_pci_reset1, 171 isp_pci_dumpregs, 172 ISP_12160_RISC_CODE, 173 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 174 }; 175 #endif 176 177 #ifndef ISP_DISABLE_2100_SUPPORT 178 static struct ispmdvec mdvec_2100 = { 179 isp_pci_rd_isr, 180 isp_pci_rd_reg, 181 isp_pci_wr_reg, 182 isp_pci_mbxdma, 183 isp_pci_dmasetup, 184 isp_pci_dmateardown, 185 NULL, 186 isp_pci_reset1, 187 isp_pci_dumpregs, 188 ISP_2100_RISC_CODE 189 }; 190 #endif 191 192 #ifndef ISP_DISABLE_2200_SUPPORT 193 static struct ispmdvec mdvec_2200 = { 194 isp_pci_rd_isr, 195 isp_pci_rd_reg, 196 isp_pci_wr_reg, 197 isp_pci_mbxdma, 198 isp_pci_dmasetup, 199 isp_pci_dmateardown, 200 NULL, 201 isp_pci_reset1, 202 isp_pci_dumpregs, 203 ISP_2200_RISC_CODE 204 }; 205 #endif 206 207 #ifndef ISP_DISABLE_2300_SUPPORT 208 static struct ispmdvec mdvec_2300 = { 209 isp_pci_rd_isr_2300, 210 isp_pci_rd_reg, 211 isp_pci_wr_reg, 212 isp_pci_mbxdma, 213 isp_pci_dmasetup, 214 isp_pci_dmateardown, 215 NULL, 216 isp_pci_reset1, 217 isp_pci_dumpregs, 218 ISP_2300_RISC_CODE 219 }; 220 #endif 221 222 #ifndef PCI_VENDOR_QLOGIC 223 #define PCI_VENDOR_QLOGIC 0x1077 224 #endif 225 226 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 227 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 228 #endif 229 230 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 231 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 232 #endif 233 234 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 235 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 236 #endif 237 238 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 239 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 240 #endif 241 242 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 243 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 244 #endif 245 246 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 247 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 248 #endif 249 250 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 251 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 252 #endif 253 254 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 255 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 256 #endif 257 258 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 259 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 260 #endif 261 262 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 263 264 #define PCI_QLOGIC_ISP1080 \ 265 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 266 267 #define PCI_QLOGIC_ISP1240 \ 268 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 269 270 #define PCI_QLOGIC_ISP1280 \ 271 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 272 273 #define PCI_QLOGIC_ISP12160 \ 274 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 275 276 #define PCI_QLOGIC_ISP2100 \ 277 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 278 279 #define PCI_QLOGIC_ISP2200 \ 280 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP2300 \ 283 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP2312 \ 286 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define IO_MAP_REG 0x10 289 #define MEM_MAP_REG 0x14 290 #define PCIR_ROMADDR 0x30 291 292 #define PCI_DFLT_LTNCY 0x40 293 #define PCI_DFLT_LNSZ 0x10 294 295 296 static int isp_pci_probe(struct device *, struct cfdata *, void *); 297 static void isp_pci_attach(struct device *, struct device *, void *); 298 299 struct isp_pcisoftc { 300 struct ispsoftc pci_isp; 301 pci_chipset_tag_t pci_pc; 302 pcitag_t pci_tag; 303 bus_space_tag_t pci_st; 304 bus_space_handle_t pci_sh; 305 bus_dma_tag_t pci_dmat; 306 bus_dmamap_t pci_scratch_dmap; /* for fcp only */ 307 bus_dmamap_t pci_rquest_dmap; 308 bus_dmamap_t pci_result_dmap; 309 bus_dmamap_t *pci_xfer_dmap; 310 void * pci_ih; 311 int16_t pci_poff[_NREG_BLKS]; 312 }; 313 314 struct cfattach isp_pci_ca = { 315 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach 316 }; 317 318 #ifdef DEBUG 319 const char vstring[] = 320 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 321 #endif 322 323 static int 324 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux) 325 { 326 struct pci_attach_args *pa = aux; 327 switch (pa->pa_id) { 328 #ifndef ISP_DISABLE_1020_SUPPORT 329 case PCI_QLOGIC_ISP: 330 return (1); 331 #endif 332 #ifndef ISP_DISABLE_1080_SUPPORT 333 case PCI_QLOGIC_ISP1080: 334 case PCI_QLOGIC_ISP1240: 335 case PCI_QLOGIC_ISP1280: 336 return (1); 337 #endif 338 #ifndef ISP_DISABLE_12160_SUPPORT 339 case PCI_QLOGIC_ISP12160: 340 return (1); 341 #endif 342 #ifndef ISP_DISABLE_2100_SUPPORT 343 case PCI_QLOGIC_ISP2100: 344 return (1); 345 #endif 346 #ifndef ISP_DISABLE_2200_SUPPORT 347 case PCI_QLOGIC_ISP2200: 348 return (1); 349 #endif 350 #ifndef ISP_DISABLE_2300_SUPPORT 351 case PCI_QLOGIC_ISP2300: 352 case PCI_QLOGIC_ISP2312: 353 return (1); 354 #endif 355 default: 356 return (0); 357 } 358 } 359 360 361 static void 362 isp_pci_attach(struct device *parent, struct device *self, void *aux) 363 { 364 #ifdef DEBUG 365 static char oneshot = 1; 366 #endif 367 static const char nomem[] = "%s: no mem for sdparam table\n"; 368 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 369 struct pci_attach_args *pa = aux; 370 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 371 struct ispsoftc *isp = &pcs->pci_isp; 372 bus_space_tag_t st, iot, memt; 373 bus_space_handle_t sh, ioh, memh; 374 pci_intr_handle_t ih; 375 const char *intrstr; 376 int ioh_valid, memh_valid; 377 378 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 379 PCI_MAPREG_TYPE_IO, 0, 380 &iot, &ioh, NULL, NULL) == 0); 381 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 382 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 383 &memt, &memh, NULL, NULL) == 0); 384 if (memh_valid) { 385 st = memt; 386 sh = memh; 387 } else if (ioh_valid) { 388 st = iot; 389 sh = ioh; 390 } else { 391 printf(": unable to map device registers\n"); 392 return; 393 } 394 printf("\n"); 395 396 pcs->pci_st = st; 397 pcs->pci_sh = sh; 398 pcs->pci_dmat = pa->pa_dmat; 399 pcs->pci_pc = pa->pa_pc; 400 pcs->pci_tag = pa->pa_tag; 401 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 402 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 403 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 404 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 405 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 406 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 407 408 #ifndef ISP_DISABLE_1020_SUPPORT 409 if (pa->pa_id == PCI_QLOGIC_ISP) { 410 isp->isp_mdvec = &mdvec; 411 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 412 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 413 if (isp->isp_param == NULL) { 414 printf(nomem, isp->isp_name); 415 return; 416 } 417 memset(isp->isp_param, 0, sizeof (sdparam)); 418 } 419 #endif 420 #ifndef ISP_DISABLE_1080_SUPPORT 421 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 422 isp->isp_mdvec = &mdvec_1080; 423 isp->isp_type = ISP_HA_SCSI_1080; 424 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 425 if (isp->isp_param == NULL) { 426 printf(nomem, isp->isp_name); 427 return; 428 } 429 memset(isp->isp_param, 0, sizeof (sdparam)); 430 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 431 ISP1080_DMA_REGS_OFF; 432 } 433 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 434 isp->isp_mdvec = &mdvec_1080; 435 isp->isp_type = ISP_HA_SCSI_1240; 436 isp->isp_param = 437 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 438 if (isp->isp_param == NULL) { 439 printf(nomem, isp->isp_name); 440 return; 441 } 442 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 443 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 444 ISP1080_DMA_REGS_OFF; 445 } 446 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 447 isp->isp_mdvec = &mdvec_1080; 448 isp->isp_type = ISP_HA_SCSI_1280; 449 isp->isp_param = 450 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 451 if (isp->isp_param == NULL) { 452 printf(nomem, isp->isp_name); 453 return; 454 } 455 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 456 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 457 ISP1080_DMA_REGS_OFF; 458 } 459 #endif 460 #ifndef ISP_DISABLE_12160_SUPPORT 461 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 462 isp->isp_mdvec = &mdvec_12160; 463 isp->isp_type = ISP_HA_SCSI_12160; 464 isp->isp_param = 465 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 466 if (isp->isp_param == NULL) { 467 printf(nomem, isp->isp_name); 468 return; 469 } 470 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 471 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 472 ISP1080_DMA_REGS_OFF; 473 } 474 #endif 475 #ifndef ISP_DISABLE_2100_SUPPORT 476 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 477 isp->isp_mdvec = &mdvec_2100; 478 isp->isp_type = ISP_HA_FC_2100; 479 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 480 if (isp->isp_param == NULL) { 481 printf(nomem, isp->isp_name); 482 return; 483 } 484 memset(isp->isp_param, 0, sizeof (fcparam)); 485 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 486 PCI_MBOX_REGS2100_OFF; 487 if (rev < 3) { 488 /* 489 * XXX: Need to get the actual revision 490 * XXX: number of the 2100 FB. At any rate, 491 * XXX: lower cache line size for early revision 492 * XXX; boards. 493 */ 494 linesz = 1; 495 } 496 } 497 #endif 498 #ifndef ISP_DISABLE_2200_SUPPORT 499 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 500 isp->isp_mdvec = &mdvec_2200; 501 isp->isp_type = ISP_HA_FC_2200; 502 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 503 if (isp->isp_param == NULL) { 504 printf(nomem, isp->isp_name); 505 return; 506 } 507 memset(isp->isp_param, 0, sizeof (fcparam)); 508 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 509 PCI_MBOX_REGS2100_OFF; 510 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 511 } 512 #endif 513 #ifndef ISP_DISABLE_2300_SUPPORT 514 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 515 pa->pa_id == PCI_QLOGIC_ISP2312) { 516 isp->isp_mdvec = &mdvec_2300; 517 isp->isp_type = ISP_HA_FC_2300; 518 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 519 if (isp->isp_param == NULL) { 520 printf(nomem, isp->isp_name); 521 return; 522 } 523 memset(isp->isp_param, 0, sizeof (fcparam)); 524 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 525 PCI_MBOX_REGS2300_OFF; 526 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 527 } 528 #endif 529 /* 530 * Set up logging levels. 531 */ 532 #ifdef ISP_LOGDEFAULT 533 isp->isp_dblev = ISP_LOGDEFAULT; 534 #else 535 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 536 if (bootverbose) 537 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 538 #ifdef SCSIDEBUG 539 isp->isp_dblev |= ISP_LOGDEBUG1|ISP_LOGDEBUG2; 540 #endif 541 #ifdef DEBUG 542 isp->isp_dblev |= ISP_LOGDEBUG0; 543 #endif 544 #endif 545 546 #ifdef DEBUG 547 if (oneshot) { 548 oneshot = 0; 549 isp_prt(isp, ISP_LOGCONFIG, vstring, 550 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 551 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 552 } 553 #endif 554 555 isp->isp_revision = rev; 556 557 /* 558 * Make sure that command register set sanely. 559 */ 560 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 561 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 562 563 /* 564 * Not so sure about these- but I think it's important that they get 565 * enabled...... 566 */ 567 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 568 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 569 570 /* 571 * Make sure that the latency timer, cache line size, 572 * and ROM is disabled. 573 */ 574 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 575 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 576 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 577 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 578 data |= (linesz << PCI_CACHELINE_SHIFT); 579 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 580 581 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 582 data &= ~1; 583 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 584 585 if (pci_intr_map(pa, &ih)) { 586 printf("%s: couldn't map interrupt\n", isp->isp_name); 587 free(isp->isp_param, M_DEVBUF); 588 return; 589 } 590 intrstr = pci_intr_string(pa->pa_pc, ih); 591 if (intrstr == NULL) 592 intrstr = "<I dunno>"; 593 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 594 isp_pci_intr, isp); 595 if (pcs->pci_ih == NULL) { 596 printf("%s: couldn't establish interrupt at %s\n", 597 isp->isp_name, intrstr); 598 free(isp->isp_param, M_DEVBUF); 599 return; 600 } 601 602 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 603 604 if (IS_FC(isp)) { 605 DEFAULT_NODEWWN(isp) = 0x400000007F000002; 606 DEFAULT_PORTWWN(isp) = 0x400000007F000002; 607 } 608 609 isp->isp_confopts = self->dv_cfdata->cf_flags; 610 isp->isp_role = ISP_DEFAULT_ROLES; 611 ISP_LOCK(isp); 612 isp->isp_osinfo.no_mbox_ints = 1; 613 isp_reset(isp); 614 if (isp->isp_state != ISP_RESETSTATE) { 615 ISP_UNLOCK(isp); 616 free(isp->isp_param, M_DEVBUF); 617 return; 618 } 619 ENABLE_INTS(isp); 620 isp_init(isp); 621 if (isp->isp_state != ISP_INITSTATE) { 622 isp_uninit(isp); 623 ISP_UNLOCK(isp); 624 free(isp->isp_param, M_DEVBUF); 625 return; 626 } 627 /* 628 * Do platform attach. 629 */ 630 ISP_UNLOCK(isp); 631 isp_attach(isp); 632 if (isp->isp_state != ISP_RUNSTATE) { 633 ISP_LOCK(isp); 634 isp_uninit(isp); 635 free(isp->isp_param, M_DEVBUF); 636 ISP_UNLOCK(isp); 637 } 638 } 639 640 #define IspVirt2Off(a, x) \ 641 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 642 _BLK_REG_SHFT] + ((x) & 0xff)) 643 644 #define BXR2(pcs, off) \ 645 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 646 #define BXW2(pcs, off, v) \ 647 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 648 649 650 static INLINE int 651 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 652 { 653 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 654 u_int16_t val0, val1; 655 int i = 0; 656 657 do { 658 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 659 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 660 } while (val0 != val1 && ++i < 1000); 661 if (val0 != val1) { 662 return (1); 663 } 664 *rp = val0; 665 return (0); 666 } 667 668 static int 669 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 670 u_int16_t *semap, u_int16_t *mbp) 671 { 672 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 673 u_int16_t isr, sema; 674 675 if (IS_2100(isp)) { 676 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 677 return (0); 678 } 679 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 680 return (0); 681 } 682 } else { 683 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 684 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 685 } 686 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 687 isr &= INT_PENDING_MASK(isp); 688 sema &= BIU_SEMA_LOCK; 689 if (isr == 0 && sema == 0) { 690 return (0); 691 } 692 *isrp = isr; 693 if ((*semap = sema) != 0) { 694 if (IS_2100(isp)) { 695 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 696 return (0); 697 } 698 } else { 699 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 700 } 701 } 702 return (1); 703 } 704 705 #ifndef ISP_DISABLE_2300_SUPPORT 706 static int 707 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 708 u_int16_t *semap, u_int16_t *mbox0p) 709 { 710 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 711 u_int32_t r2hisr; 712 713 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 714 *isrp = 0; 715 return (0); 716 } 717 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 718 IspVirt2Off(pcs, BIU_R2HSTSLO)); 719 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 720 if ((r2hisr & BIU_R2HST_INTR) == 0) { 721 *isrp = 0; 722 return (0); 723 } 724 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 725 case ISPR2HST_ROM_MBX_OK: 726 case ISPR2HST_ROM_MBX_FAIL: 727 case ISPR2HST_MBX_OK: 728 case ISPR2HST_MBX_FAIL: 729 case ISPR2HST_ASYNC_EVENT: 730 case ISPR2HST_FPOST: 731 case ISPR2HST_FPOST_CTIO: 732 *isrp = r2hisr & 0xffff; 733 *mbox0p = (r2hisr >> 16); 734 *semap = 1; 735 return (1); 736 case ISPR2HST_RSPQ_UPDATE: 737 *isrp = r2hisr & 0xffff; 738 *mbox0p = 0; 739 *semap = 0; 740 return (1); 741 default: 742 return (0); 743 } 744 } 745 #endif 746 747 static u_int16_t 748 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 749 { 750 u_int16_t rv; 751 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 752 int oldconf = 0; 753 754 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 755 /* 756 * We will assume that someone has paused the RISC processor. 757 */ 758 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 759 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 760 oldconf | BIU_PCI_CONF1_SXP); 761 } 762 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 763 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 764 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 765 } 766 return (rv); 767 } 768 769 static void 770 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 771 { 772 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 773 int oldconf = 0; 774 775 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 776 /* 777 * We will assume that someone has paused the RISC processor. 778 */ 779 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 780 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 781 oldconf | BIU_PCI_CONF1_SXP); 782 } 783 BXW2(pcs, IspVirt2Off(isp, regoff), val); 784 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 785 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 786 } 787 } 788 789 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 790 static u_int16_t 791 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 792 { 793 u_int16_t rv, oc = 0; 794 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 795 796 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 797 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 798 u_int16_t tc; 799 /* 800 * We will assume that someone has paused the RISC processor. 801 */ 802 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 803 tc = oc & ~BIU_PCI1080_CONF1_DMA; 804 if (regoff & SXP_BANK1_SELECT) 805 tc |= BIU_PCI1080_CONF1_SXP1; 806 else 807 tc |= BIU_PCI1080_CONF1_SXP0; 808 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 809 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 810 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 811 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 812 oc | BIU_PCI1080_CONF1_DMA); 813 } 814 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 815 if (oc) { 816 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 817 } 818 return (rv); 819 } 820 821 static void 822 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 823 { 824 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 825 int oc = 0; 826 827 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 828 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 829 u_int16_t tc; 830 /* 831 * We will assume that someone has paused the RISC processor. 832 */ 833 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 834 tc = oc & ~BIU_PCI1080_CONF1_DMA; 835 if (regoff & SXP_BANK1_SELECT) 836 tc |= BIU_PCI1080_CONF1_SXP1; 837 else 838 tc |= BIU_PCI1080_CONF1_SXP0; 839 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 840 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 841 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 842 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 843 oc | BIU_PCI1080_CONF1_DMA); 844 } 845 BXW2(pcs, IspVirt2Off(isp, regoff), val); 846 if (oc) { 847 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 848 } 849 } 850 #endif 851 852 static int 853 isp_pci_mbxdma(struct ispsoftc *isp) 854 { 855 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 856 bus_dma_tag_t dmat = pcs->pci_dmat; 857 bus_dma_segment_t sg; 858 bus_size_t len; 859 fcparam *fcp; 860 int rs, i; 861 862 if (isp->isp_rquest_dma) /* been here before? */ 863 return (0); 864 865 len = isp->isp_maxcmds * sizeof (XS_T *); 866 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 867 if (isp->isp_xflist == NULL) { 868 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 869 return (1); 870 } 871 memset(isp->isp_xflist, 0, len); 872 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 873 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 874 if (pcs->pci_xfer_dmap == NULL) { 875 free(isp->isp_xflist, M_DEVBUF); 876 isp->isp_xflist = NULL; 877 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array"); 878 return (1); 879 } 880 for (i = 0; i < isp->isp_maxcmds; i++) { 881 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 882 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 883 isp_prt(isp, ISP_LOGERR, "cannot create dma maps"); 884 break; 885 } 886 } 887 if (i < isp->isp_maxcmds) { 888 while (--i >= 0) { 889 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 890 } 891 free(isp->isp_xflist, M_DEVBUF); 892 free(pcs->pci_xfer_dmap, M_DEVBUF); 893 isp->isp_xflist = NULL; 894 pcs->pci_xfer_dmap = NULL; 895 return (1); 896 } 897 898 /* 899 * Allocate and map the request queue. 900 */ 901 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 902 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 903 BUS_DMA_NOWAIT) || 904 bus_dmamem_map(pcs->pci_dmat, &sg, rs, len, 905 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 906 goto dmafail; 907 } 908 909 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 910 &pcs->pci_rquest_dmap) || bus_dmamap_load(dmat, 911 pcs->pci_rquest_dmap, (caddr_t)isp->isp_rquest, len, NULL, 912 BUS_DMA_NOWAIT)) { 913 goto dmafail; 914 } 915 916 isp->isp_rquest_dma = pcs->pci_rquest_dmap->dm_segs[0].ds_addr; 917 918 /* 919 * Allocate and map the result queue. 920 */ 921 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 922 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 923 BUS_DMA_NOWAIT) || 924 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 925 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 926 goto dmafail; 927 } 928 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 929 &pcs->pci_result_dmap) || bus_dmamap_load(pcs->pci_dmat, 930 pcs->pci_result_dmap, (caddr_t)isp->isp_result, len, NULL, 931 BUS_DMA_NOWAIT)) { 932 goto dmafail; 933 } 934 isp->isp_result_dma = pcs->pci_result_dmap->dm_segs[0].ds_addr; 935 936 if (IS_SCSI(isp)) { 937 return (0); 938 } 939 940 fcp = isp->isp_param; 941 len = ISP2100_SCRLEN; 942 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 943 BUS_DMA_NOWAIT) || 944 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 945 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 946 goto dmafail; 947 } 948 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 949 &pcs->pci_scratch_dmap) || bus_dmamap_load(dmat, 950 pcs->pci_scratch_dmap, (caddr_t)fcp->isp_scratch, len, NULL, 951 BUS_DMA_NOWAIT)) { 952 goto dmafail; 953 } 954 fcp->isp_scdma = pcs->pci_scratch_dmap->dm_segs[0].ds_addr; 955 return (0); 956 dmafail: 957 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure"); 958 for (i = 0; i < isp->isp_maxcmds; i++) { 959 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 960 } 961 free(isp->isp_xflist, M_DEVBUF); 962 free(pcs->pci_xfer_dmap, M_DEVBUF); 963 isp->isp_xflist = NULL; 964 pcs->pci_xfer_dmap = NULL; 965 return (1); 966 } 967 968 static int 969 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq, 970 u_int16_t *iptrp, u_int16_t optr) 971 { 972 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 973 bus_dmamap_t dmap; 974 ispcontreq_t *crq; 975 int segcnt, seg, error, ovseg, seglim, drq; 976 977 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 978 979 if (xs->datalen == 0) { 980 rq->req_seg_count = 1; 981 goto mbxsync; 982 } 983 if (xs->xs_control & XS_CTL_DATA_IN) { 984 drq = REQFLAG_DATA_IN; 985 } else { 986 drq = REQFLAG_DATA_OUT; 987 } 988 989 if (IS_FC(isp)) { 990 seglim = ISP_RQDSEG_T2; 991 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 992 ((ispreqt2_t *)rq)->req_flags |= drq; 993 } else { 994 rq->req_flags |= drq; 995 if (XS_CDBLEN(xs) > 12) { 996 seglim = 0; 997 } else { 998 seglim = ISP_RQDSEG; 999 } 1000 } 1001 error = bus_dmamap_load(pcs->pci_dmat, dmap, xs->data, xs->datalen, 1002 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 1003 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 1004 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1005 if (error) { 1006 XS_SETERR(xs, HBA_BOTCH); 1007 return (CMD_COMPLETE); 1008 } 1009 1010 segcnt = dmap->dm_nsegs; 1011 1012 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 1013 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 1014 "write from", xs->data, segcnt); 1015 1016 for (seg = 0, rq->req_seg_count = 0; 1017 seglim && seg < segcnt && rq->req_seg_count < seglim; 1018 seg++, rq->req_seg_count++) { 1019 if (IS_FC(isp)) { 1020 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1021 #if _BYTE_ORDER == _BIG_ENDIAN 1022 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1023 bswap32(dmap->dm_segs[seg].ds_len); 1024 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1025 bswap32(dmap->dm_segs[seg].ds_addr); 1026 #else 1027 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1028 dmap->dm_segs[seg].ds_len; 1029 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1030 dmap->dm_segs[seg].ds_addr; 1031 #endif 1032 } else { 1033 #if _BYTE_ORDER == _BIG_ENDIAN 1034 rq->req_dataseg[rq->req_seg_count].ds_count = 1035 bswap32(dmap->dm_segs[seg].ds_len); 1036 rq->req_dataseg[rq->req_seg_count].ds_base = 1037 bswap32(dmap->dm_segs[seg].ds_addr); 1038 #else 1039 rq->req_dataseg[rq->req_seg_count].ds_count = 1040 dmap->dm_segs[seg].ds_len; 1041 rq->req_dataseg[rq->req_seg_count].ds_base = 1042 dmap->dm_segs[seg].ds_addr; 1043 #endif 1044 } 1045 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 1046 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 1047 (unsigned long) dmap->dm_segs[seg].ds_len); 1048 } 1049 1050 if (seg == segcnt) 1051 goto dmasync; 1052 1053 do { 1054 crq = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp); 1055 *iptrp = ISP_NXT_QENTRY(*iptrp, RQUEST_QUEUE_LEN(isp)); 1056 if (*iptrp == optr) { 1057 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1058 bus_dmamap_unload(pcs->pci_dmat, dmap); 1059 XS_SETERR(xs, HBA_BOTCH); 1060 return (CMD_EAGAIN); 1061 } 1062 rq->req_header.rqs_entry_count++; 1063 memset((void *)crq, 0, sizeof (*crq)); 1064 crq->req_header.rqs_entry_count = 1; 1065 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1066 1067 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 1068 rq->req_seg_count++, seg++, ovseg++) { 1069 #if _BYTE_ORDER == _BIG_ENDIAN 1070 crq->req_dataseg[ovseg].ds_count = 1071 bswap32(dmap->dm_segs[seg].ds_len); 1072 crq->req_dataseg[ovseg].ds_base = 1073 bswap32(dmap->dm_segs[seg].ds_addr); 1074 #else 1075 crq->req_dataseg[ovseg].ds_count = 1076 dmap->dm_segs[seg].ds_len; 1077 crq->req_dataseg[ovseg].ds_base = 1078 dmap->dm_segs[seg].ds_addr; 1079 #endif 1080 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 1081 rq->req_header.rqs_entry_count - 1, 1082 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 1083 (unsigned long) dmap->dm_segs[seg].ds_len); 1084 } 1085 } while (seg < segcnt); 1086 1087 1088 dmasync: 1089 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 1090 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 1091 BUS_DMASYNC_PREWRITE); 1092 1093 mbxsync: 1094 ISP_SWIZZLE_REQUEST(isp, rq); 1095 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_rquest_dmap, 0, 1096 pcs->pci_rquest_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1097 return (CMD_QUEUED); 1098 } 1099 1100 static int 1101 isp_pci_intr(void *arg) 1102 { 1103 u_int16_t isr, sema, mbox; 1104 struct ispsoftc *isp = arg; 1105 1106 isp->isp_intcnt++; 1107 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1108 isp->isp_intbogus++; 1109 return (0); 1110 } else { 1111 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)arg; 1112 bus_dmamap_sync(pcs->pci_dmat, pcs->pci_result_dmap, 0, 1113 pcs->pci_result_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1114 isp->isp_osinfo.onintstack = 1; 1115 isp_intr(isp, isr, sema, mbox); 1116 isp->isp_osinfo.onintstack = 0; 1117 return (1); 1118 } 1119 } 1120 1121 static void 1122 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1123 { 1124 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1125 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 1126 bus_dmamap_sync(pcs->pci_dmat, dmap, 0, dmap->dm_mapsize, 1127 xs->xs_control & XS_CTL_DATA_IN ? 1128 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1129 bus_dmamap_unload(pcs->pci_dmat, dmap); 1130 } 1131 1132 static void 1133 isp_pci_reset1(struct ispsoftc *isp) 1134 { 1135 /* Make sure the BIOS is disabled */ 1136 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1137 } 1138 1139 static void 1140 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1141 { 1142 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1143 if (msg) 1144 printf("%s: %s\n", isp->isp_name, msg); 1145 if (IS_SCSI(isp)) 1146 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1147 else 1148 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1149 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1150 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1151 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1152 1153 1154 if (IS_SCSI(isp)) { 1155 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1156 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1157 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1158 ISP_READ(isp, CDMA_FIFO_STS)); 1159 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1160 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1161 ISP_READ(isp, DDMA_FIFO_STS)); 1162 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1163 ISP_READ(isp, SXP_INTERRUPT), 1164 ISP_READ(isp, SXP_GROSS_ERR), 1165 ISP_READ(isp, SXP_PINS_CTRL)); 1166 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1167 } 1168 printf(" mbox regs: %x %x %x %x %x\n", 1169 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1170 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1171 ISP_READ(isp, OUTMAILBOX4)); 1172 printf(" PCI Status Command/Status=%x\n", 1173 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1174 } 1175
Indexes created Sat Sep 27 14:09:57 GMT 2025