isp_pci.c revision 1.75
1 /* $NetBSD: isp_pci.c,v 1.75 2001/12/14 00:13:47 mjacob Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 */ 33 /* 34 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 35 * All rights reserved. 36 * 37 * Additional Copyright (C) 2000, 2001 by Matthew Jacob 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.75 2001/12/14 00:13:47 mjacob Exp $"); 61 62 #include <dev/ic/isp_netbsd.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 #include <uvm/uvm_extern.h> 67 #include <sys/reboot.h> 68 69 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 70 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 71 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 72 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 73 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 74 #endif 75 static int 76 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 77 static int 78 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 79 static int isp_pci_mbxdma(struct ispsoftc *); 80 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, 81 u_int16_t *, u_int16_t); 82 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 83 static void isp_pci_reset1(struct ispsoftc *); 84 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 85 static int isp_pci_intr(void *); 86 87 #if defined(ISP_DISABLE_1020_SUPPORT) 88 #define ISP_1040_RISC_CODE NULL 89 #else 90 #define ISP_1040_RISC_CODE isp_1040_risc_code 91 #include <dev/microcode/isp/asm_1040.h> 92 #endif 93 94 #if defined(ISP_DISABLE_1080_SUPPORT) 95 #define ISP_1080_RISC_CODE NULL 96 #else 97 #define ISP_1080_RISC_CODE isp_1080_risc_code 98 #include <dev/microcode/isp/asm_1080.h> 99 #endif 100 101 #if defined(ISP_DISABLE_12160_SUPPORT) 102 #define ISP_12160_RISC_CODE NULL 103 #else 104 #define ISP_12160_RISC_CODE isp_12160_risc_code 105 #include <dev/microcode/isp/asm_12160.h> 106 #endif 107 108 #if defined(ISP_DISABLE_2100_SUPPORT) 109 #define ISP_2100_RISC_CODE NULL 110 #else 111 #define ISP_2100_RISC_CODE isp_2100_risc_code 112 #include <dev/microcode/isp/asm_2100.h> 113 #endif 114 115 #if defined(ISP_DISABLE_2200_SUPPORT) 116 #define ISP_2200_RISC_CODE NULL 117 #else 118 #define ISP_2200_RISC_CODE isp_2200_risc_code 119 #include <dev/microcode/isp/asm_2200.h> 120 #endif 121 122 #if defined(ISP_DISABLE_2300_SUPPORT) 123 #define ISP_2300_RISC_CODE NULL 124 #else 125 #define ISP_2300_RISC_CODE isp_2300_risc_code 126 #include <dev/microcode/isp/asm_2300.h> 127 #endif 128 129 #ifndef ISP_DISABLE_1020_SUPPORT 130 static struct ispmdvec mdvec = { 131 isp_pci_rd_isr, 132 isp_pci_rd_reg, 133 isp_pci_wr_reg, 134 isp_pci_mbxdma, 135 isp_pci_dmasetup, 136 isp_pci_dmateardown, 137 NULL, 138 isp_pci_reset1, 139 isp_pci_dumpregs, 140 ISP_1040_RISC_CODE, 141 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 142 }; 143 #endif 144 145 #ifndef ISP_DISABLE_1080_SUPPORT 146 static struct ispmdvec mdvec_1080 = { 147 isp_pci_rd_isr, 148 isp_pci_rd_reg_1080, 149 isp_pci_wr_reg_1080, 150 isp_pci_mbxdma, 151 isp_pci_dmasetup, 152 isp_pci_dmateardown, 153 NULL, 154 isp_pci_reset1, 155 isp_pci_dumpregs, 156 ISP_1080_RISC_CODE, 157 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 158 }; 159 #endif 160 161 #ifndef ISP_DISABLE_12160_SUPPORT 162 static struct ispmdvec mdvec_12160 = { 163 isp_pci_rd_isr, 164 isp_pci_rd_reg_1080, 165 isp_pci_wr_reg_1080, 166 isp_pci_mbxdma, 167 isp_pci_dmasetup, 168 isp_pci_dmateardown, 169 NULL, 170 isp_pci_reset1, 171 isp_pci_dumpregs, 172 ISP_12160_RISC_CODE, 173 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 174 }; 175 #endif 176 177 #ifndef ISP_DISABLE_2100_SUPPORT 178 static struct ispmdvec mdvec_2100 = { 179 isp_pci_rd_isr, 180 isp_pci_rd_reg, 181 isp_pci_wr_reg, 182 isp_pci_mbxdma, 183 isp_pci_dmasetup, 184 isp_pci_dmateardown, 185 NULL, 186 isp_pci_reset1, 187 isp_pci_dumpregs, 188 ISP_2100_RISC_CODE 189 }; 190 #endif 191 192 #ifndef ISP_DISABLE_2200_SUPPORT 193 static struct ispmdvec mdvec_2200 = { 194 isp_pci_rd_isr, 195 isp_pci_rd_reg, 196 isp_pci_wr_reg, 197 isp_pci_mbxdma, 198 isp_pci_dmasetup, 199 isp_pci_dmateardown, 200 NULL, 201 isp_pci_reset1, 202 isp_pci_dumpregs, 203 ISP_2200_RISC_CODE 204 }; 205 #endif 206 207 #ifndef ISP_DISABLE_2300_SUPPORT 208 static struct ispmdvec mdvec_2300 = { 209 isp_pci_rd_isr_2300, 210 isp_pci_rd_reg, 211 isp_pci_wr_reg, 212 isp_pci_mbxdma, 213 isp_pci_dmasetup, 214 isp_pci_dmateardown, 215 NULL, 216 isp_pci_reset1, 217 isp_pci_dumpregs, 218 ISP_2300_RISC_CODE 219 }; 220 #endif 221 222 #ifndef PCI_VENDOR_QLOGIC 223 #define PCI_VENDOR_QLOGIC 0x1077 224 #endif 225 226 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 227 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 228 #endif 229 230 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 231 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 232 #endif 233 234 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 235 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 236 #endif 237 238 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 239 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 240 #endif 241 242 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 243 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 244 #endif 245 246 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 247 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 248 #endif 249 250 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 251 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 252 #endif 253 254 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 255 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 256 #endif 257 258 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 259 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 260 #endif 261 262 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 263 264 #define PCI_QLOGIC_ISP1080 \ 265 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 266 267 #define PCI_QLOGIC_ISP1240 \ 268 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 269 270 #define PCI_QLOGIC_ISP1280 \ 271 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 272 273 #define PCI_QLOGIC_ISP12160 \ 274 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 275 276 #define PCI_QLOGIC_ISP2100 \ 277 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 278 279 #define PCI_QLOGIC_ISP2200 \ 280 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP2300 \ 283 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP2312 \ 286 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define IO_MAP_REG 0x10 289 #define MEM_MAP_REG 0x14 290 #define PCIR_ROMADDR 0x30 291 292 #define PCI_DFLT_LTNCY 0x40 293 #define PCI_DFLT_LNSZ 0x10 294 295 296 static int isp_pci_probe(struct device *, struct cfdata *, void *); 297 static void isp_pci_attach(struct device *, struct device *, void *); 298 299 struct isp_pcisoftc { 300 struct ispsoftc pci_isp; 301 pci_chipset_tag_t pci_pc; 302 pcitag_t pci_tag; 303 bus_space_tag_t pci_st; 304 bus_space_handle_t pci_sh; 305 bus_dmamap_t *pci_xfer_dmap; 306 void * pci_ih; 307 int16_t pci_poff[_NREG_BLKS]; 308 }; 309 310 struct cfattach isp_pci_ca = { 311 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach 312 }; 313 314 #ifdef DEBUG 315 const char vstring[] = 316 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 317 #endif 318 319 static int 320 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux) 321 { 322 struct pci_attach_args *pa = aux; 323 switch (pa->pa_id) { 324 #ifndef ISP_DISABLE_1020_SUPPORT 325 case PCI_QLOGIC_ISP: 326 return (1); 327 #endif 328 #ifndef ISP_DISABLE_1080_SUPPORT 329 case PCI_QLOGIC_ISP1080: 330 case PCI_QLOGIC_ISP1240: 331 case PCI_QLOGIC_ISP1280: 332 return (1); 333 #endif 334 #ifndef ISP_DISABLE_12160_SUPPORT 335 case PCI_QLOGIC_ISP12160: 336 return (1); 337 #endif 338 #ifndef ISP_DISABLE_2100_SUPPORT 339 case PCI_QLOGIC_ISP2100: 340 return (1); 341 #endif 342 #ifndef ISP_DISABLE_2200_SUPPORT 343 case PCI_QLOGIC_ISP2200: 344 return (1); 345 #endif 346 #ifndef ISP_DISABLE_2300_SUPPORT 347 case PCI_QLOGIC_ISP2300: 348 case PCI_QLOGIC_ISP2312: 349 return (1); 350 #endif 351 default: 352 return (0); 353 } 354 } 355 356 357 static void 358 isp_pci_attach(struct device *parent, struct device *self, void *aux) 359 { 360 #ifdef DEBUG 361 static char oneshot = 1; 362 #endif 363 static const char nomem[] = "%s: no mem for sdparam table\n"; 364 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 365 struct pci_attach_args *pa = aux; 366 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 367 struct ispsoftc *isp = &pcs->pci_isp; 368 bus_space_tag_t st, iot, memt; 369 bus_space_handle_t sh, ioh, memh; 370 pci_intr_handle_t ih; 371 const char *intrstr; 372 int ioh_valid, memh_valid; 373 374 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 375 PCI_MAPREG_TYPE_IO, 0, 376 &iot, &ioh, NULL, NULL) == 0); 377 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 378 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 379 &memt, &memh, NULL, NULL) == 0); 380 if (memh_valid) { 381 st = memt; 382 sh = memh; 383 } else if (ioh_valid) { 384 st = iot; 385 sh = ioh; 386 } else { 387 printf(": unable to map device registers\n"); 388 return; 389 } 390 printf("\n"); 391 392 pcs->pci_st = st; 393 pcs->pci_sh = sh; 394 pcs->pci_pc = pa->pa_pc; 395 pcs->pci_tag = pa->pa_tag; 396 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 397 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 398 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 399 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 400 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 401 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 402 403 #ifndef ISP_DISABLE_1020_SUPPORT 404 if (pa->pa_id == PCI_QLOGIC_ISP) { 405 isp->isp_mdvec = &mdvec; 406 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 407 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 408 if (isp->isp_param == NULL) { 409 printf(nomem, isp->isp_name); 410 return; 411 } 412 memset(isp->isp_param, 0, sizeof (sdparam)); 413 } 414 #endif 415 #ifndef ISP_DISABLE_1080_SUPPORT 416 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 417 isp->isp_mdvec = &mdvec_1080; 418 isp->isp_type = ISP_HA_SCSI_1080; 419 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 420 if (isp->isp_param == NULL) { 421 printf(nomem, isp->isp_name); 422 return; 423 } 424 memset(isp->isp_param, 0, sizeof (sdparam)); 425 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 426 ISP1080_DMA_REGS_OFF; 427 } 428 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 429 isp->isp_mdvec = &mdvec_1080; 430 isp->isp_type = ISP_HA_SCSI_1240; 431 isp->isp_param = 432 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 433 if (isp->isp_param == NULL) { 434 printf(nomem, isp->isp_name); 435 return; 436 } 437 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 438 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 439 ISP1080_DMA_REGS_OFF; 440 } 441 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 442 isp->isp_mdvec = &mdvec_1080; 443 isp->isp_type = ISP_HA_SCSI_1280; 444 isp->isp_param = 445 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 446 if (isp->isp_param == NULL) { 447 printf(nomem, isp->isp_name); 448 return; 449 } 450 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 451 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 452 ISP1080_DMA_REGS_OFF; 453 } 454 #endif 455 #ifndef ISP_DISABLE_12160_SUPPORT 456 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 457 isp->isp_mdvec = &mdvec_12160; 458 isp->isp_type = ISP_HA_SCSI_12160; 459 isp->isp_param = 460 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 461 if (isp->isp_param == NULL) { 462 printf(nomem, isp->isp_name); 463 return; 464 } 465 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 466 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 467 ISP1080_DMA_REGS_OFF; 468 } 469 #endif 470 #ifndef ISP_DISABLE_2100_SUPPORT 471 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 472 isp->isp_mdvec = &mdvec_2100; 473 isp->isp_type = ISP_HA_FC_2100; 474 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 475 if (isp->isp_param == NULL) { 476 printf(nomem, isp->isp_name); 477 return; 478 } 479 memset(isp->isp_param, 0, sizeof (fcparam)); 480 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 481 PCI_MBOX_REGS2100_OFF; 482 if (rev < 3) { 483 /* 484 * XXX: Need to get the actual revision 485 * XXX: number of the 2100 FB. At any rate, 486 * XXX: lower cache line size for early revision 487 * XXX; boards. 488 */ 489 linesz = 1; 490 } 491 } 492 #endif 493 #ifndef ISP_DISABLE_2200_SUPPORT 494 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 495 isp->isp_mdvec = &mdvec_2200; 496 isp->isp_type = ISP_HA_FC_2200; 497 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 498 if (isp->isp_param == NULL) { 499 printf(nomem, isp->isp_name); 500 return; 501 } 502 memset(isp->isp_param, 0, sizeof (fcparam)); 503 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 504 PCI_MBOX_REGS2100_OFF; 505 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 506 } 507 #endif 508 #ifndef ISP_DISABLE_2300_SUPPORT 509 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 510 pa->pa_id == PCI_QLOGIC_ISP2312) { 511 isp->isp_mdvec = &mdvec_2300; 512 isp->isp_type = ISP_HA_FC_2300; 513 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 514 if (isp->isp_param == NULL) { 515 printf(nomem, isp->isp_name); 516 return; 517 } 518 memset(isp->isp_param, 0, sizeof (fcparam)); 519 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 520 PCI_MBOX_REGS2300_OFF; 521 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 522 } 523 #endif 524 /* 525 * Set up logging levels. 526 */ 527 #ifdef ISP_LOGDEFAULT 528 isp->isp_dblev = ISP_LOGDEFAULT; 529 #else 530 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 531 if (bootverbose) 532 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 533 #ifdef SCSIDEBUG 534 isp->isp_dblev |= ISP_LOGDEBUG1|ISP_LOGDEBUG2; 535 #endif 536 #ifdef DEBUG 537 isp->isp_dblev |= ISP_LOGDEBUG0; 538 #endif 539 #endif 540 541 #ifdef DEBUG 542 if (oneshot) { 543 oneshot = 0; 544 isp_prt(isp, ISP_LOGCONFIG, vstring, 545 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 546 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 547 } 548 #endif 549 550 isp->isp_dmatag = pa->pa_dmat; 551 isp->isp_revision = rev; 552 553 /* 554 * Make sure that command register set sanely. 555 */ 556 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 557 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 558 559 /* 560 * Not so sure about these- but I think it's important that they get 561 * enabled...... 562 */ 563 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 564 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 565 566 /* 567 * Make sure that the latency timer, cache line size, 568 * and ROM is disabled. 569 */ 570 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 571 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 572 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 573 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 574 data |= (linesz << PCI_CACHELINE_SHIFT); 575 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 576 577 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 578 data &= ~1; 579 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 580 581 if (pci_intr_map(pa, &ih)) { 582 printf("%s: couldn't map interrupt\n", isp->isp_name); 583 free(isp->isp_param, M_DEVBUF); 584 return; 585 } 586 intrstr = pci_intr_string(pa->pa_pc, ih); 587 if (intrstr == NULL) 588 intrstr = "<I dunno>"; 589 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 590 isp_pci_intr, isp); 591 if (pcs->pci_ih == NULL) { 592 printf("%s: couldn't establish interrupt at %s\n", 593 isp->isp_name, intrstr); 594 free(isp->isp_param, M_DEVBUF); 595 return; 596 } 597 598 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 599 600 if (IS_FC(isp)) { 601 DEFAULT_NODEWWN(isp) = 0x400000007F000002; 602 DEFAULT_PORTWWN(isp) = 0x400000007F000002; 603 } 604 605 isp->isp_confopts = self->dv_cfdata->cf_flags; 606 isp->isp_role = ISP_DEFAULT_ROLES; 607 ISP_LOCK(isp); 608 isp->isp_osinfo.no_mbox_ints = 1; 609 isp_reset(isp); 610 if (isp->isp_state != ISP_RESETSTATE) { 611 ISP_UNLOCK(isp); 612 free(isp->isp_param, M_DEVBUF); 613 return; 614 } 615 ENABLE_INTS(isp); 616 isp_init(isp); 617 if (isp->isp_state != ISP_INITSTATE) { 618 isp_uninit(isp); 619 ISP_UNLOCK(isp); 620 free(isp->isp_param, M_DEVBUF); 621 return; 622 } 623 /* 624 * Do platform attach. 625 */ 626 ISP_UNLOCK(isp); 627 isp_attach(isp); 628 if (isp->isp_state != ISP_RUNSTATE) { 629 ISP_LOCK(isp); 630 isp_uninit(isp); 631 free(isp->isp_param, M_DEVBUF); 632 ISP_UNLOCK(isp); 633 } 634 } 635 636 #define IspVirt2Off(a, x) \ 637 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 638 _BLK_REG_SHFT] + ((x) & 0xff)) 639 640 #define BXR2(pcs, off) \ 641 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 642 #define BXW2(pcs, off, v) \ 643 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 644 645 646 static INLINE int 647 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 648 { 649 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 650 u_int16_t val0, val1; 651 int i = 0; 652 653 do { 654 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 655 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 656 } while (val0 != val1 && ++i < 1000); 657 if (val0 != val1) { 658 return (1); 659 } 660 *rp = val0; 661 return (0); 662 } 663 664 static int 665 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 666 u_int16_t *semap, u_int16_t *mbp) 667 { 668 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 669 u_int16_t isr, sema; 670 671 if (IS_2100(isp)) { 672 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 673 return (0); 674 } 675 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 676 return (0); 677 } 678 } else { 679 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 680 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 681 } 682 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 683 isr &= INT_PENDING_MASK(isp); 684 sema &= BIU_SEMA_LOCK; 685 if (isr == 0 && sema == 0) { 686 return (0); 687 } 688 *isrp = isr; 689 if ((*semap = sema) != 0) { 690 if (IS_2100(isp)) { 691 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 692 return (0); 693 } 694 } else { 695 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 696 } 697 } 698 return (1); 699 } 700 701 #ifndef ISP_DISABLE_2300_SUPPORT 702 static int 703 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 704 u_int16_t *semap, u_int16_t *mbox0p) 705 { 706 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 707 u_int32_t r2hisr; 708 709 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 710 *isrp = 0; 711 return (0); 712 } 713 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 714 IspVirt2Off(pcs, BIU_R2HSTSLO)); 715 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 716 if ((r2hisr & BIU_R2HST_INTR) == 0) { 717 *isrp = 0; 718 return (0); 719 } 720 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 721 case ISPR2HST_ROM_MBX_OK: 722 case ISPR2HST_ROM_MBX_FAIL: 723 case ISPR2HST_MBX_OK: 724 case ISPR2HST_MBX_FAIL: 725 case ISPR2HST_ASYNC_EVENT: 726 case ISPR2HST_FPOST: 727 case ISPR2HST_FPOST_CTIO: 728 *isrp = r2hisr & 0xffff; 729 *mbox0p = (r2hisr >> 16); 730 *semap = 1; 731 return (1); 732 case ISPR2HST_RSPQ_UPDATE: 733 *isrp = r2hisr & 0xffff; 734 *mbox0p = 0; 735 *semap = 0; 736 return (1); 737 default: 738 return (0); 739 } 740 } 741 #endif 742 743 static u_int16_t 744 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 745 { 746 u_int16_t rv; 747 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 748 int oldconf = 0; 749 750 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 751 /* 752 * We will assume that someone has paused the RISC processor. 753 */ 754 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 755 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 756 oldconf | BIU_PCI_CONF1_SXP); 757 } 758 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 759 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 760 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 761 } 762 return (rv); 763 } 764 765 static void 766 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 767 { 768 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 769 int oldconf = 0; 770 771 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 772 /* 773 * We will assume that someone has paused the RISC processor. 774 */ 775 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 776 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 777 oldconf | BIU_PCI_CONF1_SXP); 778 } 779 BXW2(pcs, IspVirt2Off(isp, regoff), val); 780 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 781 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 782 } 783 } 784 785 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 786 static u_int16_t 787 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 788 { 789 u_int16_t rv, oc = 0; 790 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 791 792 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 793 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 794 u_int16_t tc; 795 /* 796 * We will assume that someone has paused the RISC processor. 797 */ 798 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 799 tc = oc & ~BIU_PCI1080_CONF1_DMA; 800 if (regoff & SXP_BANK1_SELECT) 801 tc |= BIU_PCI1080_CONF1_SXP1; 802 else 803 tc |= BIU_PCI1080_CONF1_SXP0; 804 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 805 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 806 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 807 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 808 oc | BIU_PCI1080_CONF1_DMA); 809 } 810 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 811 if (oc) { 812 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 813 } 814 return (rv); 815 } 816 817 static void 818 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 819 { 820 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 821 int oc = 0; 822 823 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 824 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 825 u_int16_t tc; 826 /* 827 * We will assume that someone has paused the RISC processor. 828 */ 829 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 830 tc = oc & ~BIU_PCI1080_CONF1_DMA; 831 if (regoff & SXP_BANK1_SELECT) 832 tc |= BIU_PCI1080_CONF1_SXP1; 833 else 834 tc |= BIU_PCI1080_CONF1_SXP0; 835 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 836 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 837 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 838 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 839 oc | BIU_PCI1080_CONF1_DMA); 840 } 841 BXW2(pcs, IspVirt2Off(isp, regoff), val); 842 if (oc) { 843 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 844 } 845 } 846 #endif 847 848 static int 849 isp_pci_mbxdma(struct ispsoftc *isp) 850 { 851 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 852 bus_dma_tag_t dmat = isp->isp_dmatag; 853 bus_dma_segment_t sg; 854 bus_size_t len; 855 fcparam *fcp; 856 int rs, i; 857 858 if (isp->isp_rquest_dma) /* been here before? */ 859 return (0); 860 861 len = isp->isp_maxcmds * sizeof (XS_T *); 862 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 863 if (isp->isp_xflist == NULL) { 864 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 865 return (1); 866 } 867 memset(isp->isp_xflist, 0, len); 868 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 869 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 870 if (pcs->pci_xfer_dmap == NULL) { 871 free(isp->isp_xflist, M_DEVBUF); 872 isp->isp_xflist = NULL; 873 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array"); 874 return (1); 875 } 876 for (i = 0; i < isp->isp_maxcmds; i++) { 877 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 878 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 879 isp_prt(isp, ISP_LOGERR, "cannot create dma maps"); 880 break; 881 } 882 } 883 if (i < isp->isp_maxcmds) { 884 while (--i >= 0) { 885 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 886 } 887 free(isp->isp_xflist, M_DEVBUF); 888 free(pcs->pci_xfer_dmap, M_DEVBUF); 889 isp->isp_xflist = NULL; 890 pcs->pci_xfer_dmap = NULL; 891 return (1); 892 } 893 894 /* 895 * Allocate and map the request queue. 896 */ 897 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 898 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 899 BUS_DMA_NOWAIT) || 900 bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 901 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 902 goto dmafail; 903 } 904 905 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 906 &isp->isp_rqdmap) || bus_dmamap_load(dmat, isp->isp_rqdmap, 907 (caddr_t)isp->isp_rquest, len, NULL, 908 BUS_DMA_NOWAIT)) { 909 goto dmafail; 910 } 911 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 912 913 /* 914 * Allocate and map the result queue. 915 */ 916 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 917 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 918 BUS_DMA_NOWAIT) || 919 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 920 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 921 goto dmafail; 922 } 923 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 924 &isp->isp_rsdmap) || bus_dmamap_load(isp->isp_dmatag, 925 isp->isp_rsdmap, (caddr_t)isp->isp_result, len, NULL, 926 BUS_DMA_NOWAIT)) { 927 goto dmafail; 928 } 929 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 930 931 if (IS_SCSI(isp)) { 932 return (0); 933 } 934 935 fcp = isp->isp_param; 936 len = ISP2100_SCRLEN; 937 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 938 BUS_DMA_NOWAIT) || 939 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 940 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 941 goto dmafail; 942 } 943 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 944 &isp->isp_scdmap) || bus_dmamap_load(dmat, 945 isp->isp_scdmap, (caddr_t)fcp->isp_scratch, len, NULL, 946 BUS_DMA_NOWAIT)) { 947 goto dmafail; 948 } 949 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 950 return (0); 951 dmafail: 952 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure"); 953 for (i = 0; i < isp->isp_maxcmds; i++) { 954 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 955 } 956 free(isp->isp_xflist, M_DEVBUF); 957 free(pcs->pci_xfer_dmap, M_DEVBUF); 958 isp->isp_xflist = NULL; 959 pcs->pci_xfer_dmap = NULL; 960 return (1); 961 } 962 963 static int 964 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq, 965 u_int16_t *nxtip, u_int16_t optr) 966 { 967 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 968 bus_dmamap_t dmap; 969 u_int16_t starti = isp->isp_reqidx, nxti = *nxtip; 970 ispreq_t *qep; 971 int segcnt, seg, error, ovseg, seglim, drq; 972 973 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, starti); 974 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 975 if (xs->datalen == 0) { 976 rq->req_seg_count = 1; 977 goto mbxsync; 978 } 979 if (xs->xs_control & XS_CTL_DATA_IN) { 980 drq = REQFLAG_DATA_IN; 981 } else { 982 drq = REQFLAG_DATA_OUT; 983 } 984 985 if (IS_FC(isp)) { 986 seglim = ISP_RQDSEG_T2; 987 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 988 ((ispreqt2_t *)rq)->req_flags |= drq; 989 } else { 990 rq->req_flags |= drq; 991 if (XS_CDBLEN(xs) > 12) { 992 seglim = 0; 993 } else { 994 seglim = ISP_RQDSEG; 995 } 996 } 997 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 998 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 999 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 1000 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1001 if (error) { 1002 XS_SETERR(xs, HBA_BOTCH); 1003 return (CMD_COMPLETE); 1004 } 1005 1006 segcnt = dmap->dm_nsegs; 1007 1008 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 1009 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 1010 "write from", xs->data, segcnt); 1011 1012 for (seg = 0, rq->req_seg_count = 0; 1013 seglim && seg < segcnt && rq->req_seg_count < seglim; 1014 seg++, rq->req_seg_count++) { 1015 if (IS_FC(isp)) { 1016 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1017 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1018 dmap->dm_segs[seg].ds_len; 1019 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1020 dmap->dm_segs[seg].ds_addr; 1021 } else { 1022 rq->req_dataseg[rq->req_seg_count].ds_count = 1023 dmap->dm_segs[seg].ds_len; 1024 rq->req_dataseg[rq->req_seg_count].ds_base = 1025 dmap->dm_segs[seg].ds_addr; 1026 } 1027 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 1028 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 1029 (unsigned long) dmap->dm_segs[seg].ds_len); 1030 } 1031 1032 if (seg == segcnt) { 1033 goto dmasync; 1034 } 1035 1036 do { 1037 u_int16_t onxti; 1038 ispcontreq_t *crq, *cqe, local; 1039 1040 crq = &local; 1041 1042 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1043 onxti = nxti; 1044 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1045 if (nxti == optr) { 1046 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1047 bus_dmamap_unload(isp->isp_dmatag, dmap); 1048 XS_SETERR(xs, HBA_BOTCH); 1049 return (CMD_EAGAIN); 1050 } 1051 rq->req_header.rqs_entry_count++; 1052 memset((void *)crq, 0, sizeof (*crq)); 1053 crq->req_header.rqs_entry_count = 1; 1054 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1055 1056 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 1057 rq->req_seg_count++, seg++, ovseg++) { 1058 crq->req_dataseg[ovseg].ds_count = 1059 dmap->dm_segs[seg].ds_len; 1060 crq->req_dataseg[ovseg].ds_base = 1061 dmap->dm_segs[seg].ds_addr; 1062 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 1063 rq->req_header.rqs_entry_count - 1, 1064 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 1065 (unsigned long) dmap->dm_segs[seg].ds_len); 1066 } 1067 isp_put_cont_req(isp, crq, cqe); 1068 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1069 } while (seg < segcnt); 1070 1071 1072 dmasync: 1073 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1074 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 1075 BUS_DMASYNC_PREWRITE); 1076 1077 mbxsync: 1078 switch (rq->req_header.rqs_entry_type) { 1079 case RQSTYPE_REQUEST: 1080 isp_put_request(isp, rq, qep); 1081 break; 1082 case RQSTYPE_CMDONLY: 1083 isp_put_extended_request(isp, (ispextreq_t *)rq, 1084 (ispextreq_t *)qep); 1085 break; 1086 case RQSTYPE_T2RQS: 1087 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1088 break; 1089 } 1090 *nxtip = nxti; 1091 return (CMD_QUEUED); 1092 } 1093 1094 static int 1095 isp_pci_intr(void *arg) 1096 { 1097 u_int16_t isr, sema, mbox; 1098 struct ispsoftc *isp = arg; 1099 1100 isp->isp_intcnt++; 1101 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1102 isp->isp_intbogus++; 1103 return (0); 1104 } else { 1105 isp->isp_osinfo.onintstack = 1; 1106 isp_intr(isp, isr, sema, mbox); 1107 isp->isp_osinfo.onintstack = 0; 1108 return (1); 1109 } 1110 } 1111 1112 static void 1113 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1114 { 1115 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1116 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 1117 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1118 xs->xs_control & XS_CTL_DATA_IN ? 1119 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1120 bus_dmamap_unload(isp->isp_dmatag, dmap); 1121 } 1122 1123 static void 1124 isp_pci_reset1(struct ispsoftc *isp) 1125 { 1126 /* Make sure the BIOS is disabled */ 1127 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1128 } 1129 1130 static void 1131 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1132 { 1133 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1134 if (msg) 1135 printf("%s: %s\n", isp->isp_name, msg); 1136 if (IS_SCSI(isp)) 1137 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1138 else 1139 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1140 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1141 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1142 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1143 1144 1145 if (IS_SCSI(isp)) { 1146 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1147 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1148 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1149 ISP_READ(isp, CDMA_FIFO_STS)); 1150 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1151 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1152 ISP_READ(isp, DDMA_FIFO_STS)); 1153 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1154 ISP_READ(isp, SXP_INTERRUPT), 1155 ISP_READ(isp, SXP_GROSS_ERR), 1156 ISP_READ(isp, SXP_PINS_CTRL)); 1157 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1158 } 1159 printf(" mbox regs: %x %x %x %x %x\n", 1160 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1161 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1162 ISP_READ(isp, OUTMAILBOX4)); 1163 printf(" PCI Status Command/Status=%x\n", 1164 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1165 } 1166
Indexes created Mon Sep 29 03:10:08 GMT 2025