isp_pci.c revision 1.76
1 /* $NetBSD: isp_pci.c,v 1.76 2002/02/21 22:32:43 mjacob Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 */ 33 /* 34 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 35 * All rights reserved. 36 * 37 * Additional Copyright (C) 2000, 2001 by Matthew Jacob 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.76 2002/02/21 22:32:43 mjacob Exp $"); 61 62 #include <dev/ic/isp_netbsd.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 #include <uvm/uvm_extern.h> 67 #include <sys/reboot.h> 68 69 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 70 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 71 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 72 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 73 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 74 #endif 75 static int 76 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 77 static int 78 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 79 static int isp_pci_mbxdma(struct ispsoftc *); 80 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, 81 u_int16_t *, u_int16_t); 82 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 83 static void isp_pci_reset1(struct ispsoftc *); 84 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 85 static int isp_pci_intr(void *); 86 87 #if defined(ISP_DISABLE_1020_SUPPORT) 88 #define ISP_1040_RISC_CODE NULL 89 #else 90 #define ISP_1040_RISC_CODE isp_1040_risc_code 91 #include <dev/microcode/isp/asm_1040.h> 92 #endif 93 94 #if defined(ISP_DISABLE_1080_SUPPORT) 95 #define ISP_1080_RISC_CODE NULL 96 #else 97 #define ISP_1080_RISC_CODE isp_1080_risc_code 98 #include <dev/microcode/isp/asm_1080.h> 99 #endif 100 101 #if defined(ISP_DISABLE_12160_SUPPORT) 102 #define ISP_12160_RISC_CODE NULL 103 #else 104 #define ISP_12160_RISC_CODE isp_12160_risc_code 105 #include <dev/microcode/isp/asm_12160.h> 106 #endif 107 108 #if defined(ISP_DISABLE_2100_SUPPORT) 109 #define ISP_2100_RISC_CODE NULL 110 #else 111 #define ISP_2100_RISC_CODE isp_2100_risc_code 112 #include <dev/microcode/isp/asm_2100.h> 113 #endif 114 115 #if defined(ISP_DISABLE_2200_SUPPORT) 116 #define ISP_2200_RISC_CODE NULL 117 #else 118 #define ISP_2200_RISC_CODE isp_2200_risc_code 119 #include <dev/microcode/isp/asm_2200.h> 120 #endif 121 122 #if defined(ISP_DISABLE_2300_SUPPORT) 123 #define ISP_2300_RISC_CODE NULL 124 #else 125 #define ISP_2300_RISC_CODE isp_2300_risc_code 126 #include <dev/microcode/isp/asm_2300.h> 127 #endif 128 129 #ifndef ISP_DISABLE_1020_SUPPORT 130 static struct ispmdvec mdvec = { 131 isp_pci_rd_isr, 132 isp_pci_rd_reg, 133 isp_pci_wr_reg, 134 isp_pci_mbxdma, 135 isp_pci_dmasetup, 136 isp_pci_dmateardown, 137 NULL, 138 isp_pci_reset1, 139 isp_pci_dumpregs, 140 ISP_1040_RISC_CODE, 141 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 142 }; 143 #endif 144 145 #ifndef ISP_DISABLE_1080_SUPPORT 146 static struct ispmdvec mdvec_1080 = { 147 isp_pci_rd_isr, 148 isp_pci_rd_reg_1080, 149 isp_pci_wr_reg_1080, 150 isp_pci_mbxdma, 151 isp_pci_dmasetup, 152 isp_pci_dmateardown, 153 NULL, 154 isp_pci_reset1, 155 isp_pci_dumpregs, 156 ISP_1080_RISC_CODE, 157 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 158 }; 159 #endif 160 161 #ifndef ISP_DISABLE_12160_SUPPORT 162 static struct ispmdvec mdvec_12160 = { 163 isp_pci_rd_isr, 164 isp_pci_rd_reg_1080, 165 isp_pci_wr_reg_1080, 166 isp_pci_mbxdma, 167 isp_pci_dmasetup, 168 isp_pci_dmateardown, 169 NULL, 170 isp_pci_reset1, 171 isp_pci_dumpregs, 172 ISP_12160_RISC_CODE, 173 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 174 }; 175 #endif 176 177 #ifndef ISP_DISABLE_2100_SUPPORT 178 static struct ispmdvec mdvec_2100 = { 179 isp_pci_rd_isr, 180 isp_pci_rd_reg, 181 isp_pci_wr_reg, 182 isp_pci_mbxdma, 183 isp_pci_dmasetup, 184 isp_pci_dmateardown, 185 NULL, 186 isp_pci_reset1, 187 isp_pci_dumpregs, 188 ISP_2100_RISC_CODE 189 }; 190 #endif 191 192 #ifndef ISP_DISABLE_2200_SUPPORT 193 static struct ispmdvec mdvec_2200 = { 194 isp_pci_rd_isr, 195 isp_pci_rd_reg, 196 isp_pci_wr_reg, 197 isp_pci_mbxdma, 198 isp_pci_dmasetup, 199 isp_pci_dmateardown, 200 NULL, 201 isp_pci_reset1, 202 isp_pci_dumpregs, 203 ISP_2200_RISC_CODE 204 }; 205 #endif 206 207 #ifndef ISP_DISABLE_2300_SUPPORT 208 static struct ispmdvec mdvec_2300 = { 209 isp_pci_rd_isr_2300, 210 isp_pci_rd_reg, 211 isp_pci_wr_reg, 212 isp_pci_mbxdma, 213 isp_pci_dmasetup, 214 isp_pci_dmateardown, 215 NULL, 216 isp_pci_reset1, 217 isp_pci_dumpregs, 218 ISP_2300_RISC_CODE 219 }; 220 #endif 221 222 #ifndef PCI_VENDOR_QLOGIC 223 #define PCI_VENDOR_QLOGIC 0x1077 224 #endif 225 226 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 227 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 228 #endif 229 230 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 231 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 232 #endif 233 234 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 235 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 236 #endif 237 238 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 239 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 240 #endif 241 242 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 243 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 244 #endif 245 246 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 247 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 248 #endif 249 250 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 251 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 252 #endif 253 254 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 255 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 256 #endif 257 258 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 259 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 260 #endif 261 262 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 263 264 #define PCI_QLOGIC_ISP1080 \ 265 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 266 267 #define PCI_QLOGIC_ISP1240 \ 268 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 269 270 #define PCI_QLOGIC_ISP1280 \ 271 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 272 273 #define PCI_QLOGIC_ISP12160 \ 274 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 275 276 #define PCI_QLOGIC_ISP2100 \ 277 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 278 279 #define PCI_QLOGIC_ISP2200 \ 280 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP2300 \ 283 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP2312 \ 286 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define IO_MAP_REG 0x10 289 #define MEM_MAP_REG 0x14 290 #define PCIR_ROMADDR 0x30 291 292 #define PCI_DFLT_LTNCY 0x40 293 #define PCI_DFLT_LNSZ 0x10 294 295 296 static int isp_pci_probe(struct device *, struct cfdata *, void *); 297 static void isp_pci_attach(struct device *, struct device *, void *); 298 299 struct isp_pcisoftc { 300 struct ispsoftc pci_isp; 301 pci_chipset_tag_t pci_pc; 302 pcitag_t pci_tag; 303 bus_space_tag_t pci_st; 304 bus_space_handle_t pci_sh; 305 bus_dmamap_t *pci_xfer_dmap; 306 void * pci_ih; 307 int16_t pci_poff[_NREG_BLKS]; 308 }; 309 310 struct cfattach isp_pci_ca = { 311 sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach 312 }; 313 314 #ifdef DEBUG 315 const char vstring[] = 316 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 317 #endif 318 319 static int 320 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux) 321 { 322 struct pci_attach_args *pa = aux; 323 switch (pa->pa_id) { 324 #ifndef ISP_DISABLE_1020_SUPPORT 325 case PCI_QLOGIC_ISP: 326 return (1); 327 #endif 328 #ifndef ISP_DISABLE_1080_SUPPORT 329 case PCI_QLOGIC_ISP1080: 330 case PCI_QLOGIC_ISP1240: 331 case PCI_QLOGIC_ISP1280: 332 return (1); 333 #endif 334 #ifndef ISP_DISABLE_12160_SUPPORT 335 case PCI_QLOGIC_ISP12160: 336 return (1); 337 #endif 338 #ifndef ISP_DISABLE_2100_SUPPORT 339 case PCI_QLOGIC_ISP2100: 340 return (1); 341 #endif 342 #ifndef ISP_DISABLE_2200_SUPPORT 343 case PCI_QLOGIC_ISP2200: 344 return (1); 345 #endif 346 #ifndef ISP_DISABLE_2300_SUPPORT 347 case PCI_QLOGIC_ISP2300: 348 case PCI_QLOGIC_ISP2312: 349 return (1); 350 #endif 351 default: 352 return (0); 353 } 354 } 355 356 357 static void 358 isp_pci_attach(struct device *parent, struct device *self, void *aux) 359 { 360 #ifdef DEBUG 361 static char oneshot = 1; 362 #endif 363 static const char nomem[] = "%s: no mem for sdparam table\n"; 364 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 365 struct pci_attach_args *pa = aux; 366 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 367 struct ispsoftc *isp = &pcs->pci_isp; 368 bus_space_tag_t st, iot, memt; 369 bus_space_handle_t sh, ioh, memh; 370 pci_intr_handle_t ih; 371 const char *intrstr; 372 int ioh_valid, memh_valid; 373 374 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 375 PCI_MAPREG_TYPE_IO, 0, 376 &iot, &ioh, NULL, NULL) == 0); 377 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 378 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 379 &memt, &memh, NULL, NULL) == 0); 380 if (memh_valid) { 381 st = memt; 382 sh = memh; 383 } else if (ioh_valid) { 384 st = iot; 385 sh = ioh; 386 } else { 387 printf(": unable to map device registers\n"); 388 return; 389 } 390 printf("\n"); 391 392 pcs->pci_st = st; 393 pcs->pci_sh = sh; 394 pcs->pci_pc = pa->pa_pc; 395 pcs->pci_tag = pa->pa_tag; 396 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 397 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 398 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 399 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 400 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 401 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 402 403 #ifndef ISP_DISABLE_1020_SUPPORT 404 if (pa->pa_id == PCI_QLOGIC_ISP) { 405 isp->isp_mdvec = &mdvec; 406 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 407 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 408 if (isp->isp_param == NULL) { 409 printf(nomem, isp->isp_name); 410 return; 411 } 412 memset(isp->isp_param, 0, sizeof (sdparam)); 413 } 414 #endif 415 #ifndef ISP_DISABLE_1080_SUPPORT 416 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 417 isp->isp_mdvec = &mdvec_1080; 418 isp->isp_type = ISP_HA_SCSI_1080; 419 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 420 if (isp->isp_param == NULL) { 421 printf(nomem, isp->isp_name); 422 return; 423 } 424 memset(isp->isp_param, 0, sizeof (sdparam)); 425 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 426 ISP1080_DMA_REGS_OFF; 427 } 428 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 429 isp->isp_mdvec = &mdvec_1080; 430 isp->isp_type = ISP_HA_SCSI_1240; 431 isp->isp_param = 432 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 433 if (isp->isp_param == NULL) { 434 printf(nomem, isp->isp_name); 435 return; 436 } 437 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 438 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 439 ISP1080_DMA_REGS_OFF; 440 } 441 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 442 isp->isp_mdvec = &mdvec_1080; 443 isp->isp_type = ISP_HA_SCSI_1280; 444 isp->isp_param = 445 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 446 if (isp->isp_param == NULL) { 447 printf(nomem, isp->isp_name); 448 return; 449 } 450 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 451 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 452 ISP1080_DMA_REGS_OFF; 453 } 454 #endif 455 #ifndef ISP_DISABLE_12160_SUPPORT 456 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 457 isp->isp_mdvec = &mdvec_12160; 458 isp->isp_type = ISP_HA_SCSI_12160; 459 isp->isp_param = 460 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 461 if (isp->isp_param == NULL) { 462 printf(nomem, isp->isp_name); 463 return; 464 } 465 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 466 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 467 ISP1080_DMA_REGS_OFF; 468 } 469 #endif 470 #ifndef ISP_DISABLE_2100_SUPPORT 471 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 472 isp->isp_mdvec = &mdvec_2100; 473 isp->isp_type = ISP_HA_FC_2100; 474 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 475 if (isp->isp_param == NULL) { 476 printf(nomem, isp->isp_name); 477 return; 478 } 479 memset(isp->isp_param, 0, sizeof (fcparam)); 480 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 481 PCI_MBOX_REGS2100_OFF; 482 if (rev < 3) { 483 /* 484 * XXX: Need to get the actual revision 485 * XXX: number of the 2100 FB. At any rate, 486 * XXX: lower cache line size for early revision 487 * XXX; boards. 488 */ 489 linesz = 1; 490 } 491 } 492 #endif 493 #ifndef ISP_DISABLE_2200_SUPPORT 494 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 495 isp->isp_mdvec = &mdvec_2200; 496 isp->isp_type = ISP_HA_FC_2200; 497 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 498 if (isp->isp_param == NULL) { 499 printf(nomem, isp->isp_name); 500 return; 501 } 502 memset(isp->isp_param, 0, sizeof (fcparam)); 503 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 504 PCI_MBOX_REGS2100_OFF; 505 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 506 } 507 #endif 508 #ifndef ISP_DISABLE_2300_SUPPORT 509 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 510 pa->pa_id == PCI_QLOGIC_ISP2312) { 511 isp->isp_mdvec = &mdvec_2300; 512 if (pa->pa_id == PCI_QLOGIC_ISP2300) { 513 isp->isp_type = ISP_HA_FC_2300; 514 } else { 515 isp->isp_type = ISP_HA_FC_2312; 516 isp->isp_port = pa->pa_function; 517 } 518 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 519 if (isp->isp_param == NULL) { 520 printf(nomem, isp->isp_name); 521 return; 522 } 523 memset(isp->isp_param, 0, sizeof (fcparam)); 524 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 525 PCI_MBOX_REGS2300_OFF; 526 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 527 } 528 #endif 529 /* 530 * Set up logging levels. 531 */ 532 #ifdef ISP_LOGDEFAULT 533 isp->isp_dblev = ISP_LOGDEFAULT; 534 #else 535 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 536 if (bootverbose) 537 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 538 #ifdef SCSIDEBUG 539 isp->isp_dblev |= ISP_LOGDEBUG1|ISP_LOGDEBUG2; 540 #endif 541 #ifdef DEBUG 542 isp->isp_dblev |= ISP_LOGDEBUG0; 543 #endif 544 #endif 545 546 #ifdef DEBUG 547 if (oneshot) { 548 oneshot = 0; 549 isp_prt(isp, ISP_LOGCONFIG, vstring, 550 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 551 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 552 } 553 #endif 554 555 isp->isp_dmatag = pa->pa_dmat; 556 isp->isp_revision = rev; 557 558 /* 559 * Make sure that command register set sanely. 560 */ 561 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 562 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 563 564 /* 565 * Not so sure about these- but I think it's important that they get 566 * enabled...... 567 */ 568 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 569 if (IS_2300(isp)) { /* per QLogic errata */ 570 data &= ~PCI_COMMAND_INVALIDATE_ENABLE; 571 } 572 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 573 574 /* 575 * Make sure that the latency timer, cache line size, 576 * and ROM is disabled. 577 */ 578 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 579 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 580 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 581 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 582 data |= (linesz << PCI_CACHELINE_SHIFT); 583 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 584 585 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 586 data &= ~1; 587 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 588 589 if (pci_intr_map(pa, &ih)) { 590 printf("%s: couldn't map interrupt\n", isp->isp_name); 591 free(isp->isp_param, M_DEVBUF); 592 return; 593 } 594 intrstr = pci_intr_string(pa->pa_pc, ih); 595 if (intrstr == NULL) 596 intrstr = "<I dunno>"; 597 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 598 isp_pci_intr, isp); 599 if (pcs->pci_ih == NULL) { 600 printf("%s: couldn't establish interrupt at %s\n", 601 isp->isp_name, intrstr); 602 free(isp->isp_param, M_DEVBUF); 603 return; 604 } 605 606 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 607 608 if (IS_FC(isp)) { 609 DEFAULT_NODEWWN(isp) = 0x400000007F000002; 610 DEFAULT_PORTWWN(isp) = 0x400000007F000002; 611 } 612 613 isp->isp_confopts = self->dv_cfdata->cf_flags; 614 isp->isp_role = ISP_DEFAULT_ROLES; 615 ISP_LOCK(isp); 616 isp->isp_osinfo.no_mbox_ints = 1; 617 isp_reset(isp); 618 if (isp->isp_state != ISP_RESETSTATE) { 619 ISP_UNLOCK(isp); 620 free(isp->isp_param, M_DEVBUF); 621 return; 622 } 623 ENABLE_INTS(isp); 624 isp_init(isp); 625 if (isp->isp_state != ISP_INITSTATE) { 626 isp_uninit(isp); 627 ISP_UNLOCK(isp); 628 free(isp->isp_param, M_DEVBUF); 629 return; 630 } 631 /* 632 * Do platform attach. 633 */ 634 ISP_UNLOCK(isp); 635 isp_attach(isp); 636 if (isp->isp_state != ISP_RUNSTATE) { 637 ISP_LOCK(isp); 638 isp_uninit(isp); 639 free(isp->isp_param, M_DEVBUF); 640 ISP_UNLOCK(isp); 641 } 642 } 643 644 #define IspVirt2Off(a, x) \ 645 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 646 _BLK_REG_SHFT] + ((x) & 0xff)) 647 648 #define BXR2(pcs, off) \ 649 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 650 #define BXW2(pcs, off, v) \ 651 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 652 653 654 static INLINE int 655 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 656 { 657 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 658 u_int16_t val0, val1; 659 int i = 0; 660 661 do { 662 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 663 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 664 } while (val0 != val1 && ++i < 1000); 665 if (val0 != val1) { 666 return (1); 667 } 668 *rp = val0; 669 return (0); 670 } 671 672 static int 673 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 674 u_int16_t *semap, u_int16_t *mbp) 675 { 676 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 677 u_int16_t isr, sema; 678 679 if (IS_2100(isp)) { 680 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 681 return (0); 682 } 683 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 684 return (0); 685 } 686 } else { 687 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 688 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 689 } 690 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 691 isr &= INT_PENDING_MASK(isp); 692 sema &= BIU_SEMA_LOCK; 693 if (isr == 0 && sema == 0) { 694 return (0); 695 } 696 *isrp = isr; 697 if ((*semap = sema) != 0) { 698 if (IS_2100(isp)) { 699 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 700 return (0); 701 } 702 } else { 703 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 704 } 705 } 706 return (1); 707 } 708 709 #ifndef ISP_DISABLE_2300_SUPPORT 710 static int 711 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 712 u_int16_t *semap, u_int16_t *mbox0p) 713 { 714 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 715 u_int32_t r2hisr; 716 717 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 718 *isrp = 0; 719 return (0); 720 } 721 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 722 IspVirt2Off(pcs, BIU_R2HSTSLO)); 723 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 724 if ((r2hisr & BIU_R2HST_INTR) == 0) { 725 *isrp = 0; 726 return (0); 727 } 728 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 729 case ISPR2HST_ROM_MBX_OK: 730 case ISPR2HST_ROM_MBX_FAIL: 731 case ISPR2HST_MBX_OK: 732 case ISPR2HST_MBX_FAIL: 733 case ISPR2HST_ASYNC_EVENT: 734 case ISPR2HST_RIO_16: 735 case ISPR2HST_FPOST: 736 case ISPR2HST_FPOST_CTIO: 737 *isrp = r2hisr & 0xffff; 738 *mbox0p = (r2hisr >> 16); 739 *semap = 1; 740 return (1); 741 case ISPR2HST_RSPQ_UPDATE: 742 *isrp = r2hisr & 0xffff; 743 *mbox0p = 0; 744 *semap = 0; 745 return (1); 746 default: 747 return (0); 748 } 749 } 750 #endif 751 752 static u_int16_t 753 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 754 { 755 u_int16_t rv; 756 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 757 int oldconf = 0; 758 759 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 760 /* 761 * We will assume that someone has paused the RISC processor. 762 */ 763 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 764 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 765 oldconf | BIU_PCI_CONF1_SXP); 766 } 767 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 768 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 769 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 770 } 771 return (rv); 772 } 773 774 static void 775 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 776 { 777 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 778 int oldconf = 0; 779 780 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 781 /* 782 * We will assume that someone has paused the RISC processor. 783 */ 784 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 785 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 786 oldconf | BIU_PCI_CONF1_SXP); 787 } 788 BXW2(pcs, IspVirt2Off(isp, regoff), val); 789 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 790 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 791 } 792 } 793 794 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 795 static u_int16_t 796 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 797 { 798 u_int16_t rv, oc = 0; 799 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 800 801 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 802 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 803 u_int16_t tc; 804 /* 805 * We will assume that someone has paused the RISC processor. 806 */ 807 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 808 tc = oc & ~BIU_PCI1080_CONF1_DMA; 809 if (regoff & SXP_BANK1_SELECT) 810 tc |= BIU_PCI1080_CONF1_SXP1; 811 else 812 tc |= BIU_PCI1080_CONF1_SXP0; 813 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 814 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 815 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 816 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 817 oc | BIU_PCI1080_CONF1_DMA); 818 } 819 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 820 if (oc) { 821 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 822 } 823 return (rv); 824 } 825 826 static void 827 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 828 { 829 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 830 int oc = 0; 831 832 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 833 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 834 u_int16_t tc; 835 /* 836 * We will assume that someone has paused the RISC processor. 837 */ 838 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 839 tc = oc & ~BIU_PCI1080_CONF1_DMA; 840 if (regoff & SXP_BANK1_SELECT) 841 tc |= BIU_PCI1080_CONF1_SXP1; 842 else 843 tc |= BIU_PCI1080_CONF1_SXP0; 844 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 845 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 846 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 847 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 848 oc | BIU_PCI1080_CONF1_DMA); 849 } 850 BXW2(pcs, IspVirt2Off(isp, regoff), val); 851 if (oc) { 852 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 853 } 854 } 855 #endif 856 857 static int 858 isp_pci_mbxdma(struct ispsoftc *isp) 859 { 860 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 861 bus_dma_tag_t dmat = isp->isp_dmatag; 862 bus_dma_segment_t sg; 863 bus_size_t len; 864 fcparam *fcp; 865 int rs, i; 866 867 if (isp->isp_rquest_dma) /* been here before? */ 868 return (0); 869 870 len = isp->isp_maxcmds * sizeof (XS_T *); 871 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 872 if (isp->isp_xflist == NULL) { 873 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 874 return (1); 875 } 876 memset(isp->isp_xflist, 0, len); 877 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 878 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 879 if (pcs->pci_xfer_dmap == NULL) { 880 free(isp->isp_xflist, M_DEVBUF); 881 isp->isp_xflist = NULL; 882 isp_prt(isp, ISP_LOGERR, "cannot malloc dma map array"); 883 return (1); 884 } 885 for (i = 0; i < isp->isp_maxcmds; i++) { 886 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 887 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 888 isp_prt(isp, ISP_LOGERR, "cannot create dma maps"); 889 break; 890 } 891 } 892 if (i < isp->isp_maxcmds) { 893 while (--i >= 0) { 894 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 895 } 896 free(isp->isp_xflist, M_DEVBUF); 897 free(pcs->pci_xfer_dmap, M_DEVBUF); 898 isp->isp_xflist = NULL; 899 pcs->pci_xfer_dmap = NULL; 900 return (1); 901 } 902 903 /* 904 * Allocate and map the request queue. 905 */ 906 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 907 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 908 BUS_DMA_NOWAIT) || 909 bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 910 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 911 goto dmafail; 912 } 913 914 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 915 &isp->isp_rqdmap) || bus_dmamap_load(dmat, isp->isp_rqdmap, 916 (caddr_t)isp->isp_rquest, len, NULL, 917 BUS_DMA_NOWAIT)) { 918 goto dmafail; 919 } 920 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 921 922 /* 923 * Allocate and map the result queue. 924 */ 925 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 926 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 927 BUS_DMA_NOWAIT) || 928 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 929 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 930 goto dmafail; 931 } 932 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 933 &isp->isp_rsdmap) || bus_dmamap_load(isp->isp_dmatag, 934 isp->isp_rsdmap, (caddr_t)isp->isp_result, len, NULL, 935 BUS_DMA_NOWAIT)) { 936 goto dmafail; 937 } 938 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 939 940 if (IS_SCSI(isp)) { 941 return (0); 942 } 943 944 fcp = isp->isp_param; 945 len = ISP2100_SCRLEN; 946 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 947 BUS_DMA_NOWAIT) || 948 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 949 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 950 goto dmafail; 951 } 952 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 953 &isp->isp_scdmap) || bus_dmamap_load(dmat, 954 isp->isp_scdmap, (caddr_t)fcp->isp_scratch, len, NULL, 955 BUS_DMA_NOWAIT)) { 956 goto dmafail; 957 } 958 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 959 return (0); 960 dmafail: 961 isp_prt(isp, ISP_LOGERR, "mailbox dma setup failure"); 962 for (i = 0; i < isp->isp_maxcmds; i++) { 963 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 964 } 965 free(isp->isp_xflist, M_DEVBUF); 966 free(pcs->pci_xfer_dmap, M_DEVBUF); 967 isp->isp_xflist = NULL; 968 pcs->pci_xfer_dmap = NULL; 969 return (1); 970 } 971 972 static int 973 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq, 974 u_int16_t *nxtip, u_int16_t optr) 975 { 976 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 977 bus_dmamap_t dmap; 978 u_int16_t starti = isp->isp_reqidx, nxti = *nxtip; 979 ispreq_t *qep; 980 int segcnt, seg, error, ovseg, seglim, drq; 981 982 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, starti); 983 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 984 if (xs->datalen == 0) { 985 rq->req_seg_count = 1; 986 goto mbxsync; 987 } 988 if (xs->xs_control & XS_CTL_DATA_IN) { 989 drq = REQFLAG_DATA_IN; 990 } else { 991 drq = REQFLAG_DATA_OUT; 992 } 993 994 if (IS_FC(isp)) { 995 seglim = ISP_RQDSEG_T2; 996 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 997 ((ispreqt2_t *)rq)->req_flags |= drq; 998 } else { 999 rq->req_flags |= drq; 1000 if (XS_CDBLEN(xs) > 12) { 1001 seglim = 0; 1002 } else { 1003 seglim = ISP_RQDSEG; 1004 } 1005 } 1006 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 1007 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 1008 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 1009 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1010 if (error) { 1011 XS_SETERR(xs, HBA_BOTCH); 1012 return (CMD_COMPLETE); 1013 } 1014 1015 segcnt = dmap->dm_nsegs; 1016 1017 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 1018 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 1019 "write from", xs->data, segcnt); 1020 1021 for (seg = 0, rq->req_seg_count = 0; 1022 seglim && seg < segcnt && rq->req_seg_count < seglim; 1023 seg++, rq->req_seg_count++) { 1024 if (IS_FC(isp)) { 1025 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1026 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1027 dmap->dm_segs[seg].ds_len; 1028 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1029 dmap->dm_segs[seg].ds_addr; 1030 } else { 1031 rq->req_dataseg[rq->req_seg_count].ds_count = 1032 dmap->dm_segs[seg].ds_len; 1033 rq->req_dataseg[rq->req_seg_count].ds_base = 1034 dmap->dm_segs[seg].ds_addr; 1035 } 1036 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 1037 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 1038 (unsigned long) dmap->dm_segs[seg].ds_len); 1039 } 1040 1041 if (seg == segcnt) { 1042 goto dmasync; 1043 } 1044 1045 do { 1046 u_int16_t onxti; 1047 ispcontreq_t *crq, *cqe, local; 1048 1049 crq = &local; 1050 1051 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1052 onxti = nxti; 1053 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1054 if (nxti == optr) { 1055 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1056 bus_dmamap_unload(isp->isp_dmatag, dmap); 1057 XS_SETERR(xs, HBA_BOTCH); 1058 return (CMD_EAGAIN); 1059 } 1060 rq->req_header.rqs_entry_count++; 1061 memset((void *)crq, 0, sizeof (*crq)); 1062 crq->req_header.rqs_entry_count = 1; 1063 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1064 1065 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 1066 rq->req_seg_count++, seg++, ovseg++) { 1067 crq->req_dataseg[ovseg].ds_count = 1068 dmap->dm_segs[seg].ds_len; 1069 crq->req_dataseg[ovseg].ds_base = 1070 dmap->dm_segs[seg].ds_addr; 1071 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 1072 rq->req_header.rqs_entry_count - 1, 1073 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 1074 (unsigned long) dmap->dm_segs[seg].ds_len); 1075 } 1076 isp_put_cont_req(isp, crq, cqe); 1077 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1078 } while (seg < segcnt); 1079 1080 1081 dmasync: 1082 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1083 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 1084 BUS_DMASYNC_PREWRITE); 1085 1086 mbxsync: 1087 switch (rq->req_header.rqs_entry_type) { 1088 case RQSTYPE_REQUEST: 1089 isp_put_request(isp, rq, qep); 1090 break; 1091 case RQSTYPE_CMDONLY: 1092 isp_put_extended_request(isp, (ispextreq_t *)rq, 1093 (ispextreq_t *)qep); 1094 break; 1095 case RQSTYPE_T2RQS: 1096 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1097 break; 1098 } 1099 *nxtip = nxti; 1100 return (CMD_QUEUED); 1101 } 1102 1103 static int 1104 isp_pci_intr(void *arg) 1105 { 1106 u_int16_t isr, sema, mbox; 1107 struct ispsoftc *isp = arg; 1108 1109 isp->isp_intcnt++; 1110 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1111 isp->isp_intbogus++; 1112 return (0); 1113 } else { 1114 isp->isp_osinfo.onintstack = 1; 1115 isp_intr(isp, isr, sema, mbox); 1116 isp->isp_osinfo.onintstack = 0; 1117 return (1); 1118 } 1119 } 1120 1121 static void 1122 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1123 { 1124 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1125 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 1126 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1127 xs->xs_control & XS_CTL_DATA_IN ? 1128 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1129 bus_dmamap_unload(isp->isp_dmatag, dmap); 1130 } 1131 1132 static void 1133 isp_pci_reset1(struct ispsoftc *isp) 1134 { 1135 /* Make sure the BIOS is disabled */ 1136 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1137 if (isp->isp_osinfo.no_mbox_ints == 0) { 1138 ENABLE_INTS(isp); 1139 } 1140 1141 } 1142 1143 static void 1144 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1145 { 1146 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1147 if (msg) 1148 printf("%s: %s\n", isp->isp_name, msg); 1149 if (IS_SCSI(isp)) 1150 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1151 else 1152 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1153 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1154 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1155 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1156 1157 1158 if (IS_SCSI(isp)) { 1159 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1160 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1161 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1162 ISP_READ(isp, CDMA_FIFO_STS)); 1163 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1164 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1165 ISP_READ(isp, DDMA_FIFO_STS)); 1166 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1167 ISP_READ(isp, SXP_INTERRUPT), 1168 ISP_READ(isp, SXP_GROSS_ERR), 1169 ISP_READ(isp, SXP_PINS_CTRL)); 1170 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1171 } 1172 printf(" mbox regs: %x %x %x %x %x\n", 1173 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1174 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1175 ISP_READ(isp, OUTMAILBOX4)); 1176 printf(" PCI Status Command/Status=%x\n", 1177 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1178 } 1179
Indexes created Thu Sep 25 16:09:42 GMT 2025