isp_pci.c revision 1.89
1 /* $NetBSD: isp_pci.c,v 1.89 2003/08/07 01:05:56 mjacob Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 */ 33 /* 34 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 35 * All rights reserved. 36 * 37 * Additional Copyright (C) 2000, 2001 by Matthew Jacob 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.89 2003/08/07 01:05:56 mjacob Exp $"); 61 62 #include <dev/ic/isp_netbsd.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 #include <uvm/uvm_extern.h> 67 #include <sys/reboot.h> 68 69 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 70 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 71 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 72 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 73 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 74 #endif 75 static int 76 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 77 static int 78 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 79 static int isp_pci_mbxdma(struct ispsoftc *); 80 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, 81 u_int16_t *, u_int16_t); 82 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 83 static void isp_pci_reset1(struct ispsoftc *); 84 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 85 static int isp_pci_intr(void *); 86 87 #if defined(ISP_DISABLE_1020_SUPPORT) 88 #define ISP_1040_RISC_CODE NULL 89 #else 90 #define ISP_1040_RISC_CODE (u_int16_t *) isp_1040_risc_code 91 #include <dev/microcode/isp/asm_1040.h> 92 #endif 93 94 #if defined(ISP_DISABLE_1080_SUPPORT) 95 #define ISP_1080_RISC_CODE NULL 96 #else 97 #define ISP_1080_RISC_CODE (u_int16_t *) isp_1080_risc_code 98 #include <dev/microcode/isp/asm_1080.h> 99 #endif 100 101 #if defined(ISP_DISABLE_12160_SUPPORT) 102 #define ISP_12160_RISC_CODE NULL 103 #else 104 #define ISP_12160_RISC_CODE (u_int16_t *) isp_12160_risc_code 105 #include <dev/microcode/isp/asm_12160.h> 106 #endif 107 108 #if defined(ISP_DISABLE_2100_SUPPORT) 109 #define ISP_2100_RISC_CODE NULL 110 #else 111 #define ISP_2100_RISC_CODE (u_int16_t *) isp_2100_risc_code 112 #include <dev/microcode/isp/asm_2100.h> 113 #endif 114 115 #if defined(ISP_DISABLE_2200_SUPPORT) 116 #define ISP_2200_RISC_CODE NULL 117 #else 118 #define ISP_2200_RISC_CODE (u_int16_t *) isp_2200_risc_code 119 #include <dev/microcode/isp/asm_2200.h> 120 #endif 121 122 #if defined(ISP_DISABLE_2300_SUPPORT) 123 #define ISP_2300_RISC_CODE NULL 124 #else 125 #define ISP_2300_RISC_CODE (u_int16_t *) isp_2300_risc_code 126 #include <dev/microcode/isp/asm_2300.h> 127 #endif 128 129 #ifndef ISP_DISABLE_1020_SUPPORT 130 static struct ispmdvec mdvec = { 131 isp_pci_rd_isr, 132 isp_pci_rd_reg, 133 isp_pci_wr_reg, 134 isp_pci_mbxdma, 135 isp_pci_dmasetup, 136 isp_pci_dmateardown, 137 NULL, 138 isp_pci_reset1, 139 isp_pci_dumpregs, 140 ISP_1040_RISC_CODE, 141 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 142 }; 143 #endif 144 145 #ifndef ISP_DISABLE_1080_SUPPORT 146 static struct ispmdvec mdvec_1080 = { 147 isp_pci_rd_isr, 148 isp_pci_rd_reg_1080, 149 isp_pci_wr_reg_1080, 150 isp_pci_mbxdma, 151 isp_pci_dmasetup, 152 isp_pci_dmateardown, 153 NULL, 154 isp_pci_reset1, 155 isp_pci_dumpregs, 156 ISP_1080_RISC_CODE, 157 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 158 }; 159 #endif 160 161 #ifndef ISP_DISABLE_12160_SUPPORT 162 static struct ispmdvec mdvec_12160 = { 163 isp_pci_rd_isr, 164 isp_pci_rd_reg_1080, 165 isp_pci_wr_reg_1080, 166 isp_pci_mbxdma, 167 isp_pci_dmasetup, 168 isp_pci_dmateardown, 169 NULL, 170 isp_pci_reset1, 171 isp_pci_dumpregs, 172 ISP_12160_RISC_CODE, 173 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 174 }; 175 #endif 176 177 #ifndef ISP_DISABLE_2100_SUPPORT 178 static struct ispmdvec mdvec_2100 = { 179 isp_pci_rd_isr, 180 isp_pci_rd_reg, 181 isp_pci_wr_reg, 182 isp_pci_mbxdma, 183 isp_pci_dmasetup, 184 isp_pci_dmateardown, 185 NULL, 186 isp_pci_reset1, 187 isp_pci_dumpregs, 188 ISP_2100_RISC_CODE 189 }; 190 #endif 191 192 #ifndef ISP_DISABLE_2200_SUPPORT 193 static struct ispmdvec mdvec_2200 = { 194 isp_pci_rd_isr, 195 isp_pci_rd_reg, 196 isp_pci_wr_reg, 197 isp_pci_mbxdma, 198 isp_pci_dmasetup, 199 isp_pci_dmateardown, 200 NULL, 201 isp_pci_reset1, 202 isp_pci_dumpregs, 203 ISP_2200_RISC_CODE 204 }; 205 #endif 206 207 #ifndef ISP_DISABLE_2300_SUPPORT 208 static struct ispmdvec mdvec_2300 = { 209 isp_pci_rd_isr_2300, 210 isp_pci_rd_reg, 211 isp_pci_wr_reg, 212 isp_pci_mbxdma, 213 isp_pci_dmasetup, 214 isp_pci_dmateardown, 215 NULL, 216 isp_pci_reset1, 217 isp_pci_dumpregs, 218 ISP_2300_RISC_CODE 219 }; 220 #endif 221 222 #ifndef PCI_VENDOR_QLOGIC 223 #define PCI_VENDOR_QLOGIC 0x1077 224 #endif 225 226 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 227 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 228 #endif 229 230 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 231 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 232 #endif 233 234 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 235 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 236 #endif 237 238 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 239 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 240 #endif 241 242 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 243 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 244 #endif 245 246 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 247 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 248 #endif 249 250 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 251 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 252 #endif 253 254 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 255 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 256 #endif 257 258 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 259 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 260 #endif 261 262 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 263 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 264 #endif 265 266 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 267 268 #define PCI_QLOGIC_ISP1080 \ 269 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 270 271 #define PCI_QLOGIC_ISP1240 \ 272 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 273 274 #define PCI_QLOGIC_ISP1280 \ 275 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 276 277 #define PCI_QLOGIC_ISP10160 \ 278 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 279 280 #define PCI_QLOGIC_ISP12160 \ 281 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 282 283 #define PCI_QLOGIC_ISP2100 \ 284 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 285 286 #define PCI_QLOGIC_ISP2200 \ 287 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 288 289 #define PCI_QLOGIC_ISP2300 \ 290 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 291 292 #define PCI_QLOGIC_ISP2312 \ 293 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 294 295 #define IO_MAP_REG 0x10 296 #define MEM_MAP_REG 0x14 297 #define PCIR_ROMADDR 0x30 298 299 #define PCI_DFLT_LTNCY 0x40 300 #define PCI_DFLT_LNSZ 0x10 301 302 303 static int isp_pci_probe(struct device *, struct cfdata *, void *); 304 static void isp_pci_attach(struct device *, struct device *, void *); 305 306 struct isp_pcisoftc { 307 struct ispsoftc pci_isp; 308 pci_chipset_tag_t pci_pc; 309 pcitag_t pci_tag; 310 bus_space_tag_t pci_st; 311 bus_space_handle_t pci_sh; 312 bus_dmamap_t *pci_xfer_dmap; 313 void * pci_ih; 314 int16_t pci_poff[_NREG_BLKS]; 315 }; 316 317 CFATTACH_DECL(isp_pci, sizeof (struct isp_pcisoftc), 318 isp_pci_probe, isp_pci_attach, NULL, NULL); 319 320 #ifdef DEBUG 321 const char vstring[] = 322 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 323 #endif 324 325 static int 326 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux) 327 { 328 struct pci_attach_args *pa = aux; 329 switch (pa->pa_id) { 330 #ifndef ISP_DISABLE_1020_SUPPORT 331 case PCI_QLOGIC_ISP: 332 return (1); 333 #endif 334 #ifndef ISP_DISABLE_1080_SUPPORT 335 case PCI_QLOGIC_ISP1080: 336 case PCI_QLOGIC_ISP1240: 337 case PCI_QLOGIC_ISP1280: 338 return (1); 339 #endif 340 #ifndef ISP_DISABLE_12160_SUPPORT 341 case PCI_QLOGIC_ISP10160: 342 case PCI_QLOGIC_ISP12160: 343 return (1); 344 #endif 345 #ifndef ISP_DISABLE_2100_SUPPORT 346 case PCI_QLOGIC_ISP2100: 347 return (1); 348 #endif 349 #ifndef ISP_DISABLE_2200_SUPPORT 350 case PCI_QLOGIC_ISP2200: 351 return (1); 352 #endif 353 #ifndef ISP_DISABLE_2300_SUPPORT 354 case PCI_QLOGIC_ISP2300: 355 case PCI_QLOGIC_ISP2312: 356 return (1); 357 #endif 358 default: 359 return (0); 360 } 361 } 362 363 364 static void 365 isp_pci_attach(struct device *parent, struct device *self, void *aux) 366 { 367 #ifdef DEBUG 368 static char oneshot = 1; 369 #endif 370 static const char nomem[] = "\n%s: no mem for sdparam table\n"; 371 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 372 struct pci_attach_args *pa = aux; 373 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 374 struct ispsoftc *isp = &pcs->pci_isp; 375 bus_space_tag_t st, iot, memt; 376 bus_space_handle_t sh, ioh, memh; 377 pci_intr_handle_t ih; 378 pcireg_t mem_type; 379 char *dstring; 380 const char *intrstr; 381 int ioh_valid, memh_valid; 382 383 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 384 PCI_MAPREG_TYPE_IO, 0, 385 &iot, &ioh, NULL, NULL) == 0); 386 387 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG); 388 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) { 389 memh_valid = 0; 390 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT && 391 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) { 392 memh_valid = 0; 393 } else { 394 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0, 395 &memt, &memh, NULL, NULL) == 0); 396 } 397 if (memh_valid) { 398 st = memt; 399 sh = memh; 400 } else if (ioh_valid) { 401 st = iot; 402 sh = ioh; 403 } else { 404 printf(": unable to map device registers\n"); 405 return; 406 } 407 dstring = "\n"; 408 409 pcs->pci_st = st; 410 pcs->pci_sh = sh; 411 pcs->pci_pc = pa->pa_pc; 412 pcs->pci_tag = pa->pa_tag; 413 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 414 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 415 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 416 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 417 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 418 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 419 420 #ifndef ISP_DISABLE_1020_SUPPORT 421 if (pa->pa_id == PCI_QLOGIC_ISP) { 422 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n"; 423 isp->isp_mdvec = &mdvec; 424 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 425 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 426 if (isp->isp_param == NULL) { 427 printf(nomem, isp->isp_name); 428 return; 429 } 430 memset(isp->isp_param, 0, sizeof (sdparam)); 431 } 432 #endif 433 #ifndef ISP_DISABLE_1080_SUPPORT 434 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 435 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n"; 436 isp->isp_mdvec = &mdvec_1080; 437 isp->isp_type = ISP_HA_SCSI_1080; 438 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 439 if (isp->isp_param == NULL) { 440 printf(nomem, isp->isp_name); 441 return; 442 } 443 memset(isp->isp_param, 0, sizeof (sdparam)); 444 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 445 ISP1080_DMA_REGS_OFF; 446 } 447 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 448 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n"; 449 isp->isp_mdvec = &mdvec_1080; 450 isp->isp_type = ISP_HA_SCSI_1240; 451 isp->isp_param = 452 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 453 if (isp->isp_param == NULL) { 454 printf(nomem, isp->isp_name); 455 return; 456 } 457 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 458 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 459 ISP1080_DMA_REGS_OFF; 460 } 461 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 462 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n"; 463 isp->isp_mdvec = &mdvec_1080; 464 isp->isp_type = ISP_HA_SCSI_1280; 465 isp->isp_param = 466 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 467 if (isp->isp_param == NULL) { 468 printf(nomem, isp->isp_name); 469 return; 470 } 471 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 472 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 473 ISP1080_DMA_REGS_OFF; 474 } 475 #endif 476 #ifndef ISP_DISABLE_12160_SUPPORT 477 if (pa->pa_id == PCI_QLOGIC_ISP10160) { 478 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n"; 479 isp->isp_mdvec = &mdvec_12160; 480 isp->isp_type = ISP_HA_SCSI_10160; 481 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 482 if (isp->isp_param == NULL) { 483 printf(nomem, isp->isp_name); 484 return; 485 } 486 memset(isp->isp_param, 0, sizeof (sdparam)); 487 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 488 ISP1080_DMA_REGS_OFF; 489 } 490 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 491 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n"; 492 isp->isp_mdvec = &mdvec_12160; 493 isp->isp_type = ISP_HA_SCSI_12160; 494 isp->isp_param = 495 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 496 if (isp->isp_param == NULL) { 497 printf(nomem, isp->isp_name); 498 return; 499 } 500 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 501 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 502 ISP1080_DMA_REGS_OFF; 503 } 504 #endif 505 #ifndef ISP_DISABLE_2100_SUPPORT 506 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 507 dstring = ": QLogic FC-AL HBA\n"; 508 isp->isp_mdvec = &mdvec_2100; 509 isp->isp_type = ISP_HA_FC_2100; 510 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 511 if (isp->isp_param == NULL) { 512 printf(nomem, isp->isp_name); 513 return; 514 } 515 memset(isp->isp_param, 0, sizeof (fcparam)); 516 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 517 PCI_MBOX_REGS2100_OFF; 518 if (rev < 3) { 519 /* 520 * XXX: Need to get the actual revision 521 * XXX: number of the 2100 FB. At any rate, 522 * XXX: lower cache line size for early revision 523 * XXX; boards. 524 */ 525 linesz = 1; 526 } 527 } 528 #endif 529 #ifndef ISP_DISABLE_2200_SUPPORT 530 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 531 dstring = ": QLogic FC-AL and Fabric HBA\n"; 532 isp->isp_mdvec = &mdvec_2200; 533 isp->isp_type = ISP_HA_FC_2200; 534 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 535 if (isp->isp_param == NULL) { 536 printf(nomem, isp->isp_name); 537 return; 538 } 539 memset(isp->isp_param, 0, sizeof (fcparam)); 540 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 541 PCI_MBOX_REGS2100_OFF; 542 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 543 } 544 #endif 545 #ifndef ISP_DISABLE_2300_SUPPORT 546 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 547 pa->pa_id == PCI_QLOGIC_ISP2312) { 548 isp->isp_mdvec = &mdvec_2300; 549 if (pa->pa_id == PCI_QLOGIC_ISP2300) { 550 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n"; 551 isp->isp_type = ISP_HA_FC_2300; 552 } else { 553 dstring = 554 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n"; 555 isp->isp_type = ISP_HA_FC_2312; 556 isp->isp_port = pa->pa_function; 557 } 558 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 559 if (isp->isp_param == NULL) { 560 printf(nomem, isp->isp_name); 561 return; 562 } 563 memset(isp->isp_param, 0, sizeof (fcparam)); 564 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 565 PCI_MBOX_REGS2300_OFF; 566 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 567 } 568 #endif 569 /* 570 * Set up logging levels. 571 */ 572 #ifdef ISP_LOGDEFAULT 573 isp->isp_dblev = ISP_LOGDEFAULT; 574 #else 575 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 576 if (bootverbose) 577 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 578 #ifdef SCSIDEBUG 579 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2; 580 #endif 581 #endif 582 if (isp->isp_dblev & ISP_LOGCONFIG) { 583 printf("\n"); 584 } else { 585 printf(dstring); 586 } 587 588 #ifdef DEBUG 589 if (oneshot) { 590 oneshot = 0; 591 isp_prt(isp, ISP_LOGCONFIG, vstring, 592 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 593 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 594 } 595 #endif 596 597 isp->isp_dmatag = pa->pa_dmat; 598 isp->isp_revision = rev; 599 600 /* 601 * Make sure that command register set sanely. 602 */ 603 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 604 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 605 606 /* 607 * Not so sure about these- but I think it's important that they get 608 * enabled...... 609 */ 610 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 611 if (IS_2300(isp)) { /* per QLogic errata */ 612 data &= ~PCI_COMMAND_INVALIDATE_ENABLE; 613 } 614 if (IS_23XX(isp)) { 615 isp->isp_touched = 1; 616 } 617 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 618 619 /* 620 * Make sure that the latency timer, cache line size, 621 * and ROM is disabled. 622 */ 623 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 624 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 625 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 626 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 627 data |= (linesz << PCI_CACHELINE_SHIFT); 628 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 629 630 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 631 data &= ~1; 632 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 633 634 if (pci_intr_map(pa, &ih)) { 635 printf("%s: couldn't map interrupt\n", isp->isp_name); 636 free(isp->isp_param, M_DEVBUF); 637 return; 638 } 639 intrstr = pci_intr_string(pa->pa_pc, ih); 640 if (intrstr == NULL) 641 intrstr = "<I dunno>"; 642 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 643 isp_pci_intr, isp); 644 if (pcs->pci_ih == NULL) { 645 printf("%s: couldn't establish interrupt at %s\n", 646 isp->isp_name, intrstr); 647 free(isp->isp_param, M_DEVBUF); 648 return; 649 } 650 651 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 652 653 if (IS_FC(isp)) { 654 DEFAULT_NODEWWN(isp) = 0x400000007F000002ULL; 655 DEFAULT_PORTWWN(isp) = 0x400000007F000002ULL; 656 } 657 658 isp->isp_confopts = self->dv_cfdata->cf_flags; 659 isp->isp_role = ISP_DEFAULT_ROLES; 660 ISP_LOCK(isp); 661 isp->isp_osinfo.no_mbox_ints = 1; 662 isp_reset(isp); 663 if (isp->isp_state != ISP_RESETSTATE) { 664 ISP_UNLOCK(isp); 665 free(isp->isp_param, M_DEVBUF); 666 return; 667 } 668 ENABLE_INTS(isp); 669 isp_init(isp); 670 if (isp->isp_state != ISP_INITSTATE) { 671 isp_uninit(isp); 672 ISP_UNLOCK(isp); 673 free(isp->isp_param, M_DEVBUF); 674 return; 675 } 676 /* 677 * Do platform attach. 678 */ 679 ISP_UNLOCK(isp); 680 isp_attach(isp); 681 if (isp->isp_state != ISP_RUNSTATE) { 682 ISP_LOCK(isp); 683 isp_uninit(isp); 684 free(isp->isp_param, M_DEVBUF); 685 ISP_UNLOCK(isp); 686 } 687 } 688 689 #define IspVirt2Off(a, x) \ 690 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 691 _BLK_REG_SHFT] + ((x) & 0xff)) 692 693 #define BXR2(pcs, off) \ 694 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 695 #define BXW2(pcs, off, v) \ 696 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 697 698 699 static INLINE int 700 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 701 { 702 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 703 u_int16_t val0, val1; 704 int i = 0; 705 706 do { 707 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 708 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 709 } while (val0 != val1 && ++i < 1000); 710 if (val0 != val1) { 711 return (1); 712 } 713 *rp = val0; 714 return (0); 715 } 716 717 static int 718 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 719 u_int16_t *semap, u_int16_t *mbp) 720 { 721 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 722 u_int16_t isr, sema; 723 724 if (IS_2100(isp)) { 725 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 726 return (0); 727 } 728 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 729 return (0); 730 } 731 } else { 732 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 733 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 734 } 735 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 736 isr &= INT_PENDING_MASK(isp); 737 sema &= BIU_SEMA_LOCK; 738 if (isr == 0 && sema == 0) { 739 return (0); 740 } 741 *isrp = isr; 742 if ((*semap = sema) != 0) { 743 if (IS_2100(isp)) { 744 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 745 return (0); 746 } 747 } else { 748 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 749 } 750 } 751 return (1); 752 } 753 754 #ifndef ISP_DISABLE_2300_SUPPORT 755 static int 756 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 757 u_int16_t *semap, u_int16_t *mbox0p) 758 { 759 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 760 u_int32_t r2hisr; 761 762 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 763 *isrp = 0; 764 return (0); 765 } 766 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 767 IspVirt2Off(pcs, BIU_R2HSTSLO)); 768 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 769 if ((r2hisr & BIU_R2HST_INTR) == 0) { 770 *isrp = 0; 771 return (0); 772 } 773 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 774 case ISPR2HST_ROM_MBX_OK: 775 case ISPR2HST_ROM_MBX_FAIL: 776 case ISPR2HST_MBX_OK: 777 case ISPR2HST_MBX_FAIL: 778 case ISPR2HST_ASYNC_EVENT: 779 *isrp = r2hisr & 0xffff; 780 *mbox0p = (r2hisr >> 16); 781 *semap = 1; 782 return (1); 783 case ISPR2HST_RIO_16: 784 *isrp = r2hisr & 0xffff; 785 *mbox0p = ASYNC_RIO1; 786 *semap = 1; 787 return (1); 788 case ISPR2HST_FPOST: 789 *isrp = r2hisr & 0xffff; 790 *mbox0p = ASYNC_CMD_CMPLT; 791 *semap = 1; 792 return (1); 793 case ISPR2HST_FPOST_CTIO: 794 *isrp = r2hisr & 0xffff; 795 *mbox0p = ASYNC_CTIO_DONE; 796 *semap = 1; 797 return (1); 798 case ISPR2HST_RSPQ_UPDATE: 799 *isrp = r2hisr & 0xffff; 800 *mbox0p = 0; 801 *semap = 0; 802 return (1); 803 default: 804 return (0); 805 } 806 } 807 #endif 808 809 static u_int16_t 810 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 811 { 812 u_int16_t rv; 813 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 814 int oldconf = 0; 815 816 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 817 /* 818 * We will assume that someone has paused the RISC processor. 819 */ 820 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 821 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 822 oldconf | BIU_PCI_CONF1_SXP); 823 } 824 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 825 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 826 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 827 } 828 return (rv); 829 } 830 831 static void 832 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 833 { 834 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 835 int oldconf = 0; 836 837 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 838 /* 839 * We will assume that someone has paused the RISC processor. 840 */ 841 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 842 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 843 oldconf | BIU_PCI_CONF1_SXP); 844 } 845 BXW2(pcs, IspVirt2Off(isp, regoff), val); 846 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 847 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 848 } 849 } 850 851 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 852 static u_int16_t 853 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 854 { 855 u_int16_t rv, oc = 0; 856 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 857 858 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 859 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 860 u_int16_t tc; 861 /* 862 * We will assume that someone has paused the RISC processor. 863 */ 864 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 865 tc = oc & ~BIU_PCI1080_CONF1_DMA; 866 if (regoff & SXP_BANK1_SELECT) 867 tc |= BIU_PCI1080_CONF1_SXP1; 868 else 869 tc |= BIU_PCI1080_CONF1_SXP0; 870 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 871 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 872 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 873 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 874 oc | BIU_PCI1080_CONF1_DMA); 875 } 876 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 877 if (oc) { 878 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 879 } 880 return (rv); 881 } 882 883 static void 884 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 885 { 886 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 887 int oc = 0; 888 889 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 890 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 891 u_int16_t tc; 892 /* 893 * We will assume that someone has paused the RISC processor. 894 */ 895 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 896 tc = oc & ~BIU_PCI1080_CONF1_DMA; 897 if (regoff & SXP_BANK1_SELECT) 898 tc |= BIU_PCI1080_CONF1_SXP1; 899 else 900 tc |= BIU_PCI1080_CONF1_SXP0; 901 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 902 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 903 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 904 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 905 oc | BIU_PCI1080_CONF1_DMA); 906 } 907 BXW2(pcs, IspVirt2Off(isp, regoff), val); 908 if (oc) { 909 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 910 } 911 } 912 #endif 913 914 static int 915 isp_pci_mbxdma(struct ispsoftc *isp) 916 { 917 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 918 bus_dma_tag_t dmat = isp->isp_dmatag; 919 bus_dma_segment_t sg; 920 bus_size_t len; 921 fcparam *fcp; 922 int rs, i; 923 924 if (isp->isp_rquest_dma) /* been here before? */ 925 return (0); 926 927 len = isp->isp_maxcmds * sizeof (XS_T *); 928 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 929 if (isp->isp_xflist == NULL) { 930 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 931 return (1); 932 } 933 memset(isp->isp_xflist, 0, len); 934 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 935 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 936 if (pcs->pci_xfer_dmap == NULL) { 937 free(isp->isp_xflist, M_DEVBUF); 938 isp->isp_xflist = NULL; 939 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array"); 940 return (1); 941 } 942 for (i = 0; i < isp->isp_maxcmds; i++) { 943 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 944 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 945 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps"); 946 break; 947 } 948 } 949 if (i < isp->isp_maxcmds) { 950 while (--i >= 0) { 951 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 952 } 953 free(isp->isp_xflist, M_DEVBUF); 954 free(pcs->pci_xfer_dmap, M_DEVBUF); 955 isp->isp_xflist = NULL; 956 pcs->pci_xfer_dmap = NULL; 957 return (1); 958 } 959 960 /* 961 * Allocate and map the request queue. 962 */ 963 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 964 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 965 BUS_DMA_NOWAIT) || 966 bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 967 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 968 goto dmafail; 969 } 970 971 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 972 &isp->isp_rqdmap) || bus_dmamap_load(dmat, isp->isp_rqdmap, 973 (caddr_t)isp->isp_rquest, len, NULL, 974 BUS_DMA_NOWAIT)) { 975 goto dmafail; 976 } 977 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 978 979 /* 980 * Allocate and map the result queue. 981 */ 982 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 983 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 984 BUS_DMA_NOWAIT) || 985 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 986 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 987 goto dmafail; 988 } 989 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 990 &isp->isp_rsdmap) || bus_dmamap_load(isp->isp_dmatag, 991 isp->isp_rsdmap, (caddr_t)isp->isp_result, len, NULL, 992 BUS_DMA_NOWAIT)) { 993 goto dmafail; 994 } 995 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 996 997 if (IS_SCSI(isp)) { 998 return (0); 999 } 1000 1001 fcp = isp->isp_param; 1002 len = ISP2100_SCRLEN; 1003 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 1004 BUS_DMA_NOWAIT) || 1005 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 1006 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1007 goto dmafail; 1008 } 1009 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 1010 &isp->isp_scdmap) || bus_dmamap_load(dmat, 1011 isp->isp_scdmap, (caddr_t)fcp->isp_scratch, len, NULL, 1012 BUS_DMA_NOWAIT)) { 1013 goto dmafail; 1014 } 1015 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 1016 return (0); 1017 dmafail: 1018 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure"); 1019 for (i = 0; i < isp->isp_maxcmds; i++) { 1020 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1021 } 1022 free(isp->isp_xflist, M_DEVBUF); 1023 free(pcs->pci_xfer_dmap, M_DEVBUF); 1024 isp->isp_xflist = NULL; 1025 pcs->pci_xfer_dmap = NULL; 1026 return (1); 1027 } 1028 1029 static int 1030 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq, 1031 u_int16_t *nxtip, u_int16_t optr) 1032 { 1033 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1034 bus_dmamap_t dmap; 1035 u_int16_t starti = isp->isp_reqidx, nxti = *nxtip; 1036 ispreq_t *qep; 1037 int segcnt, seg, error, ovseg, seglim, drq; 1038 1039 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, starti); 1040 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 1041 if (xs->datalen == 0) { 1042 rq->req_seg_count = 1; 1043 goto mbxsync; 1044 } 1045 if (xs->xs_control & XS_CTL_DATA_IN) { 1046 drq = REQFLAG_DATA_IN; 1047 } else { 1048 drq = REQFLAG_DATA_OUT; 1049 } 1050 1051 if (IS_FC(isp)) { 1052 seglim = ISP_RQDSEG_T2; 1053 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 1054 ((ispreqt2_t *)rq)->req_flags |= drq; 1055 } else { 1056 rq->req_flags |= drq; 1057 if (XS_CDBLEN(xs) > 12) { 1058 seglim = 0; 1059 } else { 1060 seglim = ISP_RQDSEG; 1061 } 1062 } 1063 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 1064 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 1065 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 1066 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1067 if (error) { 1068 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", error); 1069 XS_SETERR(xs, HBA_BOTCH); 1070 if (error == EAGAIN || error == ENOMEM) 1071 return (CMD_EAGAIN); 1072 else 1073 return (CMD_COMPLETE); 1074 } 1075 1076 segcnt = dmap->dm_nsegs; 1077 1078 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 1079 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 1080 "write from", xs->data, segcnt); 1081 1082 for (seg = 0, rq->req_seg_count = 0; 1083 seglim && seg < segcnt && rq->req_seg_count < seglim; 1084 seg++, rq->req_seg_count++) { 1085 if (IS_FC(isp)) { 1086 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1087 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1088 dmap->dm_segs[seg].ds_len; 1089 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1090 dmap->dm_segs[seg].ds_addr; 1091 } else { 1092 rq->req_dataseg[rq->req_seg_count].ds_count = 1093 dmap->dm_segs[seg].ds_len; 1094 rq->req_dataseg[rq->req_seg_count].ds_base = 1095 dmap->dm_segs[seg].ds_addr; 1096 } 1097 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 1098 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 1099 (unsigned long) dmap->dm_segs[seg].ds_len); 1100 } 1101 1102 if (seg == segcnt) { 1103 goto dmasync; 1104 } 1105 1106 do { 1107 u_int16_t onxti; 1108 ispcontreq_t *crq, *cqe, local; 1109 1110 crq = &local; 1111 1112 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1113 onxti = nxti; 1114 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1115 if (nxti == optr) { 1116 isp_prt(isp, /* ISP_LOGDEBUG0 */ ISP_LOGERR, "Request Queue Overflow++"); 1117 bus_dmamap_unload(isp->isp_dmatag, dmap); 1118 XS_SETERR(xs, HBA_BOTCH); 1119 return (CMD_EAGAIN); 1120 } 1121 rq->req_header.rqs_entry_count++; 1122 memset((void *)crq, 0, sizeof (*crq)); 1123 crq->req_header.rqs_entry_count = 1; 1124 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1125 1126 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 1127 rq->req_seg_count++, seg++, ovseg++) { 1128 crq->req_dataseg[ovseg].ds_count = 1129 dmap->dm_segs[seg].ds_len; 1130 crq->req_dataseg[ovseg].ds_base = 1131 dmap->dm_segs[seg].ds_addr; 1132 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 1133 rq->req_header.rqs_entry_count - 1, 1134 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 1135 (unsigned long) dmap->dm_segs[seg].ds_len); 1136 } 1137 isp_put_cont_req(isp, crq, cqe); 1138 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1139 } while (seg < segcnt); 1140 1141 1142 dmasync: 1143 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1144 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 1145 BUS_DMASYNC_PREWRITE); 1146 1147 mbxsync: 1148 switch (rq->req_header.rqs_entry_type) { 1149 case RQSTYPE_REQUEST: 1150 isp_put_request(isp, rq, qep); 1151 break; 1152 case RQSTYPE_CMDONLY: 1153 isp_put_extended_request(isp, (ispextreq_t *)rq, 1154 (ispextreq_t *)qep); 1155 break; 1156 case RQSTYPE_T2RQS: 1157 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1158 break; 1159 } 1160 *nxtip = nxti; 1161 return (CMD_QUEUED); 1162 } 1163 1164 static int 1165 isp_pci_intr(void *arg) 1166 { 1167 u_int16_t isr, sema, mbox; 1168 struct ispsoftc *isp = arg; 1169 1170 isp->isp_intcnt++; 1171 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1172 isp->isp_intbogus++; 1173 return (0); 1174 } else { 1175 isp->isp_osinfo.onintstack = 1; 1176 isp_intr(isp, isr, sema, mbox); 1177 isp->isp_osinfo.onintstack = 0; 1178 return (1); 1179 } 1180 } 1181 1182 static void 1183 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1184 { 1185 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1186 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 1187 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1188 xs->xs_control & XS_CTL_DATA_IN ? 1189 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1190 bus_dmamap_unload(isp->isp_dmatag, dmap); 1191 } 1192 1193 static void 1194 isp_pci_reset1(struct ispsoftc *isp) 1195 { 1196 /* Make sure the BIOS is disabled */ 1197 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1198 if (isp->isp_osinfo.no_mbox_ints == 0) { 1199 ENABLE_INTS(isp); 1200 } 1201 1202 } 1203 1204 static void 1205 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1206 { 1207 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1208 if (msg) 1209 printf("%s: %s\n", isp->isp_name, msg); 1210 if (IS_SCSI(isp)) 1211 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1212 else 1213 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1214 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1215 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1216 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1217 1218 1219 if (IS_SCSI(isp)) { 1220 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1221 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1222 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1223 ISP_READ(isp, CDMA_FIFO_STS)); 1224 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1225 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1226 ISP_READ(isp, DDMA_FIFO_STS)); 1227 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1228 ISP_READ(isp, SXP_INTERRUPT), 1229 ISP_READ(isp, SXP_GROSS_ERR), 1230 ISP_READ(isp, SXP_PINS_CTRL)); 1231 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1232 } 1233 printf(" mbox regs: %x %x %x %x %x\n", 1234 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1235 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1236 ISP_READ(isp, OUTMAILBOX4)); 1237 printf(" PCI Status Command/Status=%x\n", 1238 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1239 } 1240
Indexes created Sat Sep 27 14:09:57 GMT 2025