isp_pci.c revision 1.96
1 /* $NetBSD: isp_pci.c,v 1.96 2006/09/02 17:02:58 christos Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) NetBSD.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 */ 33 /* 34 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 35 * All rights reserved. 36 * 37 * Additional Copyright (C) 2000, 2001 by Matthew Jacob 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.96 2006/09/02 17:02:58 christos Exp $"); 61 62 #include <dev/ic/isp_netbsd.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 #include <uvm/uvm_extern.h> 67 #include <sys/reboot.h> 68 69 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 70 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 71 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 72 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 73 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 74 #endif 75 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 76 !defined(ISP_DISABLE_2200_SUPPORT) && \ 77 !defined(ISP_DISABLE_1020_SUPPORT) && \ 78 !defined(ISP_DISABLE_1080_SUPPORT) && \ 79 !defined(ISP_DISABLE_12160_SUPPORT) 80 static int 81 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 82 #endif 83 #if !defined(ISP_DISABLE_2300_SUPPORT) 84 static int 85 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 86 #endif 87 static int isp_pci_mbxdma(struct ispsoftc *); 88 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, 89 u_int16_t *, u_int16_t); 90 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 91 static void isp_pci_reset1(struct ispsoftc *); 92 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 93 static int isp_pci_intr(void *); 94 95 #if defined(ISP_DISABLE_1020_SUPPORT) 96 #define ISP_1040_RISC_CODE NULL 97 #else 98 #define ISP_1040_RISC_CODE (const u_int16_t *) isp_1040_risc_code 99 #include <dev/microcode/isp/asm_1040.h> 100 #endif 101 102 #if defined(ISP_DISABLE_1080_SUPPORT) 103 #define ISP_1080_RISC_CODE NULL 104 #else 105 #define ISP_1080_RISC_CODE (const u_int16_t *) isp_1080_risc_code 106 #include <dev/microcode/isp/asm_1080.h> 107 #endif 108 109 #if defined(ISP_DISABLE_12160_SUPPORT) 110 #define ISP_12160_RISC_CODE NULL 111 #else 112 #define ISP_12160_RISC_CODE (const u_int16_t *) isp_12160_risc_code 113 #include <dev/microcode/isp/asm_12160.h> 114 #endif 115 116 #if defined(ISP_DISABLE_2100_SUPPORT) 117 #define ISP_2100_RISC_CODE NULL 118 #else 119 #define ISP_2100_RISC_CODE (const u_int16_t *) isp_2100_risc_code 120 #include <dev/microcode/isp/asm_2100.h> 121 #endif 122 123 #if defined(ISP_DISABLE_2200_SUPPORT) 124 #define ISP_2200_RISC_CODE NULL 125 #else 126 #define ISP_2200_RISC_CODE (const u_int16_t *) isp_2200_risc_code 127 #include <dev/microcode/isp/asm_2200.h> 128 #endif 129 130 #if defined(ISP_DISABLE_2300_SUPPORT) 131 #define ISP_2300_RISC_CODE NULL 132 #else 133 #define ISP_2300_RISC_CODE (const u_int16_t *) isp_2300_risc_code 134 #include <dev/microcode/isp/asm_2300.h> 135 #endif 136 137 #ifndef ISP_DISABLE_1020_SUPPORT 138 static struct ispmdvec mdvec = { 139 isp_pci_rd_isr, 140 isp_pci_rd_reg, 141 isp_pci_wr_reg, 142 isp_pci_mbxdma, 143 isp_pci_dmasetup, 144 isp_pci_dmateardown, 145 NULL, 146 isp_pci_reset1, 147 isp_pci_dumpregs, 148 ISP_1040_RISC_CODE, 149 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 150 0, /* dv_clock */ 151 }; 152 #endif 153 154 #ifndef ISP_DISABLE_1080_SUPPORT 155 static struct ispmdvec mdvec_1080 = { 156 isp_pci_rd_isr, 157 isp_pci_rd_reg_1080, 158 isp_pci_wr_reg_1080, 159 isp_pci_mbxdma, 160 isp_pci_dmasetup, 161 isp_pci_dmateardown, 162 NULL, 163 isp_pci_reset1, 164 isp_pci_dumpregs, 165 ISP_1080_RISC_CODE, 166 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 167 0, /* dv_clock */ 168 }; 169 #endif 170 171 #ifndef ISP_DISABLE_12160_SUPPORT 172 static struct ispmdvec mdvec_12160 = { 173 isp_pci_rd_isr, 174 isp_pci_rd_reg_1080, 175 isp_pci_wr_reg_1080, 176 isp_pci_mbxdma, 177 isp_pci_dmasetup, 178 isp_pci_dmateardown, 179 NULL, 180 isp_pci_reset1, 181 isp_pci_dumpregs, 182 ISP_12160_RISC_CODE, 183 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 184 0, /* dv_clock */ 185 }; 186 #endif 187 188 #ifndef ISP_DISABLE_2100_SUPPORT 189 static struct ispmdvec mdvec_2100 = { 190 isp_pci_rd_isr, 191 isp_pci_rd_reg, 192 isp_pci_wr_reg, 193 isp_pci_mbxdma, 194 isp_pci_dmasetup, 195 isp_pci_dmateardown, 196 NULL, 197 isp_pci_reset1, 198 isp_pci_dumpregs, 199 ISP_2100_RISC_CODE, 200 0, /* dv_conf1 */ 201 0, /* dv_clock */ 202 }; 203 #endif 204 205 #ifndef ISP_DISABLE_2200_SUPPORT 206 static struct ispmdvec mdvec_2200 = { 207 isp_pci_rd_isr, 208 isp_pci_rd_reg, 209 isp_pci_wr_reg, 210 isp_pci_mbxdma, 211 isp_pci_dmasetup, 212 isp_pci_dmateardown, 213 NULL, 214 isp_pci_reset1, 215 isp_pci_dumpregs, 216 ISP_2200_RISC_CODE, 217 0, /* dv_conf1 */ 218 0, /* dv_clock */ 219 }; 220 #endif 221 222 #ifndef ISP_DISABLE_2300_SUPPORT 223 static struct ispmdvec mdvec_2300 = { 224 isp_pci_rd_isr_2300, 225 isp_pci_rd_reg, 226 isp_pci_wr_reg, 227 isp_pci_mbxdma, 228 isp_pci_dmasetup, 229 isp_pci_dmateardown, 230 NULL, 231 isp_pci_reset1, 232 isp_pci_dumpregs, 233 ISP_2300_RISC_CODE, 234 0, /* dv_conf1 */ 235 0, /* dv_clock */ 236 }; 237 #endif 238 239 #ifndef PCI_VENDOR_QLOGIC 240 #define PCI_VENDOR_QLOGIC 0x1077 241 #endif 242 243 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 244 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 245 #endif 246 247 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 248 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 249 #endif 250 251 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 252 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 253 #endif 254 255 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 256 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 257 #endif 258 259 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 260 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 261 #endif 262 263 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 264 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 265 #endif 266 267 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 268 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 269 #endif 270 271 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 272 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 273 #endif 274 275 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 276 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 277 #endif 278 279 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 280 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 281 #endif 282 283 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP1080 \ 286 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define PCI_QLOGIC_ISP1240 \ 289 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 290 291 #define PCI_QLOGIC_ISP1280 \ 292 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 293 294 #define PCI_QLOGIC_ISP10160 \ 295 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 296 297 #define PCI_QLOGIC_ISP12160 \ 298 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 299 300 #define PCI_QLOGIC_ISP2100 \ 301 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 302 303 #define PCI_QLOGIC_ISP2200 \ 304 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 305 306 #define PCI_QLOGIC_ISP2300 \ 307 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 308 309 #define PCI_QLOGIC_ISP2312 \ 310 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 311 312 #define IO_MAP_REG 0x10 313 #define MEM_MAP_REG 0x14 314 #define PCIR_ROMADDR 0x30 315 316 #define PCI_DFLT_LTNCY 0x40 317 #define PCI_DFLT_LNSZ 0x10 318 319 320 static int isp_pci_probe(struct device *, struct cfdata *, void *); 321 static void isp_pci_attach(struct device *, struct device *, void *); 322 323 struct isp_pcisoftc { 324 struct ispsoftc pci_isp; 325 pci_chipset_tag_t pci_pc; 326 pcitag_t pci_tag; 327 bus_space_tag_t pci_st; 328 bus_space_handle_t pci_sh; 329 bus_dmamap_t *pci_xfer_dmap; 330 void * pci_ih; 331 int16_t pci_poff[_NREG_BLKS]; 332 }; 333 334 CFATTACH_DECL(isp_pci, sizeof (struct isp_pcisoftc), 335 isp_pci_probe, isp_pci_attach, NULL, NULL); 336 337 #ifdef DEBUG 338 const char vstring[] = 339 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 340 #endif 341 342 static int 343 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux) 344 { 345 struct pci_attach_args *pa = aux; 346 switch (pa->pa_id) { 347 #ifndef ISP_DISABLE_1020_SUPPORT 348 case PCI_QLOGIC_ISP: 349 return (1); 350 #endif 351 #ifndef ISP_DISABLE_1080_SUPPORT 352 case PCI_QLOGIC_ISP1080: 353 case PCI_QLOGIC_ISP1240: 354 case PCI_QLOGIC_ISP1280: 355 return (1); 356 #endif 357 #ifndef ISP_DISABLE_12160_SUPPORT 358 case PCI_QLOGIC_ISP10160: 359 case PCI_QLOGIC_ISP12160: 360 return (1); 361 #endif 362 #ifndef ISP_DISABLE_2100_SUPPORT 363 case PCI_QLOGIC_ISP2100: 364 return (1); 365 #endif 366 #ifndef ISP_DISABLE_2200_SUPPORT 367 case PCI_QLOGIC_ISP2200: 368 return (1); 369 #endif 370 #ifndef ISP_DISABLE_2300_SUPPORT 371 case PCI_QLOGIC_ISP2300: 372 case PCI_QLOGIC_ISP2312: 373 return (1); 374 #endif 375 default: 376 return (0); 377 } 378 } 379 380 381 static void 382 isp_pci_attach(struct device *parent, struct device *self, void *aux) 383 { 384 #ifdef DEBUG 385 static char oneshot = 1; 386 #endif 387 static const char nomem[] = "\n%s: no mem for sdparam table\n"; 388 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 389 struct pci_attach_args *pa = aux; 390 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 391 struct ispsoftc *isp = &pcs->pci_isp; 392 bus_space_tag_t st, iot, memt; 393 bus_space_handle_t sh, ioh, memh; 394 pci_intr_handle_t ih; 395 pcireg_t mem_type; 396 const char *dstring; 397 const char *intrstr; 398 int ioh_valid, memh_valid; 399 400 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 401 PCI_MAPREG_TYPE_IO, 0, 402 &iot, &ioh, NULL, NULL) == 0); 403 404 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG); 405 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) { 406 memh_valid = 0; 407 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT && 408 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) { 409 memh_valid = 0; 410 } else { 411 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0, 412 &memt, &memh, NULL, NULL) == 0); 413 } 414 if (memh_valid) { 415 st = memt; 416 sh = memh; 417 } else if (ioh_valid) { 418 st = iot; 419 sh = ioh; 420 } else { 421 printf(": unable to map device registers\n"); 422 return; 423 } 424 dstring = "\n"; 425 426 pcs->pci_st = st; 427 pcs->pci_sh = sh; 428 pcs->pci_pc = pa->pa_pc; 429 pcs->pci_tag = pa->pa_tag; 430 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 431 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 432 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 433 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 434 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 435 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 436 437 #ifndef ISP_DISABLE_1020_SUPPORT 438 if (pa->pa_id == PCI_QLOGIC_ISP) { 439 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n"; 440 isp->isp_mdvec = &mdvec; 441 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 442 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 443 if (isp->isp_param == NULL) { 444 printf(nomem, isp->isp_name); 445 return; 446 } 447 memset(isp->isp_param, 0, sizeof (sdparam)); 448 } 449 #endif 450 #ifndef ISP_DISABLE_1080_SUPPORT 451 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 452 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n"; 453 isp->isp_mdvec = &mdvec_1080; 454 isp->isp_type = ISP_HA_SCSI_1080; 455 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 456 if (isp->isp_param == NULL) { 457 printf(nomem, isp->isp_name); 458 return; 459 } 460 memset(isp->isp_param, 0, sizeof (sdparam)); 461 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 462 ISP1080_DMA_REGS_OFF; 463 } 464 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 465 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n"; 466 isp->isp_mdvec = &mdvec_1080; 467 isp->isp_type = ISP_HA_SCSI_1240; 468 isp->isp_param = 469 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 470 if (isp->isp_param == NULL) { 471 printf(nomem, isp->isp_name); 472 return; 473 } 474 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 475 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 476 ISP1080_DMA_REGS_OFF; 477 } 478 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 479 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n"; 480 isp->isp_mdvec = &mdvec_1080; 481 isp->isp_type = ISP_HA_SCSI_1280; 482 isp->isp_param = 483 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 484 if (isp->isp_param == NULL) { 485 printf(nomem, isp->isp_name); 486 return; 487 } 488 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 489 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 490 ISP1080_DMA_REGS_OFF; 491 } 492 #endif 493 #ifndef ISP_DISABLE_12160_SUPPORT 494 if (pa->pa_id == PCI_QLOGIC_ISP10160) { 495 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n"; 496 isp->isp_mdvec = &mdvec_12160; 497 isp->isp_type = ISP_HA_SCSI_10160; 498 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 499 if (isp->isp_param == NULL) { 500 printf(nomem, isp->isp_name); 501 return; 502 } 503 memset(isp->isp_param, 0, sizeof (sdparam)); 504 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 505 ISP1080_DMA_REGS_OFF; 506 } 507 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 508 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n"; 509 isp->isp_mdvec = &mdvec_12160; 510 isp->isp_type = ISP_HA_SCSI_12160; 511 isp->isp_param = 512 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 513 if (isp->isp_param == NULL) { 514 printf(nomem, isp->isp_name); 515 return; 516 } 517 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 518 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 519 ISP1080_DMA_REGS_OFF; 520 } 521 #endif 522 #ifndef ISP_DISABLE_2100_SUPPORT 523 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 524 dstring = ": QLogic FC-AL HBA\n"; 525 isp->isp_mdvec = &mdvec_2100; 526 isp->isp_type = ISP_HA_FC_2100; 527 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 528 if (isp->isp_param == NULL) { 529 printf(nomem, isp->isp_name); 530 return; 531 } 532 memset(isp->isp_param, 0, sizeof (fcparam)); 533 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 534 PCI_MBOX_REGS2100_OFF; 535 if (rev < 3) { 536 /* 537 * XXX: Need to get the actual revision 538 * XXX: number of the 2100 FB. At any rate, 539 * XXX: lower cache line size for early revision 540 * XXX; boards. 541 */ 542 linesz = 1; 543 } 544 } 545 #endif 546 #ifndef ISP_DISABLE_2200_SUPPORT 547 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 548 dstring = ": QLogic FC-AL and Fabric HBA\n"; 549 isp->isp_mdvec = &mdvec_2200; 550 isp->isp_type = ISP_HA_FC_2200; 551 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 552 if (isp->isp_param == NULL) { 553 printf(nomem, isp->isp_name); 554 return; 555 } 556 memset(isp->isp_param, 0, sizeof (fcparam)); 557 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 558 PCI_MBOX_REGS2100_OFF; 559 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 560 } 561 #endif 562 #ifndef ISP_DISABLE_2300_SUPPORT 563 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 564 pa->pa_id == PCI_QLOGIC_ISP2312) { 565 isp->isp_mdvec = &mdvec_2300; 566 if (pa->pa_id == PCI_QLOGIC_ISP2300) { 567 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n"; 568 isp->isp_type = ISP_HA_FC_2300; 569 } else { 570 dstring = 571 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n"; 572 isp->isp_type = ISP_HA_FC_2312; 573 isp->isp_port = pa->pa_function; 574 } 575 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 576 if (isp->isp_param == NULL) { 577 printf(nomem, isp->isp_name); 578 return; 579 } 580 memset(isp->isp_param, 0, sizeof (fcparam)); 581 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 582 PCI_MBOX_REGS2300_OFF; 583 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 584 } 585 #endif 586 /* 587 * Set up logging levels. 588 */ 589 #ifdef ISP_LOGDEFAULT 590 isp->isp_dblev = ISP_LOGDEFAULT; 591 #else 592 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 593 if (bootverbose) 594 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 595 #ifdef SCSIDEBUG 596 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2; 597 #endif 598 #endif 599 if (isp->isp_dblev & ISP_LOGCONFIG) { 600 printf("\n"); 601 } else { 602 printf(dstring); 603 } 604 605 #ifdef DEBUG 606 if (oneshot) { 607 oneshot = 0; 608 isp_prt(isp, ISP_LOGCONFIG, vstring, 609 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 610 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 611 } 612 #endif 613 614 isp->isp_dmatag = pa->pa_dmat; 615 isp->isp_revision = rev; 616 617 /* 618 * Make sure that command register set sanely. 619 */ 620 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 621 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 622 623 /* 624 * Not so sure about these- but I think it's important that they get 625 * enabled...... 626 */ 627 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 628 if (IS_2300(isp)) { /* per QLogic errata */ 629 data &= ~PCI_COMMAND_INVALIDATE_ENABLE; 630 } 631 if (IS_23XX(isp)) { 632 isp->isp_touched = 1; 633 } 634 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 635 636 /* 637 * Make sure that the latency timer, cache line size, 638 * and ROM is disabled. 639 */ 640 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 641 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 642 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 643 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 644 data |= (linesz << PCI_CACHELINE_SHIFT); 645 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 646 647 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 648 data &= ~1; 649 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 650 651 if (pci_intr_map(pa, &ih)) { 652 printf("%s: couldn't map interrupt\n", isp->isp_name); 653 free(isp->isp_param, M_DEVBUF); 654 return; 655 } 656 intrstr = pci_intr_string(pa->pa_pc, ih); 657 if (intrstr == NULL) 658 intrstr = "<I dunno>"; 659 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 660 isp_pci_intr, isp); 661 if (pcs->pci_ih == NULL) { 662 printf("%s: couldn't establish interrupt at %s\n", 663 isp->isp_name, intrstr); 664 free(isp->isp_param, M_DEVBUF); 665 return; 666 } 667 668 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 669 670 if (IS_FC(isp)) { 671 DEFAULT_NODEWWN(isp) = 0x400000007F000002ULL; 672 DEFAULT_PORTWWN(isp) = 0x400000007F000002ULL; 673 } 674 675 isp->isp_confopts = device_cfdata(self)->cf_flags; 676 isp->isp_role = ISP_DEFAULT_ROLES; 677 ISP_LOCK(isp); 678 isp->isp_osinfo.no_mbox_ints = 1; 679 isp_reset(isp); 680 if (isp->isp_state != ISP_RESETSTATE) { 681 ISP_UNLOCK(isp); 682 free(isp->isp_param, M_DEVBUF); 683 return; 684 } 685 ENABLE_INTS(isp); 686 isp_init(isp); 687 if (isp->isp_state != ISP_INITSTATE) { 688 isp_uninit(isp); 689 ISP_UNLOCK(isp); 690 free(isp->isp_param, M_DEVBUF); 691 return; 692 } 693 /* 694 * Do platform attach. 695 */ 696 ISP_UNLOCK(isp); 697 isp_attach(isp); 698 if (isp->isp_state != ISP_RUNSTATE) { 699 ISP_LOCK(isp); 700 isp_uninit(isp); 701 free(isp->isp_param, M_DEVBUF); 702 ISP_UNLOCK(isp); 703 } 704 } 705 706 #define IspVirt2Off(a, x) \ 707 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 708 _BLK_REG_SHFT] + ((x) & 0xff)) 709 710 #define BXR2(pcs, off) \ 711 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 712 #define BXW2(pcs, off, v) \ 713 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 714 715 716 static INLINE int 717 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 718 { 719 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 720 u_int16_t val0, val1; 721 int i = 0; 722 723 do { 724 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 725 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 726 } while (val0 != val1 && ++i < 1000); 727 if (val0 != val1) { 728 return (1); 729 } 730 *rp = val0; 731 return (0); 732 } 733 734 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 735 !defined(ISP_DISABLE_2200_SUPPORT) && \ 736 !defined(ISP_DISABLE_1020_SUPPORT) && \ 737 !defined(ISP_DISABLE_1080_SUPPORT) && \ 738 !defined(ISP_DISABLE_12160_SUPPORT) 739 static int 740 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 741 u_int16_t *semap, u_int16_t *mbp) 742 { 743 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 744 u_int16_t isr, sema; 745 746 if (IS_2100(isp)) { 747 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 748 return (0); 749 } 750 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 751 return (0); 752 } 753 } else { 754 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 755 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 756 } 757 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 758 isr &= INT_PENDING_MASK(isp); 759 sema &= BIU_SEMA_LOCK; 760 if (isr == 0 && sema == 0) { 761 return (0); 762 } 763 *isrp = isr; 764 if ((*semap = sema) != 0) { 765 if (IS_2100(isp)) { 766 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 767 return (0); 768 } 769 } else { 770 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 771 } 772 } 773 return (1); 774 } 775 #endif 776 777 #ifndef ISP_DISABLE_2300_SUPPORT 778 static int 779 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 780 u_int16_t *semap, u_int16_t *mbox0p) 781 { 782 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 783 u_int32_t r2hisr; 784 785 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 786 *isrp = 0; 787 return (0); 788 } 789 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 790 IspVirt2Off(pcs, BIU_R2HSTSLO)); 791 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 792 if ((r2hisr & BIU_R2HST_INTR) == 0) { 793 *isrp = 0; 794 return (0); 795 } 796 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 797 case ISPR2HST_ROM_MBX_OK: 798 case ISPR2HST_ROM_MBX_FAIL: 799 case ISPR2HST_MBX_OK: 800 case ISPR2HST_MBX_FAIL: 801 case ISPR2HST_ASYNC_EVENT: 802 *isrp = r2hisr & 0xffff; 803 *mbox0p = (r2hisr >> 16); 804 *semap = 1; 805 return (1); 806 case ISPR2HST_RIO_16: 807 *isrp = r2hisr & 0xffff; 808 *mbox0p = ASYNC_RIO1; 809 *semap = 1; 810 return (1); 811 case ISPR2HST_FPOST: 812 *isrp = r2hisr & 0xffff; 813 *mbox0p = ASYNC_CMD_CMPLT; 814 *semap = 1; 815 return (1); 816 case ISPR2HST_FPOST_CTIO: 817 *isrp = r2hisr & 0xffff; 818 *mbox0p = ASYNC_CTIO_DONE; 819 *semap = 1; 820 return (1); 821 case ISPR2HST_RSPQ_UPDATE: 822 *isrp = r2hisr & 0xffff; 823 *mbox0p = 0; 824 *semap = 0; 825 return (1); 826 default: 827 return (0); 828 } 829 } 830 #endif 831 832 static u_int16_t 833 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 834 { 835 u_int16_t rv; 836 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 837 int oldconf = 0; 838 839 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 840 /* 841 * We will assume that someone has paused the RISC processor. 842 */ 843 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 844 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 845 oldconf | BIU_PCI_CONF1_SXP); 846 } 847 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 848 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 849 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 850 } 851 return (rv); 852 } 853 854 static void 855 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 856 { 857 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 858 int oldconf = 0; 859 860 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 861 /* 862 * We will assume that someone has paused the RISC processor. 863 */ 864 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 865 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 866 oldconf | BIU_PCI_CONF1_SXP); 867 } 868 BXW2(pcs, IspVirt2Off(isp, regoff), val); 869 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 870 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 871 } 872 } 873 874 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 875 static u_int16_t 876 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 877 { 878 u_int16_t rv, oc = 0; 879 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 880 881 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 882 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 883 u_int16_t tc; 884 /* 885 * We will assume that someone has paused the RISC processor. 886 */ 887 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 888 tc = oc & ~BIU_PCI1080_CONF1_DMA; 889 if (regoff & SXP_BANK1_SELECT) 890 tc |= BIU_PCI1080_CONF1_SXP1; 891 else 892 tc |= BIU_PCI1080_CONF1_SXP0; 893 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 894 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 895 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 896 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 897 oc | BIU_PCI1080_CONF1_DMA); 898 } 899 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 900 if (oc) { 901 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 902 } 903 return (rv); 904 } 905 906 static void 907 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 908 { 909 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 910 int oc = 0; 911 912 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 913 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 914 u_int16_t tc; 915 /* 916 * We will assume that someone has paused the RISC processor. 917 */ 918 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 919 tc = oc & ~BIU_PCI1080_CONF1_DMA; 920 if (regoff & SXP_BANK1_SELECT) 921 tc |= BIU_PCI1080_CONF1_SXP1; 922 else 923 tc |= BIU_PCI1080_CONF1_SXP0; 924 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 925 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 926 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 927 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 928 oc | BIU_PCI1080_CONF1_DMA); 929 } 930 BXW2(pcs, IspVirt2Off(isp, regoff), val); 931 if (oc) { 932 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 933 } 934 } 935 #endif 936 937 static int 938 isp_pci_mbxdma(struct ispsoftc *isp) 939 { 940 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 941 bus_dma_tag_t dmat = isp->isp_dmatag; 942 bus_dma_segment_t sg; 943 bus_size_t len; 944 fcparam *fcp; 945 int rs, i; 946 947 if (isp->isp_rquest_dma) /* been here before? */ 948 return (0); 949 950 len = isp->isp_maxcmds * sizeof (XS_T *); 951 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 952 if (isp->isp_xflist == NULL) { 953 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 954 return (1); 955 } 956 memset(isp->isp_xflist, 0, len); 957 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 958 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 959 if (pcs->pci_xfer_dmap == NULL) { 960 free(isp->isp_xflist, M_DEVBUF); 961 isp->isp_xflist = NULL; 962 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array"); 963 return (1); 964 } 965 for (i = 0; i < isp->isp_maxcmds; i++) { 966 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 967 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 968 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps"); 969 break; 970 } 971 } 972 if (i < isp->isp_maxcmds) { 973 while (--i >= 0) { 974 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 975 } 976 free(isp->isp_xflist, M_DEVBUF); 977 free(pcs->pci_xfer_dmap, M_DEVBUF); 978 isp->isp_xflist = NULL; 979 pcs->pci_xfer_dmap = NULL; 980 return (1); 981 } 982 983 /* 984 * Allocate and map the request queue. 985 */ 986 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 987 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 988 BUS_DMA_NOWAIT) || 989 bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 990 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 991 goto dmafail; 992 } 993 994 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 995 &isp->isp_rqdmap) || bus_dmamap_load(dmat, isp->isp_rqdmap, 996 (caddr_t)isp->isp_rquest, len, NULL, 997 BUS_DMA_NOWAIT)) { 998 goto dmafail; 999 } 1000 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 1001 1002 /* 1003 * Allocate and map the result queue. 1004 */ 1005 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1006 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 1007 BUS_DMA_NOWAIT) || 1008 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 1009 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1010 goto dmafail; 1011 } 1012 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 1013 &isp->isp_rsdmap) || bus_dmamap_load(isp->isp_dmatag, 1014 isp->isp_rsdmap, (caddr_t)isp->isp_result, len, NULL, 1015 BUS_DMA_NOWAIT)) { 1016 goto dmafail; 1017 } 1018 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 1019 1020 if (IS_SCSI(isp)) { 1021 return (0); 1022 } 1023 1024 fcp = isp->isp_param; 1025 len = ISP2100_SCRLEN; 1026 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 1027 BUS_DMA_NOWAIT) || 1028 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 1029 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1030 goto dmafail; 1031 } 1032 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 1033 &isp->isp_scdmap) || bus_dmamap_load(dmat, 1034 isp->isp_scdmap, (caddr_t)fcp->isp_scratch, len, NULL, 1035 BUS_DMA_NOWAIT)) { 1036 goto dmafail; 1037 } 1038 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 1039 return (0); 1040 dmafail: 1041 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure"); 1042 for (i = 0; i < isp->isp_maxcmds; i++) { 1043 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1044 } 1045 free(isp->isp_xflist, M_DEVBUF); 1046 free(pcs->pci_xfer_dmap, M_DEVBUF); 1047 isp->isp_xflist = NULL; 1048 pcs->pci_xfer_dmap = NULL; 1049 return (1); 1050 } 1051 1052 static int 1053 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq, 1054 u_int16_t *nxtip, u_int16_t optr) 1055 { 1056 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1057 bus_dmamap_t dmap; 1058 u_int16_t starti = isp->isp_reqidx, nxti = *nxtip; 1059 ispreq_t *qep; 1060 int segcnt, seg, error, ovseg, seglim, drq; 1061 1062 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, starti); 1063 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 1064 if (xs->datalen == 0) { 1065 rq->req_seg_count = 1; 1066 goto mbxsync; 1067 } 1068 if (xs->xs_control & XS_CTL_DATA_IN) { 1069 drq = REQFLAG_DATA_IN; 1070 } else { 1071 drq = REQFLAG_DATA_OUT; 1072 } 1073 1074 if (IS_FC(isp)) { 1075 seglim = ISP_RQDSEG_T2; 1076 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 1077 ((ispreqt2_t *)rq)->req_flags |= drq; 1078 } else { 1079 rq->req_flags |= drq; 1080 if (XS_CDBLEN(xs) > 12) { 1081 seglim = 0; 1082 } else { 1083 seglim = ISP_RQDSEG; 1084 } 1085 } 1086 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 1087 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 1088 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 1089 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1090 if (error) { 1091 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", error); 1092 XS_SETERR(xs, HBA_BOTCH); 1093 if (error == EAGAIN || error == ENOMEM) 1094 return (CMD_EAGAIN); 1095 else 1096 return (CMD_COMPLETE); 1097 } 1098 1099 segcnt = dmap->dm_nsegs; 1100 1101 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 1102 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 1103 "write from", xs->data, segcnt); 1104 1105 for (seg = 0, rq->req_seg_count = 0; 1106 seglim && seg < segcnt && rq->req_seg_count < seglim; 1107 seg++, rq->req_seg_count++) { 1108 if (IS_FC(isp)) { 1109 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1110 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1111 dmap->dm_segs[seg].ds_len; 1112 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1113 dmap->dm_segs[seg].ds_addr; 1114 } else { 1115 rq->req_dataseg[rq->req_seg_count].ds_count = 1116 dmap->dm_segs[seg].ds_len; 1117 rq->req_dataseg[rq->req_seg_count].ds_base = 1118 dmap->dm_segs[seg].ds_addr; 1119 } 1120 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 1121 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 1122 (unsigned long) dmap->dm_segs[seg].ds_len); 1123 } 1124 1125 if (seg == segcnt) { 1126 goto dmasync; 1127 } 1128 1129 do { 1130 u_int16_t onxti; 1131 ispcontreq_t *crq, *cqe, local; 1132 1133 crq = &local; 1134 1135 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1136 onxti = nxti; 1137 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1138 if (nxti == optr) { 1139 isp_prt(isp, /* ISP_LOGDEBUG0 */ ISP_LOGERR, "Request Queue Overflow++"); 1140 bus_dmamap_unload(isp->isp_dmatag, dmap); 1141 XS_SETERR(xs, HBA_BOTCH); 1142 return (CMD_EAGAIN); 1143 } 1144 rq->req_header.rqs_entry_count++; 1145 memset((void *)crq, 0, sizeof (*crq)); 1146 crq->req_header.rqs_entry_count = 1; 1147 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1148 1149 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 1150 rq->req_seg_count++, seg++, ovseg++) { 1151 crq->req_dataseg[ovseg].ds_count = 1152 dmap->dm_segs[seg].ds_len; 1153 crq->req_dataseg[ovseg].ds_base = 1154 dmap->dm_segs[seg].ds_addr; 1155 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 1156 rq->req_header.rqs_entry_count - 1, 1157 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 1158 (unsigned long) dmap->dm_segs[seg].ds_len); 1159 } 1160 isp_put_cont_req(isp, crq, cqe); 1161 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1162 } while (seg < segcnt); 1163 1164 1165 dmasync: 1166 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1167 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 1168 BUS_DMASYNC_PREWRITE); 1169 1170 mbxsync: 1171 switch (rq->req_header.rqs_entry_type) { 1172 case RQSTYPE_REQUEST: 1173 isp_put_request(isp, rq, qep); 1174 break; 1175 case RQSTYPE_CMDONLY: 1176 isp_put_extended_request(isp, (ispextreq_t *)rq, 1177 (ispextreq_t *)qep); 1178 break; 1179 case RQSTYPE_T2RQS: 1180 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1181 break; 1182 } 1183 *nxtip = nxti; 1184 return (CMD_QUEUED); 1185 } 1186 1187 static int 1188 isp_pci_intr(void *arg) 1189 { 1190 u_int16_t isr, sema, mbox; 1191 struct ispsoftc *isp = arg; 1192 1193 isp->isp_intcnt++; 1194 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1195 isp->isp_intbogus++; 1196 return (0); 1197 } else { 1198 isp->isp_osinfo.onintstack = 1; 1199 isp_intr(isp, isr, sema, mbox); 1200 isp->isp_osinfo.onintstack = 0; 1201 return (1); 1202 } 1203 } 1204 1205 static void 1206 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1207 { 1208 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1209 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 1210 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1211 xs->xs_control & XS_CTL_DATA_IN ? 1212 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1213 bus_dmamap_unload(isp->isp_dmatag, dmap); 1214 } 1215 1216 static void 1217 isp_pci_reset1(struct ispsoftc *isp) 1218 { 1219 /* Make sure the BIOS is disabled */ 1220 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1221 if (isp->isp_osinfo.no_mbox_ints == 0) { 1222 ENABLE_INTS(isp); 1223 } 1224 1225 } 1226 1227 static void 1228 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1229 { 1230 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1231 if (msg) 1232 printf("%s: %s\n", isp->isp_name, msg); 1233 if (IS_SCSI(isp)) 1234 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1235 else 1236 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1237 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1238 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1239 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1240 1241 1242 if (IS_SCSI(isp)) { 1243 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1244 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1245 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1246 ISP_READ(isp, CDMA_FIFO_STS)); 1247 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1248 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1249 ISP_READ(isp, DDMA_FIFO_STS)); 1250 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1251 ISP_READ(isp, SXP_INTERRUPT), 1252 ISP_READ(isp, SXP_GROSS_ERR), 1253 ISP_READ(isp, SXP_PINS_CTRL)); 1254 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1255 } 1256 printf(" mbox regs: %x %x %x %x %x\n", 1257 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1258 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1259 ISP_READ(isp, OUTMAILBOX4)); 1260 printf(" PCI Status Command/Status=%x\n", 1261 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1262 } 1263
Indexes created Thu Sep 25 16:09:42 GMT 2025