ixgbe_82599.c revision 1.1
1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.6 2011/01/19 19:36:27 jfv Exp $*/ 34 /*$NetBSD: ixgbe_82599.c,v 1.1 2011/08/12 21:55:29 dyoung Exp $*/ 35 36 #include "ixgbe_type.h" 37 #include "ixgbe_api.h" 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 41 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 42 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 43 ixgbe_link_speed *speed, 44 bool *autoneg); 45 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); 46 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 47 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 48 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 49 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, bool autoneg, 51 bool autoneg_wait_to_complete); 52 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 53 ixgbe_link_speed speed, bool autoneg, 54 bool autoneg_wait_to_complete); 55 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 56 bool autoneg_wait_to_complete); 57 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 58 ixgbe_link_speed speed, 59 bool autoneg, 60 bool autoneg_wait_to_complete); 61 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 62 ixgbe_link_speed speed, 63 bool autoneg, 64 bool autoneg_wait_to_complete); 65 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); 66 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); 67 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw); 68 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val); 69 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val); 70 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw); 71 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw); 72 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); 73 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); 74 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval); 75 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 76 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 77 78 79 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 80 { 81 struct ixgbe_mac_info *mac = &hw->mac; 82 83 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 84 85 /* enable the laser control functions for SFP+ fiber */ 86 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { 87 mac->ops.disable_tx_laser = 88 &ixgbe_disable_tx_laser_multispeed_fiber; 89 mac->ops.enable_tx_laser = 90 &ixgbe_enable_tx_laser_multispeed_fiber; 91 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 92 93 } else { 94 mac->ops.disable_tx_laser = NULL; 95 mac->ops.enable_tx_laser = NULL; 96 mac->ops.flap_tx_laser = NULL; 97 } 98 99 if (hw->phy.multispeed_fiber) { 100 /* Set up dual speed SFP+ support */ 101 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 102 } else { 103 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 104 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 105 hw->phy.smart_speed == ixgbe_smart_speed_on) && 106 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 107 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 108 } else { 109 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 110 } 111 } 112 } 113 114 /** 115 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 116 * @hw: pointer to hardware structure 117 * 118 * Initialize any function pointers that were not able to be 119 * set during init_shared_code because the PHY/SFP type was 120 * not known. Perform the SFP init if necessary. 121 * 122 **/ 123 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 124 { 125 struct ixgbe_mac_info *mac = &hw->mac; 126 struct ixgbe_phy_info *phy = &hw->phy; 127 s32 ret_val = IXGBE_SUCCESS; 128 129 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 130 131 /* Identify the PHY or SFP module */ 132 ret_val = phy->ops.identify(hw); 133 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 134 goto init_phy_ops_out; 135 136 /* Setup function pointers based on detected SFP module and speeds */ 137 ixgbe_init_mac_link_ops_82599(hw); 138 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 139 hw->phy.ops.reset = NULL; 140 141 /* If copper media, overwrite with copper function pointers */ 142 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 143 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 144 mac->ops.get_link_capabilities = 145 &ixgbe_get_copper_link_capabilities_generic; 146 } 147 148 /* Set necessary function pointers based on phy type */ 149 switch (hw->phy.type) { 150 case ixgbe_phy_tn: 151 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 152 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 153 phy->ops.get_firmware_version = 154 &ixgbe_get_phy_firmware_version_tnx; 155 break; 156 case ixgbe_phy_aq: 157 phy->ops.get_firmware_version = 158 &ixgbe_get_phy_firmware_version_generic; 159 break; 160 default: 161 break; 162 } 163 init_phy_ops_out: 164 return ret_val; 165 } 166 167 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 168 { 169 s32 ret_val = IXGBE_SUCCESS; 170 u32 reg_anlp1 = 0; 171 u32 i = 0; 172 u16 list_offset, data_offset, data_value; 173 174 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 175 176 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 177 ixgbe_init_mac_link_ops_82599(hw); 178 179 hw->phy.ops.reset = NULL; 180 181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 182 &data_offset); 183 if (ret_val != IXGBE_SUCCESS) 184 goto setup_sfp_out; 185 186 /* PHY config will finish before releasing the semaphore */ 187 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 188 if (ret_val != IXGBE_SUCCESS) { 189 ret_val = IXGBE_ERR_SWFW_SYNC; 190 goto setup_sfp_out; 191 } 192 193 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 194 while (data_value != 0xffff) { 195 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 196 IXGBE_WRITE_FLUSH(hw); 197 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 198 } 199 200 /* Release the semaphore */ 201 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 202 /* Delay obtaining semaphore again to allow FW access */ 203 msec_delay(hw->eeprom.semaphore_delay); 204 205 /* Now restart DSP by setting Restart_AN and clearing LMS */ 206 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw, 207 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) | 208 IXGBE_AUTOC_AN_RESTART)); 209 210 /* Wait for AN to leave state 0 */ 211 for (i = 0; i < 10; i++) { 212 msec_delay(4); 213 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1); 214 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK) 215 break; 216 } 217 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) { 218 DEBUGOUT("sfp module setup not complete\n"); 219 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 220 goto setup_sfp_out; 221 } 222 223 /* Restart DSP by setting Restart_AN and return to SFI mode */ 224 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw, 225 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL | 226 IXGBE_AUTOC_AN_RESTART)); 227 } 228 229 setup_sfp_out: 230 return ret_val; 231 } 232 233 /** 234 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 235 * @hw: pointer to hardware structure 236 * 237 * Initialize the function pointers and assign the MAC type for 82599. 238 * Does not touch the hardware. 239 **/ 240 241 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 242 { 243 struct ixgbe_mac_info *mac = &hw->mac; 244 struct ixgbe_phy_info *phy = &hw->phy; 245 s32 ret_val; 246 247 DEBUGFUNC("ixgbe_init_ops_82599"); 248 249 ret_val = ixgbe_init_phy_ops_generic(hw); 250 ret_val = ixgbe_init_ops_generic(hw); 251 252 /* PHY */ 253 phy->ops.identify = &ixgbe_identify_phy_82599; 254 phy->ops.init = &ixgbe_init_phy_ops_82599; 255 256 /* MAC */ 257 mac->ops.reset_hw = &ixgbe_reset_hw_82599; 258 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 259 mac->ops.get_media_type = &ixgbe_get_media_type_82599; 260 mac->ops.get_supported_physical_layer = 261 &ixgbe_get_supported_physical_layer_82599; 262 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; 263 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; 264 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; 265 mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599; 266 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 267 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 268 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 269 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 270 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; 271 272 /* RAR, Multicast, VLAN */ 273 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 274 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 275 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 276 mac->rar_highwater = 1; 277 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 278 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 279 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 280 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; 281 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; 282 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; 283 284 /* Link */ 285 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; 286 mac->ops.check_link = &ixgbe_check_mac_link_generic; 287 ixgbe_init_mac_link_ops_82599(hw); 288 289 mac->mcft_size = 128; 290 mac->vft_size = 128; 291 mac->num_rar_entries = 128; 292 mac->rx_pb_size = 512; 293 mac->max_tx_queues = 128; 294 mac->max_rx_queues = 128; 295 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 296 297 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 298 299 return ret_val; 300 } 301 302 /** 303 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 304 * @hw: pointer to hardware structure 305 * @speed: pointer to link speed 306 * @negotiation: TRUE when autoneg or autotry is enabled 307 * 308 * Determines the link capabilities by reading the AUTOC register. 309 **/ 310 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 311 ixgbe_link_speed *speed, 312 bool *negotiation) 313 { 314 s32 status = IXGBE_SUCCESS; 315 u32 autoc = 0; 316 317 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 318 319 320 /* Check if 1G SFP module. */ 321 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 322 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) { 323 *speed = IXGBE_LINK_SPEED_1GB_FULL; 324 *negotiation = TRUE; 325 goto out; 326 } 327 328 /* 329 * Determine link capabilities based on the stored value of AUTOC, 330 * which represents EEPROM defaults. If AUTOC value has not 331 * been stored, use the current register values. 332 */ 333 if (hw->mac.orig_link_settings_stored) 334 autoc = hw->mac.orig_autoc; 335 else 336 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 337 338 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 339 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 340 *speed = IXGBE_LINK_SPEED_1GB_FULL; 341 *negotiation = FALSE; 342 break; 343 344 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 345 *speed = IXGBE_LINK_SPEED_10GB_FULL; 346 *negotiation = FALSE; 347 break; 348 349 case IXGBE_AUTOC_LMS_1G_AN: 350 *speed = IXGBE_LINK_SPEED_1GB_FULL; 351 *negotiation = TRUE; 352 break; 353 354 case IXGBE_AUTOC_LMS_10G_SERIAL: 355 *speed = IXGBE_LINK_SPEED_10GB_FULL; 356 *negotiation = FALSE; 357 break; 358 359 case IXGBE_AUTOC_LMS_KX4_KX_KR: 360 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 361 *speed = IXGBE_LINK_SPEED_UNKNOWN; 362 if (autoc & IXGBE_AUTOC_KR_SUPP) 363 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 364 if (autoc & IXGBE_AUTOC_KX4_SUPP) 365 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 366 if (autoc & IXGBE_AUTOC_KX_SUPP) 367 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 368 *negotiation = TRUE; 369 break; 370 371 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 372 *speed = IXGBE_LINK_SPEED_100_FULL; 373 if (autoc & IXGBE_AUTOC_KR_SUPP) 374 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 375 if (autoc & IXGBE_AUTOC_KX4_SUPP) 376 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 377 if (autoc & IXGBE_AUTOC_KX_SUPP) 378 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 379 *negotiation = TRUE; 380 break; 381 382 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 383 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 384 *negotiation = FALSE; 385 break; 386 387 default: 388 status = IXGBE_ERR_LINK_SETUP; 389 goto out; 390 break; 391 } 392 393 if (hw->phy.multispeed_fiber) { 394 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 395 IXGBE_LINK_SPEED_1GB_FULL; 396 *negotiation = TRUE; 397 } 398 399 out: 400 return status; 401 } 402 403 /** 404 * ixgbe_get_media_type_82599 - Get media type 405 * @hw: pointer to hardware structure 406 * 407 * Returns the media type (fiber, copper, backplane) 408 **/ 409 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 410 { 411 enum ixgbe_media_type media_type; 412 413 DEBUGFUNC("ixgbe_get_media_type_82599"); 414 415 /* Detect if there is a copper PHY attached. */ 416 switch (hw->phy.type) { 417 case ixgbe_phy_cu_unknown: 418 case ixgbe_phy_tn: 419 case ixgbe_phy_aq: 420 media_type = ixgbe_media_type_copper; 421 goto out; 422 default: 423 break; 424 } 425 426 switch (hw->device_id) { 427 case IXGBE_DEV_ID_82599_KX4: 428 case IXGBE_DEV_ID_82599_KX4_MEZZ: 429 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 430 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 431 case IXGBE_DEV_ID_82599_XAUI_LOM: 432 /* Default device ID is mezzanine card KX/KX4 */ 433 media_type = ixgbe_media_type_backplane; 434 break; 435 case IXGBE_DEV_ID_82599_SFP: 436 case IXGBE_DEV_ID_82599_SFP_FCOE: 437 media_type = ixgbe_media_type_fiber; 438 break; 439 case IXGBE_DEV_ID_82599_CX4: 440 media_type = ixgbe_media_type_cx4; 441 break; 442 case IXGBE_DEV_ID_82599_T3_LOM: 443 media_type = ixgbe_media_type_copper; 444 break; 445 default: 446 media_type = ixgbe_media_type_unknown; 447 break; 448 } 449 out: 450 return media_type; 451 } 452 453 /** 454 * ixgbe_start_mac_link_82599 - Setup MAC link settings 455 * @hw: pointer to hardware structure 456 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 457 * 458 * Configures link settings based on values in the ixgbe_hw struct. 459 * Restarts the link. Performs autonegotiation if needed. 460 **/ 461 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 462 bool autoneg_wait_to_complete) 463 { 464 u32 autoc_reg; 465 u32 links_reg; 466 u32 i; 467 s32 status = IXGBE_SUCCESS; 468 469 DEBUGFUNC("ixgbe_start_mac_link_82599"); 470 471 472 /* Restart link */ 473 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 474 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 475 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 476 477 /* Only poll for autoneg to complete if specified to do so */ 478 if (autoneg_wait_to_complete) { 479 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 480 IXGBE_AUTOC_LMS_KX4_KX_KR || 481 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 482 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 483 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 484 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 485 links_reg = 0; /* Just in case Autoneg time = 0 */ 486 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 487 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 488 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 489 break; 490 msec_delay(100); 491 } 492 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 493 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 494 DEBUGOUT("Autoneg did not complete.\n"); 495 } 496 } 497 } 498 499 /* Add delay to filter out noises during initial link setup */ 500 msec_delay(50); 501 502 return status; 503 } 504 505 /** 506 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 507 * @hw: pointer to hardware structure 508 * 509 * The base drivers may require better control over SFP+ module 510 * PHY states. This includes selectively shutting down the Tx 511 * laser on the PHY, effectively halting physical link. 512 **/ 513 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 514 { 515 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 516 517 /* Disable tx laser; allow 100us to go dark per spec */ 518 esdp_reg |= IXGBE_ESDP_SDP3; 519 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 520 IXGBE_WRITE_FLUSH(hw); 521 usec_delay(100); 522 } 523 524 /** 525 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 526 * @hw: pointer to hardware structure 527 * 528 * The base drivers may require better control over SFP+ module 529 * PHY states. This includes selectively turning on the Tx 530 * laser on the PHY, effectively starting physical link. 531 **/ 532 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 533 { 534 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 535 536 /* Enable tx laser; allow 100ms to light up */ 537 esdp_reg &= ~IXGBE_ESDP_SDP3; 538 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 539 IXGBE_WRITE_FLUSH(hw); 540 msec_delay(100); 541 } 542 543 /** 544 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 545 * @hw: pointer to hardware structure 546 * 547 * When the driver changes the link speeds that it can support, 548 * it sets autotry_restart to TRUE to indicate that we need to 549 * initiate a new autotry session with the link partner. To do 550 * so, we set the speed then disable and re-enable the tx laser, to 551 * alert the link partner that it also needs to restart autotry on its 552 * end. This is consistent with TRUE clause 37 autoneg, which also 553 * involves a loss of signal. 554 **/ 555 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 556 { 557 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 558 559 if (hw->mac.autotry_restart) { 560 ixgbe_disable_tx_laser_multispeed_fiber(hw); 561 ixgbe_enable_tx_laser_multispeed_fiber(hw); 562 hw->mac.autotry_restart = FALSE; 563 } 564 } 565 566 /** 567 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 568 * @hw: pointer to hardware structure 569 * @speed: new link speed 570 * @autoneg: TRUE if autonegotiation enabled 571 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 572 * 573 * Set the link speed in the AUTOC register and restarts link. 574 **/ 575 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 576 ixgbe_link_speed speed, bool autoneg, 577 bool autoneg_wait_to_complete) 578 { 579 s32 status = IXGBE_SUCCESS; 580 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 581 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 582 u32 speedcnt = 0; 583 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 584 u32 i = 0; 585 bool link_up = FALSE; 586 bool negotiation; 587 588 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 589 590 /* Mask off requested but non-supported speeds */ 591 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation); 592 if (status != IXGBE_SUCCESS) 593 return status; 594 595 speed &= link_speed; 596 597 /* 598 * Try each speed one by one, highest priority first. We do this in 599 * software because 10gb fiber doesn't support speed autonegotiation. 600 */ 601 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 602 speedcnt++; 603 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 604 605 /* If we already have link at this speed, just jump out */ 606 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 607 if (status != IXGBE_SUCCESS) 608 return status; 609 610 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 611 goto out; 612 613 /* Set the module link speed */ 614 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 615 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 616 IXGBE_WRITE_FLUSH(hw); 617 618 /* Allow module to change analog characteristics (1G->10G) */ 619 msec_delay(40); 620 621 status = ixgbe_setup_mac_link_82599(hw, 622 IXGBE_LINK_SPEED_10GB_FULL, 623 autoneg, 624 autoneg_wait_to_complete); 625 if (status != IXGBE_SUCCESS) 626 return status; 627 628 /* Flap the tx laser if it has not already been done */ 629 ixgbe_flap_tx_laser(hw); 630 631 /* 632 * Wait for the controller to acquire link. Per IEEE 802.3ap, 633 * Section 73.10.2, we may have to wait up to 500ms if KR is 634 * attempted. 82599 uses the same timing for 10g SFI. 635 */ 636 for (i = 0; i < 5; i++) { 637 /* Wait for the link partner to also set speed */ 638 msec_delay(100); 639 640 /* If we have link, just jump out */ 641 status = ixgbe_check_link(hw, &link_speed, 642 &link_up, FALSE); 643 if (status != IXGBE_SUCCESS) 644 return status; 645 646 if (link_up) 647 goto out; 648 } 649 } 650 651 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 652 speedcnt++; 653 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 654 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 655 656 /* If we already have link at this speed, just jump out */ 657 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 658 if (status != IXGBE_SUCCESS) 659 return status; 660 661 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 662 goto out; 663 664 /* Set the module link speed */ 665 esdp_reg &= ~IXGBE_ESDP_SDP5; 666 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 667 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 668 IXGBE_WRITE_FLUSH(hw); 669 670 /* Allow module to change analog characteristics (10G->1G) */ 671 msec_delay(40); 672 673 status = ixgbe_setup_mac_link_82599(hw, 674 IXGBE_LINK_SPEED_1GB_FULL, 675 autoneg, 676 autoneg_wait_to_complete); 677 if (status != IXGBE_SUCCESS) 678 return status; 679 680 /* Flap the tx laser if it has not already been done */ 681 ixgbe_flap_tx_laser(hw); 682 683 /* Wait for the link partner to also set speed */ 684 msec_delay(100); 685 686 /* If we have link, just jump out */ 687 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 688 if (status != IXGBE_SUCCESS) 689 return status; 690 691 if (link_up) 692 goto out; 693 } 694 695 /* 696 * We didn't get link. Configure back to the highest speed we tried, 697 * (if there was more than one). We call ourselves back with just the 698 * single highest speed that the user requested. 699 */ 700 if (speedcnt > 1) 701 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 702 highest_link_speed, autoneg, autoneg_wait_to_complete); 703 704 out: 705 /* Set autoneg_advertised value based on input link speed */ 706 hw->phy.autoneg_advertised = 0; 707 708 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 709 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 710 711 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 712 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 713 714 return status; 715 } 716 717 /** 718 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 719 * @hw: pointer to hardware structure 720 * @speed: new link speed 721 * @autoneg: TRUE if autonegotiation enabled 722 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 723 * 724 * Implements the Intel SmartSpeed algorithm. 725 **/ 726 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 727 ixgbe_link_speed speed, bool autoneg, 728 bool autoneg_wait_to_complete) 729 { 730 s32 status = IXGBE_SUCCESS; 731 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 732 s32 i, j; 733 bool link_up = FALSE; 734 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 735 736 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 737 738 /* Set autoneg_advertised value based on input link speed */ 739 hw->phy.autoneg_advertised = 0; 740 741 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 742 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 743 744 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 745 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 746 747 if (speed & IXGBE_LINK_SPEED_100_FULL) 748 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 749 750 /* 751 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 752 * autoneg advertisement if link is unable to be established at the 753 * highest negotiated rate. This can sometimes happen due to integrity 754 * issues with the physical media connection. 755 */ 756 757 /* First, try to get link with full advertisement */ 758 hw->phy.smart_speed_active = FALSE; 759 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 760 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 761 autoneg_wait_to_complete); 762 if (status != IXGBE_SUCCESS) 763 goto out; 764 765 /* 766 * Wait for the controller to acquire link. Per IEEE 802.3ap, 767 * Section 73.10.2, we may have to wait up to 500ms if KR is 768 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 769 * Table 9 in the AN MAS. 770 */ 771 for (i = 0; i < 5; i++) { 772 msec_delay(100); 773 774 /* If we have link, just jump out */ 775 status = ixgbe_check_link(hw, &link_speed, &link_up, 776 FALSE); 777 if (status != IXGBE_SUCCESS) 778 goto out; 779 780 if (link_up) 781 goto out; 782 } 783 } 784 785 /* 786 * We didn't get link. If we advertised KR plus one of KX4/KX 787 * (or BX4/BX), then disable KR and try again. 788 */ 789 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 790 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 791 goto out; 792 793 /* Turn SmartSpeed on to disable KR support */ 794 hw->phy.smart_speed_active = TRUE; 795 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 796 autoneg_wait_to_complete); 797 if (status != IXGBE_SUCCESS) 798 goto out; 799 800 /* 801 * Wait for the controller to acquire link. 600ms will allow for 802 * the AN link_fail_inhibit_timer as well for multiple cycles of 803 * parallel detect, both 10g and 1g. This allows for the maximum 804 * connect attempts as defined in the AN MAS table 73-7. 805 */ 806 for (i = 0; i < 6; i++) { 807 msec_delay(100); 808 809 /* If we have link, just jump out */ 810 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 811 if (status != IXGBE_SUCCESS) 812 goto out; 813 814 if (link_up) 815 goto out; 816 } 817 818 /* We didn't get link. Turn SmartSpeed back off. */ 819 hw->phy.smart_speed_active = FALSE; 820 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 821 autoneg_wait_to_complete); 822 823 out: 824 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 825 DEBUGOUT("Smartspeed has downgraded the link speed " 826 "from the maximum advertised\n"); 827 return status; 828 } 829 830 /** 831 * ixgbe_setup_mac_link_82599 - Set MAC link speed 832 * @hw: pointer to hardware structure 833 * @speed: new link speed 834 * @autoneg: TRUE if autonegotiation enabled 835 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 836 * 837 * Set the link speed in the AUTOC register and restarts link. 838 **/ 839 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 840 ixgbe_link_speed speed, bool autoneg, 841 bool autoneg_wait_to_complete) 842 { 843 s32 status = IXGBE_SUCCESS; 844 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 845 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 846 u32 start_autoc = autoc; 847 u32 orig_autoc = 0; 848 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 849 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 850 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 851 u32 links_reg; 852 u32 i; 853 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 854 855 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 856 857 /* Check to see if speed passed in is supported. */ 858 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 859 if (status != IXGBE_SUCCESS) 860 goto out; 861 862 speed &= link_capabilities; 863 864 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 865 status = IXGBE_ERR_LINK_SETUP; 866 goto out; 867 } 868 869 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 870 if (hw->mac.orig_link_settings_stored) 871 orig_autoc = hw->mac.orig_autoc; 872 else 873 orig_autoc = autoc; 874 875 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 876 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 877 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 878 /* Set KX4/KX/KR support according to speed requested */ 879 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 880 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 881 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 882 autoc |= IXGBE_AUTOC_KX4_SUPP; 883 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 884 (hw->phy.smart_speed_active == FALSE)) 885 autoc |= IXGBE_AUTOC_KR_SUPP; 886 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 887 autoc |= IXGBE_AUTOC_KX_SUPP; 888 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 889 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 890 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 891 /* Switch from 1G SFI to 10G SFI if requested */ 892 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 893 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 894 autoc &= ~IXGBE_AUTOC_LMS_MASK; 895 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 896 } 897 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 898 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 899 /* Switch from 10G SFI to 1G SFI if requested */ 900 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 901 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 902 autoc &= ~IXGBE_AUTOC_LMS_MASK; 903 if (autoneg) 904 autoc |= IXGBE_AUTOC_LMS_1G_AN; 905 else 906 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 907 } 908 } 909 910 if (autoc != start_autoc) { 911 /* Restart link */ 912 autoc |= IXGBE_AUTOC_AN_RESTART; 913 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 914 915 /* Only poll for autoneg to complete if specified to do so */ 916 if (autoneg_wait_to_complete) { 917 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 918 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 919 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 920 links_reg = 0; /*Just in case Autoneg time=0*/ 921 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 922 links_reg = 923 IXGBE_READ_REG(hw, IXGBE_LINKS); 924 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 925 break; 926 msec_delay(100); 927 } 928 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 929 status = 930 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 931 DEBUGOUT("Autoneg did not complete.\n"); 932 } 933 } 934 } 935 936 /* Add delay to filter out noises during initial link setup */ 937 msec_delay(50); 938 } 939 940 out: 941 return status; 942 } 943 944 /** 945 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 946 * @hw: pointer to hardware structure 947 * @speed: new link speed 948 * @autoneg: TRUE if autonegotiation enabled 949 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 950 * 951 * Restarts link on PHY and MAC based on settings passed in. 952 **/ 953 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 954 ixgbe_link_speed speed, 955 bool autoneg, 956 bool autoneg_wait_to_complete) 957 { 958 s32 status; 959 960 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 961 962 /* Setup the PHY according to input speed */ 963 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 964 autoneg_wait_to_complete); 965 /* Set up MAC */ 966 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 967 968 return status; 969 } 970 971 /** 972 * ixgbe_reset_hw_82599 - Perform hardware reset 973 * @hw: pointer to hardware structure 974 * 975 * Resets the hardware by resetting the transmit and receive units, masks 976 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 977 * reset. 978 **/ 979 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 980 { 981 s32 status = IXGBE_SUCCESS; 982 u32 ctrl; 983 u32 i; 984 u32 autoc; 985 u32 autoc2; 986 987 DEBUGFUNC("ixgbe_reset_hw_82599"); 988 989 /* Call adapter stop to disable tx/rx and clear interrupts */ 990 hw->mac.ops.stop_adapter(hw); 991 992 /* PHY ops must be identified and initialized prior to reset */ 993 994 /* Identify PHY and related function pointers */ 995 status = hw->phy.ops.init(hw); 996 997 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 998 goto reset_hw_out; 999 1000 /* Setup SFP module if there is one present. */ 1001 if (hw->phy.sfp_setup_needed) { 1002 status = hw->mac.ops.setup_sfp(hw); 1003 hw->phy.sfp_setup_needed = FALSE; 1004 } 1005 1006 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1007 goto reset_hw_out; 1008 1009 /* Reset PHY */ 1010 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) 1011 hw->phy.ops.reset(hw); 1012 1013 /* 1014 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 1015 * access and verify no pending requests before reset 1016 */ 1017 ixgbe_disable_pcie_master(hw); 1018 1019 mac_reset_top: 1020 /* 1021 * Issue global reset to the MAC. This needs to be a SW reset. 1022 * If link reset is used, it might reset the MAC when mng is using it 1023 */ 1024 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1025 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 1026 IXGBE_WRITE_FLUSH(hw); 1027 1028 /* Poll for reset bit to self-clear indicating reset is complete */ 1029 for (i = 0; i < 10; i++) { 1030 usec_delay(1); 1031 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1032 if (!(ctrl & IXGBE_CTRL_RST)) 1033 break; 1034 } 1035 if (ctrl & IXGBE_CTRL_RST) { 1036 status = IXGBE_ERR_RESET_FAILED; 1037 DEBUGOUT("Reset polling failed to complete.\n"); 1038 } 1039 1040 /* 1041 * Double resets are required for recovery from certain error 1042 * conditions. Between resets, it is necessary to stall to allow time 1043 * for any pending HW events to complete. We use 1usec since that is 1044 * what is needed for ixgbe_disable_pcie_master(). The second reset 1045 * then clears out any effects of those events. 1046 */ 1047 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1048 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1049 usec_delay(1); 1050 goto mac_reset_top; 1051 } 1052 1053 msec_delay(50); 1054 1055 /* 1056 * Store the original AUTOC/AUTOC2 values if they have not been 1057 * stored off yet. Otherwise restore the stored original 1058 * values since the reset operation sets back to defaults. 1059 */ 1060 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1061 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1062 if (hw->mac.orig_link_settings_stored == FALSE) { 1063 hw->mac.orig_autoc = autoc; 1064 hw->mac.orig_autoc2 = autoc2; 1065 hw->mac.orig_link_settings_stored = TRUE; 1066 } else { 1067 if (autoc != hw->mac.orig_autoc) 1068 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | 1069 IXGBE_AUTOC_AN_RESTART)); 1070 1071 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1072 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1073 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1074 autoc2 |= (hw->mac.orig_autoc2 & 1075 IXGBE_AUTOC2_UPPER_MASK); 1076 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1077 } 1078 } 1079 1080 /* Store the permanent mac address */ 1081 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1082 1083 /* 1084 * Store MAC address from RAR0, clear receive address registers, and 1085 * clear the multicast table. Also reset num_rar_entries to 128, 1086 * since we modify this value when programming the SAN MAC address. 1087 */ 1088 hw->mac.num_rar_entries = 128; 1089 hw->mac.ops.init_rx_addrs(hw); 1090 1091 /* Store the permanent SAN mac address */ 1092 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1093 1094 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1095 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1096 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1097 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1098 1099 /* Reserve the last RAR for the SAN MAC address */ 1100 hw->mac.num_rar_entries--; 1101 } 1102 1103 /* Store the alternative WWNN/WWPN prefix */ 1104 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1105 &hw->mac.wwpn_prefix); 1106 1107 reset_hw_out: 1108 return status; 1109 } 1110 1111 /** 1112 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1113 * @hw: pointer to hardware structure 1114 **/ 1115 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1116 { 1117 int i; 1118 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1119 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1120 1121 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); 1122 1123 /* 1124 * Before starting reinitialization process, 1125 * FDIRCMD.CMD must be zero. 1126 */ 1127 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1128 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1129 IXGBE_FDIRCMD_CMD_MASK)) 1130 break; 1131 usec_delay(10); 1132 } 1133 if (i >= IXGBE_FDIRCMD_CMD_POLL) { 1134 DEBUGOUT("Flow Director previous command isn't complete, " 1135 "aborting table re-initialization. \n"); 1136 return IXGBE_ERR_FDIR_REINIT_FAILED; 1137 } 1138 1139 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1140 IXGBE_WRITE_FLUSH(hw); 1141 /* 1142 * 82599 adapters flow director init flow cannot be restarted, 1143 * Workaround 82599 silicon errata by performing the following steps 1144 * before re-writing the FDIRCTRL control register with the same value. 1145 * - write 1 to bit 8 of FDIRCMD register & 1146 * - write 0 to bit 8 of FDIRCMD register 1147 */ 1148 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1149 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1150 IXGBE_FDIRCMD_CLEARHT)); 1151 IXGBE_WRITE_FLUSH(hw); 1152 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1153 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1154 ~IXGBE_FDIRCMD_CLEARHT)); 1155 IXGBE_WRITE_FLUSH(hw); 1156 /* 1157 * Clear FDIR Hash register to clear any leftover hashes 1158 * waiting to be programmed. 1159 */ 1160 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1161 IXGBE_WRITE_FLUSH(hw); 1162 1163 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1164 IXGBE_WRITE_FLUSH(hw); 1165 1166 /* Poll init-done after we write FDIRCTRL register */ 1167 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1168 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1169 IXGBE_FDIRCTRL_INIT_DONE) 1170 break; 1171 usec_delay(10); 1172 } 1173 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1174 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1175 return IXGBE_ERR_FDIR_REINIT_FAILED; 1176 } 1177 1178 /* Clear FDIR statistics registers (read to clear) */ 1179 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1180 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1181 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1182 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1183 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1184 1185 return IXGBE_SUCCESS; 1186 } 1187 1188 /** 1189 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1190 * @hw: pointer to hardware structure 1191 * @pballoc: which mode to allocate filters with 1192 **/ 1193 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) 1194 { 1195 u32 fdirctrl = 0; 1196 u32 pbsize; 1197 int i; 1198 1199 DEBUGFUNC("ixgbe_init_fdir_signature_82599"); 1200 1201 /* 1202 * Before enabling Flow Director, the Rx Packet Buffer size 1203 * must be reduced. The new value is the current size minus 1204 * flow director memory usage size. 1205 */ 1206 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); 1207 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 1208 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); 1209 1210 /* 1211 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1212 * intialized to zero for non DCB mode otherwise actual total RX PB 1213 * would be bigger than programmed and filter space would run into 1214 * the PB 0 region. 1215 */ 1216 for (i = 1; i < 8; i++) 1217 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 1218 1219 /* Send interrupt when 64 filters are left */ 1220 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; 1221 1222 /* Set the maximum length per hash bucket to 0xA filters */ 1223 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT; 1224 1225 switch (pballoc) { 1226 case IXGBE_FDIR_PBALLOC_64K: 1227 /* 8k - 1 signature filters */ 1228 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 1229 break; 1230 case IXGBE_FDIR_PBALLOC_128K: 1231 /* 16k - 1 signature filters */ 1232 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 1233 break; 1234 case IXGBE_FDIR_PBALLOC_256K: 1235 /* 32k - 1 signature filters */ 1236 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 1237 break; 1238 default: 1239 /* bad value */ 1240 return IXGBE_ERR_CONFIG; 1241 }; 1242 1243 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1244 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1245 1246 1247 /* Prime the keys for hashing */ 1248 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1249 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1250 1251 /* 1252 * Poll init-done after we write the register. Estimated times: 1253 * 10G: PBALLOC = 11b, timing is 60us 1254 * 1G: PBALLOC = 11b, timing is 600us 1255 * 100M: PBALLOC = 11b, timing is 6ms 1256 * 1257 * Multiple these timings by 4 if under full Rx load 1258 * 1259 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1260 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1261 * this might not finish in our poll time, but we can live with that 1262 * for now. 1263 */ 1264 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1265 IXGBE_WRITE_FLUSH(hw); 1266 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1267 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1268 IXGBE_FDIRCTRL_INIT_DONE) 1269 break; 1270 msec_delay(1); 1271 } 1272 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1273 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1274 1275 return IXGBE_SUCCESS; 1276 } 1277 1278 /** 1279 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1280 * @hw: pointer to hardware structure 1281 * @pballoc: which mode to allocate filters with 1282 **/ 1283 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) 1284 { 1285 u32 fdirctrl = 0; 1286 u32 pbsize; 1287 int i; 1288 1289 DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); 1290 1291 /* 1292 * Before enabling Flow Director, the Rx Packet Buffer size 1293 * must be reduced. The new value is the current size minus 1294 * flow director memory usage size. 1295 */ 1296 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); 1297 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 1298 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); 1299 1300 /* 1301 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1302 * intialized to zero for non DCB mode otherwise actual total RX PB 1303 * would be bigger than programmed and filter space would run into 1304 * the PB 0 region. 1305 */ 1306 for (i = 1; i < 8; i++) 1307 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 1308 1309 /* Send interrupt when 64 filters are left */ 1310 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; 1311 1312 /* Initialize the drop queue to Rx queue 127 */ 1313 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT); 1314 1315 switch (pballoc) { 1316 case IXGBE_FDIR_PBALLOC_64K: 1317 /* 2k - 1 perfect filters */ 1318 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 1319 break; 1320 case IXGBE_FDIR_PBALLOC_128K: 1321 /* 4k - 1 perfect filters */ 1322 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 1323 break; 1324 case IXGBE_FDIR_PBALLOC_256K: 1325 /* 8k - 1 perfect filters */ 1326 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 1327 break; 1328 default: 1329 /* bad value */ 1330 return IXGBE_ERR_CONFIG; 1331 }; 1332 1333 /* Turn perfect match filtering on */ 1334 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; 1335 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; 1336 1337 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1338 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1339 1340 /* Prime the keys for hashing */ 1341 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1342 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,IXGBE_ATR_SIGNATURE_HASH_KEY); 1343 1344 /* 1345 * Poll init-done after we write the register. Estimated times: 1346 * 10G: PBALLOC = 11b, timing is 60us 1347 * 1G: PBALLOC = 11b, timing is 600us 1348 * 100M: PBALLOC = 11b, timing is 6ms 1349 * 1350 * Multiple these timings by 4 if under full Rx load 1351 * 1352 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1353 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1354 * this might not finish in our poll time, but we can live with that 1355 * for now. 1356 */ 1357 1358 /* Set the maximum length per hash bucket to 0xA filters */ 1359 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT); 1360 1361 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1362 IXGBE_WRITE_FLUSH(hw); 1363 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1364 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1365 IXGBE_FDIRCTRL_INIT_DONE) 1366 break; 1367 msec_delay(1); 1368 } 1369 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1370 DEBUGOUT("Flow Director Perfect poll time exceeded!\n"); 1371 1372 return IXGBE_SUCCESS; 1373 } 1374 1375 /** 1376 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR 1377 * @stream: input bitstream to compute the hash on 1378 * @key: 32-bit hash key 1379 **/ 1380 u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, 1381 u32 key) 1382 { 1383 /* 1384 * The algorithm is as follows: 1385 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 1386 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] 1387 * and A[n] x B[n] is bitwise AND between same length strings 1388 * 1389 * K[n] is 16 bits, defined as: 1390 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] 1391 * for n modulo 32 < 15, K[n] = 1392 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] 1393 * 1394 * S[n] is 16 bits, defined as: 1395 * for n >= 15, S[n] = S[n:n - 15] 1396 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] 1397 * 1398 * To simplify for programming, the algorithm is implemented 1399 * in software this way: 1400 * 1401 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0] 1402 * 1403 * for (i = 0; i < 352; i+=32) 1404 * hi_hash_dword[31:0] ^= Stream[(i+31):i]; 1405 * 1406 * lo_hash_dword[15:0] ^= Stream[15:0]; 1407 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16]; 1408 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0]; 1409 * 1410 * hi_hash_dword[31:0] ^= Stream[351:320]; 1411 * 1412 * if(key[0]) 1413 * hash[15:0] ^= Stream[15:0]; 1414 * 1415 * for (i = 0; i < 16; i++) { 1416 * if (key[i]) 1417 * hash[15:0] ^= lo_hash_dword[(i+15):i]; 1418 * if (key[i + 16]) 1419 * hash[15:0] ^= hi_hash_dword[(i+15):i]; 1420 * } 1421 * 1422 */ 1423 __be32 common_hash_dword = 0; 1424 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1425 u32 hash_result = 0; 1426 u8 i; 1427 1428 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1429 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]); 1430 1431 /* generate common hash dword */ 1432 for (i = 10; i; i -= 2) 1433 common_hash_dword ^= atr_input->dword_stream[i] ^ 1434 atr_input->dword_stream[i - 1]; 1435 1436 hi_hash_dword = IXGBE_NTOHL(common_hash_dword); 1437 1438 /* low dword is word swapped version of common */ 1439 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1440 1441 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1442 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1443 1444 /* Process bits 0 and 16 */ 1445 if (key & 0x0001) hash_result ^= lo_hash_dword; 1446 if (key & 0x00010000) hash_result ^= hi_hash_dword; 1447 1448 /* 1449 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1450 * delay this because bit 0 of the stream should not be processed 1451 * so we do not add the vlan until after bit 0 was processed 1452 */ 1453 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1454 1455 1456 /* process the remaining 30 bits in the key 2 bits at a time */ 1457 for (i = 15; i; i-- ) { 1458 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i; 1459 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i; 1460 } 1461 1462 return hash_result & IXGBE_ATR_HASH_MASK; 1463 } 1464 1465 /* 1466 * These defines allow us to quickly generate all of the necessary instructions 1467 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1468 * for values 0 through 15 1469 */ 1470 #define IXGBE_ATR_COMMON_HASH_KEY \ 1471 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1472 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1473 do { \ 1474 u32 n = (_n); \ 1475 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1476 common_hash ^= lo_hash_dword >> n; \ 1477 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1478 bucket_hash ^= lo_hash_dword >> n; \ 1479 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1480 sig_hash ^= lo_hash_dword << (16 - n); \ 1481 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1482 common_hash ^= hi_hash_dword >> n; \ 1483 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1484 bucket_hash ^= hi_hash_dword >> n; \ 1485 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1486 sig_hash ^= hi_hash_dword << (16 - n); \ 1487 } while (0); 1488 1489 /** 1490 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1491 * @stream: input bitstream to compute the hash on 1492 * 1493 * This function is almost identical to the function above but contains 1494 * several optomizations such as unwinding all of the loops, letting the 1495 * compiler work out all of the conditional ifs since the keys are static 1496 * defines, and computing two keys at once since the hashed dword stream 1497 * will be the same for both keys. 1498 **/ 1499 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1500 union ixgbe_atr_hash_dword common) 1501 { 1502 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1503 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1504 1505 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1506 flow_vm_vlan = IXGBE_NTOHL(input.dword); 1507 1508 /* generate common hash dword */ 1509 hi_hash_dword = IXGBE_NTOHL(common.dword); 1510 1511 /* low dword is word swapped version of common */ 1512 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1513 1514 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1515 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1516 1517 /* Process bits 0 and 16 */ 1518 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1519 1520 /* 1521 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1522 * delay this because bit 0 of the stream should not be processed 1523 * so we do not add the vlan until after bit 0 was processed 1524 */ 1525 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1526 1527 /* Process remaining 30 bit of the key */ 1528 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1529 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1530 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1531 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1532 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1533 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1534 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1535 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1536 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1537 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1538 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1539 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1540 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1541 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1542 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1543 1544 /* combine common_hash result with signature and bucket hashes */ 1545 bucket_hash ^= common_hash; 1546 bucket_hash &= IXGBE_ATR_HASH_MASK; 1547 1548 sig_hash ^= common_hash << 16; 1549 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1550 1551 /* return completed signature hash */ 1552 return sig_hash ^ bucket_hash; 1553 } 1554 1555 /** 1556 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1557 * @hw: pointer to hardware structure 1558 * @stream: input bitstream 1559 * @queue: queue index to direct traffic to 1560 **/ 1561 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1562 union ixgbe_atr_hash_dword input, 1563 union ixgbe_atr_hash_dword common, 1564 u8 queue) 1565 { 1566 u64 fdirhashcmd; 1567 u32 fdircmd; 1568 1569 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); 1570 1571 /* 1572 * Get the flow_type in order to program FDIRCMD properly 1573 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1574 */ 1575 switch (input.formatted.flow_type) { 1576 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1577 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1578 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1579 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1580 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1581 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1582 break; 1583 default: 1584 DEBUGOUT(" Error on flow type input\n"); 1585 return IXGBE_ERR_CONFIG; 1586 } 1587 1588 /* configure FDIRCMD register */ 1589 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1590 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1591 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1592 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1593 1594 /* 1595 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1596 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1597 */ 1598 fdirhashcmd = (u64)fdircmd << 32; 1599 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1600 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1601 1602 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1603 1604 return IXGBE_SUCCESS; 1605 } 1606 1607 /** 1608 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1609 * @input_mask: mask to be bit swapped 1610 * 1611 * The source and destination port masks for flow director are bit swapped 1612 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1613 * generate a correctly swapped value we need to bit swap the mask and that 1614 * is what is accomplished by this function. 1615 **/ 1616 static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks) 1617 { 1618 u32 mask = IXGBE_NTOHS(input_masks->dst_port_mask); 1619 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1620 mask |= IXGBE_NTOHS(input_masks->src_port_mask); 1621 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1622 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1623 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1624 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1625 } 1626 1627 /* 1628 * These two macros are meant to address the fact that we have registers 1629 * that are either all or in part big-endian. As a result on big-endian 1630 * systems we will end up byte swapping the value to little-endian before 1631 * it is byte swapped again and written to the hardware in the original 1632 * big-endian format. 1633 */ 1634 #define IXGBE_STORE_AS_BE32(_value) \ 1635 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1636 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1637 1638 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1639 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value))) 1640 1641 #define IXGBE_STORE_AS_BE16(_value) \ 1642 (((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1643 1644 1645 /** 1646 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 1647 * @hw: pointer to hardware structure 1648 * @input: input bitstream 1649 * @input_masks: masks for the input bitstream 1650 * @soft_id: software index for the filters 1651 * @queue: queue index to direct traffic to 1652 * 1653 * Note that the caller to this function must lock before calling, since the 1654 * hardware writes must be protected from one another. 1655 **/ 1656 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 1657 union ixgbe_atr_input *input, 1658 struct ixgbe_atr_input_masks *input_masks, 1659 u16 soft_id, u8 queue) 1660 { 1661 u32 fdirhash; 1662 u32 fdircmd; 1663 u32 fdirport, fdirtcpm; 1664 u32 fdirvlan; 1665 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */ 1666 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX | 1667 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6; 1668 1669 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); 1670 1671 /* 1672 * Check flow_type formatting, and bail out before we touch the hardware 1673 * if there's a configuration issue 1674 */ 1675 switch (input->formatted.flow_type) { 1676 case IXGBE_ATR_FLOW_TYPE_IPV4: 1677 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */ 1678 fdirm |= IXGBE_FDIRM_L4P; 1679 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1680 if (input_masks->dst_port_mask || input_masks->src_port_mask) { 1681 DEBUGOUT(" Error on src/dst port mask\n"); 1682 return IXGBE_ERR_CONFIG; 1683 } 1684 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1685 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1686 break; 1687 default: 1688 DEBUGOUT(" Error on flow type input\n"); 1689 return IXGBE_ERR_CONFIG; 1690 } 1691 1692 /* 1693 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1694 * are zero, then assume a full mask for that field. Also assume that 1695 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1696 * cannot be masked out in this implementation. 1697 * 1698 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1699 * point in time. 1700 */ 1701 1702 /* Program FDIRM */ 1703 switch (IXGBE_NTOHS(input_masks->vlan_id_mask) & 0xEFFF) { 1704 case 0xEFFF: 1705 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */ 1706 fdirm &= ~IXGBE_FDIRM_VLANID; 1707 case 0xE000: 1708 /* Unmask VLAN prio - bit 1 */ 1709 fdirm &= ~IXGBE_FDIRM_VLANP; 1710 break; 1711 case 0x0FFF: 1712 /* Unmask VLAN ID - bit 0 */ 1713 fdirm &= ~IXGBE_FDIRM_VLANID; 1714 break; 1715 case 0x0000: 1716 /* do nothing, vlans already masked */ 1717 break; 1718 default: 1719 DEBUGOUT(" Error on VLAN mask\n"); 1720 return IXGBE_ERR_CONFIG; 1721 } 1722 1723 if (input_masks->flex_mask & 0xFFFF) { 1724 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) { 1725 DEBUGOUT(" Error on flexible byte mask\n"); 1726 return IXGBE_ERR_CONFIG; 1727 } 1728 /* Unmask Flex Bytes - bit 4 */ 1729 fdirm &= ~IXGBE_FDIRM_FLEX; 1730 } 1731 1732 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1733 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1734 1735 /* store the TCP/UDP port masks, bit reversed from port layout */ 1736 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks); 1737 1738 /* write both the same so that UDP and TCP use the same mask */ 1739 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1740 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1741 1742 /* store source and destination IP masks (big-enian) */ 1743 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1744 ~input_masks->src_ip_mask[0]); 1745 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1746 ~input_masks->dst_ip_mask[0]); 1747 1748 /* Apply masks to input data */ 1749 input->formatted.vlan_id &= input_masks->vlan_id_mask; 1750 input->formatted.flex_bytes &= input_masks->flex_mask; 1751 input->formatted.src_port &= input_masks->src_port_mask; 1752 input->formatted.dst_port &= input_masks->dst_port_mask; 1753 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0]; 1754 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0]; 1755 1756 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1757 fdirvlan = 1758 IXGBE_STORE_AS_BE16(IXGBE_NTOHS(input->formatted.flex_bytes)); 1759 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1760 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); 1761 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1762 1763 /* record source and destination port (little-endian)*/ 1764 fdirport = IXGBE_NTOHS(input->formatted.dst_port); 1765 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1766 fdirport |= IXGBE_NTOHS(input->formatted.src_port); 1767 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1768 1769 /* record the first 32 bits of the destination address (big-endian) */ 1770 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1771 1772 /* record the source address (big-endian) */ 1773 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1774 1775 /* configure FDIRCMD register */ 1776 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1777 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1778 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1779 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1780 1781 /* we only want the bucket hash so drop the upper 16 bits */ 1782 fdirhash = ixgbe_atr_compute_hash_82599(input, 1783 IXGBE_ATR_BUCKET_HASH_KEY); 1784 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1785 1786 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1787 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1788 1789 return IXGBE_SUCCESS; 1790 } 1791 1792 /** 1793 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1794 * @hw: pointer to hardware structure 1795 * @reg: analog register to read 1796 * @val: read value 1797 * 1798 * Performs read operation to Omer analog register specified. 1799 **/ 1800 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1801 { 1802 u32 core_ctl; 1803 1804 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 1805 1806 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1807 (reg << 8)); 1808 IXGBE_WRITE_FLUSH(hw); 1809 usec_delay(10); 1810 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1811 *val = (u8)core_ctl; 1812 1813 return IXGBE_SUCCESS; 1814 } 1815 1816 /** 1817 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1818 * @hw: pointer to hardware structure 1819 * @reg: atlas register to write 1820 * @val: value to write 1821 * 1822 * Performs write operation to Omer analog register specified. 1823 **/ 1824 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1825 { 1826 u32 core_ctl; 1827 1828 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 1829 1830 core_ctl = (reg << 8) | val; 1831 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1832 IXGBE_WRITE_FLUSH(hw); 1833 usec_delay(10); 1834 1835 return IXGBE_SUCCESS; 1836 } 1837 1838 /** 1839 * ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx 1840 * @hw: pointer to hardware structure 1841 * 1842 * Starts the hardware using the generic start_hw function 1843 * and the generation start_hw function. 1844 * Then performs revision-specific operations, if any. 1845 **/ 1846 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw) 1847 { 1848 s32 ret_val = IXGBE_SUCCESS; 1849 1850 DEBUGFUNC("ixgbe_start_hw_rev_1__82599"); 1851 1852 ret_val = ixgbe_start_hw_generic(hw); 1853 if (ret_val != IXGBE_SUCCESS) 1854 goto out; 1855 1856 ret_val = ixgbe_start_hw_gen2(hw); 1857 if (ret_val != IXGBE_SUCCESS) 1858 goto out; 1859 1860 /* We need to run link autotry after the driver loads */ 1861 hw->mac.autotry_restart = TRUE; 1862 1863 if (ret_val == IXGBE_SUCCESS) 1864 ret_val = ixgbe_verify_fw_version_82599(hw); 1865 out: 1866 return ret_val; 1867 } 1868 1869 /** 1870 * ixgbe_identify_phy_82599 - Get physical layer module 1871 * @hw: pointer to hardware structure 1872 * 1873 * Determines the physical layer module found on the current adapter. 1874 * If PHY already detected, maintains current PHY type in hw struct, 1875 * otherwise executes the PHY detection routine. 1876 **/ 1877 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1878 { 1879 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1880 1881 DEBUGFUNC("ixgbe_identify_phy_82599"); 1882 1883 /* Detect PHY if not unknown - returns success if already detected. */ 1884 status = ixgbe_identify_phy_generic(hw); 1885 if (status != IXGBE_SUCCESS) { 1886 /* 82599 10GBASE-T requires an external PHY */ 1887 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1888 goto out; 1889 else 1890 status = ixgbe_identify_sfp_module_generic(hw); 1891 } 1892 1893 /* Set PHY type none if no PHY detected */ 1894 if (hw->phy.type == ixgbe_phy_unknown) { 1895 hw->phy.type = ixgbe_phy_none; 1896 status = IXGBE_SUCCESS; 1897 } 1898 1899 /* Return error if SFP module has been detected but is not supported */ 1900 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1901 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1902 1903 out: 1904 return status; 1905 } 1906 1907 /** 1908 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1909 * @hw: pointer to hardware structure 1910 * 1911 * Determines physical layer capabilities of the current configuration. 1912 **/ 1913 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1914 { 1915 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1916 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1917 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1918 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1919 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1920 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1921 u16 ext_ability = 0; 1922 u8 comp_codes_10g = 0; 1923 u8 comp_codes_1g = 0; 1924 1925 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 1926 1927 hw->phy.ops.identify(hw); 1928 1929 switch (hw->phy.type) { 1930 case ixgbe_phy_tn: 1931 case ixgbe_phy_aq: 1932 case ixgbe_phy_cu_unknown: 1933 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1934 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1935 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1936 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1937 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1938 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1939 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1940 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1941 goto out; 1942 default: 1943 break; 1944 } 1945 1946 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1947 case IXGBE_AUTOC_LMS_1G_AN: 1948 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1949 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1950 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1951 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1952 goto out; 1953 } else 1954 /* SFI mode so read SFP module */ 1955 goto sfp_check; 1956 break; 1957 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1958 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 1959 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1960 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 1961 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1962 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 1963 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 1964 goto out; 1965 break; 1966 case IXGBE_AUTOC_LMS_10G_SERIAL: 1967 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 1968 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1969 goto out; 1970 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 1971 goto sfp_check; 1972 break; 1973 case IXGBE_AUTOC_LMS_KX4_KX_KR: 1974 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 1975 if (autoc & IXGBE_AUTOC_KX_SUPP) 1976 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1977 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1978 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1979 if (autoc & IXGBE_AUTOC_KR_SUPP) 1980 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1981 goto out; 1982 break; 1983 default: 1984 goto out; 1985 break; 1986 } 1987 1988 sfp_check: 1989 /* SFP check must be done last since DA modules are sometimes used to 1990 * test KR mode - we need to id KR mode correctly before SFP module. 1991 * Call identify_sfp because the pluggable module may have changed */ 1992 hw->phy.ops.identify_sfp(hw); 1993 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1994 goto out; 1995 1996 switch (hw->phy.type) { 1997 case ixgbe_phy_sfp_passive_tyco: 1998 case ixgbe_phy_sfp_passive_unknown: 1999 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 2000 break; 2001 case ixgbe_phy_sfp_ftl_active: 2002 case ixgbe_phy_sfp_active_unknown: 2003 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 2004 break; 2005 case ixgbe_phy_sfp_avago: 2006 case ixgbe_phy_sfp_ftl: 2007 case ixgbe_phy_sfp_intel: 2008 case ixgbe_phy_sfp_unknown: 2009 hw->phy.ops.read_i2c_eeprom(hw, 2010 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 2011 hw->phy.ops.read_i2c_eeprom(hw, 2012 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 2013 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 2014 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 2015 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 2016 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 2017 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 2018 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 2019 break; 2020 default: 2021 break; 2022 } 2023 2024 out: 2025 return physical_layer; 2026 } 2027 2028 /** 2029 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2030 * @hw: pointer to hardware structure 2031 * @regval: register value to write to RXCTRL 2032 * 2033 * Enables the Rx DMA unit for 82599 2034 **/ 2035 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2036 { 2037 #define IXGBE_MAX_SECRX_POLL 30 2038 int i; 2039 int secrxreg; 2040 2041 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 2042 2043 /* 2044 * Workaround for 82599 silicon errata when enabling the Rx datapath. 2045 * If traffic is incoming before we enable the Rx unit, it could hang 2046 * the Rx DMA unit. Therefore, make sure the security engine is 2047 * completely disabled prior to enabling the Rx unit. 2048 */ 2049 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2050 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2051 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2052 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2053 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2054 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2055 break; 2056 else 2057 /* Use interrupt-safe sleep just in case */ 2058 usec_delay(10); 2059 } 2060 2061 /* For informational purposes only */ 2062 if (i >= IXGBE_MAX_SECRX_POLL) 2063 DEBUGOUT("Rx unit being enabled before security " 2064 "path fully disabled. Continuing with init.\n"); 2065 2066 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2067 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2068 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2069 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2070 IXGBE_WRITE_FLUSH(hw); 2071 2072 return IXGBE_SUCCESS; 2073 } 2074 2075 /** 2076 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 2077 * @hw: pointer to hardware structure 2078 * 2079 * Verifies that installed the firmware version is 0.6 or higher 2080 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2081 * 2082 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2083 * if the FW version is not supported. 2084 **/ 2085 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2086 { 2087 s32 status = IXGBE_ERR_EEPROM_VERSION; 2088 u16 fw_offset, fw_ptp_cfg_offset; 2089 u16 fw_version = 0; 2090 2091 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 2092 2093 /* firmware check is only necessary for SFI devices */ 2094 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2095 status = IXGBE_SUCCESS; 2096 goto fw_version_out; 2097 } 2098 2099 /* get the offset to the Firmware Module block */ 2100 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2101 2102 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2103 goto fw_version_out; 2104 2105 /* get the offset to the Pass Through Patch Configuration block */ 2106 hw->eeprom.ops.read(hw, (fw_offset + 2107 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 2108 &fw_ptp_cfg_offset); 2109 2110 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2111 goto fw_version_out; 2112 2113 /* get the firmware version */ 2114 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 2115 IXGBE_FW_PATCH_VERSION_4), 2116 &fw_version); 2117 2118 if (fw_version > 0x5) 2119 status = IXGBE_SUCCESS; 2120 2121 fw_version_out: 2122 return status; 2123 } 2124 2125 /** 2126 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2127 * @hw: pointer to hardware structure 2128 * 2129 * Returns TRUE if the LESM FW module is present and enabled. Otherwise 2130 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. 2131 **/ 2132 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2133 { 2134 bool lesm_enabled = FALSE; 2135 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2136 s32 status; 2137 2138 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 2139 2140 /* get the offset to the Firmware Module block */ 2141 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2142 2143 if ((status != IXGBE_SUCCESS) || 2144 (fw_offset == 0) || (fw_offset == 0xFFFF)) 2145 goto out; 2146 2147 /* get the offset to the LESM Parameters block */ 2148 status = hw->eeprom.ops.read(hw, (fw_offset + 2149 IXGBE_FW_LESM_PARAMETERS_PTR), 2150 &fw_lesm_param_offset); 2151 2152 if ((status != IXGBE_SUCCESS) || 2153 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2154 goto out; 2155 2156 /* get the lesm state word */ 2157 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2158 IXGBE_FW_LESM_STATE_1), 2159 &fw_lesm_state); 2160 2161 if ((status == IXGBE_SUCCESS) && 2162 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2163 lesm_enabled = TRUE; 2164 2165 out: 2166 return lesm_enabled; 2167 } 2168 2169 2170
Indexes created Mon Sep 29 21:09:56 GMT 2025