ixgbe_82599.c revision 1.4
1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.6 2011/01/19 19:36:27 jfv Exp $*/ 34 /*$NetBSD: ixgbe_82599.c,v 1.4 2015/02/24 14:14:50 msaitoh Exp $*/ 35 36 #include "ixgbe_type.h" 37 #include "ixgbe_api.h" 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 41 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); 42 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 43 ixgbe_link_speed *speed, 44 bool *autoneg); 45 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); 46 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 47 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 48 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 49 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, bool autoneg, 51 bool autoneg_wait_to_complete); 52 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 53 ixgbe_link_speed speed, bool autoneg, 54 bool autoneg_wait_to_complete); 55 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 56 bool autoneg_wait_to_complete); 57 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 58 ixgbe_link_speed speed, 59 bool autoneg, 60 bool autoneg_wait_to_complete); 61 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 62 ixgbe_link_speed speed, 63 bool autoneg, 64 bool autoneg_wait_to_complete); 65 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); 66 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); 67 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw); 68 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val); 69 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val); 70 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw); 71 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw); 72 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); 73 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); 74 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval); 75 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 76 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 77 78 79 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 80 { 81 struct ixgbe_mac_info *mac = &hw->mac; 82 83 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 84 85 /* enable the laser control functions for SFP+ fiber */ 86 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { 87 mac->ops.disable_tx_laser = 88 &ixgbe_disable_tx_laser_multispeed_fiber; 89 mac->ops.enable_tx_laser = 90 &ixgbe_enable_tx_laser_multispeed_fiber; 91 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 92 93 } else { 94 mac->ops.disable_tx_laser = NULL; 95 mac->ops.enable_tx_laser = NULL; 96 mac->ops.flap_tx_laser = NULL; 97 } 98 99 if (hw->phy.multispeed_fiber) { 100 /* Set up dual speed SFP+ support */ 101 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 102 } else { 103 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 104 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 105 hw->phy.smart_speed == ixgbe_smart_speed_on) && 106 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 107 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 108 } else { 109 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 110 } 111 } 112 } 113 114 /** 115 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 116 * @hw: pointer to hardware structure 117 * 118 * Initialize any function pointers that were not able to be 119 * set during init_shared_code because the PHY/SFP type was 120 * not known. Perform the SFP init if necessary. 121 * 122 **/ 123 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 124 { 125 struct ixgbe_mac_info *mac = &hw->mac; 126 struct ixgbe_phy_info *phy = &hw->phy; 127 s32 ret_val = IXGBE_SUCCESS; 128 129 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 130 131 /* Identify the PHY or SFP module */ 132 ret_val = phy->ops.identify(hw); 133 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 134 goto init_phy_ops_out; 135 136 /* Setup function pointers based on detected SFP module and speeds */ 137 ixgbe_init_mac_link_ops_82599(hw); 138 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 139 hw->phy.ops.reset = NULL; 140 141 /* If copper media, overwrite with copper function pointers */ 142 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 143 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 144 mac->ops.get_link_capabilities = 145 &ixgbe_get_copper_link_capabilities_generic; 146 } 147 148 /* Set necessary function pointers based on phy type */ 149 switch (hw->phy.type) { 150 case ixgbe_phy_tn: 151 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 152 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 153 phy->ops.get_firmware_version = 154 &ixgbe_get_phy_firmware_version_tnx; 155 break; 156 case ixgbe_phy_aq: 157 phy->ops.get_firmware_version = 158 &ixgbe_get_phy_firmware_version_generic; 159 break; 160 default: 161 break; 162 } 163 init_phy_ops_out: 164 return ret_val; 165 } 166 167 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 168 { 169 s32 ret_val = IXGBE_SUCCESS; 170 u32 reg_anlp1 = 0; 171 u32 i = 0; 172 u16 list_offset, data_offset, data_value; 173 174 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 175 176 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 177 ixgbe_init_mac_link_ops_82599(hw); 178 179 hw->phy.ops.reset = NULL; 180 181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 182 &data_offset); 183 if (ret_val != IXGBE_SUCCESS) 184 goto setup_sfp_out; 185 186 /* PHY config will finish before releasing the semaphore */ 187 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 188 if (ret_val != IXGBE_SUCCESS) { 189 ret_val = IXGBE_ERR_SWFW_SYNC; 190 goto setup_sfp_out; 191 } 192 193 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 194 while (data_value != 0xffff) { 195 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 196 IXGBE_WRITE_FLUSH(hw); 197 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 198 } 199 200 /* Release the semaphore */ 201 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 202 /* Delay obtaining semaphore again to allow FW access */ 203 msec_delay(hw->eeprom.semaphore_delay); 204 205 /* Now restart DSP by setting Restart_AN and clearing LMS */ 206 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw, 207 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) | 208 IXGBE_AUTOC_AN_RESTART)); 209 210 /* Wait for AN to leave state 0 */ 211 for (i = 0; i < 10; i++) { 212 msec_delay(4); 213 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1); 214 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK) 215 break; 216 } 217 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) { 218 DEBUGOUT("sfp module setup not complete\n"); 219 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 220 goto setup_sfp_out; 221 } 222 223 /* Restart DSP by setting Restart_AN and return to SFI mode */ 224 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw, 225 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL | 226 IXGBE_AUTOC_AN_RESTART)); 227 } 228 229 setup_sfp_out: 230 return ret_val; 231 } 232 233 /** 234 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 235 * @hw: pointer to hardware structure 236 * 237 * Initialize the function pointers and assign the MAC type for 82599. 238 * Does not touch the hardware. 239 **/ 240 241 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) 242 { 243 struct ixgbe_mac_info *mac = &hw->mac; 244 struct ixgbe_phy_info *phy = &hw->phy; 245 s32 ret_val; 246 247 DEBUGFUNC("ixgbe_init_ops_82599"); 248 249 ret_val = ixgbe_init_phy_ops_generic(hw); 250 ret_val = ixgbe_init_ops_generic(hw); 251 252 /* PHY */ 253 phy->ops.identify = &ixgbe_identify_phy_82599; 254 phy->ops.init = &ixgbe_init_phy_ops_82599; 255 256 /* MAC */ 257 mac->ops.reset_hw = &ixgbe_reset_hw_82599; 258 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 259 mac->ops.get_media_type = &ixgbe_get_media_type_82599; 260 mac->ops.get_supported_physical_layer = 261 &ixgbe_get_supported_physical_layer_82599; 262 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; 263 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; 264 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; 265 mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599; 266 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 267 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 268 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 269 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 270 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; 271 272 /* RAR, Multicast, VLAN */ 273 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 274 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 275 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 276 mac->rar_highwater = 1; 277 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 278 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 279 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 280 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599; 281 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; 282 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; 283 284 /* Link */ 285 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599; 286 mac->ops.check_link = &ixgbe_check_mac_link_generic; 287 ixgbe_init_mac_link_ops_82599(hw); 288 289 mac->mcft_size = 128; 290 mac->vft_size = 128; 291 mac->num_rar_entries = 128; 292 mac->rx_pb_size = 512; 293 mac->max_tx_queues = 128; 294 mac->max_rx_queues = 128; 295 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 296 297 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 298 299 return ret_val; 300 } 301 302 /** 303 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 304 * @hw: pointer to hardware structure 305 * @speed: pointer to link speed 306 * @negotiation: TRUE when autoneg or autotry is enabled 307 * 308 * Determines the link capabilities by reading the AUTOC register. 309 **/ 310 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 311 ixgbe_link_speed *speed, 312 bool *negotiation) 313 { 314 s32 status = IXGBE_SUCCESS; 315 u32 autoc = 0; 316 317 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 318 319 320 /* Check if 1G SFP module. */ 321 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 322 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) { 323 *speed = IXGBE_LINK_SPEED_1GB_FULL; 324 *negotiation = TRUE; 325 goto out; 326 } 327 328 /* 329 * Determine link capabilities based on the stored value of AUTOC, 330 * which represents EEPROM defaults. If AUTOC value has not 331 * been stored, use the current register values. 332 */ 333 if (hw->mac.orig_link_settings_stored) 334 autoc = hw->mac.orig_autoc; 335 else 336 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 337 338 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 339 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 340 *speed = IXGBE_LINK_SPEED_1GB_FULL; 341 *negotiation = FALSE; 342 break; 343 344 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 345 *speed = IXGBE_LINK_SPEED_10GB_FULL; 346 *negotiation = FALSE; 347 break; 348 349 case IXGBE_AUTOC_LMS_1G_AN: 350 *speed = IXGBE_LINK_SPEED_1GB_FULL; 351 *negotiation = TRUE; 352 break; 353 354 case IXGBE_AUTOC_LMS_10G_SERIAL: 355 *speed = IXGBE_LINK_SPEED_10GB_FULL; 356 *negotiation = FALSE; 357 break; 358 359 case IXGBE_AUTOC_LMS_KX4_KX_KR: 360 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 361 *speed = IXGBE_LINK_SPEED_UNKNOWN; 362 if (autoc & IXGBE_AUTOC_KR_SUPP) 363 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 364 if (autoc & IXGBE_AUTOC_KX4_SUPP) 365 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 366 if (autoc & IXGBE_AUTOC_KX_SUPP) 367 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 368 *negotiation = TRUE; 369 break; 370 371 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 372 *speed = IXGBE_LINK_SPEED_100_FULL; 373 if (autoc & IXGBE_AUTOC_KR_SUPP) 374 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 375 if (autoc & IXGBE_AUTOC_KX4_SUPP) 376 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 377 if (autoc & IXGBE_AUTOC_KX_SUPP) 378 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 379 *negotiation = TRUE; 380 break; 381 382 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 383 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 384 *negotiation = FALSE; 385 break; 386 387 default: 388 status = IXGBE_ERR_LINK_SETUP; 389 goto out; 390 break; 391 } 392 393 if (hw->phy.multispeed_fiber) { 394 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 395 IXGBE_LINK_SPEED_1GB_FULL; 396 *negotiation = TRUE; 397 } 398 399 out: 400 return status; 401 } 402 403 /** 404 * ixgbe_get_media_type_82599 - Get media type 405 * @hw: pointer to hardware structure 406 * 407 * Returns the media type (fiber, copper, backplane) 408 **/ 409 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 410 { 411 enum ixgbe_media_type media_type; 412 413 DEBUGFUNC("ixgbe_get_media_type_82599"); 414 415 /* Detect if there is a copper PHY attached. */ 416 switch (hw->phy.type) { 417 case ixgbe_phy_cu_unknown: 418 case ixgbe_phy_tn: 419 case ixgbe_phy_aq: 420 media_type = ixgbe_media_type_copper; 421 goto out; 422 default: 423 break; 424 } 425 426 switch (hw->device_id) { 427 case IXGBE_DEV_ID_82599_KX4: 428 case IXGBE_DEV_ID_82599_KX4_MEZZ: 429 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 430 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 431 case IXGBE_DEV_ID_82599_XAUI_LOM: 432 /* Default device ID is mezzanine card KX/KX4 */ 433 media_type = ixgbe_media_type_backplane; 434 break; 435 case IXGBE_DEV_ID_82599_SFP: 436 case IXGBE_DEV_ID_82599_SFP_FCOE: 437 case IXGBE_DEV_ID_82599_SFP_SF2: 438 media_type = ixgbe_media_type_fiber; 439 break; 440 case IXGBE_DEV_ID_82599_CX4: 441 media_type = ixgbe_media_type_cx4; 442 break; 443 case IXGBE_DEV_ID_82599_T3_LOM: 444 media_type = ixgbe_media_type_copper; 445 break; 446 default: 447 media_type = ixgbe_media_type_unknown; 448 break; 449 } 450 out: 451 return media_type; 452 } 453 454 /** 455 * ixgbe_start_mac_link_82599 - Setup MAC link settings 456 * @hw: pointer to hardware structure 457 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 458 * 459 * Configures link settings based on values in the ixgbe_hw struct. 460 * Restarts the link. Performs autonegotiation if needed. 461 **/ 462 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 463 bool autoneg_wait_to_complete) 464 { 465 u32 autoc_reg; 466 u32 links_reg; 467 u32 i; 468 s32 status = IXGBE_SUCCESS; 469 470 DEBUGFUNC("ixgbe_start_mac_link_82599"); 471 472 473 /* Restart link */ 474 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 475 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 476 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 477 478 /* Only poll for autoneg to complete if specified to do so */ 479 if (autoneg_wait_to_complete) { 480 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 481 IXGBE_AUTOC_LMS_KX4_KX_KR || 482 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 483 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 484 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 485 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 486 links_reg = 0; /* Just in case Autoneg time = 0 */ 487 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 488 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 489 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 490 break; 491 msec_delay(100); 492 } 493 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 494 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 495 DEBUGOUT("Autoneg did not complete.\n"); 496 } 497 } 498 } 499 500 /* Add delay to filter out noises during initial link setup */ 501 msec_delay(50); 502 503 return status; 504 } 505 506 /** 507 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 508 * @hw: pointer to hardware structure 509 * 510 * The base drivers may require better control over SFP+ module 511 * PHY states. This includes selectively shutting down the Tx 512 * laser on the PHY, effectively halting physical link. 513 **/ 514 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 515 { 516 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 517 518 /* Disable tx laser; allow 100us to go dark per spec */ 519 esdp_reg |= IXGBE_ESDP_SDP3; 520 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 521 IXGBE_WRITE_FLUSH(hw); 522 usec_delay(100); 523 } 524 525 /** 526 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 527 * @hw: pointer to hardware structure 528 * 529 * The base drivers may require better control over SFP+ module 530 * PHY states. This includes selectively turning on the Tx 531 * laser on the PHY, effectively starting physical link. 532 **/ 533 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 534 { 535 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 536 537 /* Enable tx laser; allow 100ms to light up */ 538 esdp_reg &= ~IXGBE_ESDP_SDP3; 539 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 540 IXGBE_WRITE_FLUSH(hw); 541 msec_delay(100); 542 } 543 544 /** 545 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 546 * @hw: pointer to hardware structure 547 * 548 * When the driver changes the link speeds that it can support, 549 * it sets autotry_restart to TRUE to indicate that we need to 550 * initiate a new autotry session with the link partner. To do 551 * so, we set the speed then disable and re-enable the tx laser, to 552 * alert the link partner that it also needs to restart autotry on its 553 * end. This is consistent with TRUE clause 37 autoneg, which also 554 * involves a loss of signal. 555 **/ 556 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 557 { 558 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 559 560 if (hw->mac.autotry_restart) { 561 ixgbe_disable_tx_laser_multispeed_fiber(hw); 562 ixgbe_enable_tx_laser_multispeed_fiber(hw); 563 hw->mac.autotry_restart = FALSE; 564 } 565 } 566 567 /** 568 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 569 * @hw: pointer to hardware structure 570 * @speed: new link speed 571 * @autoneg: TRUE if autonegotiation enabled 572 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 573 * 574 * Set the link speed in the AUTOC register and restarts link. 575 **/ 576 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 577 ixgbe_link_speed speed, bool autoneg, 578 bool autoneg_wait_to_complete) 579 { 580 s32 status = IXGBE_SUCCESS; 581 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 582 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 583 u32 speedcnt = 0; 584 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 585 u32 i = 0; 586 bool link_up = FALSE; 587 bool negotiation; 588 589 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 590 591 /* Mask off requested but non-supported speeds */ 592 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation); 593 if (status != IXGBE_SUCCESS) 594 return status; 595 596 speed &= link_speed; 597 598 /* 599 * Try each speed one by one, highest priority first. We do this in 600 * software because 10gb fiber doesn't support speed autonegotiation. 601 */ 602 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 603 speedcnt++; 604 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 605 606 /* If we already have link at this speed, just jump out */ 607 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 608 if (status != IXGBE_SUCCESS) 609 return status; 610 611 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 612 goto out; 613 614 /* Set the module link speed */ 615 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 616 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 617 IXGBE_WRITE_FLUSH(hw); 618 619 /* Allow module to change analog characteristics (1G->10G) */ 620 msec_delay(40); 621 622 status = ixgbe_setup_mac_link_82599(hw, 623 IXGBE_LINK_SPEED_10GB_FULL, 624 autoneg, 625 autoneg_wait_to_complete); 626 if (status != IXGBE_SUCCESS) 627 return status; 628 629 /* Flap the tx laser if it has not already been done */ 630 ixgbe_flap_tx_laser(hw); 631 632 /* 633 * Wait for the controller to acquire link. Per IEEE 802.3ap, 634 * Section 73.10.2, we may have to wait up to 500ms if KR is 635 * attempted. 82599 uses the same timing for 10g SFI. 636 */ 637 for (i = 0; i < 5; i++) { 638 /* Wait for the link partner to also set speed */ 639 msec_delay(100); 640 641 /* If we have link, just jump out */ 642 status = ixgbe_check_link(hw, &link_speed, 643 &link_up, FALSE); 644 if (status != IXGBE_SUCCESS) 645 return status; 646 647 if (link_up) 648 goto out; 649 } 650 } 651 652 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 653 speedcnt++; 654 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 655 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 656 657 /* If we already have link at this speed, just jump out */ 658 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 659 if (status != IXGBE_SUCCESS) 660 return status; 661 662 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 663 goto out; 664 665 /* Set the module link speed */ 666 esdp_reg &= ~IXGBE_ESDP_SDP5; 667 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 668 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 669 IXGBE_WRITE_FLUSH(hw); 670 671 /* Allow module to change analog characteristics (10G->1G) */ 672 msec_delay(40); 673 674 status = ixgbe_setup_mac_link_82599(hw, 675 IXGBE_LINK_SPEED_1GB_FULL, 676 autoneg, 677 autoneg_wait_to_complete); 678 if (status != IXGBE_SUCCESS) 679 return status; 680 681 /* Flap the tx laser if it has not already been done */ 682 ixgbe_flap_tx_laser(hw); 683 684 /* Wait for the link partner to also set speed */ 685 msec_delay(100); 686 687 /* If we have link, just jump out */ 688 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 689 if (status != IXGBE_SUCCESS) 690 return status; 691 692 if (link_up) 693 goto out; 694 } 695 696 /* 697 * We didn't get link. Configure back to the highest speed we tried, 698 * (if there was more than one). We call ourselves back with just the 699 * single highest speed that the user requested. 700 */ 701 if (speedcnt > 1) 702 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 703 highest_link_speed, autoneg, autoneg_wait_to_complete); 704 705 out: 706 /* Set autoneg_advertised value based on input link speed */ 707 hw->phy.autoneg_advertised = 0; 708 709 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 710 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 711 712 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 713 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 714 715 return status; 716 } 717 718 /** 719 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 720 * @hw: pointer to hardware structure 721 * @speed: new link speed 722 * @autoneg: TRUE if autonegotiation enabled 723 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 724 * 725 * Implements the Intel SmartSpeed algorithm. 726 **/ 727 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 728 ixgbe_link_speed speed, bool autoneg, 729 bool autoneg_wait_to_complete) 730 { 731 s32 status = IXGBE_SUCCESS; 732 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 733 s32 i, j; 734 bool link_up = FALSE; 735 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 736 737 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 738 739 /* Set autoneg_advertised value based on input link speed */ 740 hw->phy.autoneg_advertised = 0; 741 742 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 743 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 744 745 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 746 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 747 748 if (speed & IXGBE_LINK_SPEED_100_FULL) 749 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 750 751 /* 752 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 753 * autoneg advertisement if link is unable to be established at the 754 * highest negotiated rate. This can sometimes happen due to integrity 755 * issues with the physical media connection. 756 */ 757 758 /* First, try to get link with full advertisement */ 759 hw->phy.smart_speed_active = FALSE; 760 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 761 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 762 autoneg_wait_to_complete); 763 if (status != IXGBE_SUCCESS) 764 goto out; 765 766 /* 767 * Wait for the controller to acquire link. Per IEEE 802.3ap, 768 * Section 73.10.2, we may have to wait up to 500ms if KR is 769 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 770 * Table 9 in the AN MAS. 771 */ 772 for (i = 0; i < 5; i++) { 773 msec_delay(100); 774 775 /* If we have link, just jump out */ 776 status = ixgbe_check_link(hw, &link_speed, &link_up, 777 FALSE); 778 if (status != IXGBE_SUCCESS) 779 goto out; 780 781 if (link_up) 782 goto out; 783 } 784 } 785 786 /* 787 * We didn't get link. If we advertised KR plus one of KX4/KX 788 * (or BX4/BX), then disable KR and try again. 789 */ 790 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 791 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 792 goto out; 793 794 /* Turn SmartSpeed on to disable KR support */ 795 hw->phy.smart_speed_active = TRUE; 796 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 797 autoneg_wait_to_complete); 798 if (status != IXGBE_SUCCESS) 799 goto out; 800 801 /* 802 * Wait for the controller to acquire link. 600ms will allow for 803 * the AN link_fail_inhibit_timer as well for multiple cycles of 804 * parallel detect, both 10g and 1g. This allows for the maximum 805 * connect attempts as defined in the AN MAS table 73-7. 806 */ 807 for (i = 0; i < 6; i++) { 808 msec_delay(100); 809 810 /* If we have link, just jump out */ 811 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 812 if (status != IXGBE_SUCCESS) 813 goto out; 814 815 if (link_up) 816 goto out; 817 } 818 819 /* We didn't get link. Turn SmartSpeed back off. */ 820 hw->phy.smart_speed_active = FALSE; 821 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 822 autoneg_wait_to_complete); 823 824 out: 825 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 826 DEBUGOUT("Smartspeed has downgraded the link speed " 827 "from the maximum advertised\n"); 828 return status; 829 } 830 831 /** 832 * ixgbe_setup_mac_link_82599 - Set MAC link speed 833 * @hw: pointer to hardware structure 834 * @speed: new link speed 835 * @autoneg: TRUE if autonegotiation enabled 836 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 837 * 838 * Set the link speed in the AUTOC register and restarts link. 839 **/ 840 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 841 ixgbe_link_speed speed, bool autoneg, 842 bool autoneg_wait_to_complete) 843 { 844 s32 status = IXGBE_SUCCESS; 845 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 846 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 847 u32 start_autoc = autoc; 848 u32 orig_autoc = 0; 849 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 850 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 851 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 852 u32 links_reg; 853 u32 i; 854 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 855 856 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 857 858 /* Check to see if speed passed in is supported. */ 859 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 860 if (status != IXGBE_SUCCESS) 861 goto out; 862 863 speed &= link_capabilities; 864 865 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 866 status = IXGBE_ERR_LINK_SETUP; 867 goto out; 868 } 869 870 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 871 if (hw->mac.orig_link_settings_stored) 872 orig_autoc = hw->mac.orig_autoc; 873 else 874 orig_autoc = autoc; 875 876 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 877 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 878 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 879 /* Set KX4/KX/KR support according to speed requested */ 880 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 881 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 882 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 883 autoc |= IXGBE_AUTOC_KX4_SUPP; 884 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 885 (hw->phy.smart_speed_active == FALSE)) 886 autoc |= IXGBE_AUTOC_KR_SUPP; 887 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 888 autoc |= IXGBE_AUTOC_KX_SUPP; 889 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 890 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 891 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 892 /* Switch from 1G SFI to 10G SFI if requested */ 893 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 894 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 895 autoc &= ~IXGBE_AUTOC_LMS_MASK; 896 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 897 } 898 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 899 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 900 /* Switch from 10G SFI to 1G SFI if requested */ 901 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 902 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 903 autoc &= ~IXGBE_AUTOC_LMS_MASK; 904 if (autoneg) 905 autoc |= IXGBE_AUTOC_LMS_1G_AN; 906 else 907 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 908 } 909 } 910 911 if (autoc != start_autoc) { 912 /* Restart link */ 913 autoc |= IXGBE_AUTOC_AN_RESTART; 914 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 915 916 /* Only poll for autoneg to complete if specified to do so */ 917 if (autoneg_wait_to_complete) { 918 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 919 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 920 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 921 links_reg = 0; /*Just in case Autoneg time=0*/ 922 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 923 links_reg = 924 IXGBE_READ_REG(hw, IXGBE_LINKS); 925 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 926 break; 927 msec_delay(100); 928 } 929 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 930 status = 931 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 932 DEBUGOUT("Autoneg did not complete.\n"); 933 } 934 } 935 } 936 937 /* Add delay to filter out noises during initial link setup */ 938 msec_delay(50); 939 } 940 941 out: 942 return status; 943 } 944 945 /** 946 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 947 * @hw: pointer to hardware structure 948 * @speed: new link speed 949 * @autoneg: TRUE if autonegotiation enabled 950 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 951 * 952 * Restarts link on PHY and MAC based on settings passed in. 953 **/ 954 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 955 ixgbe_link_speed speed, 956 bool autoneg, 957 bool autoneg_wait_to_complete) 958 { 959 s32 status; 960 961 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 962 963 /* Setup the PHY according to input speed */ 964 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 965 autoneg_wait_to_complete); 966 /* Set up MAC */ 967 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 968 969 return status; 970 } 971 972 /** 973 * ixgbe_reset_hw_82599 - Perform hardware reset 974 * @hw: pointer to hardware structure 975 * 976 * Resets the hardware by resetting the transmit and receive units, masks 977 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 978 * reset. 979 **/ 980 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 981 { 982 s32 status = IXGBE_SUCCESS; 983 u32 ctrl; 984 u32 i; 985 u32 autoc; 986 u32 autoc2; 987 988 DEBUGFUNC("ixgbe_reset_hw_82599"); 989 990 /* Call adapter stop to disable tx/rx and clear interrupts */ 991 hw->mac.ops.stop_adapter(hw); 992 993 /* PHY ops must be identified and initialized prior to reset */ 994 995 /* Identify PHY and related function pointers */ 996 status = hw->phy.ops.init(hw); 997 998 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 999 goto reset_hw_out; 1000 1001 /* Setup SFP module if there is one present. */ 1002 if (hw->phy.sfp_setup_needed) { 1003 status = hw->mac.ops.setup_sfp(hw); 1004 hw->phy.sfp_setup_needed = FALSE; 1005 } 1006 1007 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1008 goto reset_hw_out; 1009 1010 /* Reset PHY */ 1011 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) 1012 hw->phy.ops.reset(hw); 1013 1014 /* 1015 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 1016 * access and verify no pending requests before reset 1017 */ 1018 ixgbe_disable_pcie_master(hw); 1019 1020 mac_reset_top: 1021 /* 1022 * Issue global reset to the MAC. This needs to be a SW reset. 1023 * If link reset is used, it might reset the MAC when mng is using it 1024 */ 1025 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1026 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 1027 IXGBE_WRITE_FLUSH(hw); 1028 1029 /* Poll for reset bit to self-clear indicating reset is complete */ 1030 for (i = 0; i < 10; i++) { 1031 usec_delay(1); 1032 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1033 if (!(ctrl & IXGBE_CTRL_RST)) 1034 break; 1035 } 1036 if (ctrl & IXGBE_CTRL_RST) { 1037 status = IXGBE_ERR_RESET_FAILED; 1038 DEBUGOUT("Reset polling failed to complete.\n"); 1039 } 1040 1041 /* 1042 * Double resets are required for recovery from certain error 1043 * conditions. Between resets, it is necessary to stall to allow time 1044 * for any pending HW events to complete. We use 1usec since that is 1045 * what is needed for ixgbe_disable_pcie_master(). The second reset 1046 * then clears out any effects of those events. 1047 */ 1048 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1049 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1050 usec_delay(1); 1051 goto mac_reset_top; 1052 } 1053 1054 msec_delay(50); 1055 1056 /* 1057 * Store the original AUTOC/AUTOC2 values if they have not been 1058 * stored off yet. Otherwise restore the stored original 1059 * values since the reset operation sets back to defaults. 1060 */ 1061 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1062 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1063 if (hw->mac.orig_link_settings_stored == FALSE) { 1064 hw->mac.orig_autoc = autoc; 1065 hw->mac.orig_autoc2 = autoc2; 1066 hw->mac.orig_link_settings_stored = TRUE; 1067 } else { 1068 if (autoc != hw->mac.orig_autoc) 1069 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | 1070 IXGBE_AUTOC_AN_RESTART)); 1071 1072 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1073 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1074 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1075 autoc2 |= (hw->mac.orig_autoc2 & 1076 IXGBE_AUTOC2_UPPER_MASK); 1077 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1078 } 1079 } 1080 1081 /* Store the permanent mac address */ 1082 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1083 1084 /* 1085 * Store MAC address from RAR0, clear receive address registers, and 1086 * clear the multicast table. Also reset num_rar_entries to 128, 1087 * since we modify this value when programming the SAN MAC address. 1088 */ 1089 hw->mac.num_rar_entries = 128; 1090 hw->mac.ops.init_rx_addrs(hw); 1091 1092 /* Store the permanent SAN mac address */ 1093 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1094 1095 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1096 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1097 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1098 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1099 1100 /* Reserve the last RAR for the SAN MAC address */ 1101 hw->mac.num_rar_entries--; 1102 } 1103 1104 /* Store the alternative WWNN/WWPN prefix */ 1105 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1106 &hw->mac.wwpn_prefix); 1107 1108 reset_hw_out: 1109 return status; 1110 } 1111 1112 /** 1113 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1114 * @hw: pointer to hardware structure 1115 **/ 1116 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1117 { 1118 int i; 1119 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1120 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1121 1122 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599"); 1123 1124 /* 1125 * Before starting reinitialization process, 1126 * FDIRCMD.CMD must be zero. 1127 */ 1128 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1129 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1130 IXGBE_FDIRCMD_CMD_MASK)) 1131 break; 1132 usec_delay(10); 1133 } 1134 if (i >= IXGBE_FDIRCMD_CMD_POLL) { 1135 DEBUGOUT("Flow Director previous command isn't complete, " 1136 "aborting table re-initialization. \n"); 1137 return IXGBE_ERR_FDIR_REINIT_FAILED; 1138 } 1139 1140 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1141 IXGBE_WRITE_FLUSH(hw); 1142 /* 1143 * 82599 adapters flow director init flow cannot be restarted, 1144 * Workaround 82599 silicon errata by performing the following steps 1145 * before re-writing the FDIRCTRL control register with the same value. 1146 * - write 1 to bit 8 of FDIRCMD register & 1147 * - write 0 to bit 8 of FDIRCMD register 1148 */ 1149 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1150 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1151 IXGBE_FDIRCMD_CLEARHT)); 1152 IXGBE_WRITE_FLUSH(hw); 1153 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1154 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1155 ~IXGBE_FDIRCMD_CLEARHT)); 1156 IXGBE_WRITE_FLUSH(hw); 1157 /* 1158 * Clear FDIR Hash register to clear any leftover hashes 1159 * waiting to be programmed. 1160 */ 1161 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1162 IXGBE_WRITE_FLUSH(hw); 1163 1164 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1165 IXGBE_WRITE_FLUSH(hw); 1166 1167 /* Poll init-done after we write FDIRCTRL register */ 1168 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1169 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1170 IXGBE_FDIRCTRL_INIT_DONE) 1171 break; 1172 usec_delay(10); 1173 } 1174 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1175 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1176 return IXGBE_ERR_FDIR_REINIT_FAILED; 1177 } 1178 1179 /* Clear FDIR statistics registers (read to clear) */ 1180 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1181 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1182 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1183 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1184 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1185 1186 return IXGBE_SUCCESS; 1187 } 1188 1189 /** 1190 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1191 * @hw: pointer to hardware structure 1192 * @pballoc: which mode to allocate filters with 1193 **/ 1194 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) 1195 { 1196 u32 fdirctrl = 0; 1197 u32 pbsize; 1198 int i; 1199 1200 DEBUGFUNC("ixgbe_init_fdir_signature_82599"); 1201 1202 /* 1203 * Before enabling Flow Director, the Rx Packet Buffer size 1204 * must be reduced. The new value is the current size minus 1205 * flow director memory usage size. 1206 */ 1207 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); 1208 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 1209 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); 1210 1211 /* 1212 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1213 * intialized to zero for non DCB mode otherwise actual total RX PB 1214 * would be bigger than programmed and filter space would run into 1215 * the PB 0 region. 1216 */ 1217 for (i = 1; i < 8; i++) 1218 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 1219 1220 /* Send interrupt when 64 filters are left */ 1221 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; 1222 1223 /* Set the maximum length per hash bucket to 0xA filters */ 1224 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT; 1225 1226 switch (pballoc) { 1227 case IXGBE_FDIR_PBALLOC_64K: 1228 /* 8k - 1 signature filters */ 1229 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 1230 break; 1231 case IXGBE_FDIR_PBALLOC_128K: 1232 /* 16k - 1 signature filters */ 1233 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 1234 break; 1235 case IXGBE_FDIR_PBALLOC_256K: 1236 /* 32k - 1 signature filters */ 1237 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 1238 break; 1239 default: 1240 /* bad value */ 1241 return IXGBE_ERR_CONFIG; 1242 }; 1243 1244 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1245 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1246 1247 1248 /* Prime the keys for hashing */ 1249 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1250 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1251 1252 /* 1253 * Poll init-done after we write the register. Estimated times: 1254 * 10G: PBALLOC = 11b, timing is 60us 1255 * 1G: PBALLOC = 11b, timing is 600us 1256 * 100M: PBALLOC = 11b, timing is 6ms 1257 * 1258 * Multiple these timings by 4 if under full Rx load 1259 * 1260 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1261 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1262 * this might not finish in our poll time, but we can live with that 1263 * for now. 1264 */ 1265 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1266 IXGBE_WRITE_FLUSH(hw); 1267 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1268 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1269 IXGBE_FDIRCTRL_INIT_DONE) 1270 break; 1271 msec_delay(1); 1272 } 1273 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1274 DEBUGOUT("Flow Director Signature poll time exceeded!\n"); 1275 1276 return IXGBE_SUCCESS; 1277 } 1278 1279 /** 1280 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1281 * @hw: pointer to hardware structure 1282 * @pballoc: which mode to allocate filters with 1283 **/ 1284 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) 1285 { 1286 u32 fdirctrl = 0; 1287 u32 pbsize; 1288 int i; 1289 1290 DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); 1291 1292 /* 1293 * Before enabling Flow Director, the Rx Packet Buffer size 1294 * must be reduced. The new value is the current size minus 1295 * flow director memory usage size. 1296 */ 1297 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); 1298 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 1299 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); 1300 1301 /* 1302 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1303 * intialized to zero for non DCB mode otherwise actual total RX PB 1304 * would be bigger than programmed and filter space would run into 1305 * the PB 0 region. 1306 */ 1307 for (i = 1; i < 8; i++) 1308 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 1309 1310 /* Send interrupt when 64 filters are left */ 1311 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; 1312 1313 /* Initialize the drop queue to Rx queue 127 */ 1314 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT); 1315 1316 switch (pballoc) { 1317 case IXGBE_FDIR_PBALLOC_64K: 1318 /* 2k - 1 perfect filters */ 1319 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; 1320 break; 1321 case IXGBE_FDIR_PBALLOC_128K: 1322 /* 4k - 1 perfect filters */ 1323 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; 1324 break; 1325 case IXGBE_FDIR_PBALLOC_256K: 1326 /* 8k - 1 perfect filters */ 1327 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; 1328 break; 1329 default: 1330 /* bad value */ 1331 return IXGBE_ERR_CONFIG; 1332 }; 1333 1334 /* Turn perfect match filtering on */ 1335 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; 1336 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; 1337 1338 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1339 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1340 1341 /* Prime the keys for hashing */ 1342 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1343 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,IXGBE_ATR_SIGNATURE_HASH_KEY); 1344 1345 /* 1346 * Poll init-done after we write the register. Estimated times: 1347 * 10G: PBALLOC = 11b, timing is 60us 1348 * 1G: PBALLOC = 11b, timing is 600us 1349 * 100M: PBALLOC = 11b, timing is 6ms 1350 * 1351 * Multiple these timings by 4 if under full Rx load 1352 * 1353 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1354 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1355 * this might not finish in our poll time, but we can live with that 1356 * for now. 1357 */ 1358 1359 /* Set the maximum length per hash bucket to 0xA filters */ 1360 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT); 1361 1362 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1363 IXGBE_WRITE_FLUSH(hw); 1364 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1365 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1366 IXGBE_FDIRCTRL_INIT_DONE) 1367 break; 1368 msec_delay(1); 1369 } 1370 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1371 DEBUGOUT("Flow Director Perfect poll time exceeded!\n"); 1372 1373 return IXGBE_SUCCESS; 1374 } 1375 1376 /** 1377 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR 1378 * @stream: input bitstream to compute the hash on 1379 * @key: 32-bit hash key 1380 **/ 1381 u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, 1382 u32 key) 1383 { 1384 /* 1385 * The algorithm is as follows: 1386 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 1387 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] 1388 * and A[n] x B[n] is bitwise AND between same length strings 1389 * 1390 * K[n] is 16 bits, defined as: 1391 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] 1392 * for n modulo 32 < 15, K[n] = 1393 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] 1394 * 1395 * S[n] is 16 bits, defined as: 1396 * for n >= 15, S[n] = S[n:n - 15] 1397 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] 1398 * 1399 * To simplify for programming, the algorithm is implemented 1400 * in software this way: 1401 * 1402 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0] 1403 * 1404 * for (i = 0; i < 352; i+=32) 1405 * hi_hash_dword[31:0] ^= Stream[(i+31):i]; 1406 * 1407 * lo_hash_dword[15:0] ^= Stream[15:0]; 1408 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16]; 1409 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0]; 1410 * 1411 * hi_hash_dword[31:0] ^= Stream[351:320]; 1412 * 1413 * if(key[0]) 1414 * hash[15:0] ^= Stream[15:0]; 1415 * 1416 * for (i = 0; i < 16; i++) { 1417 * if (key[i]) 1418 * hash[15:0] ^= lo_hash_dword[(i+15):i]; 1419 * if (key[i + 16]) 1420 * hash[15:0] ^= hi_hash_dword[(i+15):i]; 1421 * } 1422 * 1423 */ 1424 __be32 common_hash_dword = 0; 1425 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1426 u32 hash_result = 0; 1427 u8 i; 1428 1429 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1430 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]); 1431 1432 /* generate common hash dword */ 1433 for (i = 10; i; i -= 2) 1434 common_hash_dword ^= atr_input->dword_stream[i] ^ 1435 atr_input->dword_stream[i - 1]; 1436 1437 hi_hash_dword = IXGBE_NTOHL(common_hash_dword); 1438 1439 /* low dword is word swapped version of common */ 1440 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1441 1442 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1443 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1444 1445 /* Process bits 0 and 16 */ 1446 if (key & 0x0001) hash_result ^= lo_hash_dword; 1447 if (key & 0x00010000) hash_result ^= hi_hash_dword; 1448 1449 /* 1450 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1451 * delay this because bit 0 of the stream should not be processed 1452 * so we do not add the vlan until after bit 0 was processed 1453 */ 1454 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1455 1456 1457 /* process the remaining 30 bits in the key 2 bits at a time */ 1458 for (i = 15; i; i-- ) { 1459 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i; 1460 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i; 1461 } 1462 1463 return hash_result & IXGBE_ATR_HASH_MASK; 1464 } 1465 1466 /* 1467 * These defines allow us to quickly generate all of the necessary instructions 1468 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1469 * for values 0 through 15 1470 */ 1471 #define IXGBE_ATR_COMMON_HASH_KEY \ 1472 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1473 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1474 do { \ 1475 u32 n = (_n); \ 1476 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1477 common_hash ^= lo_hash_dword >> n; \ 1478 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1479 bucket_hash ^= lo_hash_dword >> n; \ 1480 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1481 sig_hash ^= lo_hash_dword << (16 - n); \ 1482 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1483 common_hash ^= hi_hash_dword >> n; \ 1484 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1485 bucket_hash ^= hi_hash_dword >> n; \ 1486 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1487 sig_hash ^= hi_hash_dword << (16 - n); \ 1488 } while (0); 1489 1490 /** 1491 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1492 * @stream: input bitstream to compute the hash on 1493 * 1494 * This function is almost identical to the function above but contains 1495 * several optomizations such as unwinding all of the loops, letting the 1496 * compiler work out all of the conditional ifs since the keys are static 1497 * defines, and computing two keys at once since the hashed dword stream 1498 * will be the same for both keys. 1499 **/ 1500 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1501 union ixgbe_atr_hash_dword common) 1502 { 1503 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1504 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1505 1506 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1507 flow_vm_vlan = IXGBE_NTOHL(input.dword); 1508 1509 /* generate common hash dword */ 1510 hi_hash_dword = IXGBE_NTOHL(common.dword); 1511 1512 /* low dword is word swapped version of common */ 1513 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1514 1515 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1516 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1517 1518 /* Process bits 0 and 16 */ 1519 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1520 1521 /* 1522 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1523 * delay this because bit 0 of the stream should not be processed 1524 * so we do not add the vlan until after bit 0 was processed 1525 */ 1526 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1527 1528 /* Process remaining 30 bit of the key */ 1529 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1530 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1531 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1532 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1533 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1534 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1535 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1536 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1537 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1538 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1539 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1540 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1541 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1542 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1543 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1544 1545 /* combine common_hash result with signature and bucket hashes */ 1546 bucket_hash ^= common_hash; 1547 bucket_hash &= IXGBE_ATR_HASH_MASK; 1548 1549 sig_hash ^= common_hash << 16; 1550 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1551 1552 /* return completed signature hash */ 1553 return sig_hash ^ bucket_hash; 1554 } 1555 1556 /** 1557 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1558 * @hw: pointer to hardware structure 1559 * @stream: input bitstream 1560 * @queue: queue index to direct traffic to 1561 **/ 1562 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1563 union ixgbe_atr_hash_dword input, 1564 union ixgbe_atr_hash_dword common, 1565 u8 queue) 1566 { 1567 u64 fdirhashcmd; 1568 u32 fdircmd; 1569 1570 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); 1571 1572 /* 1573 * Get the flow_type in order to program FDIRCMD properly 1574 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1575 */ 1576 switch (input.formatted.flow_type) { 1577 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1578 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1579 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1580 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1581 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1582 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1583 break; 1584 default: 1585 DEBUGOUT(" Error on flow type input\n"); 1586 return IXGBE_ERR_CONFIG; 1587 } 1588 1589 /* configure FDIRCMD register */ 1590 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1591 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1592 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1593 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1594 1595 /* 1596 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1597 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1598 */ 1599 fdirhashcmd = (u64)fdircmd << 32; 1600 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1601 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1602 1603 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1604 1605 return IXGBE_SUCCESS; 1606 } 1607 1608 /** 1609 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1610 * @input_mask: mask to be bit swapped 1611 * 1612 * The source and destination port masks for flow director are bit swapped 1613 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1614 * generate a correctly swapped value we need to bit swap the mask and that 1615 * is what is accomplished by this function. 1616 **/ 1617 static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks) 1618 { 1619 u32 mask = IXGBE_NTOHS(input_masks->dst_port_mask); 1620 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1621 mask |= IXGBE_NTOHS(input_masks->src_port_mask); 1622 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1623 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1624 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1625 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1626 } 1627 1628 /* 1629 * These two macros are meant to address the fact that we have registers 1630 * that are either all or in part big-endian. As a result on big-endian 1631 * systems we will end up byte swapping the value to little-endian before 1632 * it is byte swapped again and written to the hardware in the original 1633 * big-endian format. 1634 */ 1635 #define IXGBE_STORE_AS_BE32(_value) \ 1636 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1637 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1638 1639 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1640 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value))) 1641 1642 #define IXGBE_STORE_AS_BE16(_value) \ 1643 (((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1644 1645 1646 /** 1647 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 1648 * @hw: pointer to hardware structure 1649 * @input: input bitstream 1650 * @input_masks: masks for the input bitstream 1651 * @soft_id: software index for the filters 1652 * @queue: queue index to direct traffic to 1653 * 1654 * Note that the caller to this function must lock before calling, since the 1655 * hardware writes must be protected from one another. 1656 **/ 1657 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 1658 union ixgbe_atr_input *input, 1659 struct ixgbe_atr_input_masks *input_masks, 1660 u16 soft_id, u8 queue) 1661 { 1662 u32 fdirhash; 1663 u32 fdircmd; 1664 u32 fdirport, fdirtcpm; 1665 u32 fdirvlan; 1666 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */ 1667 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX | 1668 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6; 1669 1670 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599"); 1671 1672 /* 1673 * Check flow_type formatting, and bail out before we touch the hardware 1674 * if there's a configuration issue 1675 */ 1676 switch (input->formatted.flow_type) { 1677 case IXGBE_ATR_FLOW_TYPE_IPV4: 1678 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */ 1679 fdirm |= IXGBE_FDIRM_L4P; 1680 break; 1681 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1682 if (input_masks->dst_port_mask || input_masks->src_port_mask) { 1683 DEBUGOUT(" Error on src/dst port mask\n"); 1684 return IXGBE_ERR_CONFIG; 1685 } 1686 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1687 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1688 break; 1689 default: 1690 DEBUGOUT(" Error on flow type input\n"); 1691 return IXGBE_ERR_CONFIG; 1692 } 1693 1694 /* 1695 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1696 * are zero, then assume a full mask for that field. Also assume that 1697 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1698 * cannot be masked out in this implementation. 1699 * 1700 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1701 * point in time. 1702 */ 1703 1704 /* Program FDIRM */ 1705 switch (IXGBE_NTOHS(input_masks->vlan_id_mask) & 0xEFFF) { 1706 case 0xEFFF: 1707 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */ 1708 fdirm &= ~IXGBE_FDIRM_VLANID; 1709 /*FALLTHROUGH*/ 1710 case 0xE000: 1711 /* Unmask VLAN prio - bit 1 */ 1712 fdirm &= ~IXGBE_FDIRM_VLANP; 1713 break; 1714 case 0x0FFF: 1715 /* Unmask VLAN ID - bit 0 */ 1716 fdirm &= ~IXGBE_FDIRM_VLANID; 1717 break; 1718 case 0x0000: 1719 /* do nothing, vlans already masked */ 1720 break; 1721 default: 1722 DEBUGOUT(" Error on VLAN mask\n"); 1723 return IXGBE_ERR_CONFIG; 1724 } 1725 1726 if (input_masks->flex_mask & 0xFFFF) { 1727 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) { 1728 DEBUGOUT(" Error on flexible byte mask\n"); 1729 return IXGBE_ERR_CONFIG; 1730 } 1731 /* Unmask Flex Bytes - bit 4 */ 1732 fdirm &= ~IXGBE_FDIRM_FLEX; 1733 } 1734 1735 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1736 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1737 1738 /* store the TCP/UDP port masks, bit reversed from port layout */ 1739 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks); 1740 1741 /* write both the same so that UDP and TCP use the same mask */ 1742 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1743 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1744 1745 /* store source and destination IP masks (big-enian) */ 1746 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1747 ~input_masks->src_ip_mask[0]); 1748 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1749 ~input_masks->dst_ip_mask[0]); 1750 1751 /* Apply masks to input data */ 1752 input->formatted.vlan_id &= input_masks->vlan_id_mask; 1753 input->formatted.flex_bytes &= input_masks->flex_mask; 1754 input->formatted.src_port &= input_masks->src_port_mask; 1755 input->formatted.dst_port &= input_masks->dst_port_mask; 1756 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0]; 1757 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0]; 1758 1759 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1760 fdirvlan = 1761 IXGBE_STORE_AS_BE16(IXGBE_NTOHS(input->formatted.flex_bytes)); 1762 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1763 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id); 1764 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1765 1766 /* record source and destination port (little-endian)*/ 1767 fdirport = IXGBE_NTOHS(input->formatted.dst_port); 1768 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1769 fdirport |= IXGBE_NTOHS(input->formatted.src_port); 1770 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1771 1772 /* record the first 32 bits of the destination address (big-endian) */ 1773 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1774 1775 /* record the source address (big-endian) */ 1776 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1777 1778 /* configure FDIRCMD register */ 1779 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1780 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1781 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1782 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1783 1784 /* we only want the bucket hash so drop the upper 16 bits */ 1785 fdirhash = ixgbe_atr_compute_hash_82599(input, 1786 IXGBE_ATR_BUCKET_HASH_KEY); 1787 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1788 1789 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1790 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1791 1792 return IXGBE_SUCCESS; 1793 } 1794 1795 /** 1796 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1797 * @hw: pointer to hardware structure 1798 * @reg: analog register to read 1799 * @val: read value 1800 * 1801 * Performs read operation to Omer analog register specified. 1802 **/ 1803 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1804 { 1805 u32 core_ctl; 1806 1807 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 1808 1809 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1810 (reg << 8)); 1811 IXGBE_WRITE_FLUSH(hw); 1812 usec_delay(10); 1813 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1814 *val = (u8)core_ctl; 1815 1816 return IXGBE_SUCCESS; 1817 } 1818 1819 /** 1820 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1821 * @hw: pointer to hardware structure 1822 * @reg: atlas register to write 1823 * @val: value to write 1824 * 1825 * Performs write operation to Omer analog register specified. 1826 **/ 1827 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1828 { 1829 u32 core_ctl; 1830 1831 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 1832 1833 core_ctl = (reg << 8) | val; 1834 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1835 IXGBE_WRITE_FLUSH(hw); 1836 usec_delay(10); 1837 1838 return IXGBE_SUCCESS; 1839 } 1840 1841 /** 1842 * ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx 1843 * @hw: pointer to hardware structure 1844 * 1845 * Starts the hardware using the generic start_hw function 1846 * and the generation start_hw function. 1847 * Then performs revision-specific operations, if any. 1848 **/ 1849 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw) 1850 { 1851 s32 ret_val = IXGBE_SUCCESS; 1852 1853 DEBUGFUNC("ixgbe_start_hw_rev_1__82599"); 1854 1855 ret_val = ixgbe_start_hw_generic(hw); 1856 if (ret_val != IXGBE_SUCCESS) 1857 goto out; 1858 1859 ret_val = ixgbe_start_hw_gen2(hw); 1860 if (ret_val != IXGBE_SUCCESS) 1861 goto out; 1862 1863 /* We need to run link autotry after the driver loads */ 1864 hw->mac.autotry_restart = TRUE; 1865 1866 if (ret_val == IXGBE_SUCCESS) 1867 ret_val = ixgbe_verify_fw_version_82599(hw); 1868 out: 1869 return ret_val; 1870 } 1871 1872 /** 1873 * ixgbe_identify_phy_82599 - Get physical layer module 1874 * @hw: pointer to hardware structure 1875 * 1876 * Determines the physical layer module found on the current adapter. 1877 * If PHY already detected, maintains current PHY type in hw struct, 1878 * otherwise executes the PHY detection routine. 1879 **/ 1880 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1881 { 1882 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1883 1884 DEBUGFUNC("ixgbe_identify_phy_82599"); 1885 1886 /* Detect PHY if not unknown - returns success if already detected. */ 1887 status = ixgbe_identify_phy_generic(hw); 1888 if (status != IXGBE_SUCCESS) { 1889 /* 82599 10GBASE-T requires an external PHY */ 1890 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1891 goto out; 1892 else 1893 status = ixgbe_identify_sfp_module_generic(hw); 1894 } 1895 1896 /* Set PHY type none if no PHY detected */ 1897 if (hw->phy.type == ixgbe_phy_unknown) { 1898 hw->phy.type = ixgbe_phy_none; 1899 status = IXGBE_SUCCESS; 1900 } 1901 1902 /* Return error if SFP module has been detected but is not supported */ 1903 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1904 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1905 1906 out: 1907 return status; 1908 } 1909 1910 /** 1911 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1912 * @hw: pointer to hardware structure 1913 * 1914 * Determines physical layer capabilities of the current configuration. 1915 **/ 1916 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1917 { 1918 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1919 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1920 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1921 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1922 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1923 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1924 u16 ext_ability = 0; 1925 u8 comp_codes_10g = 0; 1926 u8 comp_codes_1g = 0; 1927 1928 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 1929 1930 hw->phy.ops.identify(hw); 1931 1932 switch (hw->phy.type) { 1933 case ixgbe_phy_tn: 1934 case ixgbe_phy_aq: 1935 case ixgbe_phy_cu_unknown: 1936 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1937 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1938 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1939 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1940 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1941 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1942 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1943 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1944 goto out; 1945 default: 1946 break; 1947 } 1948 1949 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1950 case IXGBE_AUTOC_LMS_1G_AN: 1951 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1952 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1953 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1954 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1955 goto out; 1956 } else 1957 /* SFI mode so read SFP module */ 1958 goto sfp_check; 1959 break; 1960 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1961 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 1962 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1963 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 1964 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1965 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 1966 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 1967 goto out; 1968 break; 1969 case IXGBE_AUTOC_LMS_10G_SERIAL: 1970 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 1971 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1972 goto out; 1973 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 1974 goto sfp_check; 1975 break; 1976 case IXGBE_AUTOC_LMS_KX4_KX_KR: 1977 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 1978 if (autoc & IXGBE_AUTOC_KX_SUPP) 1979 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1980 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1981 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1982 if (autoc & IXGBE_AUTOC_KR_SUPP) 1983 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1984 goto out; 1985 break; 1986 default: 1987 goto out; 1988 break; 1989 } 1990 1991 sfp_check: 1992 /* SFP check must be done last since DA modules are sometimes used to 1993 * test KR mode - we need to id KR mode correctly before SFP module. 1994 * Call identify_sfp because the pluggable module may have changed */ 1995 hw->phy.ops.identify_sfp(hw); 1996 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1997 goto out; 1998 1999 switch (hw->phy.type) { 2000 case ixgbe_phy_sfp_passive_tyco: 2001 case ixgbe_phy_sfp_passive_unknown: 2002 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 2003 break; 2004 case ixgbe_phy_sfp_ftl_active: 2005 case ixgbe_phy_sfp_active_unknown: 2006 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 2007 break; 2008 case ixgbe_phy_sfp_avago: 2009 case ixgbe_phy_sfp_ftl: 2010 case ixgbe_phy_sfp_intel: 2011 case ixgbe_phy_sfp_unknown: 2012 hw->phy.ops.read_i2c_eeprom(hw, 2013 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 2014 hw->phy.ops.read_i2c_eeprom(hw, 2015 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 2016 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 2017 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 2018 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 2019 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 2020 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 2021 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 2022 break; 2023 default: 2024 break; 2025 } 2026 2027 out: 2028 return physical_layer; 2029 } 2030 2031 /** 2032 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 2033 * @hw: pointer to hardware structure 2034 * @regval: register value to write to RXCTRL 2035 * 2036 * Enables the Rx DMA unit for 82599 2037 **/ 2038 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 2039 { 2040 #define IXGBE_MAX_SECRX_POLL 30 2041 int i; 2042 int secrxreg; 2043 2044 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 2045 2046 /* 2047 * Workaround for 82599 silicon errata when enabling the Rx datapath. 2048 * If traffic is incoming before we enable the Rx unit, it could hang 2049 * the Rx DMA unit. Therefore, make sure the security engine is 2050 * completely disabled prior to enabling the Rx unit. 2051 */ 2052 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2053 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2054 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2055 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2056 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2057 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2058 break; 2059 else 2060 /* Use interrupt-safe sleep just in case */ 2061 usec_delay(10); 2062 } 2063 2064 /* For informational purposes only */ 2065 if (i >= IXGBE_MAX_SECRX_POLL) 2066 DEBUGOUT("Rx unit being enabled before security " 2067 "path fully disabled. Continuing with init.\n"); 2068 2069 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2070 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2071 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2072 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2073 IXGBE_WRITE_FLUSH(hw); 2074 2075 return IXGBE_SUCCESS; 2076 } 2077 2078 /** 2079 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 2080 * @hw: pointer to hardware structure 2081 * 2082 * Verifies that installed the firmware version is 0.6 or higher 2083 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 2084 * 2085 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 2086 * if the FW version is not supported. 2087 **/ 2088 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 2089 { 2090 s32 status = IXGBE_ERR_EEPROM_VERSION; 2091 u16 fw_offset, fw_ptp_cfg_offset; 2092 u16 fw_version = 0; 2093 2094 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 2095 2096 /* firmware check is only necessary for SFI devices */ 2097 if (hw->phy.media_type != ixgbe_media_type_fiber) { 2098 status = IXGBE_SUCCESS; 2099 goto fw_version_out; 2100 } 2101 2102 /* get the offset to the Firmware Module block */ 2103 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2104 2105 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 2106 goto fw_version_out; 2107 2108 /* get the offset to the Pass Through Patch Configuration block */ 2109 hw->eeprom.ops.read(hw, (fw_offset + 2110 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 2111 &fw_ptp_cfg_offset); 2112 2113 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 2114 goto fw_version_out; 2115 2116 /* get the firmware version */ 2117 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 2118 IXGBE_FW_PATCH_VERSION_4), 2119 &fw_version); 2120 2121 if (fw_version > 0x5) 2122 status = IXGBE_SUCCESS; 2123 2124 fw_version_out: 2125 return status; 2126 } 2127 2128 /** 2129 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 2130 * @hw: pointer to hardware structure 2131 * 2132 * Returns TRUE if the LESM FW module is present and enabled. Otherwise 2133 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. 2134 **/ 2135 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 2136 { 2137 bool lesm_enabled = FALSE; 2138 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 2139 s32 status; 2140 2141 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 2142 2143 /* get the offset to the Firmware Module block */ 2144 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 2145 2146 if ((status != IXGBE_SUCCESS) || 2147 (fw_offset == 0) || (fw_offset == 0xFFFF)) 2148 goto out; 2149 2150 /* get the offset to the LESM Parameters block */ 2151 status = hw->eeprom.ops.read(hw, (fw_offset + 2152 IXGBE_FW_LESM_PARAMETERS_PTR), 2153 &fw_lesm_param_offset); 2154 2155 if ((status != IXGBE_SUCCESS) || 2156 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2157 goto out; 2158 2159 /* get the lesm state word */ 2160 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2161 IXGBE_FW_LESM_STATE_1), 2162 &fw_lesm_state); 2163 2164 if ((status == IXGBE_SUCCESS) && 2165 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2166 lesm_enabled = TRUE; 2167 2168 out: 2169 return lesm_enabled; 2170 } 2171 2172 2173
Indexes created Mon Sep 29 13:09:55 GMT 2025