ixgbe_common.c revision 1.11
1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 299200 2016-05-06 22:54:56Z pfg $*/ 34 /*$NetBSD: ixgbe_common.c,v 1.11 2016/12/05 08:50:29 msaitoh Exp $*/ 35 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 #include "ixgbe_dcb.h" 39 #include "ixgbe_dcb_82599.h" 40 #include "ixgbe_api.h" 41 42 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 43 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 44 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 45 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 46 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 47 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 48 u16 count); 49 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 50 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 51 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 52 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 53 54 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 55 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 56 u16 *san_mac_offset); 57 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 58 u16 words, u16 *data); 59 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 60 u16 words, u16 *data); 61 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 62 u16 offset); 63 64 /** 65 * ixgbe_init_ops_generic - Inits function ptrs 66 * @hw: pointer to the hardware structure 67 * 68 * Initialize the function pointers. 69 **/ 70 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 71 { 72 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 73 struct ixgbe_mac_info *mac = &hw->mac; 74 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 75 76 DEBUGFUNC("ixgbe_init_ops_generic"); 77 78 /* EEPROM */ 79 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 80 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 81 if (eec & IXGBE_EEC_PRES) { 82 eeprom->ops.read = ixgbe_read_eerd_generic; 83 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 84 } else { 85 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 86 eeprom->ops.read_buffer = 87 ixgbe_read_eeprom_buffer_bit_bang_generic; 88 } 89 eeprom->ops.write = ixgbe_write_eeprom_generic; 90 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 91 eeprom->ops.validate_checksum = 92 ixgbe_validate_eeprom_checksum_generic; 93 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 94 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 95 96 /* MAC */ 97 mac->ops.init_hw = ixgbe_init_hw_generic; 98 mac->ops.reset_hw = NULL; 99 mac->ops.start_hw = ixgbe_start_hw_generic; 100 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 101 mac->ops.get_media_type = NULL; 102 mac->ops.get_supported_physical_layer = NULL; 103 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 104 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 105 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 106 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 107 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 108 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 109 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 110 mac->ops.prot_autoc_read = prot_autoc_read_generic; 111 mac->ops.prot_autoc_write = prot_autoc_write_generic; 112 113 /* LEDs */ 114 mac->ops.led_on = ixgbe_led_on_generic; 115 mac->ops.led_off = ixgbe_led_off_generic; 116 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 117 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 118 119 /* RAR, Multicast, VLAN */ 120 mac->ops.set_rar = ixgbe_set_rar_generic; 121 mac->ops.clear_rar = ixgbe_clear_rar_generic; 122 mac->ops.insert_mac_addr = NULL; 123 mac->ops.set_vmdq = NULL; 124 mac->ops.clear_vmdq = NULL; 125 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 126 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 127 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 128 mac->ops.enable_mc = ixgbe_enable_mc_generic; 129 mac->ops.disable_mc = ixgbe_disable_mc_generic; 130 mac->ops.clear_vfta = NULL; 131 mac->ops.set_vfta = NULL; 132 mac->ops.set_vlvf = NULL; 133 mac->ops.init_uta_tables = NULL; 134 mac->ops.enable_rx = ixgbe_enable_rx_generic; 135 mac->ops.disable_rx = ixgbe_disable_rx_generic; 136 137 /* Flow Control */ 138 mac->ops.fc_enable = ixgbe_fc_enable_generic; 139 mac->ops.setup_fc = ixgbe_setup_fc_generic; 140 141 /* Link */ 142 mac->ops.get_link_capabilities = NULL; 143 mac->ops.setup_link = NULL; 144 mac->ops.check_link = NULL; 145 mac->ops.dmac_config = NULL; 146 mac->ops.dmac_update_tcs = NULL; 147 mac->ops.dmac_config_tcs = NULL; 148 149 return IXGBE_SUCCESS; 150 } 151 152 /** 153 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 154 * of flow control 155 * @hw: pointer to hardware structure 156 * 157 * This function returns TRUE if the device supports flow control 158 * autonegotiation, and FALSE if it does not. 159 * 160 **/ 161 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 162 { 163 bool supported = FALSE; 164 ixgbe_link_speed speed; 165 bool link_up; 166 167 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 168 169 switch (hw->phy.media_type) { 170 case ixgbe_media_type_fiber_fixed: 171 case ixgbe_media_type_fiber_qsfp: 172 case ixgbe_media_type_fiber: 173 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 174 /* if link is down, assume supported */ 175 if (link_up) 176 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 177 TRUE : FALSE; 178 else 179 supported = TRUE; 180 break; 181 case ixgbe_media_type_backplane: 182 supported = TRUE; 183 break; 184 case ixgbe_media_type_copper: 185 /* only some copper devices support flow control autoneg */ 186 switch (hw->device_id) { 187 case IXGBE_DEV_ID_82599_T3_LOM: 188 case IXGBE_DEV_ID_X540T: 189 case IXGBE_DEV_ID_X540T1: 190 case IXGBE_DEV_ID_X540_BYPASS: 191 case IXGBE_DEV_ID_X550T: 192 case IXGBE_DEV_ID_X550T1: 193 case IXGBE_DEV_ID_X550EM_X_10G_T: 194 supported = TRUE; 195 break; 196 default: 197 supported = FALSE; 198 } 199 default: 200 break; 201 } 202 203 if (!supported) { 204 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 205 "Device %x does not support flow control autoneg", 206 hw->device_id); 207 } 208 209 return supported; 210 } 211 212 /** 213 * ixgbe_setup_fc_generic - Set up flow control 214 * @hw: pointer to hardware structure 215 * 216 * Called at init time to set up flow control. 217 **/ 218 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 219 { 220 s32 ret_val = IXGBE_SUCCESS; 221 u32 reg = 0, reg_bp = 0; 222 u16 reg_cu = 0; 223 bool locked = FALSE; 224 225 DEBUGFUNC("ixgbe_setup_fc_generic"); 226 227 /* Validate the requested mode */ 228 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 229 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 230 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 231 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 232 goto out; 233 } 234 235 /* 236 * 10gig parts do not have a word in the EEPROM to determine the 237 * default flow control setting, so we explicitly set it to full. 238 */ 239 if (hw->fc.requested_mode == ixgbe_fc_default) 240 hw->fc.requested_mode = ixgbe_fc_full; 241 242 /* 243 * Set up the 1G and 10G flow control advertisement registers so the 244 * HW will be able to do fc autoneg once the cable is plugged in. If 245 * we link at 10G, the 1G advertisement is harmless and vice versa. 246 */ 247 switch (hw->phy.media_type) { 248 case ixgbe_media_type_backplane: 249 /* some MAC's need RMW protection on AUTOC */ 250 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 251 if (ret_val != IXGBE_SUCCESS) 252 goto out; 253 254 /* only backplane uses autoc so fall though */ 255 case ixgbe_media_type_fiber_fixed: 256 case ixgbe_media_type_fiber_qsfp: 257 case ixgbe_media_type_fiber: 258 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 259 260 break; 261 case ixgbe_media_type_copper: 262 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 263 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 264 break; 265 default: 266 break; 267 } 268 269 /* 270 * The possible values of fc.requested_mode are: 271 * 0: Flow control is completely disabled 272 * 1: Rx flow control is enabled (we can receive pause frames, 273 * but not send pause frames). 274 * 2: Tx flow control is enabled (we can send pause frames but 275 * we do not support receiving pause frames). 276 * 3: Both Rx and Tx flow control (symmetric) are enabled. 277 * other: Invalid. 278 */ 279 switch (hw->fc.requested_mode) { 280 case ixgbe_fc_none: 281 /* Flow control completely disabled by software override. */ 282 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 283 if (hw->phy.media_type == ixgbe_media_type_backplane) 284 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 285 IXGBE_AUTOC_ASM_PAUSE); 286 else if (hw->phy.media_type == ixgbe_media_type_copper) 287 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 288 break; 289 case ixgbe_fc_tx_pause: 290 /* 291 * Tx Flow control is enabled, and Rx Flow control is 292 * disabled by software override. 293 */ 294 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 295 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 296 if (hw->phy.media_type == ixgbe_media_type_backplane) { 297 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 298 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 299 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 300 reg_cu |= IXGBE_TAF_ASM_PAUSE; 301 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 302 } 303 break; 304 case ixgbe_fc_rx_pause: 305 /* 306 * Rx Flow control is enabled and Tx Flow control is 307 * disabled by software override. Since there really 308 * isn't a way to advertise that we are capable of RX 309 * Pause ONLY, we will advertise that we support both 310 * symmetric and asymmetric Rx PAUSE, as such we fall 311 * through to the fc_full statement. Later, we will 312 * disable the adapter's ability to send PAUSE frames. 313 */ 314 case ixgbe_fc_full: 315 /* Flow control (both Rx and Tx) is enabled by SW override. */ 316 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 317 if (hw->phy.media_type == ixgbe_media_type_backplane) 318 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 319 IXGBE_AUTOC_ASM_PAUSE; 320 else if (hw->phy.media_type == ixgbe_media_type_copper) 321 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 322 break; 323 default: 324 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 325 "Flow control param set incorrectly\n"); 326 ret_val = IXGBE_ERR_CONFIG; 327 goto out; 328 break; 329 } 330 331 if (hw->mac.type < ixgbe_mac_X540) { 332 /* 333 * Enable auto-negotiation between the MAC & PHY; 334 * the MAC will advertise clause 37 flow control. 335 */ 336 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 337 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 338 339 /* Disable AN timeout */ 340 if (hw->fc.strict_ieee) 341 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 342 343 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 344 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 345 } 346 347 /* 348 * AUTOC restart handles negotiation of 1G and 10G on backplane 349 * and copper. There is no need to set the PCS1GCTL register. 350 * 351 */ 352 if (hw->phy.media_type == ixgbe_media_type_backplane) { 353 reg_bp |= IXGBE_AUTOC_AN_RESTART; 354 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 355 if (ret_val) 356 goto out; 357 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 358 (ixgbe_device_supports_autoneg_fc(hw))) { 359 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 360 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 361 } 362 363 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 364 out: 365 return ret_val; 366 } 367 368 /** 369 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 370 * @hw: pointer to hardware structure 371 * 372 * Starts the hardware by filling the bus info structure and media type, clears 373 * all on chip counters, initializes receive address registers, multicast 374 * table, VLAN filter table, calls routine to set up link and flow control 375 * settings, and leaves transmit and receive units disabled and uninitialized 376 **/ 377 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 378 { 379 s32 ret_val; 380 u32 ctrl_ext; 381 382 DEBUGFUNC("ixgbe_start_hw_generic"); 383 384 /* Set the media type */ 385 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 386 387 /* PHY ops initialization must be done in reset_hw() */ 388 389 /* Clear the VLAN filter table */ 390 hw->mac.ops.clear_vfta(hw); 391 392 /* Clear statistics registers */ 393 hw->mac.ops.clear_hw_cntrs(hw); 394 395 /* Set No Snoop Disable */ 396 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 397 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 398 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 399 IXGBE_WRITE_FLUSH(hw); 400 401 /* Setup flow control */ 402 ret_val = ixgbe_setup_fc(hw); 403 if (ret_val != IXGBE_SUCCESS) 404 goto out; 405 406 /* Clear adapter stopped flag */ 407 hw->adapter_stopped = FALSE; 408 409 out: 410 return ret_val; 411 } 412 413 /** 414 * ixgbe_start_hw_gen2 - Init sequence for common device family 415 * @hw: pointer to hw structure 416 * 417 * Performs the init sequence common to the second generation 418 * of 10 GbE devices. 419 * Devices in the second generation: 420 * 82599 421 * X540 422 **/ 423 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 424 { 425 u32 i; 426 u32 regval; 427 428 /* Clear the rate limiters */ 429 for (i = 0; i < hw->mac.max_tx_queues; i++) { 430 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 431 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 432 } 433 IXGBE_WRITE_FLUSH(hw); 434 435 /* Disable relaxed ordering */ 436 for (i = 0; i < hw->mac.max_tx_queues; i++) { 437 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 438 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 439 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 440 } 441 442 for (i = 0; i < hw->mac.max_rx_queues; i++) { 443 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 444 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 445 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 446 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 447 } 448 449 return IXGBE_SUCCESS; 450 } 451 452 /** 453 * ixgbe_init_hw_generic - Generic hardware initialization 454 * @hw: pointer to hardware structure 455 * 456 * Initialize the hardware by resetting the hardware, filling the bus info 457 * structure and media type, clears all on chip counters, initializes receive 458 * address registers, multicast table, VLAN filter table, calls routine to set 459 * up link and flow control settings, and leaves transmit and receive units 460 * disabled and uninitialized 461 **/ 462 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 463 { 464 s32 status; 465 466 DEBUGFUNC("ixgbe_init_hw_generic"); 467 468 /* Reset the hardware */ 469 status = hw->mac.ops.reset_hw(hw); 470 471 if (status == IXGBE_SUCCESS) { 472 /* Start the HW */ 473 status = hw->mac.ops.start_hw(hw); 474 } 475 476 return status; 477 } 478 479 /** 480 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 481 * @hw: pointer to hardware structure 482 * 483 * Clears all hardware statistics counters by reading them from the hardware 484 * Statistics counters are clear on read. 485 **/ 486 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 487 { 488 u16 i = 0; 489 490 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 491 492 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 493 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 494 IXGBE_READ_REG(hw, IXGBE_ERRBC); 495 IXGBE_READ_REG(hw, IXGBE_MSPDC); 496 for (i = 0; i < 8; i++) 497 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 498 499 IXGBE_READ_REG(hw, IXGBE_MLFC); 500 IXGBE_READ_REG(hw, IXGBE_MRFC); 501 IXGBE_READ_REG(hw, IXGBE_RLEC); 502 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 503 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 504 if (hw->mac.type >= ixgbe_mac_82599EB) { 505 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 506 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 507 } else { 508 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 509 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 510 } 511 512 for (i = 0; i < 8; i++) { 513 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 514 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 515 if (hw->mac.type >= ixgbe_mac_82599EB) { 516 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 517 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 518 } else { 519 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 520 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 521 } 522 } 523 if (hw->mac.type >= ixgbe_mac_82599EB) 524 for (i = 0; i < 8; i++) 525 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 526 IXGBE_READ_REG(hw, IXGBE_PRC64); 527 IXGBE_READ_REG(hw, IXGBE_PRC127); 528 IXGBE_READ_REG(hw, IXGBE_PRC255); 529 IXGBE_READ_REG(hw, IXGBE_PRC511); 530 IXGBE_READ_REG(hw, IXGBE_PRC1023); 531 IXGBE_READ_REG(hw, IXGBE_PRC1522); 532 IXGBE_READ_REG(hw, IXGBE_GPRC); 533 IXGBE_READ_REG(hw, IXGBE_BPRC); 534 IXGBE_READ_REG(hw, IXGBE_MPRC); 535 IXGBE_READ_REG(hw, IXGBE_GPTC); 536 IXGBE_READ_REG(hw, IXGBE_GORCL); 537 IXGBE_READ_REG(hw, IXGBE_GORCH); 538 IXGBE_READ_REG(hw, IXGBE_GOTCL); 539 IXGBE_READ_REG(hw, IXGBE_GOTCH); 540 if (hw->mac.type == ixgbe_mac_82598EB) 541 for (i = 0; i < 8; i++) 542 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 543 IXGBE_READ_REG(hw, IXGBE_RUC); 544 IXGBE_READ_REG(hw, IXGBE_RFC); 545 IXGBE_READ_REG(hw, IXGBE_ROC); 546 IXGBE_READ_REG(hw, IXGBE_RJC); 547 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 548 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 549 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 550 IXGBE_READ_REG(hw, IXGBE_TORL); 551 IXGBE_READ_REG(hw, IXGBE_TORH); 552 IXGBE_READ_REG(hw, IXGBE_TPR); 553 IXGBE_READ_REG(hw, IXGBE_TPT); 554 IXGBE_READ_REG(hw, IXGBE_PTC64); 555 IXGBE_READ_REG(hw, IXGBE_PTC127); 556 IXGBE_READ_REG(hw, IXGBE_PTC255); 557 IXGBE_READ_REG(hw, IXGBE_PTC511); 558 IXGBE_READ_REG(hw, IXGBE_PTC1023); 559 IXGBE_READ_REG(hw, IXGBE_PTC1522); 560 IXGBE_READ_REG(hw, IXGBE_MPTC); 561 IXGBE_READ_REG(hw, IXGBE_BPTC); 562 for (i = 0; i < 16; i++) { 563 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 564 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 565 if (hw->mac.type >= ixgbe_mac_82599EB) { 566 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 567 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 568 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 569 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 570 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 571 } else { 572 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 573 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 574 } 575 } 576 577 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 578 if (hw->phy.id == 0) 579 ixgbe_identify_phy(hw); 580 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 581 IXGBE_MDIO_PCS_DEV_TYPE, &i); 582 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 583 IXGBE_MDIO_PCS_DEV_TYPE, &i); 584 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 585 IXGBE_MDIO_PCS_DEV_TYPE, &i); 586 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 587 IXGBE_MDIO_PCS_DEV_TYPE, &i); 588 } 589 590 return IXGBE_SUCCESS; 591 } 592 593 /** 594 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 595 * @hw: pointer to hardware structure 596 * @pba_num: stores the part number string from the EEPROM 597 * @pba_num_size: part number string buffer length 598 * 599 * Reads the part number string from the EEPROM. 600 **/ 601 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 602 u32 pba_num_size) 603 { 604 s32 ret_val; 605 u16 data; 606 u16 pba_ptr; 607 u16 offset; 608 u16 length; 609 610 DEBUGFUNC("ixgbe_read_pba_string_generic"); 611 612 if (pba_num == NULL) { 613 DEBUGOUT("PBA string buffer was null\n"); 614 return IXGBE_ERR_INVALID_ARGUMENT; 615 } 616 617 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 618 if (ret_val) { 619 DEBUGOUT("NVM Read Error\n"); 620 return ret_val; 621 } 622 623 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 624 if (ret_val) { 625 DEBUGOUT("NVM Read Error\n"); 626 return ret_val; 627 } 628 629 /* 630 * if data is not ptr guard the PBA must be in legacy format which 631 * means pba_ptr is actually our second data word for the PBA number 632 * and we can decode it into an ascii string 633 */ 634 if (data != IXGBE_PBANUM_PTR_GUARD) { 635 DEBUGOUT("NVM PBA number is not stored as string\n"); 636 637 /* we will need 11 characters to store the PBA */ 638 if (pba_num_size < 11) { 639 DEBUGOUT("PBA string buffer too small\n"); 640 return IXGBE_ERR_NO_SPACE; 641 } 642 643 /* extract hex string from data and pba_ptr */ 644 pba_num[0] = (data >> 12) & 0xF; 645 pba_num[1] = (data >> 8) & 0xF; 646 pba_num[2] = (data >> 4) & 0xF; 647 pba_num[3] = data & 0xF; 648 pba_num[4] = (pba_ptr >> 12) & 0xF; 649 pba_num[5] = (pba_ptr >> 8) & 0xF; 650 pba_num[6] = '-'; 651 pba_num[7] = 0; 652 pba_num[8] = (pba_ptr >> 4) & 0xF; 653 pba_num[9] = pba_ptr & 0xF; 654 655 /* put a null character on the end of our string */ 656 pba_num[10] = '\0'; 657 658 /* switch all the data but the '-' to hex char */ 659 for (offset = 0; offset < 10; offset++) { 660 if (pba_num[offset] < 0xA) 661 pba_num[offset] += '0'; 662 else if (pba_num[offset] < 0x10) 663 pba_num[offset] += 'A' - 0xA; 664 } 665 666 return IXGBE_SUCCESS; 667 } 668 669 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 670 if (ret_val) { 671 DEBUGOUT("NVM Read Error\n"); 672 return ret_val; 673 } 674 675 if (length == 0xFFFF || length == 0) { 676 DEBUGOUT("NVM PBA number section invalid length\n"); 677 return IXGBE_ERR_PBA_SECTION; 678 } 679 680 /* check if pba_num buffer is big enough */ 681 if (pba_num_size < (((u32)length * 2) - 1)) { 682 DEBUGOUT("PBA string buffer too small\n"); 683 return IXGBE_ERR_NO_SPACE; 684 } 685 686 /* trim pba length from start of string */ 687 pba_ptr++; 688 length--; 689 690 for (offset = 0; offset < length; offset++) { 691 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 692 if (ret_val) { 693 DEBUGOUT("NVM Read Error\n"); 694 return ret_val; 695 } 696 pba_num[offset * 2] = (u8)(data >> 8); 697 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 698 } 699 pba_num[offset * 2] = '\0'; 700 701 return IXGBE_SUCCESS; 702 } 703 704 /** 705 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 706 * @hw: pointer to hardware structure 707 * @pba_num: stores the part number from the EEPROM 708 * 709 * Reads the part number from the EEPROM. 710 **/ 711 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 712 { 713 s32 ret_val; 714 u16 data; 715 716 DEBUGFUNC("ixgbe_read_pba_num_generic"); 717 718 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 719 if (ret_val) { 720 DEBUGOUT("NVM Read Error\n"); 721 return ret_val; 722 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 723 DEBUGOUT("NVM Not supported\n"); 724 return IXGBE_NOT_IMPLEMENTED; 725 } 726 *pba_num = (u32)(data << 16); 727 728 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 729 if (ret_val) { 730 DEBUGOUT("NVM Read Error\n"); 731 return ret_val; 732 } 733 *pba_num |= data; 734 735 return IXGBE_SUCCESS; 736 } 737 738 /** 739 * ixgbe_read_pba_raw 740 * @hw: pointer to the HW structure 741 * @eeprom_buf: optional pointer to EEPROM image 742 * @eeprom_buf_size: size of EEPROM image in words 743 * @max_pba_block_size: PBA block size limit 744 * @pba: pointer to output PBA structure 745 * 746 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 747 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 748 * 749 **/ 750 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 751 u32 eeprom_buf_size, u16 max_pba_block_size, 752 struct ixgbe_pba *pba) 753 { 754 s32 ret_val; 755 u16 pba_block_size; 756 757 if (pba == NULL) 758 return IXGBE_ERR_PARAM; 759 760 if (eeprom_buf == NULL) { 761 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 762 &pba->word[0]); 763 if (ret_val) 764 return ret_val; 765 } else { 766 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 767 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 768 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 769 } else { 770 return IXGBE_ERR_PARAM; 771 } 772 } 773 774 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 775 if (pba->pba_block == NULL) 776 return IXGBE_ERR_PARAM; 777 778 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 779 eeprom_buf_size, 780 &pba_block_size); 781 if (ret_val) 782 return ret_val; 783 784 if (pba_block_size > max_pba_block_size) 785 return IXGBE_ERR_PARAM; 786 787 if (eeprom_buf == NULL) { 788 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 789 pba_block_size, 790 pba->pba_block); 791 if (ret_val) 792 return ret_val; 793 } else { 794 if (eeprom_buf_size > (u32)(pba->word[1] + 795 pba_block_size)) { 796 memcpy(pba->pba_block, 797 &eeprom_buf[pba->word[1]], 798 pba_block_size * sizeof(u16)); 799 } else { 800 return IXGBE_ERR_PARAM; 801 } 802 } 803 } 804 805 return IXGBE_SUCCESS; 806 } 807 808 /** 809 * ixgbe_write_pba_raw 810 * @hw: pointer to the HW structure 811 * @eeprom_buf: optional pointer to EEPROM image 812 * @eeprom_buf_size: size of EEPROM image in words 813 * @pba: pointer to PBA structure 814 * 815 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 816 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 817 * 818 **/ 819 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 820 u32 eeprom_buf_size, struct ixgbe_pba *pba) 821 { 822 s32 ret_val; 823 824 if (pba == NULL) 825 return IXGBE_ERR_PARAM; 826 827 if (eeprom_buf == NULL) { 828 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 829 &pba->word[0]); 830 if (ret_val) 831 return ret_val; 832 } else { 833 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 834 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 835 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 836 } else { 837 return IXGBE_ERR_PARAM; 838 } 839 } 840 841 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 842 if (pba->pba_block == NULL) 843 return IXGBE_ERR_PARAM; 844 845 if (eeprom_buf == NULL) { 846 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 847 pba->pba_block[0], 848 pba->pba_block); 849 if (ret_val) 850 return ret_val; 851 } else { 852 if (eeprom_buf_size > (u32)(pba->word[1] + 853 pba->pba_block[0])) { 854 memcpy(&eeprom_buf[pba->word[1]], 855 pba->pba_block, 856 pba->pba_block[0] * sizeof(u16)); 857 } else { 858 return IXGBE_ERR_PARAM; 859 } 860 } 861 } 862 863 return IXGBE_SUCCESS; 864 } 865 866 /** 867 * ixgbe_get_pba_block_size 868 * @hw: pointer to the HW structure 869 * @eeprom_buf: optional pointer to EEPROM image 870 * @eeprom_buf_size: size of EEPROM image in words 871 * @pba_data_size: pointer to output variable 872 * 873 * Returns the size of the PBA block in words. Function operates on EEPROM 874 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 875 * EEPROM device. 876 * 877 **/ 878 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 879 u32 eeprom_buf_size, u16 *pba_block_size) 880 { 881 s32 ret_val; 882 u16 pba_word[2]; 883 u16 length; 884 885 DEBUGFUNC("ixgbe_get_pba_block_size"); 886 887 if (eeprom_buf == NULL) { 888 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 889 &pba_word[0]); 890 if (ret_val) 891 return ret_val; 892 } else { 893 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 894 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 895 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 896 } else { 897 return IXGBE_ERR_PARAM; 898 } 899 } 900 901 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 902 if (eeprom_buf == NULL) { 903 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 904 &length); 905 if (ret_val) 906 return ret_val; 907 } else { 908 if (eeprom_buf_size > pba_word[1]) 909 length = eeprom_buf[pba_word[1] + 0]; 910 else 911 return IXGBE_ERR_PARAM; 912 } 913 914 if (length == 0xFFFF || length == 0) 915 return IXGBE_ERR_PBA_SECTION; 916 } else { 917 /* PBA number in legacy format, there is no PBA Block. */ 918 length = 0; 919 } 920 921 if (pba_block_size != NULL) 922 *pba_block_size = length; 923 924 return IXGBE_SUCCESS; 925 } 926 927 /** 928 * ixgbe_get_mac_addr_generic - Generic get MAC address 929 * @hw: pointer to hardware structure 930 * @mac_addr: Adapter MAC address 931 * 932 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 933 * A reset of the adapter must be performed prior to calling this function 934 * in order for the MAC address to have been loaded from the EEPROM into RAR0 935 **/ 936 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 937 { 938 u32 rar_high; 939 u32 rar_low; 940 u16 i; 941 942 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 943 944 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 945 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 946 947 for (i = 0; i < 4; i++) 948 mac_addr[i] = (u8)(rar_low >> (i*8)); 949 950 for (i = 0; i < 2; i++) 951 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 952 953 return IXGBE_SUCCESS; 954 } 955 956 /** 957 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 958 * @hw: pointer to hardware structure 959 * @link_status: the link status returned by the PCI config space 960 * 961 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 962 **/ 963 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 964 { 965 struct ixgbe_mac_info *mac = &hw->mac; 966 967 if (hw->bus.type == ixgbe_bus_type_unknown) 968 hw->bus.type = ixgbe_bus_type_pci_express; 969 970 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 971 case IXGBE_PCI_LINK_WIDTH_1: 972 hw->bus.width = ixgbe_bus_width_pcie_x1; 973 break; 974 case IXGBE_PCI_LINK_WIDTH_2: 975 hw->bus.width = ixgbe_bus_width_pcie_x2; 976 break; 977 case IXGBE_PCI_LINK_WIDTH_4: 978 hw->bus.width = ixgbe_bus_width_pcie_x4; 979 break; 980 case IXGBE_PCI_LINK_WIDTH_8: 981 hw->bus.width = ixgbe_bus_width_pcie_x8; 982 break; 983 default: 984 hw->bus.width = ixgbe_bus_width_unknown; 985 break; 986 } 987 988 switch (link_status & IXGBE_PCI_LINK_SPEED) { 989 case IXGBE_PCI_LINK_SPEED_2500: 990 hw->bus.speed = ixgbe_bus_speed_2500; 991 break; 992 case IXGBE_PCI_LINK_SPEED_5000: 993 hw->bus.speed = ixgbe_bus_speed_5000; 994 break; 995 case IXGBE_PCI_LINK_SPEED_8000: 996 hw->bus.speed = ixgbe_bus_speed_8000; 997 break; 998 default: 999 hw->bus.speed = ixgbe_bus_speed_unknown; 1000 break; 1001 } 1002 1003 mac->ops.set_lan_id(hw); 1004 } 1005 1006 /** 1007 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1008 * @hw: pointer to hardware structure 1009 * 1010 * Gets the PCI bus info (speed, width, type) then calls helper function to 1011 * store this data within the ixgbe_hw structure. 1012 **/ 1013 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1014 { 1015 u16 link_status; 1016 1017 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1018 1019 /* Get the negotiated link width and speed from PCI config space */ 1020 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 1021 1022 ixgbe_set_pci_config_data_generic(hw, link_status); 1023 1024 return IXGBE_SUCCESS; 1025 } 1026 1027 /** 1028 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1029 * @hw: pointer to the HW structure 1030 * 1031 * Determines the LAN function id by reading memory-mapped registers 1032 * and swaps the port value if requested. 1033 **/ 1034 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1035 { 1036 struct ixgbe_bus_info *bus = &hw->bus; 1037 u32 reg; 1038 1039 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1040 1041 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1042 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1043 bus->lan_id = bus->func; 1044 1045 /* check for a port swap */ 1046 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1047 if (reg & IXGBE_FACTPS_LFS) 1048 bus->func ^= 0x1; 1049 } 1050 1051 /** 1052 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1053 * @hw: pointer to hardware structure 1054 * 1055 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1056 * disables transmit and receive units. The adapter_stopped flag is used by 1057 * the shared code and drivers to determine if the adapter is in a stopped 1058 * state and should not touch the hardware. 1059 **/ 1060 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1061 { 1062 u32 reg_val; 1063 u16 i; 1064 1065 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1066 1067 /* 1068 * Set the adapter_stopped flag so other driver functions stop touching 1069 * the hardware 1070 */ 1071 hw->adapter_stopped = TRUE; 1072 1073 /* Disable the receive unit */ 1074 ixgbe_disable_rx(hw); 1075 1076 /* Clear interrupt mask to stop interrupts from being generated */ 1077 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 1078 1079 /* Clear any pending interrupts, flush previous writes */ 1080 IXGBE_READ_REG(hw, IXGBE_EICR); 1081 1082 /* Disable the transmit unit. Each queue must be disabled. */ 1083 for (i = 0; i < hw->mac.max_tx_queues; i++) 1084 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1085 1086 /* Disable the receive unit by stopping each queue */ 1087 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1088 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1089 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1090 reg_val |= IXGBE_RXDCTL_SWFLSH; 1091 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1092 } 1093 1094 /* flush all queues disables */ 1095 IXGBE_WRITE_FLUSH(hw); 1096 msec_delay(2); 1097 1098 /* 1099 * Prevent the PCI-E bus from hanging by disabling PCI-E master 1100 * access and verify no pending requests 1101 */ 1102 return ixgbe_disable_pcie_master(hw); 1103 } 1104 1105 /** 1106 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1107 * @hw: pointer to hardware structure 1108 * @index: led number to turn on 1109 **/ 1110 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1111 { 1112 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1113 1114 DEBUGFUNC("ixgbe_led_on_generic"); 1115 1116 /* To turn on the LED, set mode to ON. */ 1117 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1118 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1119 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1120 IXGBE_WRITE_FLUSH(hw); 1121 1122 return IXGBE_SUCCESS; 1123 } 1124 1125 /** 1126 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1127 * @hw: pointer to hardware structure 1128 * @index: led number to turn off 1129 **/ 1130 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1131 { 1132 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1133 1134 DEBUGFUNC("ixgbe_led_off_generic"); 1135 1136 /* To turn off the LED, set mode to OFF. */ 1137 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1138 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1139 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1140 IXGBE_WRITE_FLUSH(hw); 1141 1142 return IXGBE_SUCCESS; 1143 } 1144 1145 /** 1146 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1147 * @hw: pointer to hardware structure 1148 * 1149 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1150 * ixgbe_hw struct in order to set up EEPROM access. 1151 **/ 1152 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1153 { 1154 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1155 u32 eec; 1156 u16 eeprom_size; 1157 1158 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1159 1160 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1161 eeprom->type = ixgbe_eeprom_none; 1162 /* Set default semaphore delay to 10ms which is a well 1163 * tested value */ 1164 eeprom->semaphore_delay = 10; 1165 /* Clear EEPROM page size, it will be initialized as needed */ 1166 eeprom->word_page_size = 0; 1167 1168 /* 1169 * Check for EEPROM present first. 1170 * If not present leave as none 1171 */ 1172 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1173 if (eec & IXGBE_EEC_PRES) { 1174 eeprom->type = ixgbe_eeprom_spi; 1175 1176 /* 1177 * SPI EEPROM is assumed here. This code would need to 1178 * change if a future EEPROM is not SPI. 1179 */ 1180 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1181 IXGBE_EEC_SIZE_SHIFT); 1182 eeprom->word_size = 1 << (eeprom_size + 1183 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1184 } 1185 1186 if (eec & IXGBE_EEC_ADDR_SIZE) 1187 eeprom->address_bits = 16; 1188 else 1189 eeprom->address_bits = 8; 1190 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1191 "%d\n", eeprom->type, eeprom->word_size, 1192 eeprom->address_bits); 1193 } 1194 1195 return IXGBE_SUCCESS; 1196 } 1197 1198 /** 1199 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1200 * @hw: pointer to hardware structure 1201 * @offset: offset within the EEPROM to write 1202 * @words: number of word(s) 1203 * @data: 16 bit word(s) to write to EEPROM 1204 * 1205 * Reads 16 bit word(s) from EEPROM through bit-bang method 1206 **/ 1207 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1208 u16 words, u16 *data) 1209 { 1210 s32 status = IXGBE_SUCCESS; 1211 u16 i, count; 1212 1213 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1214 1215 hw->eeprom.ops.init_params(hw); 1216 1217 if (words == 0) { 1218 status = IXGBE_ERR_INVALID_ARGUMENT; 1219 goto out; 1220 } 1221 1222 if (offset + words > hw->eeprom.word_size) { 1223 status = IXGBE_ERR_EEPROM; 1224 goto out; 1225 } 1226 1227 /* 1228 * The EEPROM page size cannot be queried from the chip. We do lazy 1229 * initialization. It is worth to do that when we write large buffer. 1230 */ 1231 if ((hw->eeprom.word_page_size == 0) && 1232 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1233 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1234 1235 /* 1236 * We cannot hold synchronization semaphores for too long 1237 * to avoid other entity starvation. However it is more efficient 1238 * to read in bursts than synchronizing access for each word. 1239 */ 1240 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1241 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1242 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1243 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1244 count, &data[i]); 1245 1246 if (status != IXGBE_SUCCESS) 1247 break; 1248 } 1249 1250 out: 1251 return status; 1252 } 1253 1254 /** 1255 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1256 * @hw: pointer to hardware structure 1257 * @offset: offset within the EEPROM to be written to 1258 * @words: number of word(s) 1259 * @data: 16 bit word(s) to be written to the EEPROM 1260 * 1261 * If ixgbe_eeprom_update_checksum is not called after this function, the 1262 * EEPROM will most likely contain an invalid checksum. 1263 **/ 1264 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1265 u16 words, u16 *data) 1266 { 1267 s32 status; 1268 u16 word; 1269 u16 page_size; 1270 u16 i; 1271 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1272 1273 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1274 1275 /* Prepare the EEPROM for writing */ 1276 status = ixgbe_acquire_eeprom(hw); 1277 1278 if (status == IXGBE_SUCCESS) { 1279 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1280 ixgbe_release_eeprom(hw); 1281 status = IXGBE_ERR_EEPROM; 1282 } 1283 } 1284 1285 if (status == IXGBE_SUCCESS) { 1286 for (i = 0; i < words; i++) { 1287 ixgbe_standby_eeprom(hw); 1288 1289 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1290 ixgbe_shift_out_eeprom_bits(hw, 1291 IXGBE_EEPROM_WREN_OPCODE_SPI, 1292 IXGBE_EEPROM_OPCODE_BITS); 1293 1294 ixgbe_standby_eeprom(hw); 1295 1296 /* 1297 * Some SPI eeproms use the 8th address bit embedded 1298 * in the opcode 1299 */ 1300 if ((hw->eeprom.address_bits == 8) && 1301 ((offset + i) >= 128)) 1302 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1303 1304 /* Send the Write command (8-bit opcode + addr) */ 1305 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1306 IXGBE_EEPROM_OPCODE_BITS); 1307 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1308 hw->eeprom.address_bits); 1309 1310 page_size = hw->eeprom.word_page_size; 1311 1312 /* Send the data in burst via SPI*/ 1313 do { 1314 word = data[i]; 1315 word = (word >> 8) | (word << 8); 1316 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1317 1318 if (page_size == 0) 1319 break; 1320 1321 /* do not wrap around page */ 1322 if (((offset + i) & (page_size - 1)) == 1323 (page_size - 1)) 1324 break; 1325 } while (++i < words); 1326 1327 ixgbe_standby_eeprom(hw); 1328 msec_delay(10); 1329 } 1330 /* Done with writing - release the EEPROM */ 1331 ixgbe_release_eeprom(hw); 1332 } 1333 1334 return status; 1335 } 1336 1337 /** 1338 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1339 * @hw: pointer to hardware structure 1340 * @offset: offset within the EEPROM to be written to 1341 * @data: 16 bit word to be written to the EEPROM 1342 * 1343 * If ixgbe_eeprom_update_checksum is not called after this function, the 1344 * EEPROM will most likely contain an invalid checksum. 1345 **/ 1346 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1347 { 1348 s32 status; 1349 1350 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1351 1352 hw->eeprom.ops.init_params(hw); 1353 1354 if (offset >= hw->eeprom.word_size) { 1355 status = IXGBE_ERR_EEPROM; 1356 goto out; 1357 } 1358 1359 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1360 1361 out: 1362 return status; 1363 } 1364 1365 /** 1366 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1367 * @hw: pointer to hardware structure 1368 * @offset: offset within the EEPROM to be read 1369 * @data: read 16 bit words(s) from EEPROM 1370 * @words: number of word(s) 1371 * 1372 * Reads 16 bit word(s) from EEPROM through bit-bang method 1373 **/ 1374 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1375 u16 words, u16 *data) 1376 { 1377 s32 status = IXGBE_SUCCESS; 1378 u16 i, count; 1379 1380 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1381 1382 hw->eeprom.ops.init_params(hw); 1383 1384 if (words == 0) { 1385 status = IXGBE_ERR_INVALID_ARGUMENT; 1386 goto out; 1387 } 1388 1389 if (offset + words > hw->eeprom.word_size) { 1390 status = IXGBE_ERR_EEPROM; 1391 goto out; 1392 } 1393 1394 /* 1395 * We cannot hold synchronization semaphores for too long 1396 * to avoid other entity starvation. However it is more efficient 1397 * to read in bursts than synchronizing access for each word. 1398 */ 1399 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1400 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1401 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1402 1403 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1404 count, &data[i]); 1405 1406 if (status != IXGBE_SUCCESS) 1407 break; 1408 } 1409 1410 out: 1411 return status; 1412 } 1413 1414 /** 1415 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1416 * @hw: pointer to hardware structure 1417 * @offset: offset within the EEPROM to be read 1418 * @words: number of word(s) 1419 * @data: read 16 bit word(s) from EEPROM 1420 * 1421 * Reads 16 bit word(s) from EEPROM through bit-bang method 1422 **/ 1423 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1424 u16 words, u16 *data) 1425 { 1426 s32 status; 1427 u16 word_in; 1428 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1429 u16 i; 1430 1431 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1432 1433 /* Prepare the EEPROM for reading */ 1434 status = ixgbe_acquire_eeprom(hw); 1435 1436 if (status == IXGBE_SUCCESS) { 1437 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1438 ixgbe_release_eeprom(hw); 1439 status = IXGBE_ERR_EEPROM; 1440 } 1441 } 1442 1443 if (status == IXGBE_SUCCESS) { 1444 for (i = 0; i < words; i++) { 1445 ixgbe_standby_eeprom(hw); 1446 /* 1447 * Some SPI eeproms use the 8th address bit embedded 1448 * in the opcode 1449 */ 1450 if ((hw->eeprom.address_bits == 8) && 1451 ((offset + i) >= 128)) 1452 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1453 1454 /* Send the READ command (opcode + addr) */ 1455 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1456 IXGBE_EEPROM_OPCODE_BITS); 1457 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1458 hw->eeprom.address_bits); 1459 1460 /* Read the data. */ 1461 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1462 data[i] = (word_in >> 8) | (word_in << 8); 1463 } 1464 1465 /* End this read operation */ 1466 ixgbe_release_eeprom(hw); 1467 } 1468 1469 return status; 1470 } 1471 1472 /** 1473 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1474 * @hw: pointer to hardware structure 1475 * @offset: offset within the EEPROM to be read 1476 * @data: read 16 bit value from EEPROM 1477 * 1478 * Reads 16 bit value from EEPROM through bit-bang method 1479 **/ 1480 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1481 u16 *data) 1482 { 1483 s32 status; 1484 1485 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1486 1487 hw->eeprom.ops.init_params(hw); 1488 1489 if (offset >= hw->eeprom.word_size) { 1490 status = IXGBE_ERR_EEPROM; 1491 goto out; 1492 } 1493 1494 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1495 1496 out: 1497 return status; 1498 } 1499 1500 /** 1501 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1502 * @hw: pointer to hardware structure 1503 * @offset: offset of word in the EEPROM to read 1504 * @words: number of word(s) 1505 * @data: 16 bit word(s) from the EEPROM 1506 * 1507 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1508 **/ 1509 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1510 u16 words, u16 *data) 1511 { 1512 u32 eerd; 1513 s32 status = IXGBE_SUCCESS; 1514 u32 i; 1515 1516 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1517 1518 hw->eeprom.ops.init_params(hw); 1519 1520 if (words == 0) { 1521 status = IXGBE_ERR_INVALID_ARGUMENT; 1522 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1523 goto out; 1524 } 1525 1526 if (offset >= hw->eeprom.word_size) { 1527 status = IXGBE_ERR_EEPROM; 1528 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1529 goto out; 1530 } 1531 1532 for (i = 0; i < words; i++) { 1533 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1534 IXGBE_EEPROM_RW_REG_START; 1535 1536 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1537 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1538 1539 if (status == IXGBE_SUCCESS) { 1540 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1541 IXGBE_EEPROM_RW_REG_DATA); 1542 } else { 1543 DEBUGOUT("Eeprom read timed out\n"); 1544 goto out; 1545 } 1546 } 1547 out: 1548 return status; 1549 } 1550 1551 /** 1552 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1553 * @hw: pointer to hardware structure 1554 * @offset: offset within the EEPROM to be used as a scratch pad 1555 * 1556 * Discover EEPROM page size by writing marching data at given offset. 1557 * This function is called only when we are writing a new large buffer 1558 * at given offset so the data would be overwritten anyway. 1559 **/ 1560 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1561 u16 offset) 1562 { 1563 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1564 s32 status = IXGBE_SUCCESS; 1565 u16 i; 1566 1567 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1568 1569 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1570 data[i] = i; 1571 1572 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1573 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1574 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1575 hw->eeprom.word_page_size = 0; 1576 if (status != IXGBE_SUCCESS) 1577 goto out; 1578 1579 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1580 if (status != IXGBE_SUCCESS) 1581 goto out; 1582 1583 /* 1584 * When writing in burst more than the actual page size 1585 * EEPROM address wraps around current page. 1586 */ 1587 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1588 1589 DEBUGOUT1("Detected EEPROM page size = %d words.", 1590 hw->eeprom.word_page_size); 1591 out: 1592 return status; 1593 } 1594 1595 /** 1596 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1597 * @hw: pointer to hardware structure 1598 * @offset: offset of word in the EEPROM to read 1599 * @data: word read from the EEPROM 1600 * 1601 * Reads a 16 bit word from the EEPROM using the EERD register. 1602 **/ 1603 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1604 { 1605 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1606 } 1607 1608 /** 1609 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1610 * @hw: pointer to hardware structure 1611 * @offset: offset of word in the EEPROM to write 1612 * @words: number of word(s) 1613 * @data: word(s) write to the EEPROM 1614 * 1615 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1616 **/ 1617 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1618 u16 words, u16 *data) 1619 { 1620 u32 eewr; 1621 s32 status = IXGBE_SUCCESS; 1622 u16 i; 1623 1624 DEBUGFUNC("ixgbe_write_eewr_generic"); 1625 1626 hw->eeprom.ops.init_params(hw); 1627 1628 if (words == 0) { 1629 status = IXGBE_ERR_INVALID_ARGUMENT; 1630 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1631 goto out; 1632 } 1633 1634 if (offset >= hw->eeprom.word_size) { 1635 status = IXGBE_ERR_EEPROM; 1636 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1637 goto out; 1638 } 1639 1640 for (i = 0; i < words; i++) { 1641 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1642 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1643 IXGBE_EEPROM_RW_REG_START; 1644 1645 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1646 if (status != IXGBE_SUCCESS) { 1647 DEBUGOUT("Eeprom write EEWR timed out\n"); 1648 goto out; 1649 } 1650 1651 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1652 1653 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1654 if (status != IXGBE_SUCCESS) { 1655 DEBUGOUT("Eeprom write EEWR timed out\n"); 1656 goto out; 1657 } 1658 } 1659 1660 out: 1661 return status; 1662 } 1663 1664 /** 1665 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1666 * @hw: pointer to hardware structure 1667 * @offset: offset of word in the EEPROM to write 1668 * @data: word write to the EEPROM 1669 * 1670 * Write a 16 bit word to the EEPROM using the EEWR register. 1671 **/ 1672 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1673 { 1674 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1675 } 1676 1677 /** 1678 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1679 * @hw: pointer to hardware structure 1680 * @ee_reg: EEPROM flag for polling 1681 * 1682 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1683 * read or write is done respectively. 1684 **/ 1685 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1686 { 1687 u32 i; 1688 u32 reg; 1689 s32 status = IXGBE_ERR_EEPROM; 1690 1691 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1692 1693 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1694 if (ee_reg == IXGBE_NVM_POLL_READ) 1695 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1696 else 1697 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1698 1699 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1700 status = IXGBE_SUCCESS; 1701 break; 1702 } 1703 usec_delay(5); 1704 } 1705 1706 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1707 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1708 "EEPROM read/write done polling timed out"); 1709 1710 return status; 1711 } 1712 1713 /** 1714 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1715 * @hw: pointer to hardware structure 1716 * 1717 * Prepares EEPROM for access using bit-bang method. This function should 1718 * be called before issuing a command to the EEPROM. 1719 **/ 1720 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1721 { 1722 s32 status = IXGBE_SUCCESS; 1723 u32 eec; 1724 u32 i; 1725 1726 DEBUGFUNC("ixgbe_acquire_eeprom"); 1727 1728 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1729 != IXGBE_SUCCESS) 1730 status = IXGBE_ERR_SWFW_SYNC; 1731 1732 if (status == IXGBE_SUCCESS) { 1733 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1734 1735 /* Request EEPROM Access */ 1736 eec |= IXGBE_EEC_REQ; 1737 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1738 1739 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1740 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1741 if (eec & IXGBE_EEC_GNT) 1742 break; 1743 usec_delay(5); 1744 } 1745 1746 /* Release if grant not acquired */ 1747 if (!(eec & IXGBE_EEC_GNT)) { 1748 eec &= ~IXGBE_EEC_REQ; 1749 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1750 DEBUGOUT("Could not acquire EEPROM grant\n"); 1751 1752 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1753 status = IXGBE_ERR_EEPROM; 1754 } 1755 1756 /* Setup EEPROM for Read/Write */ 1757 if (status == IXGBE_SUCCESS) { 1758 /* Clear CS and SK */ 1759 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1760 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1761 IXGBE_WRITE_FLUSH(hw); 1762 usec_delay(1); 1763 } 1764 } 1765 return status; 1766 } 1767 1768 /** 1769 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1770 * @hw: pointer to hardware structure 1771 * 1772 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1773 **/ 1774 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1775 { 1776 s32 status = IXGBE_ERR_EEPROM; 1777 u32 timeout = 2000; 1778 u32 i; 1779 u32 swsm; 1780 1781 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1782 1783 1784 /* Get SMBI software semaphore between device drivers first */ 1785 for (i = 0; i < timeout; i++) { 1786 /* 1787 * If the SMBI bit is 0 when we read it, then the bit will be 1788 * set and we have the semaphore 1789 */ 1790 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1791 if (!(swsm & IXGBE_SWSM_SMBI)) { 1792 status = IXGBE_SUCCESS; 1793 break; 1794 } 1795 usec_delay(50); 1796 } 1797 1798 if (i == timeout) { 1799 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1800 "not granted.\n"); 1801 /* 1802 * this release is particularly important because our attempts 1803 * above to get the semaphore may have succeeded, and if there 1804 * was a timeout, we should unconditionally clear the semaphore 1805 * bits to free the driver to make progress 1806 */ 1807 ixgbe_release_eeprom_semaphore(hw); 1808 1809 usec_delay(50); 1810 /* 1811 * one last try 1812 * If the SMBI bit is 0 when we read it, then the bit will be 1813 * set and we have the semaphore 1814 */ 1815 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1816 if (!(swsm & IXGBE_SWSM_SMBI)) 1817 status = IXGBE_SUCCESS; 1818 } 1819 1820 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1821 if (status == IXGBE_SUCCESS) { 1822 for (i = 0; i < timeout; i++) { 1823 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1824 1825 /* Set the SW EEPROM semaphore bit to request access */ 1826 swsm |= IXGBE_SWSM_SWESMBI; 1827 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1828 1829 /* 1830 * If we set the bit successfully then we got the 1831 * semaphore. 1832 */ 1833 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1834 if (swsm & IXGBE_SWSM_SWESMBI) 1835 break; 1836 1837 usec_delay(50); 1838 } 1839 1840 /* 1841 * Release semaphores and return error if SW EEPROM semaphore 1842 * was not granted because we don't have access to the EEPROM 1843 */ 1844 if (i >= timeout) { 1845 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1846 "SWESMBI Software EEPROM semaphore not granted.\n"); 1847 ixgbe_release_eeprom_semaphore(hw); 1848 status = IXGBE_ERR_EEPROM; 1849 } 1850 } else { 1851 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1852 "Software semaphore SMBI between device drivers " 1853 "not granted.\n"); 1854 } 1855 1856 return status; 1857 } 1858 1859 /** 1860 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1861 * @hw: pointer to hardware structure 1862 * 1863 * This function clears hardware semaphore bits. 1864 **/ 1865 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1866 { 1867 u32 swsm; 1868 1869 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1870 1871 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1872 1873 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1874 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1875 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1876 IXGBE_WRITE_FLUSH(hw); 1877 } 1878 1879 /** 1880 * ixgbe_ready_eeprom - Polls for EEPROM ready 1881 * @hw: pointer to hardware structure 1882 **/ 1883 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1884 { 1885 s32 status = IXGBE_SUCCESS; 1886 u16 i; 1887 u8 spi_stat_reg; 1888 1889 DEBUGFUNC("ixgbe_ready_eeprom"); 1890 1891 /* 1892 * Read "Status Register" repeatedly until the LSB is cleared. The 1893 * EEPROM will signal that the command has been completed by clearing 1894 * bit 0 of the internal status register. If it's not cleared within 1895 * 5 milliseconds, then error out. 1896 */ 1897 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1898 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1899 IXGBE_EEPROM_OPCODE_BITS); 1900 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1901 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1902 break; 1903 1904 usec_delay(5); 1905 ixgbe_standby_eeprom(hw); 1906 } 1907 1908 /* 1909 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1910 * devices (and only 0-5mSec on 5V devices) 1911 */ 1912 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1913 DEBUGOUT("SPI EEPROM Status error\n"); 1914 status = IXGBE_ERR_EEPROM; 1915 } 1916 1917 return status; 1918 } 1919 1920 /** 1921 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1922 * @hw: pointer to hardware structure 1923 **/ 1924 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1925 { 1926 u32 eec; 1927 1928 DEBUGFUNC("ixgbe_standby_eeprom"); 1929 1930 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1931 1932 /* Toggle CS to flush commands */ 1933 eec |= IXGBE_EEC_CS; 1934 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1935 IXGBE_WRITE_FLUSH(hw); 1936 usec_delay(1); 1937 eec &= ~IXGBE_EEC_CS; 1938 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1939 IXGBE_WRITE_FLUSH(hw); 1940 usec_delay(1); 1941 } 1942 1943 /** 1944 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1945 * @hw: pointer to hardware structure 1946 * @data: data to send to the EEPROM 1947 * @count: number of bits to shift out 1948 **/ 1949 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1950 u16 count) 1951 { 1952 u32 eec; 1953 u32 mask; 1954 u32 i; 1955 1956 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 1957 1958 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1959 1960 /* 1961 * Mask is used to shift "count" bits of "data" out to the EEPROM 1962 * one bit at a time. Determine the starting bit based on count 1963 */ 1964 mask = 0x01 << (count - 1); 1965 1966 for (i = 0; i < count; i++) { 1967 /* 1968 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1969 * "1", and then raising and then lowering the clock (the SK 1970 * bit controls the clock input to the EEPROM). A "0" is 1971 * shifted out to the EEPROM by setting "DI" to "0" and then 1972 * raising and then lowering the clock. 1973 */ 1974 if (data & mask) 1975 eec |= IXGBE_EEC_DI; 1976 else 1977 eec &= ~IXGBE_EEC_DI; 1978 1979 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1980 IXGBE_WRITE_FLUSH(hw); 1981 1982 usec_delay(1); 1983 1984 ixgbe_raise_eeprom_clk(hw, &eec); 1985 ixgbe_lower_eeprom_clk(hw, &eec); 1986 1987 /* 1988 * Shift mask to signify next bit of data to shift in to the 1989 * EEPROM 1990 */ 1991 mask = mask >> 1; 1992 } 1993 1994 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1995 eec &= ~IXGBE_EEC_DI; 1996 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1997 IXGBE_WRITE_FLUSH(hw); 1998 } 1999 2000 /** 2001 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2002 * @hw: pointer to hardware structure 2003 **/ 2004 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2005 { 2006 u32 eec; 2007 u32 i; 2008 u16 data = 0; 2009 2010 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2011 2012 /* 2013 * In order to read a register from the EEPROM, we need to shift 2014 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2015 * the clock input to the EEPROM (setting the SK bit), and then reading 2016 * the value of the "DO" bit. During this "shifting in" process the 2017 * "DI" bit should always be clear. 2018 */ 2019 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2020 2021 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2022 2023 for (i = 0; i < count; i++) { 2024 data = data << 1; 2025 ixgbe_raise_eeprom_clk(hw, &eec); 2026 2027 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2028 2029 eec &= ~(IXGBE_EEC_DI); 2030 if (eec & IXGBE_EEC_DO) 2031 data |= 1; 2032 2033 ixgbe_lower_eeprom_clk(hw, &eec); 2034 } 2035 2036 return data; 2037 } 2038 2039 /** 2040 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2041 * @hw: pointer to hardware structure 2042 * @eec: EEC register's current value 2043 **/ 2044 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2045 { 2046 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2047 2048 /* 2049 * Raise the clock input to the EEPROM 2050 * (setting the SK bit), then delay 2051 */ 2052 *eec = *eec | IXGBE_EEC_SK; 2053 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2054 IXGBE_WRITE_FLUSH(hw); 2055 usec_delay(1); 2056 } 2057 2058 /** 2059 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2060 * @hw: pointer to hardware structure 2061 * @eecd: EECD's current value 2062 **/ 2063 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2064 { 2065 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2066 2067 /* 2068 * Lower the clock input to the EEPROM (clearing the SK bit), then 2069 * delay 2070 */ 2071 *eec = *eec & ~IXGBE_EEC_SK; 2072 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2073 IXGBE_WRITE_FLUSH(hw); 2074 usec_delay(1); 2075 } 2076 2077 /** 2078 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2079 * @hw: pointer to hardware structure 2080 **/ 2081 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2082 { 2083 u32 eec; 2084 2085 DEBUGFUNC("ixgbe_release_eeprom"); 2086 2087 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2088 2089 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2090 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2091 2092 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2093 IXGBE_WRITE_FLUSH(hw); 2094 2095 usec_delay(1); 2096 2097 /* Stop requesting EEPROM access */ 2098 eec &= ~IXGBE_EEC_REQ; 2099 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2100 2101 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2102 2103 /* Delay before attempt to obtain semaphore again to allow FW access */ 2104 msec_delay(hw->eeprom.semaphore_delay); 2105 } 2106 2107 /** 2108 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2109 * @hw: pointer to hardware structure 2110 * 2111 * Returns a negative error code on error, or the 16-bit checksum 2112 **/ 2113 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2114 { 2115 u16 i; 2116 u16 j; 2117 u16 checksum = 0; 2118 u16 length = 0; 2119 u16 pointer = 0; 2120 u16 word = 0; 2121 2122 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2123 2124 /* Include 0x0-0x3F in the checksum */ 2125 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2126 if (hw->eeprom.ops.read(hw, i, &word)) { 2127 DEBUGOUT("EEPROM read failed\n"); 2128 return IXGBE_ERR_EEPROM; 2129 } 2130 checksum += word; 2131 } 2132 2133 /* Include all data from pointers except for the fw pointer */ 2134 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2135 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2136 DEBUGOUT("EEPROM read failed\n"); 2137 return IXGBE_ERR_EEPROM; 2138 } 2139 2140 /* If the pointer seems invalid */ 2141 if (pointer == 0xFFFF || pointer == 0) 2142 continue; 2143 2144 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2145 DEBUGOUT("EEPROM read failed\n"); 2146 return IXGBE_ERR_EEPROM; 2147 } 2148 2149 if (length == 0xFFFF || length == 0) 2150 continue; 2151 2152 for (j = pointer + 1; j <= pointer + length; j++) { 2153 if (hw->eeprom.ops.read(hw, j, &word)) { 2154 DEBUGOUT("EEPROM read failed\n"); 2155 return IXGBE_ERR_EEPROM; 2156 } 2157 checksum += word; 2158 } 2159 } 2160 2161 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2162 2163 return (s32)checksum; 2164 } 2165 2166 /** 2167 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2168 * @hw: pointer to hardware structure 2169 * @checksum_val: calculated checksum 2170 * 2171 * Performs checksum calculation and validates the EEPROM checksum. If the 2172 * caller does not need checksum_val, the value can be NULL. 2173 **/ 2174 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2175 u16 *checksum_val) 2176 { 2177 s32 status; 2178 u16 checksum; 2179 u16 read_checksum = 0; 2180 2181 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2182 2183 /* Read the first word from the EEPROM. If this times out or fails, do 2184 * not continue or we could be in for a very long wait while every 2185 * EEPROM read fails 2186 */ 2187 status = hw->eeprom.ops.read(hw, 0, &checksum); 2188 if (status) { 2189 DEBUGOUT("EEPROM read failed\n"); 2190 return status; 2191 } 2192 2193 status = hw->eeprom.ops.calc_checksum(hw); 2194 if (status < 0) 2195 return status; 2196 2197 checksum = (u16)(status & 0xffff); 2198 2199 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2200 if (status) { 2201 DEBUGOUT("EEPROM read failed\n"); 2202 return status; 2203 } 2204 2205 /* Verify read checksum from EEPROM is the same as 2206 * calculated checksum 2207 */ 2208 if (read_checksum != checksum) 2209 status = IXGBE_ERR_EEPROM_CHECKSUM; 2210 2211 /* If the user cares, return the calculated checksum */ 2212 if (checksum_val) 2213 *checksum_val = checksum; 2214 2215 return status; 2216 } 2217 2218 /** 2219 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2220 * @hw: pointer to hardware structure 2221 **/ 2222 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2223 { 2224 s32 status; 2225 u16 checksum; 2226 2227 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2228 2229 /* Read the first word from the EEPROM. If this times out or fails, do 2230 * not continue or we could be in for a very long wait while every 2231 * EEPROM read fails 2232 */ 2233 status = hw->eeprom.ops.read(hw, 0, &checksum); 2234 if (status) { 2235 DEBUGOUT("EEPROM read failed\n"); 2236 return status; 2237 } 2238 2239 status = hw->eeprom.ops.calc_checksum(hw); 2240 if (status < 0) 2241 return status; 2242 2243 checksum = (u16)(status & 0xffff); 2244 2245 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2246 2247 return status; 2248 } 2249 2250 /** 2251 * ixgbe_validate_mac_addr - Validate MAC address 2252 * @mac_addr: pointer to MAC address. 2253 * 2254 * Tests a MAC address to ensure it is a valid Individual Address 2255 **/ 2256 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2257 { 2258 s32 status = IXGBE_SUCCESS; 2259 2260 DEBUGFUNC("ixgbe_validate_mac_addr"); 2261 2262 /* Make sure it is not a multicast address */ 2263 if (IXGBE_IS_MULTICAST(mac_addr)) { 2264 DEBUGOUT("MAC address is multicast\n"); 2265 status = IXGBE_ERR_INVALID_MAC_ADDR; 2266 /* Not a broadcast address */ 2267 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2268 DEBUGOUT("MAC address is broadcast\n"); 2269 status = IXGBE_ERR_INVALID_MAC_ADDR; 2270 /* Reject the zero address */ 2271 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2272 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2273 DEBUGOUT("MAC address is all zeros\n"); 2274 status = IXGBE_ERR_INVALID_MAC_ADDR; 2275 } 2276 return status; 2277 } 2278 2279 /** 2280 * ixgbe_set_rar_generic - Set Rx address register 2281 * @hw: pointer to hardware structure 2282 * @index: Receive address register to write 2283 * @addr: Address to put into receive address register 2284 * @vmdq: VMDq "set" or "pool" index 2285 * @enable_addr: set flag that address is active 2286 * 2287 * Puts an ethernet address into a receive address register. 2288 **/ 2289 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2290 u32 enable_addr) 2291 { 2292 u32 rar_low, rar_high; 2293 u32 rar_entries = hw->mac.num_rar_entries; 2294 2295 DEBUGFUNC("ixgbe_set_rar_generic"); 2296 2297 /* Make sure we are using a valid rar index range */ 2298 if (index >= rar_entries) { 2299 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2300 "RAR index %d is out of range.\n", index); 2301 return IXGBE_ERR_INVALID_ARGUMENT; 2302 } 2303 2304 /* setup VMDq pool selection before this RAR gets enabled */ 2305 hw->mac.ops.set_vmdq(hw, index, vmdq); 2306 2307 /* 2308 * HW expects these in little endian so we reverse the byte 2309 * order from network order (big endian) to little endian 2310 */ 2311 rar_low = ((u32)addr[0] | 2312 ((u32)addr[1] << 8) | 2313 ((u32)addr[2] << 16) | 2314 ((u32)addr[3] << 24)); 2315 /* 2316 * Some parts put the VMDq setting in the extra RAH bits, 2317 * so save everything except the lower 16 bits that hold part 2318 * of the address and the address valid bit. 2319 */ 2320 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2321 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2322 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2323 2324 if (enable_addr != 0) 2325 rar_high |= IXGBE_RAH_AV; 2326 2327 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2328 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2329 2330 return IXGBE_SUCCESS; 2331 } 2332 2333 /** 2334 * ixgbe_clear_rar_generic - Remove Rx address register 2335 * @hw: pointer to hardware structure 2336 * @index: Receive address register to write 2337 * 2338 * Clears an ethernet address from a receive address register. 2339 **/ 2340 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2341 { 2342 u32 rar_high; 2343 u32 rar_entries = hw->mac.num_rar_entries; 2344 2345 DEBUGFUNC("ixgbe_clear_rar_generic"); 2346 2347 /* Make sure we are using a valid rar index range */ 2348 if (index >= rar_entries) { 2349 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2350 "RAR index %d is out of range.\n", index); 2351 return IXGBE_ERR_INVALID_ARGUMENT; 2352 } 2353 2354 /* 2355 * Some parts put the VMDq setting in the extra RAH bits, 2356 * so save everything except the lower 16 bits that hold part 2357 * of the address and the address valid bit. 2358 */ 2359 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2360 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2361 2362 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2363 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2364 2365 /* clear VMDq pool/queue selection for this RAR */ 2366 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2367 2368 return IXGBE_SUCCESS; 2369 } 2370 2371 /** 2372 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2373 * @hw: pointer to hardware structure 2374 * 2375 * Places the MAC address in receive address register 0 and clears the rest 2376 * of the receive address registers. Clears the multicast table. Assumes 2377 * the receiver is in reset when the routine is called. 2378 **/ 2379 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2380 { 2381 u32 i; 2382 u32 rar_entries = hw->mac.num_rar_entries; 2383 2384 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2385 2386 /* 2387 * If the current mac address is valid, assume it is a software override 2388 * to the permanent address. 2389 * Otherwise, use the permanent address from the eeprom. 2390 */ 2391 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2392 IXGBE_ERR_INVALID_MAC_ADDR) { 2393 /* Get the MAC address from the RAR0 for later reference */ 2394 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2395 2396 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2397 hw->mac.addr[0], hw->mac.addr[1], 2398 hw->mac.addr[2]); 2399 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2400 hw->mac.addr[4], hw->mac.addr[5]); 2401 } else { 2402 /* Setup the receive address. */ 2403 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2404 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2405 hw->mac.addr[0], hw->mac.addr[1], 2406 hw->mac.addr[2]); 2407 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2408 hw->mac.addr[4], hw->mac.addr[5]); 2409 2410 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2411 2412 /* clear VMDq pool/queue selection for RAR 0 */ 2413 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2414 } 2415 hw->addr_ctrl.overflow_promisc = 0; 2416 2417 hw->addr_ctrl.rar_used_count = 1; 2418 2419 /* Zero out the other receive addresses. */ 2420 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2421 for (i = 1; i < rar_entries; i++) { 2422 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2423 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2424 } 2425 2426 /* Clear the MTA */ 2427 hw->addr_ctrl.mta_in_use = 0; 2428 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2429 2430 DEBUGOUT(" Clearing MTA\n"); 2431 for (i = 0; i < hw->mac.mcft_size; i++) 2432 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2433 2434 ixgbe_init_uta_tables(hw); 2435 2436 return IXGBE_SUCCESS; 2437 } 2438 2439 /** 2440 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2441 * @hw: pointer to hardware structure 2442 * @addr: new address 2443 * 2444 * Adds it to unused receive address register or goes into promiscuous mode. 2445 **/ 2446 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2447 { 2448 u32 rar_entries = hw->mac.num_rar_entries; 2449 u32 rar; 2450 2451 DEBUGFUNC("ixgbe_add_uc_addr"); 2452 2453 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2454 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2455 2456 /* 2457 * Place this address in the RAR if there is room, 2458 * else put the controller into promiscuous mode 2459 */ 2460 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2461 rar = hw->addr_ctrl.rar_used_count; 2462 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2463 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2464 hw->addr_ctrl.rar_used_count++; 2465 } else { 2466 hw->addr_ctrl.overflow_promisc++; 2467 } 2468 2469 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2470 } 2471 2472 /** 2473 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2474 * @hw: pointer to hardware structure 2475 * @addr_list: the list of new addresses 2476 * @addr_count: number of addresses 2477 * @next: iterator function to walk the address list 2478 * 2479 * The given list replaces any existing list. Clears the secondary addrs from 2480 * receive address registers. Uses unused receive address registers for the 2481 * first secondary addresses, and falls back to promiscuous mode as needed. 2482 * 2483 * Drivers using secondary unicast addresses must set user_set_promisc when 2484 * manually putting the device into promiscuous mode. 2485 **/ 2486 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2487 u32 addr_count, ixgbe_mc_addr_itr next) 2488 { 2489 u8 *addr; 2490 u32 i; 2491 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2492 u32 uc_addr_in_use; 2493 u32 fctrl; 2494 u32 vmdq; 2495 2496 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2497 2498 /* 2499 * Clear accounting of old secondary address list, 2500 * don't count RAR[0] 2501 */ 2502 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2503 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2504 hw->addr_ctrl.overflow_promisc = 0; 2505 2506 /* Zero out the other receive addresses */ 2507 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2508 for (i = 0; i < uc_addr_in_use; i++) { 2509 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2510 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2511 } 2512 2513 /* Add the new addresses */ 2514 for (i = 0; i < addr_count; i++) { 2515 DEBUGOUT(" Adding the secondary addresses:\n"); 2516 addr = next(hw, &addr_list, &vmdq); 2517 ixgbe_add_uc_addr(hw, addr, vmdq); 2518 } 2519 2520 if (hw->addr_ctrl.overflow_promisc) { 2521 /* enable promisc if not already in overflow or set by user */ 2522 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2523 DEBUGOUT(" Entering address overflow promisc mode\n"); 2524 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2525 fctrl |= IXGBE_FCTRL_UPE; 2526 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2527 } 2528 } else { 2529 /* only disable if set by overflow, not by user */ 2530 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2531 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2532 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2533 fctrl &= ~IXGBE_FCTRL_UPE; 2534 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2535 } 2536 } 2537 2538 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2539 return IXGBE_SUCCESS; 2540 } 2541 2542 /** 2543 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2544 * @hw: pointer to hardware structure 2545 * @mc_addr: the multicast address 2546 * 2547 * Extracts the 12 bits, from a multicast address, to determine which 2548 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2549 * incoming rx multicast addresses, to determine the bit-vector to check in 2550 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2551 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2552 * to mc_filter_type. 2553 **/ 2554 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2555 { 2556 u32 vector = 0; 2557 2558 DEBUGFUNC("ixgbe_mta_vector"); 2559 2560 switch (hw->mac.mc_filter_type) { 2561 case 0: /* use bits [47:36] of the address */ 2562 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2563 break; 2564 case 1: /* use bits [46:35] of the address */ 2565 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2566 break; 2567 case 2: /* use bits [45:34] of the address */ 2568 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2569 break; 2570 case 3: /* use bits [43:32] of the address */ 2571 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2572 break; 2573 default: /* Invalid mc_filter_type */ 2574 DEBUGOUT("MC filter type param set incorrectly\n"); 2575 ASSERT(0); 2576 break; 2577 } 2578 2579 /* vector can only be 12-bits or boundary will be exceeded */ 2580 vector &= 0xFFF; 2581 return vector; 2582 } 2583 2584 /** 2585 * ixgbe_set_mta - Set bit-vector in multicast table 2586 * @hw: pointer to hardware structure 2587 * @hash_value: Multicast address hash value 2588 * 2589 * Sets the bit-vector in the multicast table. 2590 **/ 2591 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2592 { 2593 u32 vector; 2594 u32 vector_bit; 2595 u32 vector_reg; 2596 2597 DEBUGFUNC("ixgbe_set_mta"); 2598 2599 hw->addr_ctrl.mta_in_use++; 2600 2601 vector = ixgbe_mta_vector(hw, mc_addr); 2602 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2603 2604 /* 2605 * The MTA is a register array of 128 32-bit registers. It is treated 2606 * like an array of 4096 bits. We want to set bit 2607 * BitArray[vector_value]. So we figure out what register the bit is 2608 * in, read it, OR in the new bit, then write back the new value. The 2609 * register is determined by the upper 7 bits of the vector value and 2610 * the bit within that register are determined by the lower 5 bits of 2611 * the value. 2612 */ 2613 vector_reg = (vector >> 5) & 0x7F; 2614 vector_bit = vector & 0x1F; 2615 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2616 } 2617 2618 /** 2619 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2620 * @hw: pointer to hardware structure 2621 * @mc_addr_list: the list of new multicast addresses 2622 * @mc_addr_count: number of addresses 2623 * @next: iterator function to walk the multicast address list 2624 * @clear: flag, when set clears the table beforehand 2625 * 2626 * When the clear flag is set, the given list replaces any existing list. 2627 * Hashes the given addresses into the multicast table. 2628 **/ 2629 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2630 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2631 bool clear) 2632 { 2633 u32 i; 2634 u32 vmdq; 2635 2636 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2637 2638 /* 2639 * Set the new number of MC addresses that we are being requested to 2640 * use. 2641 */ 2642 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2643 hw->addr_ctrl.mta_in_use = 0; 2644 2645 /* Clear mta_shadow */ 2646 if (clear) { 2647 DEBUGOUT(" Clearing MTA\n"); 2648 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2649 } 2650 2651 /* Update mta_shadow */ 2652 for (i = 0; i < mc_addr_count; i++) { 2653 DEBUGOUT(" Adding the multicast addresses:\n"); 2654 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2655 } 2656 2657 /* Enable mta */ 2658 for (i = 0; i < hw->mac.mcft_size; i++) 2659 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2660 hw->mac.mta_shadow[i]); 2661 2662 if (hw->addr_ctrl.mta_in_use > 0) 2663 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2664 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2665 2666 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2667 return IXGBE_SUCCESS; 2668 } 2669 2670 /** 2671 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2672 * @hw: pointer to hardware structure 2673 * 2674 * Enables multicast address in RAR and the use of the multicast hash table. 2675 **/ 2676 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2677 { 2678 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2679 2680 DEBUGFUNC("ixgbe_enable_mc_generic"); 2681 2682 if (a->mta_in_use > 0) 2683 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2684 hw->mac.mc_filter_type); 2685 2686 return IXGBE_SUCCESS; 2687 } 2688 2689 /** 2690 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2691 * @hw: pointer to hardware structure 2692 * 2693 * Disables multicast address in RAR and the use of the multicast hash table. 2694 **/ 2695 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2696 { 2697 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2698 2699 DEBUGFUNC("ixgbe_disable_mc_generic"); 2700 2701 if (a->mta_in_use > 0) 2702 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2703 2704 return IXGBE_SUCCESS; 2705 } 2706 2707 /** 2708 * ixgbe_fc_enable_generic - Enable flow control 2709 * @hw: pointer to hardware structure 2710 * 2711 * Enable flow control according to the current settings. 2712 **/ 2713 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2714 { 2715 s32 ret_val = IXGBE_SUCCESS; 2716 u32 mflcn_reg, fccfg_reg; 2717 u32 reg; 2718 u32 fcrtl, fcrth; 2719 int i; 2720 2721 DEBUGFUNC("ixgbe_fc_enable_generic"); 2722 2723 /* Validate the water mark configuration */ 2724 if (!hw->fc.pause_time) { 2725 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2726 goto out; 2727 } 2728 2729 /* Low water mark of zero causes XOFF floods */ 2730 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2731 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2732 hw->fc.high_water[i]) { 2733 if (!hw->fc.low_water[i] || 2734 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2735 DEBUGOUT("Invalid water mark configuration\n"); 2736 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2737 goto out; 2738 } 2739 } 2740 } 2741 2742 /* Negotiate the fc mode to use */ 2743 ixgbe_fc_autoneg(hw); 2744 2745 /* Disable any previous flow control settings */ 2746 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2747 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2748 2749 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2750 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2751 2752 /* 2753 * The possible values of fc.current_mode are: 2754 * 0: Flow control is completely disabled 2755 * 1: Rx flow control is enabled (we can receive pause frames, 2756 * but not send pause frames). 2757 * 2: Tx flow control is enabled (we can send pause frames but 2758 * we do not support receiving pause frames). 2759 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2760 * other: Invalid. 2761 */ 2762 switch (hw->fc.current_mode) { 2763 case ixgbe_fc_none: 2764 /* 2765 * Flow control is disabled by software override or autoneg. 2766 * The code below will actually disable it in the HW. 2767 */ 2768 break; 2769 case ixgbe_fc_rx_pause: 2770 /* 2771 * Rx Flow control is enabled and Tx Flow control is 2772 * disabled by software override. Since there really 2773 * isn't a way to advertise that we are capable of RX 2774 * Pause ONLY, we will advertise that we support both 2775 * symmetric and asymmetric Rx PAUSE. Later, we will 2776 * disable the adapter's ability to send PAUSE frames. 2777 */ 2778 mflcn_reg |= IXGBE_MFLCN_RFCE; 2779 break; 2780 case ixgbe_fc_tx_pause: 2781 /* 2782 * Tx Flow control is enabled, and Rx Flow control is 2783 * disabled by software override. 2784 */ 2785 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2786 break; 2787 case ixgbe_fc_full: 2788 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2789 mflcn_reg |= IXGBE_MFLCN_RFCE; 2790 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2791 break; 2792 default: 2793 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2794 "Flow control param set incorrectly\n"); 2795 ret_val = IXGBE_ERR_CONFIG; 2796 goto out; 2797 break; 2798 } 2799 2800 /* Set 802.3x based flow control settings. */ 2801 mflcn_reg |= IXGBE_MFLCN_DPF; 2802 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2803 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2804 2805 2806 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2807 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2808 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2809 hw->fc.high_water[i]) { 2810 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2811 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2812 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2813 } else { 2814 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2815 /* 2816 * In order to prevent Tx hangs when the internal Tx 2817 * switch is enabled we must set the high water mark 2818 * to the Rx packet buffer size - 24KB. This allows 2819 * the Tx switch to function even under heavy Rx 2820 * workloads. 2821 */ 2822 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2823 } 2824 2825 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2826 } 2827 2828 /* Configure pause time (2 TCs per register) */ 2829 reg = hw->fc.pause_time * 0x00010001; 2830 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2831 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2832 2833 /* Configure flow control refresh threshold value */ 2834 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2835 2836 out: 2837 return ret_val; 2838 } 2839 2840 /** 2841 * ixgbe_negotiate_fc - Negotiate flow control 2842 * @hw: pointer to hardware structure 2843 * @adv_reg: flow control advertised settings 2844 * @lp_reg: link partner's flow control settings 2845 * @adv_sym: symmetric pause bit in advertisement 2846 * @adv_asm: asymmetric pause bit in advertisement 2847 * @lp_sym: symmetric pause bit in link partner advertisement 2848 * @lp_asm: asymmetric pause bit in link partner advertisement 2849 * 2850 * Find the intersection between advertised settings and link partner's 2851 * advertised settings 2852 **/ 2853 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2854 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2855 { 2856 if ((!(adv_reg)) || (!(lp_reg))) { 2857 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2858 "Local or link partner's advertised flow control " 2859 "settings are NULL. Local: %x, link partner: %x\n", 2860 adv_reg, lp_reg); 2861 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2862 } 2863 2864 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2865 /* 2866 * Now we need to check if the user selected Rx ONLY 2867 * of pause frames. In this case, we had to advertise 2868 * FULL flow control because we could not advertise RX 2869 * ONLY. Hence, we must now check to see if we need to 2870 * turn OFF the TRANSMISSION of PAUSE frames. 2871 */ 2872 if (hw->fc.requested_mode == ixgbe_fc_full) { 2873 hw->fc.current_mode = ixgbe_fc_full; 2874 DEBUGOUT("Flow Control = FULL.\n"); 2875 } else { 2876 hw->fc.current_mode = ixgbe_fc_rx_pause; 2877 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2878 } 2879 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2880 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2881 hw->fc.current_mode = ixgbe_fc_tx_pause; 2882 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2883 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2884 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2885 hw->fc.current_mode = ixgbe_fc_rx_pause; 2886 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2887 } else { 2888 hw->fc.current_mode = ixgbe_fc_none; 2889 DEBUGOUT("Flow Control = NONE.\n"); 2890 } 2891 return IXGBE_SUCCESS; 2892 } 2893 2894 /** 2895 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2896 * @hw: pointer to hardware structure 2897 * 2898 * Enable flow control according on 1 gig fiber. 2899 **/ 2900 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2901 { 2902 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2903 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2904 2905 /* 2906 * On multispeed fiber at 1g, bail out if 2907 * - link is up but AN did not complete, or if 2908 * - link is up and AN completed but timed out 2909 */ 2910 2911 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2912 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2913 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 2914 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 2915 goto out; 2916 } 2917 2918 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2919 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2920 2921 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2922 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2923 IXGBE_PCS1GANA_ASM_PAUSE, 2924 IXGBE_PCS1GANA_SYM_PAUSE, 2925 IXGBE_PCS1GANA_ASM_PAUSE); 2926 2927 out: 2928 return ret_val; 2929 } 2930 2931 /** 2932 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2933 * @hw: pointer to hardware structure 2934 * 2935 * Enable flow control according to IEEE clause 37. 2936 **/ 2937 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2938 { 2939 u32 links2, anlp1_reg, autoc_reg, links; 2940 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2941 2942 /* 2943 * On backplane, bail out if 2944 * - backplane autoneg was not completed, or if 2945 * - we are 82599 and link partner is not AN enabled 2946 */ 2947 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2948 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 2949 DEBUGOUT("Auto-Negotiation did not complete\n"); 2950 goto out; 2951 } 2952 2953 if (hw->mac.type == ixgbe_mac_82599EB) { 2954 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2955 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 2956 DEBUGOUT("Link partner is not AN enabled\n"); 2957 goto out; 2958 } 2959 } 2960 /* 2961 * Read the 10g AN autoc and LP ability registers and resolve 2962 * local flow control settings accordingly 2963 */ 2964 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2965 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2966 2967 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2968 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2969 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2970 2971 out: 2972 return ret_val; 2973 } 2974 2975 /** 2976 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2977 * @hw: pointer to hardware structure 2978 * 2979 * Enable flow control according to IEEE clause 37. 2980 **/ 2981 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2982 { 2983 u16 technology_ability_reg = 0; 2984 u16 lp_technology_ability_reg = 0; 2985 2986 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 2987 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2988 &technology_ability_reg); 2989 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 2990 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2991 &lp_technology_ability_reg); 2992 2993 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2994 (u32)lp_technology_ability_reg, 2995 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2996 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2997 } 2998 2999 /** 3000 * ixgbe_fc_autoneg - Configure flow control 3001 * @hw: pointer to hardware structure 3002 * 3003 * Compares our advertised flow control capabilities to those advertised by 3004 * our link partner, and determines the proper flow control mode to use. 3005 **/ 3006 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3007 { 3008 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3009 ixgbe_link_speed speed; 3010 bool link_up; 3011 3012 DEBUGFUNC("ixgbe_fc_autoneg"); 3013 3014 /* 3015 * AN should have completed when the cable was plugged in. 3016 * Look for reasons to bail out. Bail out if: 3017 * - FC autoneg is disabled, or if 3018 * - link is not up. 3019 */ 3020 if (hw->fc.disable_fc_autoneg) { 3021 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 3022 "Flow control autoneg is disabled"); 3023 goto out; 3024 } 3025 3026 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3027 if (!link_up) { 3028 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3029 goto out; 3030 } 3031 3032 switch (hw->phy.media_type) { 3033 /* Autoneg flow control on fiber adapters */ 3034 case ixgbe_media_type_fiber_fixed: 3035 case ixgbe_media_type_fiber_qsfp: 3036 case ixgbe_media_type_fiber: 3037 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3038 ret_val = ixgbe_fc_autoneg_fiber(hw); 3039 break; 3040 3041 /* Autoneg flow control on backplane adapters */ 3042 case ixgbe_media_type_backplane: 3043 ret_val = ixgbe_fc_autoneg_backplane(hw); 3044 break; 3045 3046 /* Autoneg flow control on copper adapters */ 3047 case ixgbe_media_type_copper: 3048 if (ixgbe_device_supports_autoneg_fc(hw)) 3049 ret_val = ixgbe_fc_autoneg_copper(hw); 3050 break; 3051 3052 default: 3053 break; 3054 } 3055 3056 out: 3057 if (ret_val == IXGBE_SUCCESS) { 3058 hw->fc.fc_was_autonegged = TRUE; 3059 } else { 3060 hw->fc.fc_was_autonegged = FALSE; 3061 hw->fc.current_mode = hw->fc.requested_mode; 3062 } 3063 } 3064 3065 /* 3066 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3067 * @hw: pointer to hardware structure 3068 * 3069 * System-wide timeout range is encoded in PCIe Device Control2 register. 3070 * 3071 * Add 10% to specified maximum and return the number of times to poll for 3072 * completion timeout, in units of 100 microsec. Never return less than 3073 * 800 = 80 millisec. 3074 */ 3075 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3076 { 3077 s16 devctl2; 3078 u32 pollcnt; 3079 3080 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3081 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3082 3083 switch (devctl2) { 3084 case IXGBE_PCIDEVCTRL2_65_130ms: 3085 pollcnt = 1300; /* 130 millisec */ 3086 break; 3087 case IXGBE_PCIDEVCTRL2_260_520ms: 3088 pollcnt = 5200; /* 520 millisec */ 3089 break; 3090 case IXGBE_PCIDEVCTRL2_1_2s: 3091 pollcnt = 20000; /* 2 sec */ 3092 break; 3093 case IXGBE_PCIDEVCTRL2_4_8s: 3094 pollcnt = 80000; /* 8 sec */ 3095 break; 3096 case IXGBE_PCIDEVCTRL2_17_34s: 3097 pollcnt = 34000; /* 34 sec */ 3098 break; 3099 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3100 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3101 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3102 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3103 default: 3104 pollcnt = 800; /* 80 millisec minimum */ 3105 break; 3106 } 3107 3108 /* add 10% to spec maximum */ 3109 return (pollcnt * 11) / 10; 3110 } 3111 3112 /** 3113 * ixgbe_disable_pcie_master - Disable PCI-express master access 3114 * @hw: pointer to hardware structure 3115 * 3116 * Disables PCI-Express master access and verifies there are no pending 3117 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 3118 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 3119 * is returned signifying master requests disabled. 3120 **/ 3121 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 3122 { 3123 s32 status = IXGBE_SUCCESS; 3124 u32 i, poll; 3125 u16 value; 3126 3127 DEBUGFUNC("ixgbe_disable_pcie_master"); 3128 3129 /* Always set this bit to ensure any future transactions are blocked */ 3130 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3131 3132 /* Exit if master requests are blocked */ 3133 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3134 IXGBE_REMOVED(hw->hw_addr)) 3135 goto out; 3136 3137 /* Poll for master request bit to clear */ 3138 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 3139 usec_delay(100); 3140 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3141 goto out; 3142 } 3143 3144 /* 3145 * Two consecutive resets are required via CTRL.RST per datasheet 3146 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 3147 * of this need. The first reset prevents new master requests from 3148 * being issued by our device. We then must wait 1usec or more for any 3149 * remaining completions from the PCIe bus to trickle in, and then reset 3150 * again to clear out any effects they may have had on our device. 3151 */ 3152 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 3153 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3154 3155 if (hw->mac.type >= ixgbe_mac_X550) 3156 goto out; 3157 3158 /* 3159 * Before proceeding, make sure that the PCIe block does not have 3160 * transactions pending. 3161 */ 3162 poll = ixgbe_pcie_timeout_poll(hw); 3163 for (i = 0; i < poll; i++) { 3164 usec_delay(100); 3165 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3166 if (IXGBE_REMOVED(hw->hw_addr)) 3167 goto out; 3168 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3169 goto out; 3170 } 3171 3172 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3173 "PCIe transaction pending bit also did not clear.\n"); 3174 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 3175 3176 out: 3177 return status; 3178 } 3179 3180 /** 3181 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3182 * @hw: pointer to hardware structure 3183 * @mask: Mask to specify which semaphore to acquire 3184 * 3185 * Acquires the SWFW semaphore through the GSSR register for the specified 3186 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3187 **/ 3188 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3189 { 3190 u32 gssr = 0; 3191 u32 swmask = mask; 3192 u32 fwmask = mask << 5; 3193 u32 timeout = 200; 3194 u32 i; 3195 3196 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3197 3198 for (i = 0; i < timeout; i++) { 3199 /* 3200 * SW NVM semaphore bit is used for access to all 3201 * SW_FW_SYNC bits (not just NVM) 3202 */ 3203 if (ixgbe_get_eeprom_semaphore(hw)) 3204 return IXGBE_ERR_SWFW_SYNC; 3205 3206 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3207 if (!(gssr & (fwmask | swmask))) { 3208 gssr |= swmask; 3209 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3210 ixgbe_release_eeprom_semaphore(hw); 3211 return IXGBE_SUCCESS; 3212 } else { 3213 /* Resource is currently in use by FW or SW */ 3214 ixgbe_release_eeprom_semaphore(hw); 3215 msec_delay(5); 3216 } 3217 } 3218 3219 /* If time expired clear the bits holding the lock and retry */ 3220 if (gssr & (fwmask | swmask)) 3221 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3222 3223 msec_delay(5); 3224 return IXGBE_ERR_SWFW_SYNC; 3225 } 3226 3227 /** 3228 * ixgbe_release_swfw_sync - Release SWFW semaphore 3229 * @hw: pointer to hardware structure 3230 * @mask: Mask to specify which semaphore to release 3231 * 3232 * Releases the SWFW semaphore through the GSSR register for the specified 3233 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3234 **/ 3235 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3236 { 3237 u32 gssr; 3238 u32 swmask = mask; 3239 3240 DEBUGFUNC("ixgbe_release_swfw_sync"); 3241 3242 ixgbe_get_eeprom_semaphore(hw); 3243 3244 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3245 gssr &= ~swmask; 3246 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3247 3248 ixgbe_release_eeprom_semaphore(hw); 3249 } 3250 3251 /** 3252 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3253 * @hw: pointer to hardware structure 3254 * 3255 * Stops the receive data path and waits for the HW to internally empty 3256 * the Rx security block 3257 **/ 3258 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3259 { 3260 #define IXGBE_MAX_SECRX_POLL 40 3261 3262 int i; 3263 int secrxreg; 3264 3265 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3266 3267 3268 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3269 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3270 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3271 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3272 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3273 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3274 break; 3275 else 3276 /* Use interrupt-safe sleep just in case */ 3277 usec_delay(1000); 3278 } 3279 3280 /* For informational purposes only */ 3281 if (i >= IXGBE_MAX_SECRX_POLL) 3282 DEBUGOUT("Rx unit being enabled before security " 3283 "path fully disabled. Continuing with init.\n"); 3284 3285 return IXGBE_SUCCESS; 3286 } 3287 3288 /** 3289 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3290 * @hw: pointer to hardware structure 3291 * @reg_val: Value we read from AUTOC 3292 * 3293 * The default case requires no protection so just to the register read. 3294 */ 3295 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3296 { 3297 *locked = FALSE; 3298 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3299 return IXGBE_SUCCESS; 3300 } 3301 3302 /** 3303 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3304 * @hw: pointer to hardware structure 3305 * @reg_val: value to write to AUTOC 3306 * @locked: bool to indicate whether the SW/FW lock was already taken by 3307 * previous read. 3308 * 3309 * The default case requires no protection so just to the register write. 3310 */ 3311 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3312 { 3313 UNREFERENCED_1PARAMETER(locked); 3314 3315 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3316 return IXGBE_SUCCESS; 3317 } 3318 3319 /** 3320 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3321 * @hw: pointer to hardware structure 3322 * 3323 * Enables the receive data path. 3324 **/ 3325 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3326 { 3327 int secrxreg; 3328 3329 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3330 3331 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3332 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3333 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3334 IXGBE_WRITE_FLUSH(hw); 3335 3336 return IXGBE_SUCCESS; 3337 } 3338 3339 /** 3340 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3341 * @hw: pointer to hardware structure 3342 * @regval: register value to write to RXCTRL 3343 * 3344 * Enables the Rx DMA unit 3345 **/ 3346 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3347 { 3348 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3349 3350 if (regval & IXGBE_RXCTRL_RXEN) 3351 ixgbe_enable_rx(hw); 3352 else 3353 ixgbe_disable_rx(hw); 3354 3355 return IXGBE_SUCCESS; 3356 } 3357 3358 /** 3359 * ixgbe_blink_led_start_generic - Blink LED based on index. 3360 * @hw: pointer to hardware structure 3361 * @index: led number to blink 3362 **/ 3363 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3364 { 3365 ixgbe_link_speed speed = 0; 3366 bool link_up = 0; 3367 u32 autoc_reg = 0; 3368 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3369 s32 ret_val = IXGBE_SUCCESS; 3370 bool locked = FALSE; 3371 3372 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3373 3374 /* 3375 * Link must be up to auto-blink the LEDs; 3376 * Force it if link is down. 3377 */ 3378 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3379 3380 if (!link_up) { 3381 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3382 if (ret_val != IXGBE_SUCCESS) 3383 goto out; 3384 3385 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3386 autoc_reg |= IXGBE_AUTOC_FLU; 3387 3388 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3389 if (ret_val != IXGBE_SUCCESS) 3390 goto out; 3391 3392 IXGBE_WRITE_FLUSH(hw); 3393 msec_delay(10); 3394 } 3395 3396 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3397 led_reg |= IXGBE_LED_BLINK(index); 3398 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3399 IXGBE_WRITE_FLUSH(hw); 3400 3401 out: 3402 return ret_val; 3403 } 3404 3405 /** 3406 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3407 * @hw: pointer to hardware structure 3408 * @index: led number to stop blinking 3409 **/ 3410 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3411 { 3412 u32 autoc_reg = 0; 3413 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3414 s32 ret_val = IXGBE_SUCCESS; 3415 bool locked = FALSE; 3416 3417 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3418 3419 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3420 if (ret_val != IXGBE_SUCCESS) 3421 goto out; 3422 3423 autoc_reg &= ~IXGBE_AUTOC_FLU; 3424 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3425 3426 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3427 if (ret_val != IXGBE_SUCCESS) 3428 goto out; 3429 3430 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3431 led_reg &= ~IXGBE_LED_BLINK(index); 3432 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3433 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3434 IXGBE_WRITE_FLUSH(hw); 3435 3436 out: 3437 return ret_val; 3438 } 3439 3440 /** 3441 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3442 * @hw: pointer to hardware structure 3443 * @san_mac_offset: SAN MAC address offset 3444 * 3445 * This function will read the EEPROM location for the SAN MAC address 3446 * pointer, and returns the value at that location. This is used in both 3447 * get and set mac_addr routines. 3448 **/ 3449 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3450 u16 *san_mac_offset) 3451 { 3452 s32 ret_val; 3453 3454 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3455 3456 /* 3457 * First read the EEPROM pointer to see if the MAC addresses are 3458 * available. 3459 */ 3460 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3461 san_mac_offset); 3462 if (ret_val) { 3463 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3464 "eeprom at offset %d failed", 3465 IXGBE_SAN_MAC_ADDR_PTR); 3466 } 3467 3468 return ret_val; 3469 } 3470 3471 /** 3472 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3473 * @hw: pointer to hardware structure 3474 * @san_mac_addr: SAN MAC address 3475 * 3476 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3477 * per-port, so set_lan_id() must be called before reading the addresses. 3478 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3479 * upon for non-SFP connections, so we must call it here. 3480 **/ 3481 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3482 { 3483 u16 san_mac_data, san_mac_offset; 3484 u8 i; 3485 s32 ret_val; 3486 3487 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3488 3489 /* 3490 * First read the EEPROM pointer to see if the MAC addresses are 3491 * available. If they're not, no point in calling set_lan_id() here. 3492 */ 3493 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3494 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3495 goto san_mac_addr_out; 3496 3497 /* make sure we know which port we need to program */ 3498 hw->mac.ops.set_lan_id(hw); 3499 /* apply the port offset to the address offset */ 3500 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3501 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3502 for (i = 0; i < 3; i++) { 3503 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3504 &san_mac_data); 3505 if (ret_val) { 3506 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3507 "eeprom read at offset %d failed", 3508 san_mac_offset); 3509 goto san_mac_addr_out; 3510 } 3511 san_mac_addr[i * 2] = (u8)(san_mac_data); 3512 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3513 san_mac_offset++; 3514 } 3515 return IXGBE_SUCCESS; 3516 3517 san_mac_addr_out: 3518 /* 3519 * No addresses available in this EEPROM. It's not an 3520 * error though, so just wipe the local address and return. 3521 */ 3522 for (i = 0; i < 6; i++) 3523 san_mac_addr[i] = 0xFF; 3524 return IXGBE_SUCCESS; 3525 } 3526 3527 /** 3528 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3529 * @hw: pointer to hardware structure 3530 * @san_mac_addr: SAN MAC address 3531 * 3532 * Write a SAN MAC address to the EEPROM. 3533 **/ 3534 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3535 { 3536 s32 ret_val; 3537 u16 san_mac_data, san_mac_offset; 3538 u8 i; 3539 3540 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3541 3542 /* Look for SAN mac address pointer. If not defined, return */ 3543 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3544 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3545 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3546 3547 /* Make sure we know which port we need to write */ 3548 hw->mac.ops.set_lan_id(hw); 3549 /* Apply the port offset to the address offset */ 3550 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3551 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3552 3553 for (i = 0; i < 3; i++) { 3554 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3555 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3556 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3557 san_mac_offset++; 3558 } 3559 3560 return IXGBE_SUCCESS; 3561 } 3562 3563 /** 3564 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3565 * @hw: pointer to hardware structure 3566 * 3567 * Read PCIe configuration space, and get the MSI-X vector count from 3568 * the capabilities table. 3569 **/ 3570 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3571 { 3572 u16 msix_count = 1; 3573 u16 max_msix_count; 3574 u16 pcie_offset; 3575 3576 switch (hw->mac.type) { 3577 case ixgbe_mac_82598EB: 3578 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3579 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3580 break; 3581 case ixgbe_mac_82599EB: 3582 case ixgbe_mac_X540: 3583 case ixgbe_mac_X550: 3584 case ixgbe_mac_X550EM_x: 3585 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3586 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3587 break; 3588 default: 3589 return msix_count; 3590 } 3591 3592 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3593 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3594 if (IXGBE_REMOVED(hw->hw_addr)) 3595 msix_count = 0; 3596 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3597 3598 /* MSI-X count is zero-based in HW */ 3599 msix_count++; 3600 3601 if (msix_count > max_msix_count) 3602 msix_count = max_msix_count; 3603 3604 return msix_count; 3605 } 3606 3607 /** 3608 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3609 * @hw: pointer to hardware structure 3610 * @addr: Address to put into receive address register 3611 * @vmdq: VMDq pool to assign 3612 * 3613 * Puts an ethernet address into a receive address register, or 3614 * finds the rar that it is already in; adds to the pool list 3615 **/ 3616 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3617 { 3618 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3619 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3620 u32 rar; 3621 u32 rar_low, rar_high; 3622 u32 addr_low, addr_high; 3623 3624 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3625 3626 /* swap bytes for HW little endian */ 3627 addr_low = addr[0] | (addr[1] << 8) 3628 | (addr[2] << 16) 3629 | (addr[3] << 24); 3630 addr_high = addr[4] | (addr[5] << 8); 3631 3632 /* 3633 * Either find the mac_id in rar or find the first empty space. 3634 * rar_highwater points to just after the highest currently used 3635 * rar in order to shorten the search. It grows when we add a new 3636 * rar to the top. 3637 */ 3638 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3639 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3640 3641 if (((IXGBE_RAH_AV & rar_high) == 0) 3642 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3643 first_empty_rar = rar; 3644 } else if ((rar_high & 0xFFFF) == addr_high) { 3645 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3646 if (rar_low == addr_low) 3647 break; /* found it already in the rars */ 3648 } 3649 } 3650 3651 if (rar < hw->mac.rar_highwater) { 3652 /* already there so just add to the pool bits */ 3653 ixgbe_set_vmdq(hw, rar, vmdq); 3654 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3655 /* stick it into first empty RAR slot we found */ 3656 rar = first_empty_rar; 3657 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3658 } else if (rar == hw->mac.rar_highwater) { 3659 /* add it to the top of the list and inc the highwater mark */ 3660 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3661 hw->mac.rar_highwater++; 3662 } else if (rar >= hw->mac.num_rar_entries) { 3663 return IXGBE_ERR_INVALID_MAC_ADDR; 3664 } 3665 3666 /* 3667 * If we found rar[0], make sure the default pool bit (we use pool 0) 3668 * remains cleared to be sure default pool packets will get delivered 3669 */ 3670 if (rar == 0) 3671 ixgbe_clear_vmdq(hw, rar, 0); 3672 3673 return rar; 3674 } 3675 3676 /** 3677 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3678 * @hw: pointer to hardware struct 3679 * @rar: receive address register index to disassociate 3680 * @vmdq: VMDq pool index to remove from the rar 3681 **/ 3682 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3683 { 3684 u32 mpsar_lo, mpsar_hi; 3685 u32 rar_entries = hw->mac.num_rar_entries; 3686 3687 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3688 3689 /* Make sure we are using a valid rar index range */ 3690 if (rar >= rar_entries) { 3691 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3692 "RAR index %d is out of range.\n", rar); 3693 return IXGBE_ERR_INVALID_ARGUMENT; 3694 } 3695 3696 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3697 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3698 3699 if (IXGBE_REMOVED(hw->hw_addr)) 3700 goto done; 3701 3702 if (!mpsar_lo && !mpsar_hi) 3703 goto done; 3704 3705 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3706 if (mpsar_lo) { 3707 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3708 mpsar_lo = 0; 3709 } 3710 if (mpsar_hi) { 3711 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3712 mpsar_hi = 0; 3713 } 3714 } else if (vmdq < 32) { 3715 mpsar_lo &= ~(1 << vmdq); 3716 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3717 } else { 3718 mpsar_hi &= ~(1 << (vmdq - 32)); 3719 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3720 } 3721 3722 /* was that the last pool using this rar? */ 3723 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 3724 hw->mac.ops.clear_rar(hw, rar); 3725 done: 3726 return IXGBE_SUCCESS; 3727 } 3728 3729 /** 3730 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3731 * @hw: pointer to hardware struct 3732 * @rar: receive address register index to associate with a VMDq index 3733 * @vmdq: VMDq pool index 3734 **/ 3735 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3736 { 3737 u32 mpsar; 3738 u32 rar_entries = hw->mac.num_rar_entries; 3739 3740 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3741 3742 /* Make sure we are using a valid rar index range */ 3743 if (rar >= rar_entries) { 3744 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3745 "RAR index %d is out of range.\n", rar); 3746 return IXGBE_ERR_INVALID_ARGUMENT; 3747 } 3748 3749 if (vmdq < 32) { 3750 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3751 mpsar |= 1 << vmdq; 3752 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3753 } else { 3754 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3755 mpsar |= 1 << (vmdq - 32); 3756 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3757 } 3758 return IXGBE_SUCCESS; 3759 } 3760 3761 /** 3762 * This function should only be involved in the IOV mode. 3763 * In IOV mode, Default pool is next pool after the number of 3764 * VFs advertized and not 0. 3765 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3766 * 3767 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3768 * @hw: pointer to hardware struct 3769 * @vmdq: VMDq pool index 3770 **/ 3771 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3772 { 3773 u32 rar = hw->mac.san_mac_rar_index; 3774 3775 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3776 3777 if (vmdq < 32) { 3778 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3779 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3780 } else { 3781 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3782 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3783 } 3784 3785 return IXGBE_SUCCESS; 3786 } 3787 3788 /** 3789 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3790 * @hw: pointer to hardware structure 3791 **/ 3792 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3793 { 3794 int i; 3795 3796 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3797 DEBUGOUT(" Clearing UTA\n"); 3798 3799 for (i = 0; i < 128; i++) 3800 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3801 3802 return IXGBE_SUCCESS; 3803 } 3804 3805 /** 3806 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3807 * @hw: pointer to hardware structure 3808 * @vlan: VLAN id to write to VLAN filter 3809 * 3810 * return the VLVF index where this VLAN id should be placed 3811 * 3812 **/ 3813 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 3814 { 3815 u32 bits = 0; 3816 u32 first_empty_slot = 0; 3817 s32 regindex; 3818 3819 /* short cut the special case */ 3820 if (vlan == 0) 3821 return 0; 3822 3823 /* 3824 * Search for the vlan id in the VLVF entries. Save off the first empty 3825 * slot found along the way 3826 */ 3827 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 3828 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3829 if (!bits && !(first_empty_slot)) 3830 first_empty_slot = regindex; 3831 else if ((bits & 0x0FFF) == vlan) 3832 break; 3833 } 3834 3835 /* 3836 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 3837 * in the VLVF. Else use the first empty VLVF register for this 3838 * vlan id. 3839 */ 3840 if (regindex >= IXGBE_VLVF_ENTRIES) { 3841 if (first_empty_slot) 3842 regindex = first_empty_slot; 3843 else { 3844 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 3845 "No space in VLVF.\n"); 3846 regindex = IXGBE_ERR_NO_SPACE; 3847 } 3848 } 3849 3850 return regindex; 3851 } 3852 3853 /** 3854 * ixgbe_set_vfta_generic - Set VLAN filter table 3855 * @hw: pointer to hardware structure 3856 * @vlan: VLAN id to write to VLAN filter 3857 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3858 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3859 * 3860 * Turn on/off specified VLAN in the VLAN filter table. 3861 **/ 3862 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3863 bool vlan_on) 3864 { 3865 s32 regindex; 3866 u32 bitindex; 3867 u32 vfta; 3868 u32 targetbit; 3869 s32 ret_val = IXGBE_SUCCESS; 3870 bool vfta_changed = FALSE; 3871 3872 DEBUGFUNC("ixgbe_set_vfta_generic"); 3873 3874 if (vlan > 4095) 3875 return IXGBE_ERR_PARAM; 3876 3877 /* 3878 * this is a 2 part operation - first the VFTA, then the 3879 * VLVF and VLVFB if VT Mode is set 3880 * We don't write the VFTA until we know the VLVF part succeeded. 3881 */ 3882 3883 /* Part 1 3884 * The VFTA is a bitstring made up of 128 32-bit registers 3885 * that enable the particular VLAN id, much like the MTA: 3886 * bits[11-5]: which register 3887 * bits[4-0]: which bit in the register 3888 */ 3889 regindex = (vlan >> 5) & 0x7F; 3890 bitindex = vlan & 0x1F; 3891 targetbit = (1 << bitindex); 3892 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 3893 3894 if (vlan_on) { 3895 if (!(vfta & targetbit)) { 3896 vfta |= targetbit; 3897 vfta_changed = TRUE; 3898 } 3899 } else { 3900 if ((vfta & targetbit)) { 3901 vfta &= ~targetbit; 3902 vfta_changed = TRUE; 3903 } 3904 } 3905 3906 /* Part 2 3907 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 3908 */ 3909 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, 3910 &vfta_changed); 3911 if (ret_val != IXGBE_SUCCESS) 3912 return ret_val; 3913 3914 if (vfta_changed) 3915 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); 3916 3917 return IXGBE_SUCCESS; 3918 } 3919 3920 /** 3921 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 3922 * @hw: pointer to hardware structure 3923 * @vlan: VLAN id to write to VLAN filter 3924 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3925 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3926 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 3927 * should be changed 3928 * 3929 * Turn on/off specified bit in VLVF table. 3930 **/ 3931 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3932 bool vlan_on, bool *vfta_changed) 3933 { 3934 u32 vt; 3935 3936 DEBUGFUNC("ixgbe_set_vlvf_generic"); 3937 3938 if (vlan > 4095) 3939 return IXGBE_ERR_PARAM; 3940 3941 /* If VT Mode is set 3942 * Either vlan_on 3943 * make sure the vlan is in VLVF 3944 * set the vind bit in the matching VLVFB 3945 * Or !vlan_on 3946 * clear the pool bit and possibly the vind 3947 */ 3948 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3949 if (vt & IXGBE_VT_CTL_VT_ENABLE) { 3950 s32 vlvf_index; 3951 u32 bits; 3952 3953 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); 3954 if (vlvf_index < 0) 3955 return vlvf_index; 3956 3957 if (vlan_on) { 3958 /* set the pool bit */ 3959 if (vind < 32) { 3960 bits = IXGBE_READ_REG(hw, 3961 IXGBE_VLVFB(vlvf_index * 2)); 3962 bits |= (1 << vind); 3963 IXGBE_WRITE_REG(hw, 3964 IXGBE_VLVFB(vlvf_index * 2), 3965 bits); 3966 } else { 3967 bits = IXGBE_READ_REG(hw, 3968 IXGBE_VLVFB((vlvf_index * 2) + 1)); 3969 bits |= (1 << (vind - 32)); 3970 IXGBE_WRITE_REG(hw, 3971 IXGBE_VLVFB((vlvf_index * 2) + 1), 3972 bits); 3973 } 3974 } else { 3975 /* clear the pool bit */ 3976 if (vind < 32) { 3977 bits = IXGBE_READ_REG(hw, 3978 IXGBE_VLVFB(vlvf_index * 2)); 3979 bits &= ~(1 << vind); 3980 IXGBE_WRITE_REG(hw, 3981 IXGBE_VLVFB(vlvf_index * 2), 3982 bits); 3983 bits |= IXGBE_READ_REG(hw, 3984 IXGBE_VLVFB((vlvf_index * 2) + 1)); 3985 } else { 3986 bits = IXGBE_READ_REG(hw, 3987 IXGBE_VLVFB((vlvf_index * 2) + 1)); 3988 bits &= ~(1 << (vind - 32)); 3989 IXGBE_WRITE_REG(hw, 3990 IXGBE_VLVFB((vlvf_index * 2) + 1), 3991 bits); 3992 bits |= IXGBE_READ_REG(hw, 3993 IXGBE_VLVFB(vlvf_index * 2)); 3994 } 3995 } 3996 3997 /* 3998 * If there are still bits set in the VLVFB registers 3999 * for the VLAN ID indicated we need to see if the 4000 * caller is requesting that we clear the VFTA entry bit. 4001 * If the caller has requested that we clear the VFTA 4002 * entry bit but there are still pools/VFs using this VLAN 4003 * ID entry then ignore the request. We're not worried 4004 * about the case where we're turning the VFTA VLAN ID 4005 * entry bit on, only when requested to turn it off as 4006 * there may be multiple pools and/or VFs using the 4007 * VLAN ID entry. In that case we cannot clear the 4008 * VFTA bit until all pools/VFs using that VLAN ID have also 4009 * been cleared. This will be indicated by "bits" being 4010 * zero. 4011 */ 4012 if (bits) { 4013 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 4014 (IXGBE_VLVF_VIEN | vlan)); 4015 if ((!vlan_on) && (vfta_changed != NULL)) { 4016 /* someone wants to clear the vfta entry 4017 * but some pools/VFs are still using it. 4018 * Ignore it. */ 4019 *vfta_changed = FALSE; 4020 } 4021 } else 4022 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4023 } 4024 4025 return IXGBE_SUCCESS; 4026 } 4027 4028 /** 4029 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4030 * @hw: pointer to hardware structure 4031 * 4032 * Clears the VLAN filer table, and the VMDq index associated with the filter 4033 **/ 4034 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4035 { 4036 u32 offset; 4037 4038 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4039 4040 for (offset = 0; offset < hw->mac.vft_size; offset++) 4041 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4042 4043 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4044 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4045 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4046 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); 4047 } 4048 4049 return IXGBE_SUCCESS; 4050 } 4051 4052 /** 4053 * ixgbe_check_mac_link_generic - Determine link and speed status 4054 * @hw: pointer to hardware structure 4055 * @speed: pointer to link speed 4056 * @link_up: TRUE when link is up 4057 * @link_up_wait_to_complete: bool used to wait for link up or not 4058 * 4059 * Reads the links register to determine if link is up and the current speed 4060 **/ 4061 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4062 bool *link_up, bool link_up_wait_to_complete) 4063 { 4064 u32 links_reg, links_orig; 4065 u32 i; 4066 4067 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4068 4069 /* clear the old state */ 4070 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4071 4072 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4073 4074 if (links_orig != links_reg) { 4075 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4076 links_orig, links_reg); 4077 } 4078 4079 if (link_up_wait_to_complete) { 4080 for (i = 0; i < hw->mac.max_link_up_time; i++) { 4081 if (links_reg & IXGBE_LINKS_UP) { 4082 *link_up = TRUE; 4083 break; 4084 } else { 4085 *link_up = FALSE; 4086 } 4087 msec_delay(100); 4088 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4089 } 4090 } else { 4091 if (links_reg & IXGBE_LINKS_UP) 4092 *link_up = TRUE; 4093 else 4094 *link_up = FALSE; 4095 } 4096 4097 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4098 case IXGBE_LINKS_SPEED_10G_82599: 4099 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4100 if (hw->mac.type >= ixgbe_mac_X550) { 4101 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4102 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4103 } 4104 break; 4105 case IXGBE_LINKS_SPEED_1G_82599: 4106 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4107 break; 4108 case IXGBE_LINKS_SPEED_100_82599: 4109 *speed = IXGBE_LINK_SPEED_100_FULL; 4110 if (hw->mac.type >= ixgbe_mac_X550) { 4111 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4112 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4113 } 4114 break; 4115 default: 4116 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4117 } 4118 4119 return IXGBE_SUCCESS; 4120 } 4121 4122 /** 4123 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4124 * the EEPROM 4125 * @hw: pointer to hardware structure 4126 * @wwnn_prefix: the alternative WWNN prefix 4127 * @wwpn_prefix: the alternative WWPN prefix 4128 * 4129 * This function will read the EEPROM from the alternative SAN MAC address 4130 * block to check the support for the alternative WWNN/WWPN prefix support. 4131 **/ 4132 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4133 u16 *wwpn_prefix) 4134 { 4135 u16 offset, caps; 4136 u16 alt_san_mac_blk_offset; 4137 4138 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4139 4140 /* clear output first */ 4141 *wwnn_prefix = 0xFFFF; 4142 *wwpn_prefix = 0xFFFF; 4143 4144 /* check if alternative SAN MAC is supported */ 4145 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4146 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4147 goto wwn_prefix_err; 4148 4149 if ((alt_san_mac_blk_offset == 0) || 4150 (alt_san_mac_blk_offset == 0xFFFF)) 4151 goto wwn_prefix_out; 4152 4153 /* check capability in alternative san mac address block */ 4154 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4155 if (hw->eeprom.ops.read(hw, offset, &caps)) 4156 goto wwn_prefix_err; 4157 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4158 goto wwn_prefix_out; 4159 4160 /* get the corresponding prefix for WWNN/WWPN */ 4161 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4162 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4163 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4164 "eeprom read at offset %d failed", offset); 4165 } 4166 4167 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4168 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4169 goto wwn_prefix_err; 4170 4171 wwn_prefix_out: 4172 return IXGBE_SUCCESS; 4173 4174 wwn_prefix_err: 4175 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4176 "eeprom read at offset %d failed", offset); 4177 return IXGBE_SUCCESS; 4178 } 4179 4180 /** 4181 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4182 * @hw: pointer to hardware structure 4183 * @bs: the fcoe boot status 4184 * 4185 * This function will read the FCOE boot status from the iSCSI FCOE block 4186 **/ 4187 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4188 { 4189 u16 offset, caps, flags; 4190 s32 status; 4191 4192 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4193 4194 /* clear output first */ 4195 *bs = ixgbe_fcoe_bootstatus_unavailable; 4196 4197 /* check if FCOE IBA block is present */ 4198 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4199 status = hw->eeprom.ops.read(hw, offset, &caps); 4200 if (status != IXGBE_SUCCESS) 4201 goto out; 4202 4203 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4204 goto out; 4205 4206 /* check if iSCSI FCOE block is populated */ 4207 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4208 if (status != IXGBE_SUCCESS) 4209 goto out; 4210 4211 if ((offset == 0) || (offset == 0xFFFF)) 4212 goto out; 4213 4214 /* read fcoe flags in iSCSI FCOE block */ 4215 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4216 status = hw->eeprom.ops.read(hw, offset, &flags); 4217 if (status != IXGBE_SUCCESS) 4218 goto out; 4219 4220 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4221 *bs = ixgbe_fcoe_bootstatus_enabled; 4222 else 4223 *bs = ixgbe_fcoe_bootstatus_disabled; 4224 4225 out: 4226 return status; 4227 } 4228 4229 /** 4230 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4231 * @hw: pointer to hardware structure 4232 * @enable: enable or disable switch for anti-spoofing 4233 * @pf: Physical Function pool - do not enable anti-spoofing for the PF 4234 * 4235 **/ 4236 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) 4237 { 4238 int j; 4239 int pf_target_reg = pf >> 3; 4240 int pf_target_shift = pf % 8; 4241 u32 pfvfspoof = 0; 4242 4243 if (hw->mac.type == ixgbe_mac_82598EB) 4244 return; 4245 4246 if (enable) 4247 pfvfspoof = IXGBE_SPOOF_MACAS_MASK; 4248 4249 /* 4250 * PFVFSPOOF register array is size 8 with 8 bits assigned to 4251 * MAC anti-spoof enables in each register array element. 4252 */ 4253 for (j = 0; j < pf_target_reg; j++) 4254 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 4255 4256 /* 4257 * The PF should be allowed to spoof so that it can support 4258 * emulation mode NICs. Do not set the bits assigned to the PF 4259 */ 4260 pfvfspoof &= (1 << pf_target_shift) - 1; 4261 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 4262 4263 /* 4264 * Remaining pools belong to the PF so they do not need to have 4265 * anti-spoofing enabled. 4266 */ 4267 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++) 4268 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0); 4269 } 4270 4271 /** 4272 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4273 * @hw: pointer to hardware structure 4274 * @enable: enable or disable switch for VLAN anti-spoofing 4275 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4276 * 4277 **/ 4278 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4279 { 4280 int vf_target_reg = vf >> 3; 4281 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4282 u32 pfvfspoof; 4283 4284 if (hw->mac.type == ixgbe_mac_82598EB) 4285 return; 4286 4287 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4288 if (enable) 4289 pfvfspoof |= (1 << vf_target_shift); 4290 else 4291 pfvfspoof &= ~(1 << vf_target_shift); 4292 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4293 } 4294 4295 /** 4296 * ixgbe_get_device_caps_generic - Get additional device capabilities 4297 * @hw: pointer to hardware structure 4298 * @device_caps: the EEPROM word with the extra device capabilities 4299 * 4300 * This function will read the EEPROM location for the device capabilities, 4301 * and return the word through device_caps. 4302 **/ 4303 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4304 { 4305 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4306 4307 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4308 4309 return IXGBE_SUCCESS; 4310 } 4311 4312 /** 4313 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4314 * @hw: pointer to hardware structure 4315 * 4316 **/ 4317 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4318 { 4319 u32 regval; 4320 u32 i; 4321 4322 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4323 4324 /* Enable relaxed ordering */ 4325 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4326 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4327 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4328 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4329 } 4330 4331 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4332 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4333 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4334 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4335 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4336 } 4337 4338 } 4339 4340 /** 4341 * ixgbe_calculate_checksum - Calculate checksum for buffer 4342 * @buffer: pointer to EEPROM 4343 * @length: size of EEPROM to calculate a checksum for 4344 * Calculates the checksum for some buffer on a specified length. The 4345 * checksum calculated is returned. 4346 **/ 4347 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4348 { 4349 u32 i; 4350 u8 sum = 0; 4351 4352 DEBUGFUNC("ixgbe_calculate_checksum"); 4353 4354 if (!buffer) 4355 return 0; 4356 4357 for (i = 0; i < length; i++) 4358 sum += buffer[i]; 4359 4360 return (u8) (0 - sum); 4361 } 4362 4363 /** 4364 * ixgbe_host_interface_command - Issue command to manageability block 4365 * @hw: pointer to the HW structure 4366 * @buffer: contains the command to write and where the return status will 4367 * be placed 4368 * @length: length of buffer, must be multiple of 4 bytes 4369 * @timeout: time in ms to wait for command completion 4370 * @return_data: read and return data from the buffer (TRUE) or not (FALSE) 4371 * Needed because FW structures are big endian and decoding of 4372 * these fields can be 8 bit or 16 bit based on command. Decoding 4373 * is not easily understood without making a table of commands. 4374 * So we will leave this up to the caller to read back the data 4375 * in these cases. 4376 * 4377 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4378 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 4379 **/ 4380 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4381 u32 length, u32 timeout, bool return_data) 4382 { 4383 u32 hicr, i, bi, fwsts; 4384 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4385 u16 buf_len; 4386 u16 dword_len; 4387 4388 DEBUGFUNC("ixgbe_host_interface_command"); 4389 4390 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4391 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4392 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4393 } 4394 /* Set bit 9 of FWSTS clearing FW reset indication */ 4395 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4396 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4397 4398 /* Check that the host interface is enabled. */ 4399 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4400 if ((hicr & IXGBE_HICR_EN) == 0) { 4401 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4402 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4403 } 4404 4405 /* Calculate length in DWORDs. We must be DWORD aligned */ 4406 if ((length % (sizeof(u32))) != 0) { 4407 DEBUGOUT("Buffer length failure, not aligned to dword"); 4408 return IXGBE_ERR_INVALID_ARGUMENT; 4409 } 4410 4411 dword_len = length >> 2; 4412 4413 /* The device driver writes the relevant command block 4414 * into the ram area. 4415 */ 4416 for (i = 0; i < dword_len; i++) 4417 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4418 i, IXGBE_CPU_TO_LE32(buffer[i])); 4419 4420 /* Setting this bit tells the ARC that a new command is pending. */ 4421 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4422 4423 for (i = 0; i < timeout; i++) { 4424 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4425 if (!(hicr & IXGBE_HICR_C)) 4426 break; 4427 msec_delay(1); 4428 } 4429 4430 /* Check command completion */ 4431 if ((timeout != 0 && i == timeout) || 4432 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4433 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4434 "Command has failed with no status valid.\n"); 4435 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4436 } 4437 4438 if (!return_data) 4439 return 0; 4440 4441 /* Calculate length in DWORDs */ 4442 dword_len = hdr_size >> 2; 4443 4444 /* first pull in the header so we know the buffer length */ 4445 for (bi = 0; bi < dword_len; bi++) { 4446 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4447 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4448 } 4449 4450 /* If there is any thing in data position pull it in */ 4451 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; 4452 if (buf_len == 0) 4453 return 0; 4454 4455 if (length < buf_len + hdr_size) { 4456 DEBUGOUT("Buffer not large enough for reply message.\n"); 4457 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4458 } 4459 4460 /* Calculate length in DWORDs, add 3 for odd lengths */ 4461 dword_len = (buf_len + 3) >> 2; 4462 4463 /* Pull in the rest of the buffer (bi is where we left off) */ 4464 for (; bi <= dword_len; bi++) { 4465 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4466 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4467 } 4468 4469 return 0; 4470 } 4471 4472 /** 4473 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4474 * @hw: pointer to the HW structure 4475 * @maj: driver version major number 4476 * @minr: driver version minor number 4477 * @build: driver version build number 4478 * @sub: driver version sub build number 4479 * 4480 * Sends driver version number to firmware through the manageability 4481 * block. On success return IXGBE_SUCCESS 4482 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4483 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4484 **/ 4485 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 minr, 4486 u8 build, u8 sub) 4487 { 4488 struct ixgbe_hic_drv_info fw_cmd; 4489 int i; 4490 s32 ret_val = IXGBE_SUCCESS; 4491 4492 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4493 4494 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) 4495 != IXGBE_SUCCESS) { 4496 ret_val = IXGBE_ERR_SWFW_SYNC; 4497 goto out; 4498 } 4499 4500 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4501 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4502 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4503 fw_cmd.port_num = (u8)hw->bus.func; 4504 fw_cmd.ver_maj = maj; 4505 fw_cmd.ver_min = minr; 4506 fw_cmd.ver_build = build; 4507 fw_cmd.ver_sub = sub; 4508 fw_cmd.hdr.checksum = 0; 4509 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4510 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4511 fw_cmd.pad = 0; 4512 fw_cmd.pad2 = 0; 4513 4514 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4515 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4516 sizeof(fw_cmd), 4517 IXGBE_HI_COMMAND_TIMEOUT, 4518 TRUE); 4519 if (ret_val != IXGBE_SUCCESS) 4520 continue; 4521 4522 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4523 FW_CEM_RESP_STATUS_SUCCESS) 4524 ret_val = IXGBE_SUCCESS; 4525 else 4526 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4527 4528 break; 4529 } 4530 4531 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4532 out: 4533 return ret_val; 4534 } 4535 4536 /** 4537 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4538 * @hw: pointer to hardware structure 4539 * @num_pb: number of packet buffers to allocate 4540 * @headroom: reserve n KB of headroom 4541 * @strategy: packet buffer allocation strategy 4542 **/ 4543 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4544 int strategy) 4545 { 4546 u32 pbsize = hw->mac.rx_pb_size; 4547 int i = 0; 4548 u32 rxpktsize, txpktsize, txpbthresh; 4549 4550 /* Reserve headroom */ 4551 pbsize -= headroom; 4552 4553 if (!num_pb) 4554 num_pb = 1; 4555 4556 /* Divide remaining packet buffer space amongst the number of packet 4557 * buffers requested using supplied strategy. 4558 */ 4559 switch (strategy) { 4560 case PBA_STRATEGY_WEIGHTED: 4561 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4562 * buffer with 5/8 of the packet buffer space. 4563 */ 4564 rxpktsize = (pbsize * 5) / (num_pb * 4); 4565 pbsize -= rxpktsize * (num_pb / 2); 4566 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4567 for (; i < (num_pb / 2); i++) 4568 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4569 /* Fall through to configure remaining packet buffers */ 4570 case PBA_STRATEGY_EQUAL: 4571 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4572 for (; i < num_pb; i++) 4573 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4574 break; 4575 default: 4576 break; 4577 } 4578 4579 /* Only support an equally distributed Tx packet buffer strategy. */ 4580 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4581 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4582 for (i = 0; i < num_pb; i++) { 4583 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4584 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4585 } 4586 4587 /* Clear unused TCs, if any, to zero buffer size*/ 4588 for (; i < IXGBE_MAX_PB; i++) { 4589 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4590 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4591 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4592 } 4593 } 4594 4595 /** 4596 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4597 * @hw: pointer to the hardware structure 4598 * 4599 * The 82599 and x540 MACs can experience issues if TX work is still pending 4600 * when a reset occurs. This function prevents this by flushing the PCIe 4601 * buffers on the system. 4602 **/ 4603 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4604 { 4605 u32 gcr_ext, hlreg0, i, poll; 4606 u16 value; 4607 4608 /* 4609 * If double reset is not requested then all transactions should 4610 * already be clear and as such there is no work to do 4611 */ 4612 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4613 return; 4614 4615 /* 4616 * Set loopback enable to prevent any transmits from being sent 4617 * should the link come up. This assumes that the RXCTRL.RXEN bit 4618 * has already been cleared. 4619 */ 4620 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4621 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4622 4623 /* Wait for a last completion before clearing buffers */ 4624 IXGBE_WRITE_FLUSH(hw); 4625 msec_delay(3); 4626 4627 /* 4628 * Before proceeding, make sure that the PCIe block does not have 4629 * transactions pending. 4630 */ 4631 poll = ixgbe_pcie_timeout_poll(hw); 4632 for (i = 0; i < poll; i++) { 4633 usec_delay(100); 4634 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4635 if (IXGBE_REMOVED(hw->hw_addr)) 4636 goto out; 4637 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4638 goto out; 4639 } 4640 4641 out: 4642 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4643 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4644 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4645 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4646 4647 /* Flush all writes and allow 20usec for all transactions to clear */ 4648 IXGBE_WRITE_FLUSH(hw); 4649 usec_delay(20); 4650 4651 /* restore previous register values */ 4652 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4653 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4654 } 4655 4656 4657 /** 4658 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 4659 * @hw: pointer to hardware structure 4660 * @map: pointer to u8 arr for returning map 4661 * 4662 * Read the rtrup2tc HW register and resolve its content into map 4663 **/ 4664 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 4665 { 4666 u32 reg, i; 4667 4668 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 4669 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 4670 map[i] = IXGBE_RTRUP2TC_UP_MASK & 4671 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 4672 return; 4673 } 4674 4675 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 4676 { 4677 u32 pfdtxgswc; 4678 u32 rxctrl; 4679 4680 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4681 if (rxctrl & IXGBE_RXCTRL_RXEN) { 4682 if (hw->mac.type != ixgbe_mac_82598EB) { 4683 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4684 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 4685 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 4686 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4687 hw->mac.set_lben = TRUE; 4688 } else { 4689 hw->mac.set_lben = FALSE; 4690 } 4691 } 4692 rxctrl &= ~IXGBE_RXCTRL_RXEN; 4693 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 4694 } 4695 } 4696 4697 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 4698 { 4699 u32 pfdtxgswc; 4700 u32 rxctrl; 4701 4702 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4703 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 4704 4705 if (hw->mac.type != ixgbe_mac_82598EB) { 4706 if (hw->mac.set_lben) { 4707 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4708 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 4709 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4710 hw->mac.set_lben = FALSE; 4711 } 4712 } 4713 } 4714 4715 /** 4716 * ixgbe_mng_present - returns TRUE when management capability is present 4717 * @hw: pointer to hardware structure 4718 */ 4719 bool ixgbe_mng_present(struct ixgbe_hw *hw) 4720 { 4721 u32 fwsm; 4722 4723 if (hw->mac.type < ixgbe_mac_82599EB) 4724 return FALSE; 4725 4726 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 4727 fwsm &= IXGBE_FWSM_MODE_MASK; 4728 return fwsm == IXGBE_FWSM_FW_MODE_PT; 4729 } 4730 4731 /** 4732 * ixgbe_mng_enabled - Is the manageability engine enabled? 4733 * @hw: pointer to hardware structure 4734 * 4735 * Returns TRUE if the manageability engine is enabled. 4736 **/ 4737 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 4738 { 4739 u32 fwsm, manc, factps; 4740 4741 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 4742 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 4743 return FALSE; 4744 4745 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 4746 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 4747 return FALSE; 4748 4749 if (hw->mac.type <= ixgbe_mac_X540) { 4750 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 4751 if (factps & IXGBE_FACTPS_MNGCG) 4752 return FALSE; 4753 } 4754 4755 return TRUE; 4756 } 4757 4758 /** 4759 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 4760 * @hw: pointer to hardware structure 4761 * @speed: new link speed 4762 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 4763 * 4764 * Set the link speed in the MAC and/or PHY register and restarts link. 4765 **/ 4766 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 4767 ixgbe_link_speed speed, 4768 bool autoneg_wait_to_complete) 4769 { 4770 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4771 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4772 s32 status = IXGBE_SUCCESS; 4773 u32 speedcnt = 0; 4774 u32 i = 0; 4775 bool autoneg, link_up = FALSE; 4776 4777 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 4778 4779 /* Mask off requested but non-supported speeds */ 4780 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 4781 if (status != IXGBE_SUCCESS) 4782 return status; 4783 4784 speed &= link_speed; 4785 4786 /* Try each speed one by one, highest priority first. We do this in 4787 * software because 10Gb fiber doesn't support speed autonegotiation. 4788 */ 4789 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 4790 speedcnt++; 4791 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 4792 4793 /* If we already have link at this speed, just jump out */ 4794 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 4795 if (status != IXGBE_SUCCESS) 4796 return status; 4797 4798 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 4799 goto out; 4800 4801 /* Set the module link speed */ 4802 switch (hw->phy.media_type) { 4803 case ixgbe_media_type_fiber_fixed: 4804 case ixgbe_media_type_fiber: 4805 ixgbe_set_rate_select_speed(hw, 4806 IXGBE_LINK_SPEED_10GB_FULL); 4807 break; 4808 case ixgbe_media_type_fiber_qsfp: 4809 /* QSFP module automatically detects MAC link speed */ 4810 break; 4811 default: 4812 DEBUGOUT("Unexpected media type.\n"); 4813 break; 4814 } 4815 4816 /* Allow module to change analog characteristics (1G->10G) */ 4817 msec_delay(40); 4818 4819 status = ixgbe_setup_mac_link(hw, 4820 IXGBE_LINK_SPEED_10GB_FULL, 4821 autoneg_wait_to_complete); 4822 if (status != IXGBE_SUCCESS) 4823 return status; 4824 4825 /* Flap the Tx laser if it has not already been done */ 4826 ixgbe_flap_tx_laser(hw); 4827 4828 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 4829 * Section 73.10.2, we may have to wait up to 500ms if KR is 4830 * attempted. 82599 uses the same timing for 10g SFI. 4831 */ 4832 for (i = 0; i < 5; i++) { 4833 /* Wait for the link partner to also set speed */ 4834 msec_delay(100); 4835 4836 /* If we have link, just jump out */ 4837 status = ixgbe_check_link(hw, &link_speed, 4838 &link_up, FALSE); 4839 if (status != IXGBE_SUCCESS) 4840 return status; 4841 4842 if (link_up) 4843 goto out; 4844 } 4845 } 4846 4847 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 4848 speedcnt++; 4849 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 4850 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 4851 4852 /* If we already have link at this speed, just jump out */ 4853 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 4854 if (status != IXGBE_SUCCESS) 4855 return status; 4856 4857 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 4858 goto out; 4859 4860 /* Set the module link speed */ 4861 switch (hw->phy.media_type) { 4862 case ixgbe_media_type_fiber_fixed: 4863 case ixgbe_media_type_fiber: 4864 ixgbe_set_rate_select_speed(hw, 4865 IXGBE_LINK_SPEED_1GB_FULL); 4866 break; 4867 case ixgbe_media_type_fiber_qsfp: 4868 /* QSFP module automatically detects link speed */ 4869 break; 4870 default: 4871 DEBUGOUT("Unexpected media type.\n"); 4872 break; 4873 } 4874 4875 /* Allow module to change analog characteristics (10G->1G) */ 4876 msec_delay(40); 4877 4878 status = ixgbe_setup_mac_link(hw, 4879 IXGBE_LINK_SPEED_1GB_FULL, 4880 autoneg_wait_to_complete); 4881 if (status != IXGBE_SUCCESS) 4882 return status; 4883 4884 /* Flap the Tx laser if it has not already been done */ 4885 ixgbe_flap_tx_laser(hw); 4886 4887 /* Wait for the link partner to also set speed */ 4888 msec_delay(100); 4889 4890 /* If we have link, just jump out */ 4891 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 4892 if (status != IXGBE_SUCCESS) 4893 return status; 4894 4895 if (link_up) 4896 goto out; 4897 } 4898 4899 /* We didn't get link. Configure back to the highest speed we tried, 4900 * (if there was more than one). We call ourselves back with just the 4901 * single highest speed that the user requested. 4902 */ 4903 if (speedcnt > 1) 4904 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 4905 highest_link_speed, 4906 autoneg_wait_to_complete); 4907 4908 out: 4909 /* Set autoneg_advertised value based on input link speed */ 4910 hw->phy.autoneg_advertised = 0; 4911 4912 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4913 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 4914 4915 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 4916 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 4917 4918 return status; 4919 } 4920 4921 /** 4922 * ixgbe_set_soft_rate_select_speed - Set module link speed 4923 * @hw: pointer to hardware structure 4924 * @speed: link speed to set 4925 * 4926 * Set module link speed via the soft rate select. 4927 */ 4928 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 4929 ixgbe_link_speed speed) 4930 { 4931 s32 status; 4932 u8 rs, eeprom_data; 4933 4934 switch (speed) { 4935 case IXGBE_LINK_SPEED_10GB_FULL: 4936 /* one bit mask same as setting on */ 4937 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 4938 break; 4939 case IXGBE_LINK_SPEED_1GB_FULL: 4940 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 4941 break; 4942 default: 4943 DEBUGOUT("Invalid fixed module speed\n"); 4944 return; 4945 } 4946 4947 /* Set RS0 */ 4948 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4949 IXGBE_I2C_EEPROM_DEV_ADDR2, 4950 &eeprom_data); 4951 if (status) { 4952 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 4953 goto out; 4954 } 4955 4956 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4957 4958 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4959 IXGBE_I2C_EEPROM_DEV_ADDR2, 4960 eeprom_data); 4961 if (status) { 4962 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 4963 goto out; 4964 } 4965 4966 /* Set RS1 */ 4967 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4968 IXGBE_I2C_EEPROM_DEV_ADDR2, 4969 &eeprom_data); 4970 if (status) { 4971 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 4972 goto out; 4973 } 4974 4975 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4976 4977 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4978 IXGBE_I2C_EEPROM_DEV_ADDR2, 4979 eeprom_data); 4980 if (status) { 4981 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 4982 goto out; 4983 } 4984 out: 4985 return; 4986 } 4987
Indexes created Fri Sep 26 20:09:58 GMT 2025