ixgbe_common.c revision 1.24
1 /* $NetBSD: ixgbe_common.c,v 1.24 2019/07/25 07:05:44 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 #include "ixgbe_dcb.h" 41 #include "ixgbe_dcb_82599.h" 42 #include "ixgbe_api.h" 43 44 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 45 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 46 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 47 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 48 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 49 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 50 u16 count); 51 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 52 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 53 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 54 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 55 56 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 57 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 58 u16 *san_mac_offset); 59 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 60 u16 words, u16 *data); 61 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 62 u16 words, u16 *data); 63 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 64 u16 offset); 65 66 /** 67 * ixgbe_init_ops_generic - Inits function ptrs 68 * @hw: pointer to the hardware structure 69 * 70 * Initialize the function pointers. 71 **/ 72 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 73 { 74 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 75 struct ixgbe_mac_info *mac = &hw->mac; 76 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 77 78 DEBUGFUNC("ixgbe_init_ops_generic"); 79 80 /* EEPROM */ 81 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 82 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 83 if (eec & IXGBE_EEC_PRES) { 84 eeprom->ops.read = ixgbe_read_eerd_generic; 85 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 86 } else { 87 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 88 eeprom->ops.read_buffer = 89 ixgbe_read_eeprom_buffer_bit_bang_generic; 90 } 91 eeprom->ops.write = ixgbe_write_eeprom_generic; 92 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 93 eeprom->ops.validate_checksum = 94 ixgbe_validate_eeprom_checksum_generic; 95 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 96 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 97 98 /* MAC */ 99 mac->ops.init_hw = ixgbe_init_hw_generic; 100 mac->ops.reset_hw = NULL; 101 mac->ops.start_hw = ixgbe_start_hw_generic; 102 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 103 mac->ops.get_media_type = NULL; 104 mac->ops.get_supported_physical_layer = NULL; 105 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 106 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 107 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 108 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 109 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 110 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 111 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 112 mac->ops.prot_autoc_read = prot_autoc_read_generic; 113 mac->ops.prot_autoc_write = prot_autoc_write_generic; 114 115 /* LEDs */ 116 mac->ops.led_on = ixgbe_led_on_generic; 117 mac->ops.led_off = ixgbe_led_off_generic; 118 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 119 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 120 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; 121 122 /* RAR, Multicast, VLAN */ 123 mac->ops.set_rar = ixgbe_set_rar_generic; 124 mac->ops.clear_rar = ixgbe_clear_rar_generic; 125 mac->ops.insert_mac_addr = NULL; 126 mac->ops.set_vmdq = NULL; 127 mac->ops.clear_vmdq = NULL; 128 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 129 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 130 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 131 mac->ops.enable_mc = ixgbe_enable_mc_generic; 132 mac->ops.disable_mc = ixgbe_disable_mc_generic; 133 mac->ops.clear_vfta = NULL; 134 mac->ops.set_vfta = NULL; 135 mac->ops.set_vlvf = NULL; 136 mac->ops.init_uta_tables = NULL; 137 mac->ops.enable_rx = ixgbe_enable_rx_generic; 138 mac->ops.disable_rx = ixgbe_disable_rx_generic; 139 mac->ops.toggle_txdctl = ixgbe_toggle_txdctl_generic; 140 141 /* Flow Control */ 142 mac->ops.fc_enable = ixgbe_fc_enable_generic; 143 mac->ops.setup_fc = ixgbe_setup_fc_generic; 144 mac->ops.fc_autoneg = ixgbe_fc_autoneg; 145 146 /* Link */ 147 mac->ops.get_link_capabilities = NULL; 148 mac->ops.setup_link = NULL; 149 mac->ops.check_link = NULL; 150 mac->ops.dmac_config = NULL; 151 mac->ops.dmac_update_tcs = NULL; 152 mac->ops.dmac_config_tcs = NULL; 153 154 return IXGBE_SUCCESS; 155 } 156 157 /** 158 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 159 * of flow control 160 * @hw: pointer to hardware structure 161 * 162 * This function returns TRUE if the device supports flow control 163 * autonegotiation, and FALSE if it does not. 164 * 165 **/ 166 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 167 { 168 bool supported = FALSE; 169 ixgbe_link_speed speed; 170 bool link_up; 171 172 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 173 174 switch (hw->phy.media_type) { 175 case ixgbe_media_type_fiber_fixed: 176 case ixgbe_media_type_fiber_qsfp: 177 case ixgbe_media_type_fiber: 178 /* flow control autoneg black list */ 179 switch (hw->device_id) { 180 case IXGBE_DEV_ID_X550EM_A_SFP: 181 case IXGBE_DEV_ID_X550EM_A_SFP_N: 182 case IXGBE_DEV_ID_X550EM_A_QSFP: 183 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 184 supported = FALSE; 185 break; 186 default: 187 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 188 /* if link is down, assume supported */ 189 if (link_up) 190 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 191 TRUE : FALSE; 192 else 193 supported = TRUE; 194 } 195 196 break; 197 case ixgbe_media_type_backplane: 198 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 199 supported = FALSE; 200 else 201 supported = TRUE; 202 break; 203 case ixgbe_media_type_copper: 204 /* only some copper devices support flow control autoneg */ 205 switch (hw->device_id) { 206 case IXGBE_DEV_ID_82599_T3_LOM: 207 case IXGBE_DEV_ID_X540T: 208 case IXGBE_DEV_ID_X540T1: 209 case IXGBE_DEV_ID_X540_BYPASS: 210 case IXGBE_DEV_ID_X550T: 211 case IXGBE_DEV_ID_X550T1: 212 case IXGBE_DEV_ID_X550EM_X_10G_T: 213 case IXGBE_DEV_ID_X550EM_A_10G_T: 214 case IXGBE_DEV_ID_X550EM_A_1G_T: 215 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 216 supported = TRUE; 217 break; 218 default: 219 supported = FALSE; 220 } 221 default: 222 break; 223 } 224 225 if (!supported) 226 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 227 "Device %x does not support flow control autoneg", 228 hw->device_id); 229 230 return supported; 231 } 232 233 /** 234 * ixgbe_setup_fc_generic - Set up flow control 235 * @hw: pointer to hardware structure 236 * 237 * Called at init time to set up flow control. 238 **/ 239 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 240 { 241 s32 ret_val = IXGBE_SUCCESS; 242 u32 reg = 0, reg_bp = 0; 243 u16 reg_cu = 0; 244 bool locked = FALSE; 245 246 DEBUGFUNC("ixgbe_setup_fc_generic"); 247 248 /* Validate the requested mode */ 249 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 250 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 251 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 252 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 253 goto out; 254 } 255 256 /* 257 * 10gig parts do not have a word in the EEPROM to determine the 258 * default flow control setting, so we explicitly set it to full. 259 */ 260 if (hw->fc.requested_mode == ixgbe_fc_default) 261 hw->fc.requested_mode = ixgbe_fc_full; 262 263 /* 264 * Set up the 1G and 10G flow control advertisement registers so the 265 * HW will be able to do fc autoneg once the cable is plugged in. If 266 * we link at 10G, the 1G advertisement is harmless and vice versa. 267 */ 268 switch (hw->phy.media_type) { 269 case ixgbe_media_type_backplane: 270 /* some MAC's need RMW protection on AUTOC */ 271 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 272 if (ret_val != IXGBE_SUCCESS) 273 goto out; 274 275 /* fall through - only backplane uses autoc */ 276 case ixgbe_media_type_fiber_fixed: 277 case ixgbe_media_type_fiber_qsfp: 278 case ixgbe_media_type_fiber: 279 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 280 281 break; 282 case ixgbe_media_type_copper: 283 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 284 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 285 break; 286 default: 287 break; 288 } 289 290 /* 291 * The possible values of fc.requested_mode are: 292 * 0: Flow control is completely disabled 293 * 1: Rx flow control is enabled (we can receive pause frames, 294 * but not send pause frames). 295 * 2: Tx flow control is enabled (we can send pause frames but 296 * we do not support receiving pause frames). 297 * 3: Both Rx and Tx flow control (symmetric) are enabled. 298 * other: Invalid. 299 */ 300 switch (hw->fc.requested_mode) { 301 case ixgbe_fc_none: 302 /* Flow control completely disabled by software override. */ 303 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 304 if (hw->phy.media_type == ixgbe_media_type_backplane) 305 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 306 IXGBE_AUTOC_ASM_PAUSE); 307 else if (hw->phy.media_type == ixgbe_media_type_copper) 308 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 309 break; 310 case ixgbe_fc_tx_pause: 311 /* 312 * Tx Flow control is enabled, and Rx Flow control is 313 * disabled by software override. 314 */ 315 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 316 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 317 if (hw->phy.media_type == ixgbe_media_type_backplane) { 318 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 319 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 320 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 321 reg_cu |= IXGBE_TAF_ASM_PAUSE; 322 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 323 } 324 break; 325 case ixgbe_fc_rx_pause: 326 /* 327 * Rx Flow control is enabled and Tx Flow control is 328 * disabled by software override. Since there really 329 * isn't a way to advertise that we are capable of RX 330 * Pause ONLY, we will advertise that we support both 331 * symmetric and asymmetric Rx PAUSE, as such we fall 332 * through to the fc_full statement. Later, we will 333 * disable the adapter's ability to send PAUSE frames. 334 */ 335 case ixgbe_fc_full: 336 /* Flow control (both Rx and Tx) is enabled by SW override. */ 337 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 338 if (hw->phy.media_type == ixgbe_media_type_backplane) 339 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 340 IXGBE_AUTOC_ASM_PAUSE; 341 else if (hw->phy.media_type == ixgbe_media_type_copper) 342 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 343 break; 344 default: 345 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 346 "Flow control param set incorrectly\n"); 347 ret_val = IXGBE_ERR_CONFIG; 348 goto out; 349 break; 350 } 351 352 if (hw->mac.type < ixgbe_mac_X540) { 353 /* 354 * Enable auto-negotiation between the MAC & PHY; 355 * the MAC will advertise clause 37 flow control. 356 */ 357 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 358 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 359 360 /* Disable AN timeout */ 361 if (hw->fc.strict_ieee) 362 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 363 364 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 365 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 366 } 367 368 /* 369 * AUTOC restart handles negotiation of 1G and 10G on backplane 370 * and copper. There is no need to set the PCS1GCTL register. 371 * 372 */ 373 if (hw->phy.media_type == ixgbe_media_type_backplane) { 374 reg_bp |= IXGBE_AUTOC_AN_RESTART; 375 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 376 if (ret_val) 377 goto out; 378 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 379 (ixgbe_device_supports_autoneg_fc(hw))) { 380 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 381 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 382 } 383 384 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 385 out: 386 return ret_val; 387 } 388 389 /** 390 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 391 * @hw: pointer to hardware structure 392 * 393 * Starts the hardware by filling the bus info structure and media type, clears 394 * all on chip counters, initializes receive address registers, multicast 395 * table, VLAN filter table, calls routine to set up link and flow control 396 * settings, and leaves transmit and receive units disabled and uninitialized 397 **/ 398 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 399 { 400 s32 ret_val; 401 u32 ctrl_ext; 402 u16 device_caps; 403 404 DEBUGFUNC("ixgbe_start_hw_generic"); 405 406 /* Set the media type */ 407 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 408 409 /* PHY ops initialization must be done in reset_hw() */ 410 411 /* Clear the VLAN filter table */ 412 hw->mac.ops.clear_vfta(hw); 413 414 /* Clear statistics registers */ 415 hw->mac.ops.clear_hw_cntrs(hw); 416 417 /* Set No Snoop Disable */ 418 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 419 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 420 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 421 IXGBE_WRITE_FLUSH(hw); 422 423 /* Setup flow control */ 424 ret_val = ixgbe_setup_fc(hw); 425 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 426 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 427 return ret_val; 428 } 429 430 /* Cache bit indicating need for crosstalk fix */ 431 switch (hw->mac.type) { 432 case ixgbe_mac_82599EB: 433 case ixgbe_mac_X550EM_x: 434 case ixgbe_mac_X550EM_a: 435 hw->mac.ops.get_device_caps(hw, &device_caps); 436 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 437 hw->need_crosstalk_fix = FALSE; 438 else 439 hw->need_crosstalk_fix = TRUE; 440 break; 441 default: 442 hw->need_crosstalk_fix = FALSE; 443 break; 444 } 445 446 /* Clear adapter stopped flag */ 447 hw->adapter_stopped = FALSE; 448 449 return IXGBE_SUCCESS; 450 } 451 452 /** 453 * ixgbe_start_hw_gen2 - Init sequence for common device family 454 * @hw: pointer to hw structure 455 * 456 * Performs the init sequence common to the second generation 457 * of 10 GbE devices. 458 * Devices in the second generation: 459 * 82599 460 * X540 461 **/ 462 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 463 { 464 u32 i; 465 u32 regval; 466 467 /* Clear the rate limiters */ 468 for (i = 0; i < hw->mac.max_tx_queues; i++) { 469 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 470 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 471 } 472 IXGBE_WRITE_FLUSH(hw); 473 474 /* Disable relaxed ordering */ 475 for (i = 0; i < hw->mac.max_tx_queues; i++) { 476 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 477 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 478 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 479 } 480 481 for (i = 0; i < hw->mac.max_rx_queues; i++) { 482 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 483 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 484 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 485 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 486 } 487 488 return IXGBE_SUCCESS; 489 } 490 491 /** 492 * ixgbe_init_hw_generic - Generic hardware initialization 493 * @hw: pointer to hardware structure 494 * 495 * Initialize the hardware by resetting the hardware, filling the bus info 496 * structure and media type, clears all on chip counters, initializes receive 497 * address registers, multicast table, VLAN filter table, calls routine to set 498 * up link and flow control settings, and leaves transmit and receive units 499 * disabled and uninitialized 500 **/ 501 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 502 { 503 s32 status; 504 505 DEBUGFUNC("ixgbe_init_hw_generic"); 506 507 /* Reset the hardware */ 508 status = hw->mac.ops.reset_hw(hw); 509 510 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { 511 /* Start the HW */ 512 status = hw->mac.ops.start_hw(hw); 513 } 514 515 /* Initialize the LED link active for LED blink support */ 516 if (hw->mac.ops.init_led_link_act) 517 hw->mac.ops.init_led_link_act(hw); 518 519 if (status != IXGBE_SUCCESS) 520 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 521 522 return status; 523 } 524 525 /** 526 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 527 * @hw: pointer to hardware structure 528 * 529 * Clears all hardware statistics counters by reading them from the hardware 530 * Statistics counters are clear on read. 531 **/ 532 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 533 { 534 u16 i = 0; 535 536 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 537 538 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 539 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 540 IXGBE_READ_REG(hw, IXGBE_ERRBC); 541 IXGBE_READ_REG(hw, IXGBE_MSPDC); 542 if (hw->mac.type >= ixgbe_mac_X550) 543 IXGBE_READ_REG(hw, IXGBE_MBSDC); 544 for (i = 0; i < 8; i++) 545 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 546 547 IXGBE_READ_REG(hw, IXGBE_MLFC); 548 IXGBE_READ_REG(hw, IXGBE_MRFC); 549 IXGBE_READ_REG(hw, IXGBE_RLEC); 550 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 551 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 552 if (hw->mac.type >= ixgbe_mac_82599EB) { 553 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 554 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 555 } else { 556 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 557 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 558 } 559 560 for (i = 0; i < 8; i++) { 561 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 562 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 563 if (hw->mac.type >= ixgbe_mac_82599EB) { 564 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 565 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 566 } else { 567 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 568 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 569 } 570 } 571 if (hw->mac.type >= ixgbe_mac_82599EB) 572 for (i = 0; i < 8; i++) 573 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 574 IXGBE_READ_REG(hw, IXGBE_PRC64); 575 IXGBE_READ_REG(hw, IXGBE_PRC127); 576 IXGBE_READ_REG(hw, IXGBE_PRC255); 577 IXGBE_READ_REG(hw, IXGBE_PRC511); 578 IXGBE_READ_REG(hw, IXGBE_PRC1023); 579 IXGBE_READ_REG(hw, IXGBE_PRC1522); 580 IXGBE_READ_REG(hw, IXGBE_GPRC); 581 IXGBE_READ_REG(hw, IXGBE_BPRC); 582 IXGBE_READ_REG(hw, IXGBE_MPRC); 583 IXGBE_READ_REG(hw, IXGBE_GPTC); 584 IXGBE_READ_REG(hw, IXGBE_GORCL); 585 IXGBE_READ_REG(hw, IXGBE_GORCH); 586 IXGBE_READ_REG(hw, IXGBE_GOTCL); 587 IXGBE_READ_REG(hw, IXGBE_GOTCH); 588 if (hw->mac.type == ixgbe_mac_82598EB) 589 for (i = 0; i < 8; i++) 590 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 591 IXGBE_READ_REG(hw, IXGBE_RUC); 592 IXGBE_READ_REG(hw, IXGBE_RFC); 593 IXGBE_READ_REG(hw, IXGBE_ROC); 594 IXGBE_READ_REG(hw, IXGBE_RJC); 595 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 596 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 597 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 598 IXGBE_READ_REG(hw, IXGBE_TORL); 599 IXGBE_READ_REG(hw, IXGBE_TORH); 600 IXGBE_READ_REG(hw, IXGBE_TPR); 601 IXGBE_READ_REG(hw, IXGBE_TPT); 602 IXGBE_READ_REG(hw, IXGBE_PTC64); 603 IXGBE_READ_REG(hw, IXGBE_PTC127); 604 IXGBE_READ_REG(hw, IXGBE_PTC255); 605 IXGBE_READ_REG(hw, IXGBE_PTC511); 606 IXGBE_READ_REG(hw, IXGBE_PTC1023); 607 IXGBE_READ_REG(hw, IXGBE_PTC1522); 608 IXGBE_READ_REG(hw, IXGBE_MPTC); 609 IXGBE_READ_REG(hw, IXGBE_BPTC); 610 for (i = 0; i < 16; i++) { 611 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 612 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 613 if (hw->mac.type >= ixgbe_mac_82599EB) { 614 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 615 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 616 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 617 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 618 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 619 } else { 620 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 621 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 622 } 623 } 624 625 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 626 if (hw->phy.id == 0) 627 ixgbe_identify_phy(hw); 628 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 629 IXGBE_MDIO_PCS_DEV_TYPE, &i); 630 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 631 IXGBE_MDIO_PCS_DEV_TYPE, &i); 632 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 633 IXGBE_MDIO_PCS_DEV_TYPE, &i); 634 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 635 IXGBE_MDIO_PCS_DEV_TYPE, &i); 636 } 637 638 return IXGBE_SUCCESS; 639 } 640 641 /** 642 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 643 * @hw: pointer to hardware structure 644 * @pba_num: stores the part number string from the EEPROM 645 * @pba_num_size: part number string buffer length 646 * 647 * Reads the part number string from the EEPROM. 648 **/ 649 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 650 u32 pba_num_size) 651 { 652 s32 ret_val; 653 u16 data; 654 u16 pba_ptr; 655 u16 offset; 656 u16 length; 657 658 DEBUGFUNC("ixgbe_read_pba_string_generic"); 659 660 if (pba_num == NULL) { 661 DEBUGOUT("PBA string buffer was null\n"); 662 return IXGBE_ERR_INVALID_ARGUMENT; 663 } 664 665 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 666 if (ret_val) { 667 DEBUGOUT("NVM Read Error\n"); 668 return ret_val; 669 } 670 671 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 672 if (ret_val) { 673 DEBUGOUT("NVM Read Error\n"); 674 return ret_val; 675 } 676 677 /* 678 * if data is not ptr guard the PBA must be in legacy format which 679 * means pba_ptr is actually our second data word for the PBA number 680 * and we can decode it into an ascii string 681 */ 682 if (data != IXGBE_PBANUM_PTR_GUARD) { 683 DEBUGOUT("NVM PBA number is not stored as string\n"); 684 685 /* we will need 11 characters to store the PBA */ 686 if (pba_num_size < 11) { 687 DEBUGOUT("PBA string buffer too small\n"); 688 return IXGBE_ERR_NO_SPACE; 689 } 690 691 /* extract hex string from data and pba_ptr */ 692 pba_num[0] = (data >> 12) & 0xF; 693 pba_num[1] = (data >> 8) & 0xF; 694 pba_num[2] = (data >> 4) & 0xF; 695 pba_num[3] = data & 0xF; 696 pba_num[4] = (pba_ptr >> 12) & 0xF; 697 pba_num[5] = (pba_ptr >> 8) & 0xF; 698 pba_num[6] = '-'; 699 pba_num[7] = 0; 700 pba_num[8] = (pba_ptr >> 4) & 0xF; 701 pba_num[9] = pba_ptr & 0xF; 702 703 /* put a null character on the end of our string */ 704 pba_num[10] = '\0'; 705 706 /* switch all the data but the '-' to hex char */ 707 for (offset = 0; offset < 10; offset++) { 708 if (pba_num[offset] < 0xA) 709 pba_num[offset] += '0'; 710 else if (pba_num[offset] < 0x10) 711 pba_num[offset] += 'A' - 0xA; 712 } 713 714 return IXGBE_SUCCESS; 715 } 716 717 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 718 if (ret_val) { 719 DEBUGOUT("NVM Read Error\n"); 720 return ret_val; 721 } 722 723 if (length == 0xFFFF || length == 0) { 724 DEBUGOUT("NVM PBA number section invalid length\n"); 725 return IXGBE_ERR_PBA_SECTION; 726 } 727 728 /* check if pba_num buffer is big enough */ 729 if (pba_num_size < (((u32)length * 2) - 1)) { 730 DEBUGOUT("PBA string buffer too small\n"); 731 return IXGBE_ERR_NO_SPACE; 732 } 733 734 /* trim pba length from start of string */ 735 pba_ptr++; 736 length--; 737 738 for (offset = 0; offset < length; offset++) { 739 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 740 if (ret_val) { 741 DEBUGOUT("NVM Read Error\n"); 742 return ret_val; 743 } 744 pba_num[offset * 2] = (u8)(data >> 8); 745 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 746 } 747 pba_num[offset * 2] = '\0'; 748 749 return IXGBE_SUCCESS; 750 } 751 752 /** 753 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 754 * @hw: pointer to hardware structure 755 * @pba_num: stores the part number from the EEPROM 756 * 757 * Reads the part number from the EEPROM. 758 **/ 759 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 760 { 761 s32 ret_val; 762 u16 data; 763 764 DEBUGFUNC("ixgbe_read_pba_num_generic"); 765 766 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 767 if (ret_val) { 768 DEBUGOUT("NVM Read Error\n"); 769 return ret_val; 770 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 771 DEBUGOUT("NVM Not supported\n"); 772 return IXGBE_NOT_IMPLEMENTED; 773 } 774 *pba_num = (u32)(data << 16); 775 776 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 777 if (ret_val) { 778 DEBUGOUT("NVM Read Error\n"); 779 return ret_val; 780 } 781 *pba_num |= data; 782 783 return IXGBE_SUCCESS; 784 } 785 786 /** 787 * ixgbe_read_pba_raw 788 * @hw: pointer to the HW structure 789 * @eeprom_buf: optional pointer to EEPROM image 790 * @eeprom_buf_size: size of EEPROM image in words 791 * @max_pba_block_size: PBA block size limit 792 * @pba: pointer to output PBA structure 793 * 794 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 795 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 796 * 797 **/ 798 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 799 u32 eeprom_buf_size, u16 max_pba_block_size, 800 struct ixgbe_pba *pba) 801 { 802 s32 ret_val; 803 u16 pba_block_size; 804 805 if (pba == NULL) 806 return IXGBE_ERR_PARAM; 807 808 if (eeprom_buf == NULL) { 809 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 810 &pba->word[0]); 811 if (ret_val) 812 return ret_val; 813 } else { 814 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 815 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 816 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 817 } else { 818 return IXGBE_ERR_PARAM; 819 } 820 } 821 822 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 823 if (pba->pba_block == NULL) 824 return IXGBE_ERR_PARAM; 825 826 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 827 eeprom_buf_size, 828 &pba_block_size); 829 if (ret_val) 830 return ret_val; 831 832 if (pba_block_size > max_pba_block_size) 833 return IXGBE_ERR_PARAM; 834 835 if (eeprom_buf == NULL) { 836 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 837 pba_block_size, 838 pba->pba_block); 839 if (ret_val) 840 return ret_val; 841 } else { 842 if (eeprom_buf_size > (u32)(pba->word[1] + 843 pba_block_size)) { 844 memcpy(pba->pba_block, 845 &eeprom_buf[pba->word[1]], 846 pba_block_size * sizeof(u16)); 847 } else { 848 return IXGBE_ERR_PARAM; 849 } 850 } 851 } 852 853 return IXGBE_SUCCESS; 854 } 855 856 /** 857 * ixgbe_write_pba_raw 858 * @hw: pointer to the HW structure 859 * @eeprom_buf: optional pointer to EEPROM image 860 * @eeprom_buf_size: size of EEPROM image in words 861 * @pba: pointer to PBA structure 862 * 863 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 864 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 865 * 866 **/ 867 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 868 u32 eeprom_buf_size, struct ixgbe_pba *pba) 869 { 870 s32 ret_val; 871 872 if (pba == NULL) 873 return IXGBE_ERR_PARAM; 874 875 if (eeprom_buf == NULL) { 876 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 877 &pba->word[0]); 878 if (ret_val) 879 return ret_val; 880 } else { 881 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 882 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 883 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 884 } else { 885 return IXGBE_ERR_PARAM; 886 } 887 } 888 889 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 890 if (pba->pba_block == NULL) 891 return IXGBE_ERR_PARAM; 892 893 if (eeprom_buf == NULL) { 894 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 895 pba->pba_block[0], 896 pba->pba_block); 897 if (ret_val) 898 return ret_val; 899 } else { 900 if (eeprom_buf_size > (u32)(pba->word[1] + 901 pba->pba_block[0])) { 902 memcpy(&eeprom_buf[pba->word[1]], 903 pba->pba_block, 904 pba->pba_block[0] * sizeof(u16)); 905 } else { 906 return IXGBE_ERR_PARAM; 907 } 908 } 909 } 910 911 return IXGBE_SUCCESS; 912 } 913 914 /** 915 * ixgbe_get_pba_block_size 916 * @hw: pointer to the HW structure 917 * @eeprom_buf: optional pointer to EEPROM image 918 * @eeprom_buf_size: size of EEPROM image in words 919 * @pba_data_size: pointer to output variable 920 * 921 * Returns the size of the PBA block in words. Function operates on EEPROM 922 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 923 * EEPROM device. 924 * 925 **/ 926 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 927 u32 eeprom_buf_size, u16 *pba_block_size) 928 { 929 s32 ret_val; 930 u16 pba_word[2]; 931 u16 length; 932 933 DEBUGFUNC("ixgbe_get_pba_block_size"); 934 935 if (eeprom_buf == NULL) { 936 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 937 &pba_word[0]); 938 if (ret_val) 939 return ret_val; 940 } else { 941 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 942 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 943 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 944 } else { 945 return IXGBE_ERR_PARAM; 946 } 947 } 948 949 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 950 if (eeprom_buf == NULL) { 951 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 952 &length); 953 if (ret_val) 954 return ret_val; 955 } else { 956 if (eeprom_buf_size > pba_word[1]) 957 length = eeprom_buf[pba_word[1] + 0]; 958 else 959 return IXGBE_ERR_PARAM; 960 } 961 962 if (length == 0xFFFF || length == 0) 963 return IXGBE_ERR_PBA_SECTION; 964 } else { 965 /* PBA number in legacy format, there is no PBA Block. */ 966 length = 0; 967 } 968 969 if (pba_block_size != NULL) 970 *pba_block_size = length; 971 972 return IXGBE_SUCCESS; 973 } 974 975 /** 976 * ixgbe_get_mac_addr_generic - Generic get MAC address 977 * @hw: pointer to hardware structure 978 * @mac_addr: Adapter MAC address 979 * 980 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 981 * A reset of the adapter must be performed prior to calling this function 982 * in order for the MAC address to have been loaded from the EEPROM into RAR0 983 **/ 984 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 985 { 986 u32 rar_high; 987 u32 rar_low; 988 u16 i; 989 990 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 991 992 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 993 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 994 995 for (i = 0; i < 4; i++) 996 mac_addr[i] = (u8)(rar_low >> (i*8)); 997 998 for (i = 0; i < 2; i++) 999 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 1000 1001 return IXGBE_SUCCESS; 1002 } 1003 1004 /** 1005 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 1006 * @hw: pointer to hardware structure 1007 * @link_status: the link status returned by the PCI config space 1008 * 1009 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 1010 **/ 1011 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 1012 { 1013 struct ixgbe_mac_info *mac = &hw->mac; 1014 1015 if (hw->bus.type == ixgbe_bus_type_unknown) 1016 hw->bus.type = ixgbe_bus_type_pci_express; 1017 1018 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 1019 case IXGBE_PCI_LINK_WIDTH_1: 1020 hw->bus.width = ixgbe_bus_width_pcie_x1; 1021 break; 1022 case IXGBE_PCI_LINK_WIDTH_2: 1023 hw->bus.width = ixgbe_bus_width_pcie_x2; 1024 break; 1025 case IXGBE_PCI_LINK_WIDTH_4: 1026 hw->bus.width = ixgbe_bus_width_pcie_x4; 1027 break; 1028 case IXGBE_PCI_LINK_WIDTH_8: 1029 hw->bus.width = ixgbe_bus_width_pcie_x8; 1030 break; 1031 default: 1032 hw->bus.width = ixgbe_bus_width_unknown; 1033 break; 1034 } 1035 1036 switch (link_status & IXGBE_PCI_LINK_SPEED) { 1037 case IXGBE_PCI_LINK_SPEED_2500: 1038 hw->bus.speed = ixgbe_bus_speed_2500; 1039 break; 1040 case IXGBE_PCI_LINK_SPEED_5000: 1041 hw->bus.speed = ixgbe_bus_speed_5000; 1042 break; 1043 case IXGBE_PCI_LINK_SPEED_8000: 1044 hw->bus.speed = ixgbe_bus_speed_8000; 1045 break; 1046 default: 1047 hw->bus.speed = ixgbe_bus_speed_unknown; 1048 break; 1049 } 1050 1051 mac->ops.set_lan_id(hw); 1052 } 1053 1054 /** 1055 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1056 * @hw: pointer to hardware structure 1057 * 1058 * Gets the PCI bus info (speed, width, type) then calls helper function to 1059 * store this data within the ixgbe_hw structure. 1060 **/ 1061 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1062 { 1063 u16 link_status; 1064 1065 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1066 1067 /* Get the negotiated link width and speed from PCI config space */ 1068 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 1069 1070 ixgbe_set_pci_config_data_generic(hw, link_status); 1071 1072 return IXGBE_SUCCESS; 1073 } 1074 1075 /** 1076 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1077 * @hw: pointer to the HW structure 1078 * 1079 * Determines the LAN function id by reading memory-mapped registers and swaps 1080 * the port value if requested, and set MAC instance for devices that share 1081 * CS4227. 1082 **/ 1083 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1084 { 1085 struct ixgbe_bus_info *bus = &hw->bus; 1086 u32 reg; 1087 u16 ee_ctrl_4; 1088 1089 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1090 1091 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1092 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1093 bus->lan_id = (u8)bus->func; 1094 1095 /* check for a port swap */ 1096 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1097 if (reg & IXGBE_FACTPS_LFS) 1098 bus->func ^= 0x1; 1099 1100 /* Get MAC instance from EEPROM for configuring CS4227 */ 1101 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1102 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1103 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1104 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1105 } 1106 } 1107 1108 /** 1109 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1110 * @hw: pointer to hardware structure 1111 * 1112 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1113 * disables transmit and receive units. The adapter_stopped flag is used by 1114 * the shared code and drivers to determine if the adapter is in a stopped 1115 * state and should not touch the hardware. 1116 **/ 1117 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1118 { 1119 u32 reg_val; 1120 u16 i; 1121 1122 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1123 1124 /* 1125 * Set the adapter_stopped flag so other driver functions stop touching 1126 * the hardware 1127 */ 1128 hw->adapter_stopped = TRUE; 1129 1130 /* Disable the receive unit */ 1131 ixgbe_disable_rx(hw); 1132 1133 /* Clear interrupt mask to stop interrupts from being generated */ 1134 /* 1135 * XXX 1136 * This function is called in the state of both interrupt disabled 1137 * and interrupt enabled, e.g. 1138 * + interrupt disabled case: 1139 * - ixgbe_stop() 1140 * - ixgbe_disable_intr() // interrupt disabled here 1141 * - ixgbe_stop_adapter() 1142 * - hw->mac.ops.stop_adapter() 1143 * == this function 1144 * + interrupt enabled case: 1145 * - ixgbe_local_timer1() 1146 * - ixgbe_init_locked() 1147 * - ixgbe_stop_adapter() 1148 * - hw->mac.ops.stop_adapter() 1149 * == this function 1150 * Therefore, it causes nest status breaking to nest the status 1151 * (that is, que->im_nest++) at all times. So, this function must 1152 * use ixgbe_ensure_disabled_intr() instead of ixgbe_disable_intr(). 1153 */ 1154 ixgbe_ensure_disabled_intr(hw->back); 1155 1156 /* Clear any pending interrupts, flush previous writes */ 1157 IXGBE_READ_REG(hw, IXGBE_EICR); 1158 1159 /* Disable the transmit unit. Each queue must be disabled. */ 1160 for (i = 0; i < hw->mac.max_tx_queues; i++) 1161 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1162 1163 /* Disable the receive unit by stopping each queue */ 1164 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1165 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1166 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1167 reg_val |= IXGBE_RXDCTL_SWFLSH; 1168 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1169 } 1170 1171 /* flush all queues disables */ 1172 IXGBE_WRITE_FLUSH(hw); 1173 msec_delay(2); 1174 1175 /* 1176 * Prevent the PCI-E bus from hanging by disabling PCI-E master 1177 * access and verify no pending requests 1178 */ 1179 return ixgbe_disable_pcie_master(hw); 1180 } 1181 1182 /** 1183 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1184 * @hw: pointer to hardware structure 1185 * 1186 * Store the index for the link active LED. This will be used to support 1187 * blinking the LED. 1188 **/ 1189 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1190 { 1191 struct ixgbe_mac_info *mac = &hw->mac; 1192 u32 led_reg, led_mode; 1193 u8 i; 1194 1195 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1196 1197 /* Get LED link active from the LEDCTL register */ 1198 for (i = 0; i < 4; i++) { 1199 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1200 1201 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1202 IXGBE_LED_LINK_ACTIVE) { 1203 mac->led_link_act = i; 1204 return IXGBE_SUCCESS; 1205 } 1206 } 1207 1208 /* 1209 * If LEDCTL register does not have the LED link active set, then use 1210 * known MAC defaults. 1211 */ 1212 switch (hw->mac.type) { 1213 case ixgbe_mac_X550EM_a: 1214 case ixgbe_mac_X550EM_x: 1215 mac->led_link_act = 1; 1216 break; 1217 default: 1218 mac->led_link_act = 2; 1219 } 1220 return IXGBE_SUCCESS; 1221 } 1222 1223 /** 1224 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1225 * @hw: pointer to hardware structure 1226 * @index: led number to turn on 1227 **/ 1228 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1229 { 1230 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1231 1232 DEBUGFUNC("ixgbe_led_on_generic"); 1233 1234 if (index > 3) 1235 return IXGBE_ERR_PARAM; 1236 1237 /* To turn on the LED, set mode to ON. */ 1238 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1239 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1240 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1241 IXGBE_WRITE_FLUSH(hw); 1242 1243 return IXGBE_SUCCESS; 1244 } 1245 1246 /** 1247 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1248 * @hw: pointer to hardware structure 1249 * @index: led number to turn off 1250 **/ 1251 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1252 { 1253 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1254 1255 DEBUGFUNC("ixgbe_led_off_generic"); 1256 1257 if (index > 3) 1258 return IXGBE_ERR_PARAM; 1259 1260 /* To turn off the LED, set mode to OFF. */ 1261 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1262 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1263 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1264 IXGBE_WRITE_FLUSH(hw); 1265 1266 return IXGBE_SUCCESS; 1267 } 1268 1269 /** 1270 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1271 * @hw: pointer to hardware structure 1272 * 1273 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1274 * ixgbe_hw struct in order to set up EEPROM access. 1275 **/ 1276 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1277 { 1278 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1279 u32 eec; 1280 u16 eeprom_size; 1281 1282 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1283 1284 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1285 eeprom->type = ixgbe_eeprom_none; 1286 /* Set default semaphore delay to 10ms which is a well 1287 * tested value */ 1288 eeprom->semaphore_delay = 10; 1289 /* Clear EEPROM page size, it will be initialized as needed */ 1290 eeprom->word_page_size = 0; 1291 1292 /* 1293 * Check for EEPROM present first. 1294 * If not present leave as none 1295 */ 1296 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1297 if (eec & IXGBE_EEC_PRES) { 1298 eeprom->type = ixgbe_eeprom_spi; 1299 1300 /* 1301 * SPI EEPROM is assumed here. This code would need to 1302 * change if a future EEPROM is not SPI. 1303 */ 1304 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1305 IXGBE_EEC_SIZE_SHIFT); 1306 eeprom->word_size = 1 << (eeprom_size + 1307 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1308 } 1309 1310 if (eec & IXGBE_EEC_ADDR_SIZE) 1311 eeprom->address_bits = 16; 1312 else 1313 eeprom->address_bits = 8; 1314 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1315 "%d\n", eeprom->type, eeprom->word_size, 1316 eeprom->address_bits); 1317 } 1318 1319 return IXGBE_SUCCESS; 1320 } 1321 1322 /** 1323 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1324 * @hw: pointer to hardware structure 1325 * @offset: offset within the EEPROM to write 1326 * @words: number of word(s) 1327 * @data: 16 bit word(s) to write to EEPROM 1328 * 1329 * Reads 16 bit word(s) from EEPROM through bit-bang method 1330 **/ 1331 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1332 u16 words, u16 *data) 1333 { 1334 s32 status = IXGBE_SUCCESS; 1335 u16 i, count; 1336 1337 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1338 1339 hw->eeprom.ops.init_params(hw); 1340 1341 if (words == 0) { 1342 status = IXGBE_ERR_INVALID_ARGUMENT; 1343 goto out; 1344 } 1345 1346 if (offset + words > hw->eeprom.word_size) { 1347 status = IXGBE_ERR_EEPROM; 1348 goto out; 1349 } 1350 1351 /* 1352 * The EEPROM page size cannot be queried from the chip. We do lazy 1353 * initialization. It is worth to do that when we write large buffer. 1354 */ 1355 if ((hw->eeprom.word_page_size == 0) && 1356 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1357 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1358 1359 /* 1360 * We cannot hold synchronization semaphores for too long 1361 * to avoid other entity starvation. However it is more efficient 1362 * to read in bursts than synchronizing access for each word. 1363 */ 1364 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1365 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1366 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1367 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1368 count, &data[i]); 1369 1370 if (status != IXGBE_SUCCESS) 1371 break; 1372 } 1373 1374 out: 1375 return status; 1376 } 1377 1378 /** 1379 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1380 * @hw: pointer to hardware structure 1381 * @offset: offset within the EEPROM to be written to 1382 * @words: number of word(s) 1383 * @data: 16 bit word(s) to be written to the EEPROM 1384 * 1385 * If ixgbe_eeprom_update_checksum is not called after this function, the 1386 * EEPROM will most likely contain an invalid checksum. 1387 **/ 1388 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1389 u16 words, u16 *data) 1390 { 1391 s32 status; 1392 u16 word; 1393 u16 page_size; 1394 u16 i; 1395 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1396 1397 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1398 1399 /* Prepare the EEPROM for writing */ 1400 status = ixgbe_acquire_eeprom(hw); 1401 1402 if (status == IXGBE_SUCCESS) { 1403 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1404 ixgbe_release_eeprom(hw); 1405 status = IXGBE_ERR_EEPROM; 1406 } 1407 } 1408 1409 if (status == IXGBE_SUCCESS) { 1410 for (i = 0; i < words; i++) { 1411 ixgbe_standby_eeprom(hw); 1412 1413 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1414 ixgbe_shift_out_eeprom_bits(hw, 1415 IXGBE_EEPROM_WREN_OPCODE_SPI, 1416 IXGBE_EEPROM_OPCODE_BITS); 1417 1418 ixgbe_standby_eeprom(hw); 1419 1420 /* 1421 * Some SPI eeproms use the 8th address bit embedded 1422 * in the opcode 1423 */ 1424 if ((hw->eeprom.address_bits == 8) && 1425 ((offset + i) >= 128)) 1426 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1427 1428 /* Send the Write command (8-bit opcode + addr) */ 1429 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1430 IXGBE_EEPROM_OPCODE_BITS); 1431 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1432 hw->eeprom.address_bits); 1433 1434 page_size = hw->eeprom.word_page_size; 1435 1436 /* Send the data in burst via SPI*/ 1437 do { 1438 word = data[i]; 1439 word = (word >> 8) | (word << 8); 1440 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1441 1442 if (page_size == 0) 1443 break; 1444 1445 /* do not wrap around page */ 1446 if (((offset + i) & (page_size - 1)) == 1447 (page_size - 1)) 1448 break; 1449 } while (++i < words); 1450 1451 ixgbe_standby_eeprom(hw); 1452 msec_delay(10); 1453 } 1454 /* Done with writing - release the EEPROM */ 1455 ixgbe_release_eeprom(hw); 1456 } 1457 1458 return status; 1459 } 1460 1461 /** 1462 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1463 * @hw: pointer to hardware structure 1464 * @offset: offset within the EEPROM to be written to 1465 * @data: 16 bit word to be written to the EEPROM 1466 * 1467 * If ixgbe_eeprom_update_checksum is not called after this function, the 1468 * EEPROM will most likely contain an invalid checksum. 1469 **/ 1470 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1471 { 1472 s32 status; 1473 1474 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1475 1476 hw->eeprom.ops.init_params(hw); 1477 1478 if (offset >= hw->eeprom.word_size) { 1479 status = IXGBE_ERR_EEPROM; 1480 goto out; 1481 } 1482 1483 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1484 1485 out: 1486 return status; 1487 } 1488 1489 /** 1490 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1491 * @hw: pointer to hardware structure 1492 * @offset: offset within the EEPROM to be read 1493 * @data: read 16 bit words(s) from EEPROM 1494 * @words: number of word(s) 1495 * 1496 * Reads 16 bit word(s) from EEPROM through bit-bang method 1497 **/ 1498 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1499 u16 words, u16 *data) 1500 { 1501 s32 status = IXGBE_SUCCESS; 1502 u16 i, count; 1503 1504 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1505 1506 hw->eeprom.ops.init_params(hw); 1507 1508 if (words == 0) { 1509 status = IXGBE_ERR_INVALID_ARGUMENT; 1510 goto out; 1511 } 1512 1513 if (offset + words > hw->eeprom.word_size) { 1514 status = IXGBE_ERR_EEPROM; 1515 goto out; 1516 } 1517 1518 /* 1519 * We cannot hold synchronization semaphores for too long 1520 * to avoid other entity starvation. However it is more efficient 1521 * to read in bursts than synchronizing access for each word. 1522 */ 1523 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1524 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1525 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1526 1527 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1528 count, &data[i]); 1529 1530 if (status != IXGBE_SUCCESS) 1531 break; 1532 } 1533 1534 out: 1535 return status; 1536 } 1537 1538 /** 1539 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1540 * @hw: pointer to hardware structure 1541 * @offset: offset within the EEPROM to be read 1542 * @words: number of word(s) 1543 * @data: read 16 bit word(s) from EEPROM 1544 * 1545 * Reads 16 bit word(s) from EEPROM through bit-bang method 1546 **/ 1547 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1548 u16 words, u16 *data) 1549 { 1550 s32 status; 1551 u16 word_in; 1552 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1553 u16 i; 1554 1555 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1556 1557 /* Prepare the EEPROM for reading */ 1558 status = ixgbe_acquire_eeprom(hw); 1559 1560 if (status == IXGBE_SUCCESS) { 1561 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1562 ixgbe_release_eeprom(hw); 1563 status = IXGBE_ERR_EEPROM; 1564 } 1565 } 1566 1567 if (status == IXGBE_SUCCESS) { 1568 for (i = 0; i < words; i++) { 1569 ixgbe_standby_eeprom(hw); 1570 /* 1571 * Some SPI eeproms use the 8th address bit embedded 1572 * in the opcode 1573 */ 1574 if ((hw->eeprom.address_bits == 8) && 1575 ((offset + i) >= 128)) 1576 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1577 1578 /* Send the READ command (opcode + addr) */ 1579 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1580 IXGBE_EEPROM_OPCODE_BITS); 1581 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1582 hw->eeprom.address_bits); 1583 1584 /* Read the data. */ 1585 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1586 data[i] = (word_in >> 8) | (word_in << 8); 1587 } 1588 1589 /* End this read operation */ 1590 ixgbe_release_eeprom(hw); 1591 } 1592 1593 return status; 1594 } 1595 1596 /** 1597 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1598 * @hw: pointer to hardware structure 1599 * @offset: offset within the EEPROM to be read 1600 * @data: read 16 bit value from EEPROM 1601 * 1602 * Reads 16 bit value from EEPROM through bit-bang method 1603 **/ 1604 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1605 u16 *data) 1606 { 1607 s32 status; 1608 1609 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1610 1611 hw->eeprom.ops.init_params(hw); 1612 1613 if (offset >= hw->eeprom.word_size) { 1614 status = IXGBE_ERR_EEPROM; 1615 goto out; 1616 } 1617 1618 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1619 1620 out: 1621 return status; 1622 } 1623 1624 /** 1625 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1626 * @hw: pointer to hardware structure 1627 * @offset: offset of word in the EEPROM to read 1628 * @words: number of word(s) 1629 * @data: 16 bit word(s) from the EEPROM 1630 * 1631 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1632 **/ 1633 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1634 u16 words, u16 *data) 1635 { 1636 u32 eerd; 1637 s32 status = IXGBE_SUCCESS; 1638 u32 i; 1639 1640 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1641 1642 hw->eeprom.ops.init_params(hw); 1643 1644 if (words == 0) { 1645 status = IXGBE_ERR_INVALID_ARGUMENT; 1646 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1647 goto out; 1648 } 1649 1650 if (offset >= hw->eeprom.word_size) { 1651 status = IXGBE_ERR_EEPROM; 1652 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1653 goto out; 1654 } 1655 1656 for (i = 0; i < words; i++) { 1657 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1658 IXGBE_EEPROM_RW_REG_START; 1659 1660 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1661 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1662 1663 if (status == IXGBE_SUCCESS) { 1664 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1665 IXGBE_EEPROM_RW_REG_DATA); 1666 } else { 1667 DEBUGOUT("Eeprom read timed out\n"); 1668 goto out; 1669 } 1670 } 1671 out: 1672 return status; 1673 } 1674 1675 /** 1676 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1677 * @hw: pointer to hardware structure 1678 * @offset: offset within the EEPROM to be used as a scratch pad 1679 * 1680 * Discover EEPROM page size by writing marching data at given offset. 1681 * This function is called only when we are writing a new large buffer 1682 * at given offset so the data would be overwritten anyway. 1683 **/ 1684 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1685 u16 offset) 1686 { 1687 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1688 s32 status = IXGBE_SUCCESS; 1689 u16 i; 1690 1691 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1692 1693 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1694 data[i] = i; 1695 1696 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1697 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1698 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1699 hw->eeprom.word_page_size = 0; 1700 if (status != IXGBE_SUCCESS) 1701 goto out; 1702 1703 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1704 if (status != IXGBE_SUCCESS) 1705 goto out; 1706 1707 /* 1708 * When writing in burst more than the actual page size 1709 * EEPROM address wraps around current page. 1710 */ 1711 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1712 1713 DEBUGOUT1("Detected EEPROM page size = %d words.", 1714 hw->eeprom.word_page_size); 1715 out: 1716 return status; 1717 } 1718 1719 /** 1720 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1721 * @hw: pointer to hardware structure 1722 * @offset: offset of word in the EEPROM to read 1723 * @data: word read from the EEPROM 1724 * 1725 * Reads a 16 bit word from the EEPROM using the EERD register. 1726 **/ 1727 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1728 { 1729 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1730 } 1731 1732 /** 1733 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1734 * @hw: pointer to hardware structure 1735 * @offset: offset of word in the EEPROM to write 1736 * @words: number of word(s) 1737 * @data: word(s) write to the EEPROM 1738 * 1739 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1740 **/ 1741 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1742 u16 words, u16 *data) 1743 { 1744 u32 eewr; 1745 s32 status = IXGBE_SUCCESS; 1746 u16 i; 1747 1748 DEBUGFUNC("ixgbe_write_eewr_generic"); 1749 1750 hw->eeprom.ops.init_params(hw); 1751 1752 if (words == 0) { 1753 status = IXGBE_ERR_INVALID_ARGUMENT; 1754 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1755 goto out; 1756 } 1757 1758 if (offset >= hw->eeprom.word_size) { 1759 status = IXGBE_ERR_EEPROM; 1760 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1761 goto out; 1762 } 1763 1764 for (i = 0; i < words; i++) { 1765 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1766 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1767 IXGBE_EEPROM_RW_REG_START; 1768 1769 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1770 if (status != IXGBE_SUCCESS) { 1771 DEBUGOUT("Eeprom write EEWR timed out\n"); 1772 goto out; 1773 } 1774 1775 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1776 1777 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1778 if (status != IXGBE_SUCCESS) { 1779 DEBUGOUT("Eeprom write EEWR timed out\n"); 1780 goto out; 1781 } 1782 } 1783 1784 out: 1785 return status; 1786 } 1787 1788 /** 1789 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1790 * @hw: pointer to hardware structure 1791 * @offset: offset of word in the EEPROM to write 1792 * @data: word write to the EEPROM 1793 * 1794 * Write a 16 bit word to the EEPROM using the EEWR register. 1795 **/ 1796 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1797 { 1798 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1799 } 1800 1801 /** 1802 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1803 * @hw: pointer to hardware structure 1804 * @ee_reg: EEPROM flag for polling 1805 * 1806 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1807 * read or write is done respectively. 1808 **/ 1809 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1810 { 1811 u32 i; 1812 u32 reg; 1813 s32 status = IXGBE_ERR_EEPROM; 1814 1815 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1816 1817 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1818 if (ee_reg == IXGBE_NVM_POLL_READ) 1819 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1820 else 1821 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1822 1823 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1824 status = IXGBE_SUCCESS; 1825 break; 1826 } 1827 usec_delay(5); 1828 } 1829 1830 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1831 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1832 "EEPROM read/write done polling timed out"); 1833 1834 return status; 1835 } 1836 1837 /** 1838 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1839 * @hw: pointer to hardware structure 1840 * 1841 * Prepares EEPROM for access using bit-bang method. This function should 1842 * be called before issuing a command to the EEPROM. 1843 **/ 1844 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1845 { 1846 s32 status = IXGBE_SUCCESS; 1847 u32 eec; 1848 u32 i; 1849 1850 DEBUGFUNC("ixgbe_acquire_eeprom"); 1851 1852 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1853 != IXGBE_SUCCESS) 1854 status = IXGBE_ERR_SWFW_SYNC; 1855 1856 if (status == IXGBE_SUCCESS) { 1857 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1858 1859 /* Request EEPROM Access */ 1860 eec |= IXGBE_EEC_REQ; 1861 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1862 1863 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1864 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1865 if (eec & IXGBE_EEC_GNT) 1866 break; 1867 usec_delay(5); 1868 } 1869 1870 /* Release if grant not acquired */ 1871 if (!(eec & IXGBE_EEC_GNT)) { 1872 eec &= ~IXGBE_EEC_REQ; 1873 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1874 DEBUGOUT("Could not acquire EEPROM grant\n"); 1875 1876 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1877 status = IXGBE_ERR_EEPROM; 1878 } 1879 1880 /* Setup EEPROM for Read/Write */ 1881 if (status == IXGBE_SUCCESS) { 1882 /* Clear CS and SK */ 1883 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1884 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1885 IXGBE_WRITE_FLUSH(hw); 1886 usec_delay(1); 1887 } 1888 } 1889 return status; 1890 } 1891 1892 /** 1893 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1894 * @hw: pointer to hardware structure 1895 * 1896 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1897 **/ 1898 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1899 { 1900 s32 status = IXGBE_ERR_EEPROM; 1901 u32 timeout = 2000; 1902 u32 i; 1903 u32 swsm; 1904 1905 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1906 1907 1908 /* Get SMBI software semaphore between device drivers first */ 1909 for (i = 0; i < timeout; i++) { 1910 /* 1911 * If the SMBI bit is 0 when we read it, then the bit will be 1912 * set and we have the semaphore 1913 */ 1914 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1915 if (!(swsm & IXGBE_SWSM_SMBI)) { 1916 status = IXGBE_SUCCESS; 1917 break; 1918 } 1919 usec_delay(50); 1920 } 1921 1922 if (i == timeout) { 1923 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1924 "not granted.\n"); 1925 /* 1926 * this release is particularly important because our attempts 1927 * above to get the semaphore may have succeeded, and if there 1928 * was a timeout, we should unconditionally clear the semaphore 1929 * bits to free the driver to make progress 1930 */ 1931 ixgbe_release_eeprom_semaphore(hw); 1932 1933 usec_delay(50); 1934 /* 1935 * one last try 1936 * If the SMBI bit is 0 when we read it, then the bit will be 1937 * set and we have the semaphore 1938 */ 1939 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1940 if (!(swsm & IXGBE_SWSM_SMBI)) 1941 status = IXGBE_SUCCESS; 1942 } 1943 1944 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1945 if (status == IXGBE_SUCCESS) { 1946 for (i = 0; i < timeout; i++) { 1947 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1948 1949 /* Set the SW EEPROM semaphore bit to request access */ 1950 swsm |= IXGBE_SWSM_SWESMBI; 1951 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1952 1953 /* 1954 * If we set the bit successfully then we got the 1955 * semaphore. 1956 */ 1957 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1958 if (swsm & IXGBE_SWSM_SWESMBI) 1959 break; 1960 1961 usec_delay(50); 1962 } 1963 1964 /* 1965 * Release semaphores and return error if SW EEPROM semaphore 1966 * was not granted because we don't have access to the EEPROM 1967 */ 1968 if (i >= timeout) { 1969 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1970 "SWESMBI Software EEPROM semaphore not granted.\n"); 1971 ixgbe_release_eeprom_semaphore(hw); 1972 status = IXGBE_ERR_EEPROM; 1973 } 1974 } else { 1975 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1976 "Software semaphore SMBI between device drivers " 1977 "not granted.\n"); 1978 } 1979 1980 return status; 1981 } 1982 1983 /** 1984 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1985 * @hw: pointer to hardware structure 1986 * 1987 * This function clears hardware semaphore bits. 1988 **/ 1989 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1990 { 1991 u32 swsm; 1992 1993 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1994 1995 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1996 1997 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1998 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1999 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 2000 IXGBE_WRITE_FLUSH(hw); 2001 } 2002 2003 /** 2004 * ixgbe_ready_eeprom - Polls for EEPROM ready 2005 * @hw: pointer to hardware structure 2006 **/ 2007 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 2008 { 2009 s32 status = IXGBE_SUCCESS; 2010 u16 i; 2011 u8 spi_stat_reg; 2012 2013 DEBUGFUNC("ixgbe_ready_eeprom"); 2014 2015 /* 2016 * Read "Status Register" repeatedly until the LSB is cleared. The 2017 * EEPROM will signal that the command has been completed by clearing 2018 * bit 0 of the internal status register. If it's not cleared within 2019 * 5 milliseconds, then error out. 2020 */ 2021 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 2022 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 2023 IXGBE_EEPROM_OPCODE_BITS); 2024 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 2025 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 2026 break; 2027 2028 usec_delay(5); 2029 ixgbe_standby_eeprom(hw); 2030 } 2031 2032 /* 2033 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 2034 * devices (and only 0-5mSec on 5V devices) 2035 */ 2036 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 2037 DEBUGOUT("SPI EEPROM Status error\n"); 2038 status = IXGBE_ERR_EEPROM; 2039 } 2040 2041 return status; 2042 } 2043 2044 /** 2045 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 2046 * @hw: pointer to hardware structure 2047 **/ 2048 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 2049 { 2050 u32 eec; 2051 2052 DEBUGFUNC("ixgbe_standby_eeprom"); 2053 2054 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2055 2056 /* Toggle CS to flush commands */ 2057 eec |= IXGBE_EEC_CS; 2058 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2059 IXGBE_WRITE_FLUSH(hw); 2060 usec_delay(1); 2061 eec &= ~IXGBE_EEC_CS; 2062 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2063 IXGBE_WRITE_FLUSH(hw); 2064 usec_delay(1); 2065 } 2066 2067 /** 2068 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 2069 * @hw: pointer to hardware structure 2070 * @data: data to send to the EEPROM 2071 * @count: number of bits to shift out 2072 **/ 2073 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 2074 u16 count) 2075 { 2076 u32 eec; 2077 u32 mask; 2078 u32 i; 2079 2080 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 2081 2082 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2083 2084 /* 2085 * Mask is used to shift "count" bits of "data" out to the EEPROM 2086 * one bit at a time. Determine the starting bit based on count 2087 */ 2088 mask = 0x01 << (count - 1); 2089 2090 for (i = 0; i < count; i++) { 2091 /* 2092 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 2093 * "1", and then raising and then lowering the clock (the SK 2094 * bit controls the clock input to the EEPROM). A "0" is 2095 * shifted out to the EEPROM by setting "DI" to "0" and then 2096 * raising and then lowering the clock. 2097 */ 2098 if (data & mask) 2099 eec |= IXGBE_EEC_DI; 2100 else 2101 eec &= ~IXGBE_EEC_DI; 2102 2103 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2104 IXGBE_WRITE_FLUSH(hw); 2105 2106 usec_delay(1); 2107 2108 ixgbe_raise_eeprom_clk(hw, &eec); 2109 ixgbe_lower_eeprom_clk(hw, &eec); 2110 2111 /* 2112 * Shift mask to signify next bit of data to shift in to the 2113 * EEPROM 2114 */ 2115 mask = mask >> 1; 2116 } 2117 2118 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2119 eec &= ~IXGBE_EEC_DI; 2120 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2121 IXGBE_WRITE_FLUSH(hw); 2122 } 2123 2124 /** 2125 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2126 * @hw: pointer to hardware structure 2127 * @count: number of bits to shift 2128 **/ 2129 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2130 { 2131 u32 eec; 2132 u32 i; 2133 u16 data = 0; 2134 2135 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2136 2137 /* 2138 * In order to read a register from the EEPROM, we need to shift 2139 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2140 * the clock input to the EEPROM (setting the SK bit), and then reading 2141 * the value of the "DO" bit. During this "shifting in" process the 2142 * "DI" bit should always be clear. 2143 */ 2144 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2145 2146 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2147 2148 for (i = 0; i < count; i++) { 2149 data = data << 1; 2150 ixgbe_raise_eeprom_clk(hw, &eec); 2151 2152 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2153 2154 eec &= ~(IXGBE_EEC_DI); 2155 if (eec & IXGBE_EEC_DO) 2156 data |= 1; 2157 2158 ixgbe_lower_eeprom_clk(hw, &eec); 2159 } 2160 2161 return data; 2162 } 2163 2164 /** 2165 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2166 * @hw: pointer to hardware structure 2167 * @eec: EEC register's current value 2168 **/ 2169 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2170 { 2171 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2172 2173 /* 2174 * Raise the clock input to the EEPROM 2175 * (setting the SK bit), then delay 2176 */ 2177 *eec = *eec | IXGBE_EEC_SK; 2178 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2179 IXGBE_WRITE_FLUSH(hw); 2180 usec_delay(1); 2181 } 2182 2183 /** 2184 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2185 * @hw: pointer to hardware structure 2186 * @eec: EEC's current value 2187 **/ 2188 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2189 { 2190 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2191 2192 /* 2193 * Lower the clock input to the EEPROM (clearing the SK bit), then 2194 * delay 2195 */ 2196 *eec = *eec & ~IXGBE_EEC_SK; 2197 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2198 IXGBE_WRITE_FLUSH(hw); 2199 usec_delay(1); 2200 } 2201 2202 /** 2203 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2204 * @hw: pointer to hardware structure 2205 **/ 2206 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2207 { 2208 u32 eec; 2209 2210 DEBUGFUNC("ixgbe_release_eeprom"); 2211 2212 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2213 2214 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2215 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2216 2217 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2218 IXGBE_WRITE_FLUSH(hw); 2219 2220 usec_delay(1); 2221 2222 /* Stop requesting EEPROM access */ 2223 eec &= ~IXGBE_EEC_REQ; 2224 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2225 2226 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2227 2228 /* Delay before attempt to obtain semaphore again to allow FW access */ 2229 msec_delay(hw->eeprom.semaphore_delay); 2230 } 2231 2232 /** 2233 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2234 * @hw: pointer to hardware structure 2235 * 2236 * Returns a negative error code on error, or the 16-bit checksum 2237 **/ 2238 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2239 { 2240 u16 i; 2241 u16 j; 2242 u16 checksum = 0; 2243 u16 length = 0; 2244 u16 pointer = 0; 2245 u16 word = 0; 2246 2247 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2248 2249 /* Include 0x0-0x3F in the checksum */ 2250 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2251 if (hw->eeprom.ops.read(hw, i, &word)) { 2252 DEBUGOUT("EEPROM read failed\n"); 2253 return IXGBE_ERR_EEPROM; 2254 } 2255 checksum += word; 2256 } 2257 2258 /* Include all data from pointers except for the fw pointer */ 2259 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2260 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2261 DEBUGOUT("EEPROM read failed\n"); 2262 return IXGBE_ERR_EEPROM; 2263 } 2264 2265 /* If the pointer seems invalid */ 2266 if (pointer == 0xFFFF || pointer == 0) 2267 continue; 2268 2269 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2270 DEBUGOUT("EEPROM read failed\n"); 2271 return IXGBE_ERR_EEPROM; 2272 } 2273 2274 if (length == 0xFFFF || length == 0) 2275 continue; 2276 2277 for (j = pointer + 1; j <= pointer + length; j++) { 2278 if (hw->eeprom.ops.read(hw, j, &word)) { 2279 DEBUGOUT("EEPROM read failed\n"); 2280 return IXGBE_ERR_EEPROM; 2281 } 2282 checksum += word; 2283 } 2284 } 2285 2286 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2287 2288 return (s32)checksum; 2289 } 2290 2291 /** 2292 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2293 * @hw: pointer to hardware structure 2294 * @checksum_val: calculated checksum 2295 * 2296 * Performs checksum calculation and validates the EEPROM checksum. If the 2297 * caller does not need checksum_val, the value can be NULL. 2298 **/ 2299 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2300 u16 *checksum_val) 2301 { 2302 s32 status; 2303 u16 checksum; 2304 u16 read_checksum = 0; 2305 2306 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2307 2308 /* Read the first word from the EEPROM. If this times out or fails, do 2309 * not continue or we could be in for a very long wait while every 2310 * EEPROM read fails 2311 */ 2312 status = hw->eeprom.ops.read(hw, 0, &checksum); 2313 if (status) { 2314 DEBUGOUT("EEPROM read failed\n"); 2315 return status; 2316 } 2317 2318 status = hw->eeprom.ops.calc_checksum(hw); 2319 if (status < 0) 2320 return status; 2321 2322 checksum = (u16)(status & 0xffff); 2323 2324 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2325 if (status) { 2326 DEBUGOUT("EEPROM read failed\n"); 2327 return status; 2328 } 2329 2330 /* Verify read checksum from EEPROM is the same as 2331 * calculated checksum 2332 */ 2333 if (read_checksum != checksum) 2334 status = IXGBE_ERR_EEPROM_CHECKSUM; 2335 2336 /* If the user cares, return the calculated checksum */ 2337 if (checksum_val) 2338 *checksum_val = checksum; 2339 2340 return status; 2341 } 2342 2343 /** 2344 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2345 * @hw: pointer to hardware structure 2346 **/ 2347 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2348 { 2349 s32 status; 2350 u16 checksum; 2351 2352 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2353 2354 /* Read the first word from the EEPROM. If this times out or fails, do 2355 * not continue or we could be in for a very long wait while every 2356 * EEPROM read fails 2357 */ 2358 status = hw->eeprom.ops.read(hw, 0, &checksum); 2359 if (status) { 2360 DEBUGOUT("EEPROM read failed\n"); 2361 return status; 2362 } 2363 2364 status = hw->eeprom.ops.calc_checksum(hw); 2365 if (status < 0) 2366 return status; 2367 2368 checksum = (u16)(status & 0xffff); 2369 2370 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2371 2372 return status; 2373 } 2374 2375 /** 2376 * ixgbe_validate_mac_addr - Validate MAC address 2377 * @mac_addr: pointer to MAC address. 2378 * 2379 * Tests a MAC address to ensure it is a valid Individual Address. 2380 **/ 2381 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2382 { 2383 s32 status = IXGBE_SUCCESS; 2384 2385 DEBUGFUNC("ixgbe_validate_mac_addr"); 2386 2387 /* Make sure it is not a multicast address */ 2388 if (IXGBE_IS_MULTICAST(mac_addr)) { 2389 status = IXGBE_ERR_INVALID_MAC_ADDR; 2390 /* Not a broadcast address */ 2391 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2392 status = IXGBE_ERR_INVALID_MAC_ADDR; 2393 /* Reject the zero address */ 2394 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2395 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2396 status = IXGBE_ERR_INVALID_MAC_ADDR; 2397 } 2398 return status; 2399 } 2400 2401 /** 2402 * ixgbe_set_rar_generic - Set Rx address register 2403 * @hw: pointer to hardware structure 2404 * @index: Receive address register to write 2405 * @addr: Address to put into receive address register 2406 * @vmdq: VMDq "set" or "pool" index 2407 * @enable_addr: set flag that address is active 2408 * 2409 * Puts an ethernet address into a receive address register. 2410 **/ 2411 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2412 u32 enable_addr) 2413 { 2414 u32 rar_low, rar_high; 2415 u32 rar_entries = hw->mac.num_rar_entries; 2416 2417 DEBUGFUNC("ixgbe_set_rar_generic"); 2418 2419 /* Make sure we are using a valid rar index range */ 2420 if (index >= rar_entries) { 2421 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2422 "RAR index %d is out of range.\n", index); 2423 return IXGBE_ERR_INVALID_ARGUMENT; 2424 } 2425 2426 /* setup VMDq pool selection before this RAR gets enabled */ 2427 hw->mac.ops.set_vmdq(hw, index, vmdq); 2428 2429 /* 2430 * HW expects these in little endian so we reverse the byte 2431 * order from network order (big endian) to little endian 2432 */ 2433 rar_low = ((u32)addr[0] | 2434 ((u32)addr[1] << 8) | 2435 ((u32)addr[2] << 16) | 2436 ((u32)addr[3] << 24)); 2437 /* 2438 * Some parts put the VMDq setting in the extra RAH bits, 2439 * so save everything except the lower 16 bits that hold part 2440 * of the address and the address valid bit. 2441 */ 2442 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2443 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2444 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2445 2446 if (enable_addr != 0) 2447 rar_high |= IXGBE_RAH_AV; 2448 2449 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2450 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2451 2452 return IXGBE_SUCCESS; 2453 } 2454 2455 /** 2456 * ixgbe_clear_rar_generic - Remove Rx address register 2457 * @hw: pointer to hardware structure 2458 * @index: Receive address register to write 2459 * 2460 * Clears an ethernet address from a receive address register. 2461 **/ 2462 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2463 { 2464 u32 rar_high; 2465 u32 rar_entries = hw->mac.num_rar_entries; 2466 2467 DEBUGFUNC("ixgbe_clear_rar_generic"); 2468 2469 /* Make sure we are using a valid rar index range */ 2470 if (index >= rar_entries) { 2471 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2472 "RAR index %d is out of range.\n", index); 2473 return IXGBE_ERR_INVALID_ARGUMENT; 2474 } 2475 2476 /* 2477 * Some parts put the VMDq setting in the extra RAH bits, 2478 * so save everything except the lower 16 bits that hold part 2479 * of the address and the address valid bit. 2480 */ 2481 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2482 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2483 2484 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2485 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2486 2487 /* clear VMDq pool/queue selection for this RAR */ 2488 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2489 2490 return IXGBE_SUCCESS; 2491 } 2492 2493 /** 2494 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2495 * @hw: pointer to hardware structure 2496 * 2497 * Places the MAC address in receive address register 0 and clears the rest 2498 * of the receive address registers. Clears the multicast table. Assumes 2499 * the receiver is in reset when the routine is called. 2500 **/ 2501 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2502 { 2503 u32 i; 2504 u32 rar_entries = hw->mac.num_rar_entries; 2505 2506 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2507 2508 /* 2509 * If the current mac address is valid, assume it is a software override 2510 * to the permanent address. 2511 * Otherwise, use the permanent address from the eeprom. 2512 */ 2513 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2514 IXGBE_ERR_INVALID_MAC_ADDR) { 2515 /* Get the MAC address from the RAR0 for later reference */ 2516 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2517 2518 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2519 hw->mac.addr[0], hw->mac.addr[1], 2520 hw->mac.addr[2]); 2521 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2522 hw->mac.addr[4], hw->mac.addr[5]); 2523 } else { 2524 /* Setup the receive address. */ 2525 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2526 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2527 hw->mac.addr[0], hw->mac.addr[1], 2528 hw->mac.addr[2]); 2529 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2530 hw->mac.addr[4], hw->mac.addr[5]); 2531 2532 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2533 } 2534 2535 /* clear VMDq pool/queue selection for RAR 0 */ 2536 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2537 2538 hw->addr_ctrl.overflow_promisc = 0; 2539 2540 hw->addr_ctrl.rar_used_count = 1; 2541 2542 /* Zero out the other receive addresses. */ 2543 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2544 for (i = 1; i < rar_entries; i++) { 2545 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2546 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2547 } 2548 2549 /* Clear the MTA */ 2550 hw->addr_ctrl.mta_in_use = 0; 2551 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2552 2553 DEBUGOUT(" Clearing MTA\n"); 2554 for (i = 0; i < hw->mac.mcft_size; i++) 2555 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2556 2557 ixgbe_init_uta_tables(hw); 2558 2559 return IXGBE_SUCCESS; 2560 } 2561 2562 /** 2563 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2564 * @hw: pointer to hardware structure 2565 * @addr: new address 2566 * @vmdq: VMDq "set" or "pool" index 2567 * 2568 * Adds it to unused receive address register or goes into promiscuous mode. 2569 **/ 2570 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2571 { 2572 u32 rar_entries = hw->mac.num_rar_entries; 2573 u32 rar; 2574 2575 DEBUGFUNC("ixgbe_add_uc_addr"); 2576 2577 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2578 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2579 2580 /* 2581 * Place this address in the RAR if there is room, 2582 * else put the controller into promiscuous mode 2583 */ 2584 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2585 rar = hw->addr_ctrl.rar_used_count; 2586 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2587 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2588 hw->addr_ctrl.rar_used_count++; 2589 } else { 2590 hw->addr_ctrl.overflow_promisc++; 2591 } 2592 2593 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2594 } 2595 2596 /** 2597 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2598 * @hw: pointer to hardware structure 2599 * @addr_list: the list of new addresses 2600 * @addr_count: number of addresses 2601 * @next: iterator function to walk the address list 2602 * 2603 * The given list replaces any existing list. Clears the secondary addrs from 2604 * receive address registers. Uses unused receive address registers for the 2605 * first secondary addresses, and falls back to promiscuous mode as needed. 2606 * 2607 * Drivers using secondary unicast addresses must set user_set_promisc when 2608 * manually putting the device into promiscuous mode. 2609 **/ 2610 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2611 u32 addr_count, ixgbe_mc_addr_itr next) 2612 { 2613 u8 *addr; 2614 u32 i; 2615 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2616 u32 uc_addr_in_use; 2617 u32 fctrl; 2618 u32 vmdq; 2619 2620 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2621 2622 /* 2623 * Clear accounting of old secondary address list, 2624 * don't count RAR[0] 2625 */ 2626 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2627 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2628 hw->addr_ctrl.overflow_promisc = 0; 2629 2630 /* Zero out the other receive addresses */ 2631 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2632 for (i = 0; i < uc_addr_in_use; i++) { 2633 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2634 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2635 } 2636 2637 /* Add the new addresses */ 2638 for (i = 0; i < addr_count; i++) { 2639 DEBUGOUT(" Adding the secondary addresses:\n"); 2640 addr = next(hw, &addr_list, &vmdq); 2641 ixgbe_add_uc_addr(hw, addr, vmdq); 2642 } 2643 2644 if (hw->addr_ctrl.overflow_promisc) { 2645 /* enable promisc if not already in overflow or set by user */ 2646 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2647 DEBUGOUT(" Entering address overflow promisc mode\n"); 2648 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2649 fctrl |= IXGBE_FCTRL_UPE; 2650 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2651 } 2652 } else { 2653 /* only disable if set by overflow, not by user */ 2654 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2655 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2656 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2657 fctrl &= ~IXGBE_FCTRL_UPE; 2658 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2659 } 2660 } 2661 2662 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2663 return IXGBE_SUCCESS; 2664 } 2665 2666 /** 2667 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2668 * @hw: pointer to hardware structure 2669 * @mc_addr: the multicast address 2670 * 2671 * Extracts the 12 bits, from a multicast address, to determine which 2672 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2673 * incoming rx multicast addresses, to determine the bit-vector to check in 2674 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2675 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2676 * to mc_filter_type. 2677 **/ 2678 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2679 { 2680 u32 vector = 0; 2681 2682 DEBUGFUNC("ixgbe_mta_vector"); 2683 2684 switch (hw->mac.mc_filter_type) { 2685 case 0: /* use bits [47:36] of the address */ 2686 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2687 break; 2688 case 1: /* use bits [46:35] of the address */ 2689 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2690 break; 2691 case 2: /* use bits [45:34] of the address */ 2692 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2693 break; 2694 case 3: /* use bits [43:32] of the address */ 2695 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2696 break; 2697 default: /* Invalid mc_filter_type */ 2698 DEBUGOUT("MC filter type param set incorrectly\n"); 2699 ASSERT(0); 2700 break; 2701 } 2702 2703 /* vector can only be 12-bits or boundary will be exceeded */ 2704 vector &= 0xFFF; 2705 return vector; 2706 } 2707 2708 /** 2709 * ixgbe_set_mta - Set bit-vector in multicast table 2710 * @hw: pointer to hardware structure 2711 * @mc_addr: Multicast address 2712 * 2713 * Sets the bit-vector in the multicast table. 2714 **/ 2715 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2716 { 2717 u32 vector; 2718 u32 vector_bit; 2719 u32 vector_reg; 2720 2721 DEBUGFUNC("ixgbe_set_mta"); 2722 2723 hw->addr_ctrl.mta_in_use++; 2724 2725 vector = ixgbe_mta_vector(hw, mc_addr); 2726 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2727 2728 /* 2729 * The MTA is a register array of 128 32-bit registers. It is treated 2730 * like an array of 4096 bits. We want to set bit 2731 * BitArray[vector_value]. So we figure out what register the bit is 2732 * in, read it, OR in the new bit, then write back the new value. The 2733 * register is determined by the upper 7 bits of the vector value and 2734 * the bit within that register are determined by the lower 5 bits of 2735 * the value. 2736 */ 2737 vector_reg = (vector >> 5) & 0x7F; 2738 vector_bit = vector & 0x1F; 2739 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2740 } 2741 2742 /** 2743 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2744 * @hw: pointer to hardware structure 2745 * @mc_addr_list: the list of new multicast addresses 2746 * @mc_addr_count: number of addresses 2747 * @next: iterator function to walk the multicast address list 2748 * @clear: flag, when set clears the table beforehand 2749 * 2750 * When the clear flag is set, the given list replaces any existing list. 2751 * Hashes the given addresses into the multicast table. 2752 **/ 2753 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2754 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2755 bool clear) 2756 { 2757 u32 i; 2758 u32 vmdq; 2759 2760 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2761 2762 /* 2763 * Set the new number of MC addresses that we are being requested to 2764 * use. 2765 */ 2766 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2767 hw->addr_ctrl.mta_in_use = 0; 2768 2769 /* Clear mta_shadow */ 2770 if (clear) { 2771 DEBUGOUT(" Clearing MTA\n"); 2772 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2773 } 2774 2775 /* Update mta_shadow */ 2776 for (i = 0; i < mc_addr_count; i++) { 2777 DEBUGOUT(" Adding the multicast addresses:\n"); 2778 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2779 } 2780 2781 /* Enable mta */ 2782 for (i = 0; i < hw->mac.mcft_size; i++) 2783 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2784 hw->mac.mta_shadow[i]); 2785 2786 if (hw->addr_ctrl.mta_in_use > 0) 2787 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2788 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2789 2790 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2791 return IXGBE_SUCCESS; 2792 } 2793 2794 /** 2795 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2796 * @hw: pointer to hardware structure 2797 * 2798 * Enables multicast address in RAR and the use of the multicast hash table. 2799 **/ 2800 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2801 { 2802 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2803 2804 DEBUGFUNC("ixgbe_enable_mc_generic"); 2805 2806 if (a->mta_in_use > 0) 2807 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2808 hw->mac.mc_filter_type); 2809 2810 return IXGBE_SUCCESS; 2811 } 2812 2813 /** 2814 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2815 * @hw: pointer to hardware structure 2816 * 2817 * Disables multicast address in RAR and the use of the multicast hash table. 2818 **/ 2819 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2820 { 2821 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2822 2823 DEBUGFUNC("ixgbe_disable_mc_generic"); 2824 2825 if (a->mta_in_use > 0) 2826 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2827 2828 return IXGBE_SUCCESS; 2829 } 2830 2831 /** 2832 * ixgbe_fc_enable_generic - Enable flow control 2833 * @hw: pointer to hardware structure 2834 * 2835 * Enable flow control according to the current settings. 2836 **/ 2837 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2838 { 2839 s32 ret_val = IXGBE_SUCCESS; 2840 u32 mflcn_reg, fccfg_reg; 2841 u32 reg; 2842 u32 fcrtl, fcrth; 2843 int i; 2844 2845 DEBUGFUNC("ixgbe_fc_enable_generic"); 2846 2847 /* Validate the water mark configuration */ 2848 if (!hw->fc.pause_time) { 2849 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2850 goto out; 2851 } 2852 2853 /* Low water mark of zero causes XOFF floods */ 2854 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2855 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2856 hw->fc.high_water[i]) { 2857 if (!hw->fc.low_water[i] || 2858 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2859 DEBUGOUT("Invalid water mark configuration\n"); 2860 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2861 goto out; 2862 } 2863 } 2864 } 2865 2866 /* Negotiate the fc mode to use */ 2867 hw->mac.ops.fc_autoneg(hw); 2868 2869 /* Disable any previous flow control settings */ 2870 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2871 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2872 2873 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2874 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2875 2876 /* 2877 * The possible values of fc.current_mode are: 2878 * 0: Flow control is completely disabled 2879 * 1: Rx flow control is enabled (we can receive pause frames, 2880 * but not send pause frames). 2881 * 2: Tx flow control is enabled (we can send pause frames but 2882 * we do not support receiving pause frames). 2883 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2884 * other: Invalid. 2885 */ 2886 switch (hw->fc.current_mode) { 2887 case ixgbe_fc_none: 2888 /* 2889 * Flow control is disabled by software override or autoneg. 2890 * The code below will actually disable it in the HW. 2891 */ 2892 break; 2893 case ixgbe_fc_rx_pause: 2894 /* 2895 * Rx Flow control is enabled and Tx Flow control is 2896 * disabled by software override. Since there really 2897 * isn't a way to advertise that we are capable of RX 2898 * Pause ONLY, we will advertise that we support both 2899 * symmetric and asymmetric Rx PAUSE. Later, we will 2900 * disable the adapter's ability to send PAUSE frames. 2901 */ 2902 mflcn_reg |= IXGBE_MFLCN_RFCE; 2903 break; 2904 case ixgbe_fc_tx_pause: 2905 /* 2906 * Tx Flow control is enabled, and Rx Flow control is 2907 * disabled by software override. 2908 */ 2909 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2910 break; 2911 case ixgbe_fc_full: 2912 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2913 mflcn_reg |= IXGBE_MFLCN_RFCE; 2914 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2915 break; 2916 default: 2917 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2918 "Flow control param set incorrectly\n"); 2919 ret_val = IXGBE_ERR_CONFIG; 2920 goto out; 2921 break; 2922 } 2923 2924 /* Set 802.3x based flow control settings. */ 2925 mflcn_reg |= IXGBE_MFLCN_DPF; 2926 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2927 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2928 2929 2930 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2931 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2932 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2933 hw->fc.high_water[i]) { 2934 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2935 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2936 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2937 } else { 2938 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2939 /* 2940 * In order to prevent Tx hangs when the internal Tx 2941 * switch is enabled we must set the high water mark 2942 * to the Rx packet buffer size - 24KB. This allows 2943 * the Tx switch to function even under heavy Rx 2944 * workloads. 2945 */ 2946 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2947 } 2948 2949 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2950 } 2951 2952 /* Configure pause time (2 TCs per register) */ 2953 reg = (u32)hw->fc.pause_time * 0x00010001; 2954 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2955 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2956 2957 /* Configure flow control refresh threshold value */ 2958 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2959 2960 out: 2961 return ret_val; 2962 } 2963 2964 /** 2965 * ixgbe_negotiate_fc - Negotiate flow control 2966 * @hw: pointer to hardware structure 2967 * @adv_reg: flow control advertised settings 2968 * @lp_reg: link partner's flow control settings 2969 * @adv_sym: symmetric pause bit in advertisement 2970 * @adv_asm: asymmetric pause bit in advertisement 2971 * @lp_sym: symmetric pause bit in link partner advertisement 2972 * @lp_asm: asymmetric pause bit in link partner advertisement 2973 * 2974 * Find the intersection between advertised settings and link partner's 2975 * advertised settings 2976 **/ 2977 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2978 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2979 { 2980 if ((!(adv_reg)) || (!(lp_reg))) { 2981 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2982 "Local or link partner's advertised flow control " 2983 "settings are NULL. Local: %x, link partner: %x\n", 2984 adv_reg, lp_reg); 2985 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2986 } 2987 2988 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2989 /* 2990 * Now we need to check if the user selected Rx ONLY 2991 * of pause frames. In this case, we had to advertise 2992 * FULL flow control because we could not advertise RX 2993 * ONLY. Hence, we must now check to see if we need to 2994 * turn OFF the TRANSMISSION of PAUSE frames. 2995 */ 2996 if (hw->fc.requested_mode == ixgbe_fc_full) { 2997 hw->fc.current_mode = ixgbe_fc_full; 2998 DEBUGOUT("Flow Control = FULL.\n"); 2999 } else { 3000 hw->fc.current_mode = ixgbe_fc_rx_pause; 3001 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 3002 } 3003 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 3004 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 3005 hw->fc.current_mode = ixgbe_fc_tx_pause; 3006 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 3007 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 3008 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 3009 hw->fc.current_mode = ixgbe_fc_rx_pause; 3010 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 3011 } else { 3012 hw->fc.current_mode = ixgbe_fc_none; 3013 DEBUGOUT("Flow Control = NONE.\n"); 3014 } 3015 return IXGBE_SUCCESS; 3016 } 3017 3018 /** 3019 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 3020 * @hw: pointer to hardware structure 3021 * 3022 * Enable flow control according on 1 gig fiber. 3023 **/ 3024 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 3025 { 3026 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 3027 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3028 3029 /* 3030 * On multispeed fiber at 1g, bail out if 3031 * - link is up but AN did not complete, or if 3032 * - link is up and AN completed but timed out 3033 */ 3034 3035 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 3036 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 3037 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 3038 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 3039 goto out; 3040 } 3041 3042 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 3043 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 3044 3045 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 3046 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 3047 IXGBE_PCS1GANA_ASM_PAUSE, 3048 IXGBE_PCS1GANA_SYM_PAUSE, 3049 IXGBE_PCS1GANA_ASM_PAUSE); 3050 3051 out: 3052 return ret_val; 3053 } 3054 3055 /** 3056 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 3057 * @hw: pointer to hardware structure 3058 * 3059 * Enable flow control according to IEEE clause 37. 3060 **/ 3061 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 3062 { 3063 u32 links2, anlp1_reg, autoc_reg, links; 3064 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3065 3066 /* 3067 * On backplane, bail out if 3068 * - backplane autoneg was not completed, or if 3069 * - we are 82599 and link partner is not AN enabled 3070 */ 3071 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 3072 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 3073 DEBUGOUT("Auto-Negotiation did not complete\n"); 3074 goto out; 3075 } 3076 3077 if (hw->mac.type == ixgbe_mac_82599EB) { 3078 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 3079 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 3080 DEBUGOUT("Link partner is not AN enabled\n"); 3081 goto out; 3082 } 3083 } 3084 /* 3085 * Read the 10g AN autoc and LP ability registers and resolve 3086 * local flow control settings accordingly 3087 */ 3088 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3089 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 3090 3091 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 3092 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 3093 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 3094 3095 out: 3096 return ret_val; 3097 } 3098 3099 /** 3100 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 3101 * @hw: pointer to hardware structure 3102 * 3103 * Enable flow control according to IEEE clause 37. 3104 **/ 3105 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 3106 { 3107 u16 technology_ability_reg = 0; 3108 u16 lp_technology_ability_reg = 0; 3109 3110 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 3111 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3112 &technology_ability_reg); 3113 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 3114 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3115 &lp_technology_ability_reg); 3116 3117 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 3118 (u32)lp_technology_ability_reg, 3119 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 3120 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 3121 } 3122 3123 /** 3124 * ixgbe_fc_autoneg - Configure flow control 3125 * @hw: pointer to hardware structure 3126 * 3127 * Compares our advertised flow control capabilities to those advertised by 3128 * our link partner, and determines the proper flow control mode to use. 3129 **/ 3130 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3131 { 3132 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3133 ixgbe_link_speed speed; 3134 bool link_up; 3135 3136 DEBUGFUNC("ixgbe_fc_autoneg"); 3137 3138 /* 3139 * AN should have completed when the cable was plugged in. 3140 * Look for reasons to bail out. Bail out if: 3141 * - FC autoneg is disabled, or if 3142 * - link is not up. 3143 */ 3144 if (hw->fc.disable_fc_autoneg) { 3145 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 3146 "Flow control autoneg is disabled"); 3147 goto out; 3148 } 3149 3150 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3151 if (!link_up) { 3152 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3153 goto out; 3154 } 3155 3156 switch (hw->phy.media_type) { 3157 /* Autoneg flow control on fiber adapters */ 3158 case ixgbe_media_type_fiber_fixed: 3159 case ixgbe_media_type_fiber_qsfp: 3160 case ixgbe_media_type_fiber: 3161 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3162 ret_val = ixgbe_fc_autoneg_fiber(hw); 3163 break; 3164 3165 /* Autoneg flow control on backplane adapters */ 3166 case ixgbe_media_type_backplane: 3167 ret_val = ixgbe_fc_autoneg_backplane(hw); 3168 break; 3169 3170 /* Autoneg flow control on copper adapters */ 3171 case ixgbe_media_type_copper: 3172 if (ixgbe_device_supports_autoneg_fc(hw)) 3173 ret_val = ixgbe_fc_autoneg_copper(hw); 3174 break; 3175 3176 default: 3177 break; 3178 } 3179 3180 out: 3181 if (ret_val == IXGBE_SUCCESS) { 3182 hw->fc.fc_was_autonegged = TRUE; 3183 } else { 3184 hw->fc.fc_was_autonegged = FALSE; 3185 hw->fc.current_mode = hw->fc.requested_mode; 3186 } 3187 } 3188 3189 /* 3190 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3191 * @hw: pointer to hardware structure 3192 * 3193 * System-wide timeout range is encoded in PCIe Device Control2 register. 3194 * 3195 * Add 10% to specified maximum and return the number of times to poll for 3196 * completion timeout, in units of 100 microsec. Never return less than 3197 * 800 = 80 millisec. 3198 */ 3199 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3200 { 3201 s16 devctl2; 3202 u32 pollcnt; 3203 3204 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3205 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3206 3207 switch (devctl2) { 3208 case IXGBE_PCIDEVCTRL2_65_130ms: 3209 pollcnt = 1300; /* 130 millisec */ 3210 break; 3211 case IXGBE_PCIDEVCTRL2_260_520ms: 3212 pollcnt = 5200; /* 520 millisec */ 3213 break; 3214 case IXGBE_PCIDEVCTRL2_1_2s: 3215 pollcnt = 20000; /* 2 sec */ 3216 break; 3217 case IXGBE_PCIDEVCTRL2_4_8s: 3218 pollcnt = 80000; /* 8 sec */ 3219 break; 3220 case IXGBE_PCIDEVCTRL2_17_34s: 3221 pollcnt = 34000; /* 34 sec */ 3222 break; 3223 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3224 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3225 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3226 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3227 default: 3228 pollcnt = 800; /* 80 millisec minimum */ 3229 break; 3230 } 3231 3232 /* add 10% to spec maximum */ 3233 return (pollcnt * 11) / 10; 3234 } 3235 3236 /** 3237 * ixgbe_disable_pcie_master - Disable PCI-express master access 3238 * @hw: pointer to hardware structure 3239 * 3240 * Disables PCI-Express master access and verifies there are no pending 3241 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 3242 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 3243 * is returned signifying master requests disabled. 3244 **/ 3245 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 3246 { 3247 s32 status = IXGBE_SUCCESS; 3248 u32 i, poll; 3249 u16 value; 3250 3251 DEBUGFUNC("ixgbe_disable_pcie_master"); 3252 3253 /* Always set this bit to ensure any future transactions are blocked */ 3254 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3255 3256 /* Exit if master requests are blocked */ 3257 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3258 IXGBE_REMOVED(hw->hw_addr)) 3259 goto out; 3260 3261 /* Poll for master request bit to clear */ 3262 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 3263 usec_delay(100); 3264 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3265 goto out; 3266 } 3267 3268 /* 3269 * Two consecutive resets are required via CTRL.RST per datasheet 3270 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 3271 * of this need. The first reset prevents new master requests from 3272 * being issued by our device. We then must wait 1usec or more for any 3273 * remaining completions from the PCIe bus to trickle in, and then reset 3274 * again to clear out any effects they may have had on our device. 3275 */ 3276 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 3277 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3278 3279 if (hw->mac.type >= ixgbe_mac_X550) 3280 goto out; 3281 3282 /* 3283 * Before proceeding, make sure that the PCIe block does not have 3284 * transactions pending. 3285 */ 3286 poll = ixgbe_pcie_timeout_poll(hw); 3287 for (i = 0; i < poll; i++) { 3288 usec_delay(100); 3289 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3290 if (IXGBE_REMOVED(hw->hw_addr)) 3291 goto out; 3292 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3293 goto out; 3294 } 3295 3296 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3297 "PCIe transaction pending bit also did not clear.\n"); 3298 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 3299 3300 out: 3301 return status; 3302 } 3303 3304 /** 3305 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3306 * @hw: pointer to hardware structure 3307 * @mask: Mask to specify which semaphore to acquire 3308 * 3309 * Acquires the SWFW semaphore through the GSSR register for the specified 3310 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3311 **/ 3312 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3313 { 3314 u32 gssr = 0; 3315 u32 swmask = mask; 3316 u32 fwmask = mask << 5; 3317 u32 timeout = 200; 3318 u32 i; 3319 3320 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3321 3322 for (i = 0; i < timeout; i++) { 3323 /* 3324 * SW NVM semaphore bit is used for access to all 3325 * SW_FW_SYNC bits (not just NVM) 3326 */ 3327 if (ixgbe_get_eeprom_semaphore(hw)) 3328 return IXGBE_ERR_SWFW_SYNC; 3329 3330 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3331 if (!(gssr & (fwmask | swmask))) { 3332 gssr |= swmask; 3333 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3334 ixgbe_release_eeprom_semaphore(hw); 3335 return IXGBE_SUCCESS; 3336 } else { 3337 /* Resource is currently in use by FW or SW */ 3338 ixgbe_release_eeprom_semaphore(hw); 3339 msec_delay(5); 3340 } 3341 } 3342 3343 /* If time expired clear the bits holding the lock and retry */ 3344 if (gssr & (fwmask | swmask)) 3345 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3346 3347 msec_delay(5); 3348 return IXGBE_ERR_SWFW_SYNC; 3349 } 3350 3351 /** 3352 * ixgbe_release_swfw_sync - Release SWFW semaphore 3353 * @hw: pointer to hardware structure 3354 * @mask: Mask to specify which semaphore to release 3355 * 3356 * Releases the SWFW semaphore through the GSSR register for the specified 3357 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3358 **/ 3359 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3360 { 3361 u32 gssr; 3362 u32 swmask = mask; 3363 3364 DEBUGFUNC("ixgbe_release_swfw_sync"); 3365 3366 ixgbe_get_eeprom_semaphore(hw); 3367 3368 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3369 gssr &= ~swmask; 3370 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3371 3372 ixgbe_release_eeprom_semaphore(hw); 3373 } 3374 3375 /** 3376 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3377 * @hw: pointer to hardware structure 3378 * 3379 * Stops the receive data path and waits for the HW to internally empty 3380 * the Rx security block 3381 **/ 3382 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3383 { 3384 #define IXGBE_MAX_SECRX_POLL 4000 3385 3386 int i; 3387 int secrxreg; 3388 3389 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3390 3391 3392 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3393 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3394 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3395 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3396 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3397 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3398 break; 3399 else 3400 /* Use interrupt-safe sleep just in case */ 3401 usec_delay(10); 3402 } 3403 3404 /* For informational purposes only */ 3405 if (i >= IXGBE_MAX_SECRX_POLL) 3406 DEBUGOUT("Rx unit being enabled before security " 3407 "path fully disabled. Continuing with init.\n"); 3408 3409 return IXGBE_SUCCESS; 3410 } 3411 3412 /** 3413 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3414 * @hw: pointer to hardware structure 3415 * @locked: bool to indicate whether the SW/FW lock was taken 3416 * @reg_val: Value we read from AUTOC 3417 * 3418 * The default case requires no protection so just to the register read. 3419 */ 3420 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3421 { 3422 *locked = FALSE; 3423 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3424 return IXGBE_SUCCESS; 3425 } 3426 3427 /** 3428 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3429 * @hw: pointer to hardware structure 3430 * @reg_val: value to write to AUTOC 3431 * @locked: bool to indicate whether the SW/FW lock was already taken by 3432 * previous read. 3433 * 3434 * The default case requires no protection so just to the register write. 3435 */ 3436 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3437 { 3438 UNREFERENCED_1PARAMETER(locked); 3439 3440 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3441 return IXGBE_SUCCESS; 3442 } 3443 3444 /** 3445 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3446 * @hw: pointer to hardware structure 3447 * 3448 * Enables the receive data path. 3449 **/ 3450 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3451 { 3452 u32 secrxreg; 3453 3454 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3455 3456 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3457 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3458 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3459 IXGBE_WRITE_FLUSH(hw); 3460 3461 return IXGBE_SUCCESS; 3462 } 3463 3464 /** 3465 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3466 * @hw: pointer to hardware structure 3467 * @regval: register value to write to RXCTRL 3468 * 3469 * Enables the Rx DMA unit 3470 **/ 3471 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3472 { 3473 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3474 3475 if (regval & IXGBE_RXCTRL_RXEN) 3476 ixgbe_enable_rx(hw); 3477 else 3478 ixgbe_disable_rx(hw); 3479 3480 return IXGBE_SUCCESS; 3481 } 3482 3483 /** 3484 * ixgbe_blink_led_start_generic - Blink LED based on index. 3485 * @hw: pointer to hardware structure 3486 * @index: led number to blink 3487 **/ 3488 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3489 { 3490 ixgbe_link_speed speed = 0; 3491 bool link_up = 0; 3492 u32 autoc_reg = 0; 3493 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3494 s32 ret_val = IXGBE_SUCCESS; 3495 bool locked = FALSE; 3496 3497 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3498 3499 if (index > 3) 3500 return IXGBE_ERR_PARAM; 3501 3502 /* 3503 * Link must be up to auto-blink the LEDs; 3504 * Force it if link is down. 3505 */ 3506 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3507 3508 if (!link_up) { 3509 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3510 if (ret_val != IXGBE_SUCCESS) 3511 goto out; 3512 3513 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3514 autoc_reg |= IXGBE_AUTOC_FLU; 3515 3516 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3517 if (ret_val != IXGBE_SUCCESS) 3518 goto out; 3519 3520 IXGBE_WRITE_FLUSH(hw); 3521 msec_delay(10); 3522 } 3523 3524 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3525 led_reg |= IXGBE_LED_BLINK(index); 3526 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3527 IXGBE_WRITE_FLUSH(hw); 3528 3529 out: 3530 return ret_val; 3531 } 3532 3533 /** 3534 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3535 * @hw: pointer to hardware structure 3536 * @index: led number to stop blinking 3537 **/ 3538 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3539 { 3540 u32 autoc_reg = 0; 3541 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3542 s32 ret_val = IXGBE_SUCCESS; 3543 bool locked = FALSE; 3544 3545 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3546 3547 if (index > 3) 3548 return IXGBE_ERR_PARAM; 3549 3550 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3551 if (ret_val != IXGBE_SUCCESS) 3552 goto out; 3553 3554 autoc_reg &= ~IXGBE_AUTOC_FLU; 3555 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3556 3557 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3558 if (ret_val != IXGBE_SUCCESS) 3559 goto out; 3560 3561 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3562 led_reg &= ~IXGBE_LED_BLINK(index); 3563 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3564 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3565 IXGBE_WRITE_FLUSH(hw); 3566 3567 out: 3568 return ret_val; 3569 } 3570 3571 /** 3572 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3573 * @hw: pointer to hardware structure 3574 * @san_mac_offset: SAN MAC address offset 3575 * 3576 * This function will read the EEPROM location for the SAN MAC address 3577 * pointer, and returns the value at that location. This is used in both 3578 * get and set mac_addr routines. 3579 **/ 3580 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3581 u16 *san_mac_offset) 3582 { 3583 s32 ret_val; 3584 3585 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3586 3587 /* 3588 * First read the EEPROM pointer to see if the MAC addresses are 3589 * available. 3590 */ 3591 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3592 san_mac_offset); 3593 if (ret_val) { 3594 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3595 "eeprom at offset %d failed", 3596 IXGBE_SAN_MAC_ADDR_PTR); 3597 } 3598 3599 return ret_val; 3600 } 3601 3602 /** 3603 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3604 * @hw: pointer to hardware structure 3605 * @san_mac_addr: SAN MAC address 3606 * 3607 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3608 * per-port, so set_lan_id() must be called before reading the addresses. 3609 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3610 * upon for non-SFP connections, so we must call it here. 3611 **/ 3612 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3613 { 3614 u16 san_mac_data, san_mac_offset; 3615 u8 i; 3616 s32 ret_val; 3617 3618 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3619 3620 /* 3621 * First read the EEPROM pointer to see if the MAC addresses are 3622 * available. If they're not, no point in calling set_lan_id() here. 3623 */ 3624 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3625 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3626 goto san_mac_addr_out; 3627 3628 /* make sure we know which port we need to program */ 3629 hw->mac.ops.set_lan_id(hw); 3630 /* apply the port offset to the address offset */ 3631 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3632 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3633 for (i = 0; i < 3; i++) { 3634 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3635 &san_mac_data); 3636 if (ret_val) { 3637 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3638 "eeprom read at offset %d failed", 3639 san_mac_offset); 3640 goto san_mac_addr_out; 3641 } 3642 san_mac_addr[i * 2] = (u8)(san_mac_data); 3643 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3644 san_mac_offset++; 3645 } 3646 return IXGBE_SUCCESS; 3647 3648 san_mac_addr_out: 3649 /* 3650 * No addresses available in this EEPROM. It's not an 3651 * error though, so just wipe the local address and return. 3652 */ 3653 for (i = 0; i < 6; i++) 3654 san_mac_addr[i] = 0xFF; 3655 return IXGBE_SUCCESS; 3656 } 3657 3658 /** 3659 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3660 * @hw: pointer to hardware structure 3661 * @san_mac_addr: SAN MAC address 3662 * 3663 * Write a SAN MAC address to the EEPROM. 3664 **/ 3665 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3666 { 3667 s32 ret_val; 3668 u16 san_mac_data, san_mac_offset; 3669 u8 i; 3670 3671 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3672 3673 /* Look for SAN mac address pointer. If not defined, return */ 3674 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3675 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3676 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3677 3678 /* Make sure we know which port we need to write */ 3679 hw->mac.ops.set_lan_id(hw); 3680 /* Apply the port offset to the address offset */ 3681 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3682 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3683 3684 for (i = 0; i < 3; i++) { 3685 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3686 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3687 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3688 san_mac_offset++; 3689 } 3690 3691 return IXGBE_SUCCESS; 3692 } 3693 3694 /** 3695 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3696 * @hw: pointer to hardware structure 3697 * 3698 * Read PCIe configuration space, and get the MSI-X vector count from 3699 * the capabilities table. 3700 **/ 3701 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3702 { 3703 u16 msix_count = 1; 3704 u16 max_msix_count; 3705 u16 pcie_offset; 3706 3707 switch (hw->mac.type) { 3708 case ixgbe_mac_82598EB: 3709 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3710 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3711 break; 3712 case ixgbe_mac_82599EB: 3713 case ixgbe_mac_X540: 3714 case ixgbe_mac_X550: 3715 case ixgbe_mac_X550EM_x: 3716 case ixgbe_mac_X550EM_a: 3717 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3718 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3719 break; 3720 default: 3721 return msix_count; 3722 } 3723 3724 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3725 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3726 if (IXGBE_REMOVED(hw->hw_addr)) 3727 msix_count = 0; 3728 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3729 3730 /* MSI-X count is zero-based in HW */ 3731 msix_count++; 3732 3733 if (msix_count > max_msix_count) 3734 msix_count = max_msix_count; 3735 3736 return msix_count; 3737 } 3738 3739 /** 3740 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3741 * @hw: pointer to hardware structure 3742 * @addr: Address to put into receive address register 3743 * @vmdq: VMDq pool to assign 3744 * 3745 * Puts an ethernet address into a receive address register, or 3746 * finds the rar that it is already in; adds to the pool list 3747 **/ 3748 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3749 { 3750 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3751 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3752 u32 rar; 3753 u32 rar_low, rar_high; 3754 u32 addr_low, addr_high; 3755 3756 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3757 3758 /* swap bytes for HW little endian */ 3759 addr_low = addr[0] | (addr[1] << 8) 3760 | (addr[2] << 16) 3761 | (addr[3] << 24); 3762 addr_high = addr[4] | (addr[5] << 8); 3763 3764 /* 3765 * Either find the mac_id in rar or find the first empty space. 3766 * rar_highwater points to just after the highest currently used 3767 * rar in order to shorten the search. It grows when we add a new 3768 * rar to the top. 3769 */ 3770 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3771 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3772 3773 if (((IXGBE_RAH_AV & rar_high) == 0) 3774 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3775 first_empty_rar = rar; 3776 } else if ((rar_high & 0xFFFF) == addr_high) { 3777 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3778 if (rar_low == addr_low) 3779 break; /* found it already in the rars */ 3780 } 3781 } 3782 3783 if (rar < hw->mac.rar_highwater) { 3784 /* already there so just add to the pool bits */ 3785 ixgbe_set_vmdq(hw, rar, vmdq); 3786 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3787 /* stick it into first empty RAR slot we found */ 3788 rar = first_empty_rar; 3789 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3790 } else if (rar == hw->mac.rar_highwater) { 3791 /* add it to the top of the list and inc the highwater mark */ 3792 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3793 hw->mac.rar_highwater++; 3794 } else if (rar >= hw->mac.num_rar_entries) { 3795 return IXGBE_ERR_INVALID_MAC_ADDR; 3796 } 3797 3798 /* 3799 * If we found rar[0], make sure the default pool bit (we use pool 0) 3800 * remains cleared to be sure default pool packets will get delivered 3801 */ 3802 if (rar == 0) 3803 ixgbe_clear_vmdq(hw, rar, 0); 3804 3805 return rar; 3806 } 3807 3808 /** 3809 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3810 * @hw: pointer to hardware struct 3811 * @rar: receive address register index to disassociate 3812 * @vmdq: VMDq pool index to remove from the rar 3813 **/ 3814 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3815 { 3816 u32 mpsar_lo, mpsar_hi; 3817 u32 rar_entries = hw->mac.num_rar_entries; 3818 3819 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3820 3821 /* Make sure we are using a valid rar index range */ 3822 if (rar >= rar_entries) { 3823 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3824 "RAR index %d is out of range.\n", rar); 3825 return IXGBE_ERR_INVALID_ARGUMENT; 3826 } 3827 3828 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3829 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3830 3831 if (IXGBE_REMOVED(hw->hw_addr)) 3832 goto done; 3833 3834 if (!mpsar_lo && !mpsar_hi) 3835 goto done; 3836 3837 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3838 if (mpsar_lo) { 3839 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3840 mpsar_lo = 0; 3841 } 3842 if (mpsar_hi) { 3843 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3844 mpsar_hi = 0; 3845 } 3846 } else if (vmdq < 32) { 3847 mpsar_lo &= ~(1 << vmdq); 3848 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3849 } else { 3850 mpsar_hi &= ~(1 << (vmdq - 32)); 3851 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3852 } 3853 3854 /* was that the last pool using this rar? */ 3855 if (mpsar_lo == 0 && mpsar_hi == 0 && 3856 rar != 0 && rar != hw->mac.san_mac_rar_index) 3857 hw->mac.ops.clear_rar(hw, rar); 3858 done: 3859 return IXGBE_SUCCESS; 3860 } 3861 3862 /** 3863 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3864 * @hw: pointer to hardware struct 3865 * @rar: receive address register index to associate with a VMDq index 3866 * @vmdq: VMDq pool index 3867 **/ 3868 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3869 { 3870 u32 mpsar; 3871 u32 rar_entries = hw->mac.num_rar_entries; 3872 3873 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3874 3875 /* Make sure we are using a valid rar index range */ 3876 if (rar >= rar_entries) { 3877 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3878 "RAR index %d is out of range.\n", rar); 3879 return IXGBE_ERR_INVALID_ARGUMENT; 3880 } 3881 3882 if (vmdq < 32) { 3883 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3884 mpsar |= 1 << vmdq; 3885 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3886 } else { 3887 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3888 mpsar |= 1 << (vmdq - 32); 3889 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3890 } 3891 return IXGBE_SUCCESS; 3892 } 3893 3894 /** 3895 * This function should only be involved in the IOV mode. 3896 * In IOV mode, Default pool is next pool after the number of 3897 * VFs advertized and not 0. 3898 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3899 * 3900 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3901 * @hw: pointer to hardware struct 3902 * @vmdq: VMDq pool index 3903 **/ 3904 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3905 { 3906 u32 rar = hw->mac.san_mac_rar_index; 3907 3908 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3909 3910 if (vmdq < 32) { 3911 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3912 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3913 } else { 3914 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3915 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3916 } 3917 3918 return IXGBE_SUCCESS; 3919 } 3920 3921 /** 3922 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3923 * @hw: pointer to hardware structure 3924 **/ 3925 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3926 { 3927 int i; 3928 3929 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3930 DEBUGOUT(" Clearing UTA\n"); 3931 3932 for (i = 0; i < 128; i++) 3933 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3934 3935 return IXGBE_SUCCESS; 3936 } 3937 3938 /** 3939 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3940 * @hw: pointer to hardware structure 3941 * @vlan: VLAN id to write to VLAN filter 3942 * @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if 3943 * vlanid not found 3944 * 3945 * 3946 * return the VLVF index where this VLAN id should be placed 3947 * 3948 **/ 3949 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3950 { 3951 s32 regindex, first_empty_slot; 3952 u32 bits; 3953 3954 /* short cut the special case */ 3955 if (vlan == 0) 3956 return 0; 3957 3958 /* if vlvf_bypass is set we don't want to use an empty slot, we 3959 * will simply bypass the VLVF if there are no entries present in the 3960 * VLVF that contain our VLAN 3961 */ 3962 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3963 3964 /* add VLAN enable bit for comparison */ 3965 vlan |= IXGBE_VLVF_VIEN; 3966 3967 /* Search for the vlan id in the VLVF entries. Save off the first empty 3968 * slot found along the way. 3969 * 3970 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3971 */ 3972 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3973 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3974 if (bits == vlan) 3975 return regindex; 3976 if (!first_empty_slot && !bits) 3977 first_empty_slot = regindex; 3978 } 3979 3980 /* If we are here then we didn't find the VLAN. Return first empty 3981 * slot we found during our search, else error. 3982 */ 3983 if (!first_empty_slot) 3984 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); 3985 3986 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; 3987 } 3988 3989 /** 3990 * ixgbe_set_vfta_generic - Set VLAN filter table 3991 * @hw: pointer to hardware structure 3992 * @vlan: VLAN id to write to VLAN filter 3993 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3994 * @vlan_on: boolean flag to turn on/off VLAN 3995 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3996 * 3997 * Turn on/off specified VLAN in the VLAN filter table. 3998 **/ 3999 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4000 bool vlan_on, bool vlvf_bypass) 4001 { 4002 u32 regidx, vfta_delta, vfta; 4003 s32 ret_val; 4004 4005 DEBUGFUNC("ixgbe_set_vfta_generic"); 4006 4007 if (vlan > 4095 || vind > 63) 4008 return IXGBE_ERR_PARAM; 4009 4010 /* 4011 * this is a 2 part operation - first the VFTA, then the 4012 * VLVF and VLVFB if VT Mode is set 4013 * We don't write the VFTA until we know the VLVF part succeeded. 4014 */ 4015 4016 /* Part 1 4017 * The VFTA is a bitstring made up of 128 32-bit registers 4018 * that enable the particular VLAN id, much like the MTA: 4019 * bits[11-5]: which register 4020 * bits[4-0]: which bit in the register 4021 */ 4022 regidx = vlan / 32; 4023 vfta_delta = 1 << (vlan % 32); 4024 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 4025 4026 /* 4027 * vfta_delta represents the difference between the current value 4028 * of vfta and the value we want in the register. Since the diff 4029 * is an XOR mask we can just update the vfta using an XOR 4030 */ 4031 vfta_delta &= vlan_on ? ~vfta : vfta; 4032 vfta ^= vfta_delta; 4033 4034 /* Part 2 4035 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 4036 */ 4037 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 4038 vfta, vlvf_bypass); 4039 if (ret_val != IXGBE_SUCCESS) { 4040 if (vlvf_bypass) 4041 goto vfta_update; 4042 return ret_val; 4043 } 4044 4045 vfta_update: 4046 /* Update VFTA now that we are ready for traffic */ 4047 if (vfta_delta) 4048 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 4049 4050 return IXGBE_SUCCESS; 4051 } 4052 4053 /** 4054 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 4055 * @hw: pointer to hardware structure 4056 * @vlan: VLAN id to write to VLAN filter 4057 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 4058 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 4059 * @vfta_delta: pointer to the difference between the current value of VFTA 4060 * and the desired value 4061 * @vfta: the desired value of the VFTA 4062 * @vlvf_bypass: boolean flag indicating updating default pool is okay 4063 * 4064 * Turn on/off specified bit in VLVF table. 4065 **/ 4066 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4067 bool vlan_on, u32 *vfta_delta, u32 vfta, 4068 bool vlvf_bypass) 4069 { 4070 u32 bits; 4071 s32 vlvf_index; 4072 4073 DEBUGFUNC("ixgbe_set_vlvf_generic"); 4074 4075 if (vlan > 4095 || vind > 63) 4076 return IXGBE_ERR_PARAM; 4077 4078 /* If VT Mode is set 4079 * Either vlan_on 4080 * make sure the vlan is in VLVF 4081 * set the vind bit in the matching VLVFB 4082 * Or !vlan_on 4083 * clear the pool bit and possibly the vind 4084 */ 4085 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4086 return IXGBE_SUCCESS; 4087 4088 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4089 if (vlvf_index < 0) 4090 return vlvf_index; 4091 4092 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 4093 4094 /* set the pool bit */ 4095 bits |= 1 << (vind % 32); 4096 if (vlan_on) 4097 goto vlvf_update; 4098 4099 /* clear the pool bit */ 4100 bits ^= 1 << (vind % 32); 4101 4102 if (!bits && 4103 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4104 /* Clear VFTA first, then disable VLVF. Otherwise 4105 * we run the risk of stray packets leaking into 4106 * the PF via the default pool 4107 */ 4108 if (*vfta_delta) 4109 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4110 4111 /* disable VLVF and clear remaining bit from pool */ 4112 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4113 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4114 4115 return IXGBE_SUCCESS; 4116 } 4117 4118 /* If there are still bits set in the VLVFB registers 4119 * for the VLAN ID indicated we need to see if the 4120 * caller is requesting that we clear the VFTA entry bit. 4121 * If the caller has requested that we clear the VFTA 4122 * entry bit but there are still pools/VFs using this VLAN 4123 * ID entry then ignore the request. We're not worried 4124 * about the case where we're turning the VFTA VLAN ID 4125 * entry bit on, only when requested to turn it off as 4126 * there may be multiple pools and/or VFs using the 4127 * VLAN ID entry. In that case we cannot clear the 4128 * VFTA bit until all pools/VFs using that VLAN ID have also 4129 * been cleared. This will be indicated by "bits" being 4130 * zero. 4131 */ 4132 *vfta_delta = 0; 4133 4134 vlvf_update: 4135 /* record pool change and enable VLAN ID if not already enabled */ 4136 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4137 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4138 4139 return IXGBE_SUCCESS; 4140 } 4141 4142 /** 4143 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4144 * @hw: pointer to hardware structure 4145 * 4146 * Clears the VLAN filer table, and the VMDq index associated with the filter 4147 **/ 4148 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4149 { 4150 u32 offset; 4151 4152 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4153 4154 for (offset = 0; offset < hw->mac.vft_size; offset++) 4155 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4156 4157 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4158 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4159 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4160 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); 4161 } 4162 4163 return IXGBE_SUCCESS; 4164 } 4165 4166 /** 4167 * ixgbe_toggle_txdctl_generic - Toggle VF's queues 4168 * @hw: pointer to hardware structure 4169 * @vf_number: VF index 4170 * 4171 * Enable and disable each queue in VF. 4172 */ 4173 s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number) 4174 { 4175 u8 queue_count, i; 4176 u32 offset, reg; 4177 4178 if (vf_number > 63) 4179 return IXGBE_ERR_PARAM; 4180 4181 /* 4182 * Determine number of queues by checking 4183 * number of virtual functions 4184 */ 4185 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4186 switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) { 4187 case IXGBE_GCR_EXT_VT_MODE_64: 4188 queue_count = 2; 4189 break; 4190 case IXGBE_GCR_EXT_VT_MODE_32: 4191 queue_count = 4; 4192 break; 4193 case IXGBE_GCR_EXT_VT_MODE_16: 4194 queue_count = 8; 4195 break; 4196 default: 4197 return IXGBE_ERR_CONFIG; 4198 } 4199 4200 /* Toggle queues */ 4201 for (i = 0; i < queue_count; ++i) { 4202 /* Calculate offset of current queue */ 4203 offset = queue_count * vf_number + i; 4204 4205 /* Enable queue */ 4206 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); 4207 reg |= IXGBE_TXDCTL_ENABLE; 4208 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); 4209 IXGBE_WRITE_FLUSH(hw); 4210 4211 /* Disable queue */ 4212 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); 4213 reg &= ~IXGBE_TXDCTL_ENABLE; 4214 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); 4215 IXGBE_WRITE_FLUSH(hw); 4216 } 4217 4218 return IXGBE_SUCCESS; 4219 } 4220 4221 /** 4222 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4223 * @hw: pointer to hardware structure 4224 * 4225 * Contains the logic to identify if we need to verify link for the 4226 * crosstalk fix 4227 **/ 4228 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4229 { 4230 4231 /* Does FW say we need the fix */ 4232 if (!hw->need_crosstalk_fix) 4233 return FALSE; 4234 4235 /* Only consider SFP+ PHYs i.e. media type fiber */ 4236 switch (hw->mac.ops.get_media_type(hw)) { 4237 case ixgbe_media_type_fiber: 4238 case ixgbe_media_type_fiber_qsfp: 4239 break; 4240 default: 4241 return FALSE; 4242 } 4243 4244 return TRUE; 4245 } 4246 4247 /** 4248 * ixgbe_check_mac_link_generic - Determine link and speed status 4249 * @hw: pointer to hardware structure 4250 * @speed: pointer to link speed 4251 * @link_up: TRUE when link is up 4252 * @link_up_wait_to_complete: bool used to wait for link up or not 4253 * 4254 * Reads the links register to determine if link is up and the current speed 4255 **/ 4256 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4257 bool *link_up, bool link_up_wait_to_complete) 4258 { 4259 u32 links_reg, links_orig; 4260 u32 i; 4261 4262 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4263 4264 /* If Crosstalk fix enabled do the sanity check of making sure 4265 * the SFP+ cage is full. 4266 */ 4267 if (ixgbe_need_crosstalk_fix(hw)) { 4268 u32 sfp_cage_full; 4269 4270 switch (hw->mac.type) { 4271 case ixgbe_mac_82599EB: 4272 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4273 IXGBE_ESDP_SDP2; 4274 break; 4275 case ixgbe_mac_X550EM_x: 4276 case ixgbe_mac_X550EM_a: 4277 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4278 IXGBE_ESDP_SDP0; 4279 break; 4280 default: 4281 /* sanity check - No SFP+ devices here */ 4282 sfp_cage_full = FALSE; 4283 break; 4284 } 4285 4286 if (!sfp_cage_full) { 4287 *link_up = FALSE; 4288 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4289 return IXGBE_SUCCESS; 4290 } 4291 } 4292 4293 /* clear the old state */ 4294 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4295 4296 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4297 4298 if (links_orig != links_reg) { 4299 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4300 links_orig, links_reg); 4301 } 4302 4303 if (link_up_wait_to_complete) { 4304 for (i = 0; i < hw->mac.max_link_up_time; i++) { 4305 if (links_reg & IXGBE_LINKS_UP) { 4306 *link_up = TRUE; 4307 break; 4308 } else { 4309 *link_up = FALSE; 4310 } 4311 msec_delay(100); 4312 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4313 } 4314 } else { 4315 if (links_reg & IXGBE_LINKS_UP) 4316 *link_up = TRUE; 4317 else 4318 *link_up = FALSE; 4319 } 4320 4321 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4322 case IXGBE_LINKS_SPEED_10G_82599: 4323 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4324 if (hw->mac.type >= ixgbe_mac_X550) { 4325 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4326 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4327 } 4328 break; 4329 case IXGBE_LINKS_SPEED_1G_82599: 4330 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4331 break; 4332 case IXGBE_LINKS_SPEED_100_82599: 4333 *speed = IXGBE_LINK_SPEED_100_FULL; 4334 if (hw->mac.type >= ixgbe_mac_X550) { 4335 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4336 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4337 } 4338 break; 4339 case IXGBE_LINKS_SPEED_10_X550EM_A: 4340 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4341 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4342 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4343 *speed = IXGBE_LINK_SPEED_10_FULL; 4344 break; 4345 default: 4346 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4347 } 4348 4349 return IXGBE_SUCCESS; 4350 } 4351 4352 /** 4353 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4354 * the EEPROM 4355 * @hw: pointer to hardware structure 4356 * @wwnn_prefix: the alternative WWNN prefix 4357 * @wwpn_prefix: the alternative WWPN prefix 4358 * 4359 * This function will read the EEPROM from the alternative SAN MAC address 4360 * block to check the support for the alternative WWNN/WWPN prefix support. 4361 **/ 4362 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4363 u16 *wwpn_prefix) 4364 { 4365 u16 offset, caps; 4366 u16 alt_san_mac_blk_offset; 4367 4368 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4369 4370 /* clear output first */ 4371 *wwnn_prefix = 0xFFFF; 4372 *wwpn_prefix = 0xFFFF; 4373 4374 /* check if alternative SAN MAC is supported */ 4375 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4376 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4377 goto wwn_prefix_err; 4378 4379 if ((alt_san_mac_blk_offset == 0) || 4380 (alt_san_mac_blk_offset == 0xFFFF)) 4381 goto wwn_prefix_out; 4382 4383 /* check capability in alternative san mac address block */ 4384 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4385 if (hw->eeprom.ops.read(hw, offset, &caps)) 4386 goto wwn_prefix_err; 4387 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4388 goto wwn_prefix_out; 4389 4390 /* get the corresponding prefix for WWNN/WWPN */ 4391 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4392 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4393 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4394 "eeprom read at offset %d failed", offset); 4395 } 4396 4397 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4398 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4399 goto wwn_prefix_err; 4400 4401 wwn_prefix_out: 4402 return IXGBE_SUCCESS; 4403 4404 wwn_prefix_err: 4405 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4406 "eeprom read at offset %d failed", offset); 4407 return IXGBE_SUCCESS; 4408 } 4409 4410 /** 4411 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4412 * @hw: pointer to hardware structure 4413 * @bs: the fcoe boot status 4414 * 4415 * This function will read the FCOE boot status from the iSCSI FCOE block 4416 **/ 4417 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4418 { 4419 u16 offset, caps, flags; 4420 s32 status; 4421 4422 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4423 4424 /* clear output first */ 4425 *bs = ixgbe_fcoe_bootstatus_unavailable; 4426 4427 /* check if FCOE IBA block is present */ 4428 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4429 status = hw->eeprom.ops.read(hw, offset, &caps); 4430 if (status != IXGBE_SUCCESS) 4431 goto out; 4432 4433 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4434 goto out; 4435 4436 /* check if iSCSI FCOE block is populated */ 4437 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4438 if (status != IXGBE_SUCCESS) 4439 goto out; 4440 4441 if ((offset == 0) || (offset == 0xFFFF)) 4442 goto out; 4443 4444 /* read fcoe flags in iSCSI FCOE block */ 4445 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4446 status = hw->eeprom.ops.read(hw, offset, &flags); 4447 if (status != IXGBE_SUCCESS) 4448 goto out; 4449 4450 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4451 *bs = ixgbe_fcoe_bootstatus_enabled; 4452 else 4453 *bs = ixgbe_fcoe_bootstatus_disabled; 4454 4455 out: 4456 return status; 4457 } 4458 4459 /** 4460 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4461 * @hw: pointer to hardware structure 4462 * @enable: enable or disable switch for MAC anti-spoofing 4463 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 4464 * 4465 **/ 4466 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4467 { 4468 int vf_target_reg = vf >> 3; 4469 int vf_target_shift = vf % 8; 4470 u32 pfvfspoof; 4471 4472 if (hw->mac.type == ixgbe_mac_82598EB) 4473 return; 4474 4475 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4476 if (enable) 4477 pfvfspoof |= (1 << vf_target_shift); 4478 else 4479 pfvfspoof &= ~(1 << vf_target_shift); 4480 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4481 } 4482 4483 /** 4484 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4485 * @hw: pointer to hardware structure 4486 * @enable: enable or disable switch for VLAN anti-spoofing 4487 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4488 * 4489 **/ 4490 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4491 { 4492 int vf_target_reg = vf >> 3; 4493 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4494 u32 pfvfspoof; 4495 4496 if (hw->mac.type == ixgbe_mac_82598EB) 4497 return; 4498 4499 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4500 if (enable) 4501 pfvfspoof |= (1 << vf_target_shift); 4502 else 4503 pfvfspoof &= ~(1 << vf_target_shift); 4504 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4505 } 4506 4507 /** 4508 * ixgbe_get_device_caps_generic - Get additional device capabilities 4509 * @hw: pointer to hardware structure 4510 * @device_caps: the EEPROM word with the extra device capabilities 4511 * 4512 * This function will read the EEPROM location for the device capabilities, 4513 * and return the word through device_caps. 4514 **/ 4515 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4516 { 4517 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4518 4519 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4520 4521 return IXGBE_SUCCESS; 4522 } 4523 4524 /** 4525 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4526 * @hw: pointer to hardware structure 4527 * 4528 **/ 4529 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4530 { 4531 u32 regval; 4532 u32 i; 4533 4534 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4535 4536 /* Enable relaxed ordering */ 4537 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4538 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4539 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4540 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4541 } 4542 4543 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4544 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4545 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4546 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4547 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4548 } 4549 4550 } 4551 4552 /** 4553 * ixgbe_calculate_checksum - Calculate checksum for buffer 4554 * @buffer: pointer to EEPROM 4555 * @length: size of EEPROM to calculate a checksum for 4556 * Calculates the checksum for some buffer on a specified length. The 4557 * checksum calculated is returned. 4558 **/ 4559 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4560 { 4561 u32 i; 4562 u8 sum = 0; 4563 4564 DEBUGFUNC("ixgbe_calculate_checksum"); 4565 4566 if (!buffer) 4567 return 0; 4568 4569 for (i = 0; i < length; i++) 4570 sum += buffer[i]; 4571 4572 return (u8) (0 - sum); 4573 } 4574 4575 /** 4576 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 4577 * @hw: pointer to the HW structure 4578 * @buffer: command to write and where the return status will be placed 4579 * @length: length of buffer, must be multiple of 4 bytes 4580 * @timeout: time in ms to wait for command completion 4581 * 4582 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4583 * else returns semaphore error when encountering an error acquiring 4584 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4585 * 4586 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4587 * by the caller. 4588 **/ 4589 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4590 u32 timeout) 4591 { 4592 u32 hicr, i, fwsts; 4593 u16 dword_len; 4594 4595 DEBUGFUNC("ixgbe_hic_unlocked"); 4596 4597 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4598 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4599 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4600 } 4601 4602 /* Set bit 9 of FWSTS clearing FW reset indication */ 4603 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4604 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4605 4606 /* Check that the host interface is enabled. */ 4607 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4608 if (!(hicr & IXGBE_HICR_EN)) { 4609 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4610 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4611 } 4612 4613 /* Calculate length in DWORDs. We must be DWORD aligned */ 4614 if (length % sizeof(u32)) { 4615 DEBUGOUT("Buffer length failure, not aligned to dword"); 4616 return IXGBE_ERR_INVALID_ARGUMENT; 4617 } 4618 4619 dword_len = length >> 2; 4620 4621 /* The device driver writes the relevant command block 4622 * into the ram area. 4623 */ 4624 for (i = 0; i < dword_len; i++) 4625 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4626 i, IXGBE_CPU_TO_LE32(buffer[i])); 4627 4628 /* Setting this bit tells the ARC that a new command is pending. */ 4629 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4630 4631 for (i = 0; i < timeout; i++) { 4632 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4633 if (!(hicr & IXGBE_HICR_C)) 4634 break; 4635 msec_delay(1); 4636 } 4637 4638 /* For each command except "Apply Update" perform 4639 * status checks in the HICR registry. 4640 */ 4641 if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) == 4642 IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD) 4643 return IXGBE_SUCCESS; 4644 4645 /* Check command completion */ 4646 if ((timeout && i == timeout) || 4647 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4648 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4649 "Command has failed with no status valid.\n"); 4650 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4651 } 4652 4653 return IXGBE_SUCCESS; 4654 } 4655 4656 /** 4657 * ixgbe_host_interface_command - Issue command to manageability block 4658 * @hw: pointer to the HW structure 4659 * @buffer: contains the command to write and where the return status will 4660 * be placed 4661 * @length: length of buffer, must be multiple of 4 bytes 4662 * @timeout: time in ms to wait for command completion 4663 * @return_data: read and return data from the buffer (TRUE) or not (FALSE) 4664 * Needed because FW structures are big endian and decoding of 4665 * these fields can be 8 bit or 16 bit based on command. Decoding 4666 * is not easily understood without making a table of commands. 4667 * So we will leave this up to the caller to read back the data 4668 * in these cases. 4669 * 4670 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4671 * else returns semaphore error when encountering an error acquiring 4672 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4673 **/ 4674 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4675 u32 length, u32 timeout, bool return_data) 4676 { 4677 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4678 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer; 4679 u16 buf_len; 4680 s32 status; 4681 u32 bi; 4682 u32 dword_len; 4683 4684 DEBUGFUNC("ixgbe_host_interface_command"); 4685 4686 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4687 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4688 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4689 } 4690 4691 /* Take management host interface semaphore */ 4692 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4693 if (status) 4694 return status; 4695 4696 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4697 if (status) 4698 goto rel_out; 4699 4700 if (!return_data) 4701 goto rel_out; 4702 4703 /* Calculate length in DWORDs */ 4704 dword_len = hdr_size >> 2; 4705 4706 /* first pull in the header so we know the buffer length */ 4707 for (bi = 0; bi < dword_len; bi++) { 4708 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4709 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4710 } 4711 4712 /* 4713 * If there is any thing in data position pull it in 4714 * Read Flash command requires reading buffer length from 4715 * two byes instead of one byte 4716 */ 4717 if (resp->cmd == 0x30 || resp->cmd == 0x31) { 4718 for (; bi < dword_len + 2; bi++) { 4719 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4720 bi); 4721 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4722 } 4723 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3) 4724 & 0xF00) | resp->buf_len; 4725 hdr_size += (2 << 2); 4726 } else { 4727 buf_len = resp->buf_len; 4728 } 4729 if (!buf_len) 4730 goto rel_out; 4731 4732 if (length < buf_len + hdr_size) { 4733 DEBUGOUT("Buffer not large enough for reply message.\n"); 4734 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4735 goto rel_out; 4736 } 4737 4738 /* Calculate length in DWORDs, add 3 for odd lengths */ 4739 dword_len = (buf_len + 3) >> 2; 4740 4741 /* Pull in the rest of the buffer (bi is where we left off) */ 4742 for (; bi <= dword_len; bi++) { 4743 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4744 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4745 } 4746 4747 rel_out: 4748 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4749 4750 return status; 4751 } 4752 4753 /** 4754 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4755 * @hw: pointer to the HW structure 4756 * @maj: driver version major number 4757 * @minr: driver version minor number 4758 * @build: driver version build number 4759 * @sub: driver version sub build number 4760 * @len: unused 4761 * @driver_ver: unused 4762 * 4763 * Sends driver version number to firmware through the manageability 4764 * block. On success return IXGBE_SUCCESS 4765 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4766 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4767 **/ 4768 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 minr, 4769 u8 build, u8 sub, u16 len, 4770 const char *driver_ver) 4771 { 4772 struct ixgbe_hic_drv_info fw_cmd; 4773 int i; 4774 s32 ret_val = IXGBE_SUCCESS; 4775 4776 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4777 UNREFERENCED_2PARAMETER(len, driver_ver); 4778 4779 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4780 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4781 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4782 fw_cmd.port_num = (u8)hw->bus.func; 4783 fw_cmd.ver_maj = maj; 4784 fw_cmd.ver_min = minr; 4785 fw_cmd.ver_build = build; 4786 fw_cmd.ver_sub = sub; 4787 fw_cmd.hdr.checksum = 0; 4788 fw_cmd.pad = 0; 4789 fw_cmd.pad2 = 0; 4790 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4791 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4792 4793 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4794 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4795 sizeof(fw_cmd), 4796 IXGBE_HI_COMMAND_TIMEOUT, 4797 TRUE); 4798 if (ret_val != IXGBE_SUCCESS) 4799 continue; 4800 4801 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4802 FW_CEM_RESP_STATUS_SUCCESS) 4803 ret_val = IXGBE_SUCCESS; 4804 else 4805 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4806 4807 break; 4808 } 4809 4810 return ret_val; 4811 } 4812 4813 /** 4814 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4815 * @hw: pointer to hardware structure 4816 * @num_pb: number of packet buffers to allocate 4817 * @headroom: reserve n KB of headroom 4818 * @strategy: packet buffer allocation strategy 4819 **/ 4820 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4821 int strategy) 4822 { 4823 u32 pbsize = hw->mac.rx_pb_size; 4824 int i = 0; 4825 u32 rxpktsize, txpktsize, txpbthresh; 4826 4827 /* Reserve headroom */ 4828 pbsize -= headroom; 4829 4830 if (!num_pb) 4831 num_pb = 1; 4832 4833 /* Divide remaining packet buffer space amongst the number of packet 4834 * buffers requested using supplied strategy. 4835 */ 4836 switch (strategy) { 4837 case PBA_STRATEGY_WEIGHTED: 4838 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4839 * buffer with 5/8 of the packet buffer space. 4840 */ 4841 rxpktsize = (pbsize * 5) / (num_pb * 4); 4842 pbsize -= rxpktsize * (num_pb / 2); 4843 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4844 for (; i < (num_pb / 2); i++) 4845 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4846 /* fall through - configure remaining packet buffers */ 4847 case PBA_STRATEGY_EQUAL: 4848 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4849 for (; i < num_pb; i++) 4850 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4851 break; 4852 default: 4853 break; 4854 } 4855 4856 /* Only support an equally distributed Tx packet buffer strategy. */ 4857 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4858 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4859 for (i = 0; i < num_pb; i++) { 4860 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4861 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4862 } 4863 4864 /* Clear unused TCs, if any, to zero buffer size*/ 4865 for (; i < IXGBE_MAX_PB; i++) { 4866 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4867 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4868 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4869 } 4870 } 4871 4872 /** 4873 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4874 * @hw: pointer to the hardware structure 4875 * 4876 * The 82599 and x540 MACs can experience issues if TX work is still pending 4877 * when a reset occurs. This function prevents this by flushing the PCIe 4878 * buffers on the system. 4879 **/ 4880 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4881 { 4882 u32 gcr_ext, hlreg0, i, poll; 4883 u16 value; 4884 4885 /* 4886 * If double reset is not requested then all transactions should 4887 * already be clear and as such there is no work to do 4888 */ 4889 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4890 return; 4891 4892 /* 4893 * Set loopback enable to prevent any transmits from being sent 4894 * should the link come up. This assumes that the RXCTRL.RXEN bit 4895 * has already been cleared. 4896 */ 4897 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4898 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4899 4900 /* Wait for a last completion before clearing buffers */ 4901 IXGBE_WRITE_FLUSH(hw); 4902 msec_delay(3); 4903 4904 /* 4905 * Before proceeding, make sure that the PCIe block does not have 4906 * transactions pending. 4907 */ 4908 poll = ixgbe_pcie_timeout_poll(hw); 4909 for (i = 0; i < poll; i++) { 4910 usec_delay(100); 4911 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4912 if (IXGBE_REMOVED(hw->hw_addr)) 4913 goto out; 4914 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4915 goto out; 4916 } 4917 4918 out: 4919 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4920 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4921 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4922 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4923 4924 /* Flush all writes and allow 20usec for all transactions to clear */ 4925 IXGBE_WRITE_FLUSH(hw); 4926 usec_delay(20); 4927 4928 /* restore previous register values */ 4929 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4930 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4931 } 4932 4933 /** 4934 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW 4935 * 4936 * @hw: pointer to hardware structure 4937 * @cmd: Command we send to the FW 4938 * @status: The reply from the FW 4939 * 4940 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 4941 **/ 4942 #define IXGBE_BYPASS_BB_WAIT 1 4943 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) 4944 { 4945 int i; 4946 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; 4947 u32 esdp; 4948 4949 if (!status) 4950 return IXGBE_ERR_PARAM; 4951 4952 *status = 0; 4953 4954 /* SDP vary by MAC type */ 4955 switch (hw->mac.type) { 4956 case ixgbe_mac_82599EB: 4957 sck = IXGBE_ESDP_SDP7; 4958 sdi = IXGBE_ESDP_SDP0; 4959 sdo = IXGBE_ESDP_SDP6; 4960 dir_sck = IXGBE_ESDP_SDP7_DIR; 4961 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4962 dir_sdo = IXGBE_ESDP_SDP6_DIR; 4963 break; 4964 case ixgbe_mac_X540: 4965 sck = IXGBE_ESDP_SDP2; 4966 sdi = IXGBE_ESDP_SDP0; 4967 sdo = IXGBE_ESDP_SDP1; 4968 dir_sck = IXGBE_ESDP_SDP2_DIR; 4969 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4970 dir_sdo = IXGBE_ESDP_SDP1_DIR; 4971 break; 4972 default: 4973 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 4974 } 4975 4976 /* Set SDP pins direction */ 4977 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4978 esdp |= dir_sck; /* SCK as output */ 4979 esdp |= dir_sdi; /* SDI as output */ 4980 esdp &= ~dir_sdo; /* SDO as input */ 4981 esdp |= sck; 4982 esdp |= sdi; 4983 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4984 IXGBE_WRITE_FLUSH(hw); 4985 msec_delay(IXGBE_BYPASS_BB_WAIT); 4986 4987 /* Generate start condition */ 4988 esdp &= ~sdi; 4989 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4990 IXGBE_WRITE_FLUSH(hw); 4991 msec_delay(IXGBE_BYPASS_BB_WAIT); 4992 4993 esdp &= ~sck; 4994 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4995 IXGBE_WRITE_FLUSH(hw); 4996 msec_delay(IXGBE_BYPASS_BB_WAIT); 4997 4998 /* Clock out the new control word and clock in the status */ 4999 for (i = 0; i < 32; i++) { 5000 if ((cmd >> (31 - i)) & 0x01) { 5001 esdp |= sdi; 5002 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5003 } else { 5004 esdp &= ~sdi; 5005 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5006 } 5007 IXGBE_WRITE_FLUSH(hw); 5008 msec_delay(IXGBE_BYPASS_BB_WAIT); 5009 5010 esdp |= sck; 5011 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5012 IXGBE_WRITE_FLUSH(hw); 5013 msec_delay(IXGBE_BYPASS_BB_WAIT); 5014 5015 esdp &= ~sck; 5016 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5017 IXGBE_WRITE_FLUSH(hw); 5018 msec_delay(IXGBE_BYPASS_BB_WAIT); 5019 5020 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5021 if (esdp & sdo) 5022 *status = (*status << 1) | 0x01; 5023 else 5024 *status = (*status << 1) | 0x00; 5025 msec_delay(IXGBE_BYPASS_BB_WAIT); 5026 } 5027 5028 /* stop condition */ 5029 esdp |= sck; 5030 esdp &= ~sdi; 5031 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5032 IXGBE_WRITE_FLUSH(hw); 5033 msec_delay(IXGBE_BYPASS_BB_WAIT); 5034 5035 esdp |= sdi; 5036 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5037 IXGBE_WRITE_FLUSH(hw); 5038 5039 /* set the page bits to match the cmd that the status it belongs to */ 5040 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); 5041 5042 return IXGBE_SUCCESS; 5043 } 5044 5045 /** 5046 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. 5047 * 5048 * If we send a write we can't be sure it took until we can read back 5049 * that same register. It can be a problem as some of the feilds may 5050 * for valid reasons change inbetween the time wrote the register and 5051 * we read it again to verify. So this function check everything we 5052 * can check and then assumes it worked. 5053 * 5054 * @u32 in_reg - The register cmd for the bit-bang read. 5055 * @u32 out_reg - The register returned from a bit-bang read. 5056 **/ 5057 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) 5058 { 5059 u32 mask; 5060 5061 /* Page must match for all control pages */ 5062 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) 5063 return FALSE; 5064 5065 switch (in_reg & BYPASS_PAGE_M) { 5066 case BYPASS_PAGE_CTL0: 5067 /* All the following can't change since the last write 5068 * - All the event actions 5069 * - The timeout value 5070 */ 5071 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | 5072 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | 5073 BYPASS_WDTIMEOUT_M | 5074 BYPASS_WDT_VALUE_M; 5075 if ((out_reg & mask) != (in_reg & mask)) 5076 return FALSE; 5077 5078 /* 0x0 is never a valid value for bypass status */ 5079 if (!(out_reg & BYPASS_STATUS_OFF_M)) 5080 return FALSE; 5081 break; 5082 case BYPASS_PAGE_CTL1: 5083 /* All the following can't change since the last write 5084 * - time valid bit 5085 * - time we last sent 5086 */ 5087 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; 5088 if ((out_reg & mask) != (in_reg & mask)) 5089 return FALSE; 5090 break; 5091 case BYPASS_PAGE_CTL2: 5092 /* All we can check in this page is control number 5093 * which is already done above. 5094 */ 5095 break; 5096 } 5097 5098 /* We are as sure as we can be return TRUE */ 5099 return TRUE; 5100 } 5101 5102 /** 5103 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter. 5104 * 5105 * @hw: pointer to hardware structure 5106 * @cmd: The control word we are setting. 5107 * @event: The event we are setting in the FW. This also happens to 5108 * be the mask for the event we are setting (handy) 5109 * @action: The action we set the event to in the FW. This is in a 5110 * bit field that happens to be what we want to put in 5111 * the event spot (also handy) 5112 **/ 5113 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 5114 u32 action) 5115 { 5116 u32 by_ctl = 0; 5117 u32 cmd, verify; 5118 u32 count = 0; 5119 5120 /* Get current values */ 5121 cmd = ctrl; /* just reading only need control number */ 5122 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5123 return IXGBE_ERR_INVALID_ARGUMENT; 5124 5125 /* Set to new action */ 5126 cmd = (by_ctl & ~event) | BYPASS_WE | action; 5127 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5128 return IXGBE_ERR_INVALID_ARGUMENT; 5129 5130 /* Page 0 force a FW eeprom write which is slow so verify */ 5131 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { 5132 verify = BYPASS_PAGE_CTL0; 5133 do { 5134 if (count++ > 5) 5135 return IXGBE_BYPASS_FW_WRITE_FAILURE; 5136 5137 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) 5138 return IXGBE_ERR_INVALID_ARGUMENT; 5139 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); 5140 } else { 5141 /* We have give the FW time for the write to stick */ 5142 msec_delay(100); 5143 } 5144 5145 return IXGBE_SUCCESS; 5146 } 5147 5148 /** 5149 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres. 5150 * 5151 * @hw: pointer to hardware structure 5152 * @addr: The bypass eeprom address to read. 5153 * @value: The 8b of data at the address above. 5154 **/ 5155 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) 5156 { 5157 u32 cmd; 5158 u32 status; 5159 5160 5161 /* send the request */ 5162 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; 5163 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; 5164 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5165 return IXGBE_ERR_INVALID_ARGUMENT; 5166 5167 /* We have give the FW time for the write to stick */ 5168 msec_delay(100); 5169 5170 /* now read the results */ 5171 cmd &= ~BYPASS_WE; 5172 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5173 return IXGBE_ERR_INVALID_ARGUMENT; 5174 5175 *value = status & BYPASS_CTL2_DATA_M; 5176 5177 return IXGBE_SUCCESS; 5178 } 5179 5180 /** 5181 * ixgbe_get_orom_version - Return option ROM from EEPROM 5182 * 5183 * @hw: pointer to hardware structure 5184 * @nvm_ver: pointer to output structure 5185 * 5186 * if valid option ROM version, nvm_ver->or_valid set to TRUE 5187 * else nvm_ver->or_valid is FALSE. 5188 **/ 5189 void ixgbe_get_orom_version(struct ixgbe_hw *hw, 5190 struct ixgbe_nvm_version *nvm_ver) 5191 { 5192 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 5193 5194 nvm_ver->or_valid = FALSE; 5195 /* Option Rom may or may not be present. Start with pointer */ 5196 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 5197 5198 /* make sure offset is valid */ 5199 if ((offset == 0x0) || (offset == NVM_INVALID_PTR)) 5200 return; 5201 5202 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 5203 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 5204 5205 /* option rom exists and is valid */ 5206 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 5207 eeprom_cfg_blkl == NVM_VER_INVALID || 5208 eeprom_cfg_blkh == NVM_VER_INVALID) 5209 return; 5210 5211 nvm_ver->or_valid = TRUE; 5212 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 5213 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 5214 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 5215 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 5216 } 5217 5218 /** 5219 * ixgbe_get_oem_prod_version - Return OEM Product version 5220 * 5221 * @hw: pointer to hardware structure 5222 * @nvm_ver: pointer to output structure 5223 * 5224 * if valid OEM product version, nvm_ver->oem_valid set to TRUE 5225 * else nvm_ver->oem_valid is FALSE. 5226 **/ 5227 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 5228 struct ixgbe_nvm_version *nvm_ver) 5229 { 5230 u16 rel_num, prod_ver, mod_len, cap, offset; 5231 5232 nvm_ver->oem_valid = FALSE; 5233 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 5234 5235 /* Return is offset to OEM Product Version block is invalid */ 5236 if (offset == 0x0 || offset == NVM_INVALID_PTR) 5237 return; 5238 5239 /* Read product version block */ 5240 hw->eeprom.ops.read(hw, offset, &mod_len); 5241 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 5242 5243 /* Return if OEM product version block is invalid */ 5244 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 5245 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 5246 return; 5247 5248 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 5249 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 5250 5251 /* Return if version is invalid */ 5252 if ((rel_num | prod_ver) == 0x0 || 5253 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 5254 return; 5255 5256 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 5257 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 5258 nvm_ver->oem_release = rel_num; 5259 nvm_ver->oem_valid = TRUE; 5260 } 5261 5262 /** 5263 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 5264 * 5265 * @hw: pointer to hardware structure 5266 * @nvm_ver: pointer to output structure 5267 * 5268 * word read errors will return 0xFFFF 5269 **/ 5270 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) 5271 { 5272 u16 etk_id_l, etk_id_h; 5273 5274 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 5275 etk_id_l = NVM_VER_INVALID; 5276 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 5277 etk_id_h = NVM_VER_INVALID; 5278 5279 /* The word order for the version format is determined by high order 5280 * word bit 15. 5281 */ 5282 if ((etk_id_h & NVM_ETK_VALID) == 0) { 5283 nvm_ver->etk_id = etk_id_h; 5284 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); 5285 } else { 5286 nvm_ver->etk_id = etk_id_l; 5287 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); 5288 } 5289 } 5290 5291 5292 /** 5293 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5294 * @hw: pointer to hardware structure 5295 * @map: pointer to u8 arr for returning map 5296 * 5297 * Read the rtrup2tc HW register and resolve its content into map 5298 **/ 5299 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5300 { 5301 u32 reg, i; 5302 5303 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 5304 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 5305 map[i] = IXGBE_RTRUP2TC_UP_MASK & 5306 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 5307 return; 5308 } 5309 5310 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 5311 { 5312 u32 pfdtxgswc; 5313 u32 rxctrl; 5314 5315 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5316 if (rxctrl & IXGBE_RXCTRL_RXEN) { 5317 if (hw->mac.type != ixgbe_mac_82598EB) { 5318 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5319 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 5320 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 5321 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5322 hw->mac.set_lben = TRUE; 5323 } else { 5324 hw->mac.set_lben = FALSE; 5325 } 5326 } 5327 rxctrl &= ~IXGBE_RXCTRL_RXEN; 5328 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 5329 } 5330 } 5331 5332 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 5333 { 5334 u32 pfdtxgswc; 5335 u32 rxctrl; 5336 5337 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5338 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 5339 5340 if (hw->mac.type != ixgbe_mac_82598EB) { 5341 if (hw->mac.set_lben) { 5342 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5343 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 5344 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5345 hw->mac.set_lben = FALSE; 5346 } 5347 } 5348 } 5349 5350 /** 5351 * ixgbe_mng_present - returns TRUE when management capability is present 5352 * @hw: pointer to hardware structure 5353 */ 5354 bool ixgbe_mng_present(struct ixgbe_hw *hw) 5355 { 5356 u32 fwsm; 5357 5358 if (hw->mac.type < ixgbe_mac_82599EB) 5359 return FALSE; 5360 5361 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5362 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 5363 } 5364 5365 /** 5366 * ixgbe_mng_enabled - Is the manageability engine enabled? 5367 * @hw: pointer to hardware structure 5368 * 5369 * Returns TRUE if the manageability engine is enabled. 5370 **/ 5371 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 5372 { 5373 u32 fwsm, manc, factps; 5374 5375 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5376 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 5377 return FALSE; 5378 5379 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 5380 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 5381 return FALSE; 5382 5383 if (hw->mac.type <= ixgbe_mac_X540) { 5384 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 5385 if (factps & IXGBE_FACTPS_MNGCG) 5386 return FALSE; 5387 } 5388 5389 return TRUE; 5390 } 5391 5392 /** 5393 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 5394 * @hw: pointer to hardware structure 5395 * @speed: new link speed 5396 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 5397 * 5398 * Set the link speed in the MAC and/or PHY register and restarts link. 5399 **/ 5400 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 5401 ixgbe_link_speed speed, 5402 bool autoneg_wait_to_complete) 5403 { 5404 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5405 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5406 s32 status = IXGBE_SUCCESS; 5407 u32 speedcnt = 0; 5408 u32 i = 0; 5409 bool autoneg, link_up = FALSE; 5410 5411 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 5412 5413 /* Mask off requested but non-supported speeds */ 5414 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 5415 if (status != IXGBE_SUCCESS) 5416 return status; 5417 5418 speed &= link_speed; 5419 5420 /* Try each speed one by one, highest priority first. We do this in 5421 * software because 10Gb fiber doesn't support speed autonegotiation. 5422 */ 5423 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5424 speedcnt++; 5425 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5426 5427 /* Set the module link speed */ 5428 switch (hw->phy.media_type) { 5429 case ixgbe_media_type_fiber_fixed: 5430 case ixgbe_media_type_fiber: 5431 ixgbe_set_rate_select_speed(hw, 5432 IXGBE_LINK_SPEED_10GB_FULL); 5433 break; 5434 case ixgbe_media_type_fiber_qsfp: 5435 /* QSFP module automatically detects MAC link speed */ 5436 break; 5437 default: 5438 DEBUGOUT("Unexpected media type.\n"); 5439 break; 5440 } 5441 5442 /* Allow module to change analog characteristics (1G->10G) */ 5443 msec_delay(40); 5444 5445 status = ixgbe_setup_mac_link(hw, 5446 IXGBE_LINK_SPEED_10GB_FULL, 5447 autoneg_wait_to_complete); 5448 if (status != IXGBE_SUCCESS) 5449 return status; 5450 5451 /* Flap the Tx laser if it has not already been done */ 5452 ixgbe_flap_tx_laser(hw); 5453 5454 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 5455 * Section 73.10.2, we may have to wait up to 500ms if KR is 5456 * attempted. 82599 uses the same timing for 10g SFI. 5457 */ 5458 for (i = 0; i < 5; i++) { 5459 /* Wait for the link partner to also set speed */ 5460 msec_delay(100); 5461 5462 /* If we have link, just jump out */ 5463 status = ixgbe_check_link(hw, &link_speed, 5464 &link_up, FALSE); 5465 if (status != IXGBE_SUCCESS) 5466 return status; 5467 5468 if (link_up) 5469 goto out; 5470 } 5471 } 5472 5473 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5474 speedcnt++; 5475 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5476 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5477 5478 /* Set the module link speed */ 5479 switch (hw->phy.media_type) { 5480 case ixgbe_media_type_fiber_fixed: 5481 case ixgbe_media_type_fiber: 5482 ixgbe_set_rate_select_speed(hw, 5483 IXGBE_LINK_SPEED_1GB_FULL); 5484 break; 5485 case ixgbe_media_type_fiber_qsfp: 5486 /* QSFP module automatically detects link speed */ 5487 break; 5488 default: 5489 DEBUGOUT("Unexpected media type.\n"); 5490 break; 5491 } 5492 5493 /* Allow module to change analog characteristics (10G->1G) */ 5494 msec_delay(40); 5495 5496 status = ixgbe_setup_mac_link(hw, 5497 IXGBE_LINK_SPEED_1GB_FULL, 5498 autoneg_wait_to_complete); 5499 if (status != IXGBE_SUCCESS) 5500 return status; 5501 5502 /* Flap the Tx laser if it has not already been done */ 5503 ixgbe_flap_tx_laser(hw); 5504 5505 /* Wait for the link partner to also set speed */ 5506 msec_delay(100); 5507 5508 /* If we have link, just jump out */ 5509 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 5510 if (status != IXGBE_SUCCESS) 5511 return status; 5512 5513 if (link_up) 5514 goto out; 5515 } 5516 5517 if (speed == 0) { 5518 /* Disable the Tx laser for media none */ 5519 ixgbe_disable_tx_laser(hw); 5520 5521 goto out; 5522 } 5523 5524 /* We didn't get link. Configure back to the highest speed we tried, 5525 * (if there was more than one). We call ourselves back with just the 5526 * single highest speed that the user requested. 5527 */ 5528 if (speedcnt > 1) 5529 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 5530 highest_link_speed, 5531 autoneg_wait_to_complete); 5532 5533 out: 5534 /* Set autoneg_advertised value based on input link speed */ 5535 hw->phy.autoneg_advertised = 0; 5536 5537 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 5538 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 5539 5540 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 5541 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 5542 5543 return status; 5544 } 5545 5546 /** 5547 * ixgbe_set_soft_rate_select_speed - Set module link speed 5548 * @hw: pointer to hardware structure 5549 * @speed: link speed to set 5550 * 5551 * Set module link speed via the soft rate select. 5552 */ 5553 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 5554 ixgbe_link_speed speed) 5555 { 5556 s32 status; 5557 u8 rs, eeprom_data; 5558 5559 switch (speed) { 5560 case IXGBE_LINK_SPEED_10GB_FULL: 5561 /* one bit mask same as setting on */ 5562 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 5563 break; 5564 case IXGBE_LINK_SPEED_1GB_FULL: 5565 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 5566 break; 5567 default: 5568 DEBUGOUT("Invalid fixed module speed\n"); 5569 return; 5570 } 5571 5572 /* Set RS0 */ 5573 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5574 IXGBE_I2C_EEPROM_DEV_ADDR2, 5575 &eeprom_data); 5576 if (status) { 5577 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 5578 goto out; 5579 } 5580 5581 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5582 5583 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5584 IXGBE_I2C_EEPROM_DEV_ADDR2, 5585 eeprom_data); 5586 if (status) { 5587 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 5588 goto out; 5589 } 5590 5591 /* Set RS1 */ 5592 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5593 IXGBE_I2C_EEPROM_DEV_ADDR2, 5594 &eeprom_data); 5595 if (status) { 5596 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 5597 goto out; 5598 } 5599 5600 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5601 5602 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5603 IXGBE_I2C_EEPROM_DEV_ADDR2, 5604 eeprom_data); 5605 if (status) { 5606 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 5607 goto out; 5608 } 5609 out: 5610 return; 5611 } 5612
Indexes created Fri Sep 26 08:10:20 GMT 2025