ixgbe_common.c revision 1.37
1 /* $NetBSD: ixgbe_common.c,v 1.37 2021/12/10 11:25:22 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ixgbe_common.c,v 1.37 2021/12/10 11:25:22 msaitoh Exp $"); 40 41 #include "ixgbe_common.h" 42 #include "ixgbe_phy.h" 43 #include "ixgbe_dcb.h" 44 #include "ixgbe_dcb_82599.h" 45 #include "ixgbe_api.h" 46 47 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 48 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 49 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 50 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 51 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 52 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 53 u16 count); 54 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 55 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 56 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 57 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 58 59 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 60 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 61 u16 *san_mac_offset); 62 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 63 u16 words, u16 *data); 64 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 65 u16 words, u16 *data); 66 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 67 u16 offset); 68 69 /** 70 * ixgbe_init_ops_generic - Inits function ptrs 71 * @hw: pointer to the hardware structure 72 * 73 * Initialize the function pointers. 74 **/ 75 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 76 { 77 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 78 struct ixgbe_mac_info *mac = &hw->mac; 79 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 80 81 DEBUGFUNC("ixgbe_init_ops_generic"); 82 83 /* EEPROM */ 84 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 85 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 86 if (eec & IXGBE_EEC_PRES) { 87 eeprom->ops.read = ixgbe_read_eerd_generic; 88 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 89 } else { 90 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 91 eeprom->ops.read_buffer = 92 ixgbe_read_eeprom_buffer_bit_bang_generic; 93 } 94 eeprom->ops.write = ixgbe_write_eeprom_generic; 95 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 96 eeprom->ops.validate_checksum = 97 ixgbe_validate_eeprom_checksum_generic; 98 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 99 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 100 101 /* MAC */ 102 mac->ops.init_hw = ixgbe_init_hw_generic; 103 mac->ops.reset_hw = NULL; 104 mac->ops.start_hw = ixgbe_start_hw_generic; 105 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 106 mac->ops.get_media_type = NULL; 107 mac->ops.get_supported_physical_layer = NULL; 108 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 109 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 110 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 111 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 112 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 113 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 114 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 115 mac->ops.prot_autoc_read = prot_autoc_read_generic; 116 mac->ops.prot_autoc_write = prot_autoc_write_generic; 117 118 /* LEDs */ 119 mac->ops.led_on = ixgbe_led_on_generic; 120 mac->ops.led_off = ixgbe_led_off_generic; 121 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 122 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 123 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; 124 125 /* RAR, Multicast, VLAN */ 126 mac->ops.set_rar = ixgbe_set_rar_generic; 127 mac->ops.clear_rar = ixgbe_clear_rar_generic; 128 mac->ops.insert_mac_addr = NULL; 129 mac->ops.set_vmdq = NULL; 130 mac->ops.clear_vmdq = NULL; 131 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 132 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 133 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 134 mac->ops.enable_mc = ixgbe_enable_mc_generic; 135 mac->ops.disable_mc = ixgbe_disable_mc_generic; 136 mac->ops.clear_vfta = NULL; 137 mac->ops.set_vfta = NULL; 138 mac->ops.set_vlvf = NULL; 139 mac->ops.init_uta_tables = NULL; 140 mac->ops.enable_rx = ixgbe_enable_rx_generic; 141 mac->ops.disable_rx = ixgbe_disable_rx_generic; 142 mac->ops.toggle_txdctl = ixgbe_toggle_txdctl_generic; 143 144 /* Flow Control */ 145 mac->ops.fc_enable = ixgbe_fc_enable_generic; 146 mac->ops.setup_fc = ixgbe_setup_fc_generic; 147 mac->ops.fc_autoneg = ixgbe_fc_autoneg; 148 149 /* Link */ 150 mac->ops.get_link_capabilities = NULL; 151 mac->ops.setup_link = NULL; 152 mac->ops.check_link = NULL; 153 mac->ops.dmac_config = NULL; 154 mac->ops.dmac_update_tcs = NULL; 155 mac->ops.dmac_config_tcs = NULL; 156 157 return IXGBE_SUCCESS; 158 } 159 160 /** 161 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 162 * of flow control 163 * @hw: pointer to hardware structure 164 * 165 * This function returns TRUE if the device supports flow control 166 * autonegotiation, and FALSE if it does not. 167 * 168 **/ 169 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 170 { 171 bool supported = FALSE; 172 ixgbe_link_speed speed; 173 bool link_up; 174 175 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 176 177 switch (hw->phy.media_type) { 178 case ixgbe_media_type_fiber_fixed: 179 case ixgbe_media_type_fiber_qsfp: 180 case ixgbe_media_type_fiber: 181 /* flow control autoneg black list */ 182 switch (hw->device_id) { 183 case IXGBE_DEV_ID_X550EM_A_SFP: 184 case IXGBE_DEV_ID_X550EM_A_SFP_N: 185 case IXGBE_DEV_ID_X550EM_A_QSFP: 186 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 187 supported = FALSE; 188 break; 189 default: 190 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 191 /* if link is down, assume supported */ 192 if (link_up) 193 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 194 TRUE : FALSE; 195 else 196 supported = TRUE; 197 } 198 199 break; 200 case ixgbe_media_type_backplane: 201 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 202 supported = FALSE; 203 else 204 supported = TRUE; 205 break; 206 case ixgbe_media_type_copper: 207 /* only some copper devices support flow control autoneg */ 208 switch (hw->device_id) { 209 case IXGBE_DEV_ID_82599_T3_LOM: 210 case IXGBE_DEV_ID_X540T: 211 case IXGBE_DEV_ID_X540T1: 212 case IXGBE_DEV_ID_X540_BYPASS: 213 case IXGBE_DEV_ID_X550T: 214 case IXGBE_DEV_ID_X550T1: 215 case IXGBE_DEV_ID_X550EM_X_10G_T: 216 case IXGBE_DEV_ID_X550EM_A_10G_T: 217 case IXGBE_DEV_ID_X550EM_A_1G_T: 218 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 219 supported = TRUE; 220 break; 221 default: 222 supported = FALSE; 223 } 224 default: 225 break; 226 } 227 228 return supported; 229 } 230 231 /** 232 * ixgbe_setup_fc_generic - Set up flow control 233 * @hw: pointer to hardware structure 234 * 235 * Called at init time to set up flow control. 236 **/ 237 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 238 { 239 s32 ret_val = IXGBE_SUCCESS; 240 u32 reg = 0, reg_bp = 0; 241 u16 reg_cu = 0; 242 bool locked = FALSE; 243 244 DEBUGFUNC("ixgbe_setup_fc_generic"); 245 246 /* Validate the requested mode */ 247 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 248 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 249 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 250 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 251 goto out; 252 } 253 254 /* 255 * 10gig parts do not have a word in the EEPROM to determine the 256 * default flow control setting, so we explicitly set it to full. 257 */ 258 if (hw->fc.requested_mode == ixgbe_fc_default) 259 hw->fc.requested_mode = ixgbe_fc_full; 260 261 /* 262 * Set up the 1G and 10G flow control advertisement registers so the 263 * HW will be able to do fc autoneg once the cable is plugged in. If 264 * we link at 10G, the 1G advertisement is harmless and vice versa. 265 */ 266 switch (hw->phy.media_type) { 267 case ixgbe_media_type_backplane: 268 /* some MAC's need RMW protection on AUTOC */ 269 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 270 if (ret_val != IXGBE_SUCCESS) 271 goto out; 272 273 /* fall through - only backplane uses autoc */ 274 case ixgbe_media_type_fiber_fixed: 275 case ixgbe_media_type_fiber_qsfp: 276 case ixgbe_media_type_fiber: 277 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 278 279 break; 280 case ixgbe_media_type_copper: 281 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 282 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 283 break; 284 default: 285 break; 286 } 287 288 /* 289 * The possible values of fc.requested_mode are: 290 * 0: Flow control is completely disabled 291 * 1: Rx flow control is enabled (we can receive pause frames, 292 * but not send pause frames). 293 * 2: Tx flow control is enabled (we can send pause frames but 294 * we do not support receiving pause frames). 295 * 3: Both Rx and Tx flow control (symmetric) are enabled. 296 * other: Invalid. 297 */ 298 switch (hw->fc.requested_mode) { 299 case ixgbe_fc_none: 300 /* Flow control completely disabled by software override. */ 301 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 302 if (hw->phy.media_type == ixgbe_media_type_backplane) 303 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 304 IXGBE_AUTOC_ASM_PAUSE); 305 else if (hw->phy.media_type == ixgbe_media_type_copper) 306 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 307 break; 308 case ixgbe_fc_tx_pause: 309 /* 310 * Tx Flow control is enabled, and Rx Flow control is 311 * disabled by software override. 312 */ 313 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 314 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 315 if (hw->phy.media_type == ixgbe_media_type_backplane) { 316 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 317 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 318 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 319 reg_cu |= IXGBE_TAF_ASM_PAUSE; 320 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 321 } 322 break; 323 case ixgbe_fc_rx_pause: 324 /* 325 * Rx Flow control is enabled and Tx Flow control is 326 * disabled by software override. Since there really 327 * isn't a way to advertise that we are capable of RX 328 * Pause ONLY, we will advertise that we support both 329 * symmetric and asymmetric Rx PAUSE, as such we fall 330 * through to the fc_full statement. Later, we will 331 * disable the adapter's ability to send PAUSE frames. 332 */ 333 case ixgbe_fc_full: 334 /* Flow control (both Rx and Tx) is enabled by SW override. */ 335 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 336 if (hw->phy.media_type == ixgbe_media_type_backplane) 337 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 338 IXGBE_AUTOC_ASM_PAUSE; 339 else if (hw->phy.media_type == ixgbe_media_type_copper) 340 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 341 break; 342 default: 343 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 344 "Flow control param set incorrectly\n"); 345 ret_val = IXGBE_ERR_CONFIG; 346 goto out; 347 break; 348 } 349 350 if (hw->mac.type < ixgbe_mac_X540) { 351 /* 352 * Enable auto-negotiation between the MAC & PHY; 353 * the MAC will advertise clause 37 flow control. 354 */ 355 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 356 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 357 358 /* Disable AN timeout */ 359 if (hw->fc.strict_ieee) 360 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 361 362 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 363 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 364 } 365 366 /* 367 * AUTOC restart handles negotiation of 1G and 10G on backplane 368 * and copper. There is no need to set the PCS1GCTL register. 369 * 370 */ 371 if (hw->phy.media_type == ixgbe_media_type_backplane) { 372 reg_bp |= IXGBE_AUTOC_AN_RESTART; 373 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 374 if (ret_val) 375 goto out; 376 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 377 (ixgbe_device_supports_autoneg_fc(hw))) { 378 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 379 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 380 } 381 382 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 383 out: 384 return ret_val; 385 } 386 387 /** 388 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 389 * @hw: pointer to hardware structure 390 * 391 * Starts the hardware by filling the bus info structure and media type, clears 392 * all on chip counters, initializes receive address registers, multicast 393 * table, VLAN filter table, calls routine to set up link and flow control 394 * settings, and leaves transmit and receive units disabled and uninitialized 395 **/ 396 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 397 { 398 s32 ret_val; 399 u32 ctrl_ext; 400 u16 device_caps; 401 402 DEBUGFUNC("ixgbe_start_hw_generic"); 403 404 /* Set the media type */ 405 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 406 407 /* PHY ops initialization must be done in reset_hw() */ 408 409 /* Clear the VLAN filter table */ 410 hw->mac.ops.clear_vfta(hw); 411 412 /* Clear statistics registers */ 413 hw->mac.ops.clear_hw_cntrs(hw); 414 415 /* Set No Snoop Disable */ 416 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 417 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 418 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 419 IXGBE_WRITE_FLUSH(hw); 420 421 /* Setup flow control */ 422 ret_val = ixgbe_setup_fc(hw); 423 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 424 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 425 return ret_val; 426 } 427 428 /* Cache bit indicating need for crosstalk fix */ 429 switch (hw->mac.type) { 430 case ixgbe_mac_82599EB: 431 case ixgbe_mac_X550EM_x: 432 case ixgbe_mac_X550EM_a: 433 hw->mac.ops.get_device_caps(hw, &device_caps); 434 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 435 hw->need_crosstalk_fix = FALSE; 436 else 437 hw->need_crosstalk_fix = TRUE; 438 break; 439 default: 440 hw->need_crosstalk_fix = FALSE; 441 break; 442 } 443 444 /* Clear adapter stopped flag */ 445 hw->adapter_stopped = FALSE; 446 447 return IXGBE_SUCCESS; 448 } 449 450 /** 451 * ixgbe_start_hw_gen2 - Init sequence for common device family 452 * @hw: pointer to hw structure 453 * 454 * Performs the init sequence common to the second generation 455 * of 10 GbE devices. 456 * Devices in the second generation: 457 * 82599 458 * X540 459 **/ 460 void ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 461 { 462 u32 i; 463 u32 regval; 464 465 DEBUGFUNC("ixgbe_start_hw_gen2"); 466 467 /* Clear the rate limiters */ 468 for (i = 0; i < hw->mac.max_tx_queues; i++) { 469 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 470 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 471 } 472 IXGBE_WRITE_FLUSH(hw); 473 474 /* Disable relaxed ordering */ 475 for (i = 0; i < hw->mac.max_tx_queues; i++) { 476 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 477 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 478 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 479 } 480 481 for (i = 0; i < hw->mac.max_rx_queues; i++) { 482 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 483 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 484 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 485 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 486 } 487 } 488 489 /** 490 * ixgbe_init_hw_generic - Generic hardware initialization 491 * @hw: pointer to hardware structure 492 * 493 * Initialize the hardware by resetting the hardware, filling the bus info 494 * structure and media type, clears all on chip counters, initializes receive 495 * address registers, multicast table, VLAN filter table, calls routine to set 496 * up link and flow control settings, and leaves transmit and receive units 497 * disabled and uninitialized 498 **/ 499 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 500 { 501 s32 status; 502 503 DEBUGFUNC("ixgbe_init_hw_generic"); 504 505 /* Reset the hardware */ 506 status = hw->mac.ops.reset_hw(hw); 507 508 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { 509 /* Start the HW */ 510 status = hw->mac.ops.start_hw(hw); 511 } 512 513 /* Initialize the LED link active for LED blink support */ 514 if (hw->mac.ops.init_led_link_act) 515 hw->mac.ops.init_led_link_act(hw); 516 517 if (status != IXGBE_SUCCESS) 518 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 519 520 return status; 521 } 522 523 /** 524 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 525 * @hw: pointer to hardware structure 526 * 527 * Clears all hardware statistics counters by reading them from the hardware 528 * Statistics counters are clear on read. 529 **/ 530 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 531 { 532 u16 i = 0; 533 534 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 535 536 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 537 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 538 IXGBE_READ_REG(hw, IXGBE_ERRBC); 539 IXGBE_READ_REG(hw, IXGBE_MSPDC); 540 if (hw->mac.type >= ixgbe_mac_X550) 541 IXGBE_READ_REG(hw, IXGBE_MBSDC); 542 for (i = 0; i < 8; i++) 543 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 544 545 IXGBE_READ_REG(hw, IXGBE_MLFC); 546 IXGBE_READ_REG(hw, IXGBE_MRFC); 547 IXGBE_READ_REG(hw, IXGBE_RLEC); 548 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 549 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 550 if (hw->mac.type >= ixgbe_mac_82599EB) { 551 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 552 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 553 } else { 554 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 555 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 556 } 557 558 for (i = 0; i < 8; i++) { 559 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 560 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 561 if (hw->mac.type >= ixgbe_mac_82599EB) { 562 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 563 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 564 } else { 565 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 566 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 567 } 568 } 569 if (hw->mac.type >= ixgbe_mac_82599EB) 570 for (i = 0; i < 8; i++) 571 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 572 IXGBE_READ_REG(hw, IXGBE_PRC64); 573 IXGBE_READ_REG(hw, IXGBE_PRC127); 574 IXGBE_READ_REG(hw, IXGBE_PRC255); 575 IXGBE_READ_REG(hw, IXGBE_PRC511); 576 IXGBE_READ_REG(hw, IXGBE_PRC1023); 577 IXGBE_READ_REG(hw, IXGBE_PRC1522); 578 IXGBE_READ_REG(hw, IXGBE_GPRC); 579 IXGBE_READ_REG(hw, IXGBE_BPRC); 580 IXGBE_READ_REG(hw, IXGBE_MPRC); 581 IXGBE_READ_REG(hw, IXGBE_GPTC); 582 IXGBE_READ_REG(hw, IXGBE_GORCL); 583 IXGBE_READ_REG(hw, IXGBE_GORCH); 584 IXGBE_READ_REG(hw, IXGBE_GOTCL); 585 IXGBE_READ_REG(hw, IXGBE_GOTCH); 586 if (hw->mac.type == ixgbe_mac_82598EB) 587 for (i = 0; i < 8; i++) 588 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 589 IXGBE_READ_REG(hw, IXGBE_RUC); 590 IXGBE_READ_REG(hw, IXGBE_RFC); 591 IXGBE_READ_REG(hw, IXGBE_ROC); 592 IXGBE_READ_REG(hw, IXGBE_RJC); 593 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 594 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 595 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 596 IXGBE_READ_REG(hw, IXGBE_TORL); 597 IXGBE_READ_REG(hw, IXGBE_TORH); 598 IXGBE_READ_REG(hw, IXGBE_TPR); 599 IXGBE_READ_REG(hw, IXGBE_TPT); 600 IXGBE_READ_REG(hw, IXGBE_PTC64); 601 IXGBE_READ_REG(hw, IXGBE_PTC127); 602 IXGBE_READ_REG(hw, IXGBE_PTC255); 603 IXGBE_READ_REG(hw, IXGBE_PTC511); 604 IXGBE_READ_REG(hw, IXGBE_PTC1023); 605 IXGBE_READ_REG(hw, IXGBE_PTC1522); 606 IXGBE_READ_REG(hw, IXGBE_MPTC); 607 IXGBE_READ_REG(hw, IXGBE_BPTC); 608 for (i = 0; i < 16; i++) { 609 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 610 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 611 if (hw->mac.type >= ixgbe_mac_82599EB) { 612 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 613 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 614 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 615 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 616 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 617 } else { 618 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 619 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 620 } 621 } 622 623 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 624 if (hw->phy.id == 0) 625 ixgbe_identify_phy(hw); 626 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 627 IXGBE_MDIO_PCS_DEV_TYPE, &i); 628 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 629 IXGBE_MDIO_PCS_DEV_TYPE, &i); 630 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 631 IXGBE_MDIO_PCS_DEV_TYPE, &i); 632 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 633 IXGBE_MDIO_PCS_DEV_TYPE, &i); 634 } 635 636 return IXGBE_SUCCESS; 637 } 638 639 /** 640 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 641 * @hw: pointer to hardware structure 642 * @pba_num: stores the part number string from the EEPROM 643 * @pba_num_size: part number string buffer length 644 * 645 * Reads the part number string from the EEPROM. 646 **/ 647 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 648 u32 pba_num_size) 649 { 650 s32 ret_val; 651 u16 data; 652 u16 pba_ptr; 653 u16 offset; 654 u16 length; 655 656 DEBUGFUNC("ixgbe_read_pba_string_generic"); 657 658 if (pba_num == NULL) { 659 DEBUGOUT("PBA string buffer was null\n"); 660 return IXGBE_ERR_INVALID_ARGUMENT; 661 } 662 663 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 664 if (ret_val) { 665 DEBUGOUT("NVM Read Error\n"); 666 return ret_val; 667 } 668 669 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 670 if (ret_val) { 671 DEBUGOUT("NVM Read Error\n"); 672 return ret_val; 673 } 674 675 /* 676 * if data is not ptr guard the PBA must be in legacy format which 677 * means pba_ptr is actually our second data word for the PBA number 678 * and we can decode it into an ascii string 679 */ 680 if (data != IXGBE_PBANUM_PTR_GUARD) { 681 DEBUGOUT("NVM PBA number is not stored as string\n"); 682 683 /* we will need 11 characters to store the PBA */ 684 if (pba_num_size < 11) { 685 DEBUGOUT("PBA string buffer too small\n"); 686 return IXGBE_ERR_NO_SPACE; 687 } 688 689 /* extract hex string from data and pba_ptr */ 690 pba_num[0] = (data >> 12) & 0xF; 691 pba_num[1] = (data >> 8) & 0xF; 692 pba_num[2] = (data >> 4) & 0xF; 693 pba_num[3] = data & 0xF; 694 pba_num[4] = (pba_ptr >> 12) & 0xF; 695 pba_num[5] = (pba_ptr >> 8) & 0xF; 696 pba_num[6] = '-'; 697 pba_num[7] = 0; 698 pba_num[8] = (pba_ptr >> 4) & 0xF; 699 pba_num[9] = pba_ptr & 0xF; 700 701 /* put a null character on the end of our string */ 702 pba_num[10] = '\0'; 703 704 /* switch all the data but the '-' to hex char */ 705 for (offset = 0; offset < 10; offset++) { 706 if (pba_num[offset] < 0xA) 707 pba_num[offset] += '0'; 708 else if (pba_num[offset] < 0x10) 709 pba_num[offset] += 'A' - 0xA; 710 } 711 712 return IXGBE_SUCCESS; 713 } 714 715 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 716 if (ret_val) { 717 DEBUGOUT("NVM Read Error\n"); 718 return ret_val; 719 } 720 721 if (length == 0xFFFF || length == 0) { 722 DEBUGOUT("NVM PBA number section invalid length\n"); 723 return IXGBE_ERR_PBA_SECTION; 724 } 725 726 /* check if pba_num buffer is big enough */ 727 if (pba_num_size < (((u32)length * 2) - 1)) { 728 DEBUGOUT("PBA string buffer too small\n"); 729 return IXGBE_ERR_NO_SPACE; 730 } 731 732 /* trim pba length from start of string */ 733 pba_ptr++; 734 length--; 735 736 for (offset = 0; offset < length; offset++) { 737 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 738 if (ret_val) { 739 DEBUGOUT("NVM Read Error\n"); 740 return ret_val; 741 } 742 pba_num[offset * 2] = (u8)(data >> 8); 743 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 744 } 745 pba_num[offset * 2] = '\0'; 746 747 return IXGBE_SUCCESS; 748 } 749 750 /** 751 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 752 * @hw: pointer to hardware structure 753 * @pba_num: stores the part number from the EEPROM 754 * 755 * Reads the part number from the EEPROM. 756 **/ 757 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 758 { 759 s32 ret_val; 760 u16 data; 761 762 DEBUGFUNC("ixgbe_read_pba_num_generic"); 763 764 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 765 if (ret_val) { 766 DEBUGOUT("NVM Read Error\n"); 767 return ret_val; 768 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 769 DEBUGOUT("NVM Not supported\n"); 770 return IXGBE_NOT_IMPLEMENTED; 771 } 772 *pba_num = (u32)(data << 16); 773 774 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 775 if (ret_val) { 776 DEBUGOUT("NVM Read Error\n"); 777 return ret_val; 778 } 779 *pba_num |= (u32)data; 780 781 return IXGBE_SUCCESS; 782 } 783 784 /** 785 * ixgbe_read_pba_raw 786 * @hw: pointer to the HW structure 787 * @eeprom_buf: optional pointer to EEPROM image 788 * @eeprom_buf_size: size of EEPROM image in words 789 * @max_pba_block_size: PBA block size limit 790 * @pba: pointer to output PBA structure 791 * 792 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 793 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 794 * 795 **/ 796 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 797 u32 eeprom_buf_size, u16 max_pba_block_size, 798 struct ixgbe_pba *pba) 799 { 800 s32 ret_val; 801 u16 pba_block_size; 802 803 if (pba == NULL) 804 return IXGBE_ERR_PARAM; 805 806 if (eeprom_buf == NULL) { 807 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 808 &pba->word[0]); 809 if (ret_val) 810 return ret_val; 811 } else { 812 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 813 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 814 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 815 } else { 816 return IXGBE_ERR_PARAM; 817 } 818 } 819 820 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 821 if (pba->pba_block == NULL) 822 return IXGBE_ERR_PARAM; 823 824 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 825 eeprom_buf_size, 826 &pba_block_size); 827 if (ret_val) 828 return ret_val; 829 830 if (pba_block_size > max_pba_block_size) 831 return IXGBE_ERR_PARAM; 832 833 if (eeprom_buf == NULL) { 834 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 835 pba_block_size, 836 pba->pba_block); 837 if (ret_val) 838 return ret_val; 839 } else { 840 if (eeprom_buf_size > (u32)(pba->word[1] + 841 pba_block_size)) { 842 memcpy(pba->pba_block, 843 &eeprom_buf[pba->word[1]], 844 pba_block_size * sizeof(u16)); 845 } else { 846 return IXGBE_ERR_PARAM; 847 } 848 } 849 } 850 851 return IXGBE_SUCCESS; 852 } 853 854 /** 855 * ixgbe_write_pba_raw 856 * @hw: pointer to the HW structure 857 * @eeprom_buf: optional pointer to EEPROM image 858 * @eeprom_buf_size: size of EEPROM image in words 859 * @pba: pointer to PBA structure 860 * 861 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 862 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 863 * 864 **/ 865 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 866 u32 eeprom_buf_size, struct ixgbe_pba *pba) 867 { 868 s32 ret_val; 869 870 if (pba == NULL) 871 return IXGBE_ERR_PARAM; 872 873 if (eeprom_buf == NULL) { 874 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 875 &pba->word[0]); 876 if (ret_val) 877 return ret_val; 878 } else { 879 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 880 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 881 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 882 } else { 883 return IXGBE_ERR_PARAM; 884 } 885 } 886 887 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 888 if (pba->pba_block == NULL) 889 return IXGBE_ERR_PARAM; 890 891 if (eeprom_buf == NULL) { 892 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 893 pba->pba_block[0], 894 pba->pba_block); 895 if (ret_val) 896 return ret_val; 897 } else { 898 if (eeprom_buf_size > (u32)(pba->word[1] + 899 pba->pba_block[0])) { 900 memcpy(&eeprom_buf[pba->word[1]], 901 pba->pba_block, 902 pba->pba_block[0] * sizeof(u16)); 903 } else { 904 return IXGBE_ERR_PARAM; 905 } 906 } 907 } 908 909 return IXGBE_SUCCESS; 910 } 911 912 /** 913 * ixgbe_get_pba_block_size 914 * @hw: pointer to the HW structure 915 * @eeprom_buf: optional pointer to EEPROM image 916 * @eeprom_buf_size: size of EEPROM image in words 917 * @pba_data_size: pointer to output variable 918 * 919 * Returns the size of the PBA block in words. Function operates on EEPROM 920 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 921 * EEPROM device. 922 * 923 **/ 924 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 925 u32 eeprom_buf_size, u16 *pba_block_size) 926 { 927 s32 ret_val; 928 u16 pba_word[2]; 929 u16 length; 930 931 DEBUGFUNC("ixgbe_get_pba_block_size"); 932 933 if (eeprom_buf == NULL) { 934 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 935 &pba_word[0]); 936 if (ret_val) 937 return ret_val; 938 } else { 939 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 940 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 941 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 942 } else { 943 return IXGBE_ERR_PARAM; 944 } 945 } 946 947 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 948 if (eeprom_buf == NULL) { 949 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 950 &length); 951 if (ret_val) 952 return ret_val; 953 } else { 954 if (eeprom_buf_size > pba_word[1]) 955 length = eeprom_buf[pba_word[1] + 0]; 956 else 957 return IXGBE_ERR_PARAM; 958 } 959 960 if (length == 0xFFFF || length == 0) 961 return IXGBE_ERR_PBA_SECTION; 962 } else { 963 /* PBA number in legacy format, there is no PBA Block. */ 964 length = 0; 965 } 966 967 if (pba_block_size != NULL) 968 *pba_block_size = length; 969 970 return IXGBE_SUCCESS; 971 } 972 973 /** 974 * ixgbe_get_mac_addr_generic - Generic get MAC address 975 * @hw: pointer to hardware structure 976 * @mac_addr: Adapter MAC address 977 * 978 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 979 * A reset of the adapter must be performed prior to calling this function 980 * in order for the MAC address to have been loaded from the EEPROM into RAR0 981 **/ 982 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 983 { 984 u32 rar_high; 985 u32 rar_low; 986 u16 i; 987 988 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 989 990 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 991 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 992 993 for (i = 0; i < 4; i++) 994 mac_addr[i] = (u8)(rar_low >> (i*8)); 995 996 for (i = 0; i < 2; i++) 997 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 998 999 return IXGBE_SUCCESS; 1000 } 1001 1002 /** 1003 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 1004 * @hw: pointer to hardware structure 1005 * @link_status: the link status returned by the PCI config space 1006 * 1007 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 1008 **/ 1009 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 1010 { 1011 struct ixgbe_mac_info *mac = &hw->mac; 1012 1013 if (hw->bus.type == ixgbe_bus_type_unknown) 1014 hw->bus.type = ixgbe_bus_type_pci_express; 1015 1016 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 1017 case IXGBE_PCI_LINK_WIDTH_1: 1018 hw->bus.width = ixgbe_bus_width_pcie_x1; 1019 break; 1020 case IXGBE_PCI_LINK_WIDTH_2: 1021 hw->bus.width = ixgbe_bus_width_pcie_x2; 1022 break; 1023 case IXGBE_PCI_LINK_WIDTH_4: 1024 hw->bus.width = ixgbe_bus_width_pcie_x4; 1025 break; 1026 case IXGBE_PCI_LINK_WIDTH_8: 1027 hw->bus.width = ixgbe_bus_width_pcie_x8; 1028 break; 1029 default: 1030 hw->bus.width = ixgbe_bus_width_unknown; 1031 break; 1032 } 1033 1034 switch (link_status & IXGBE_PCI_LINK_SPEED) { 1035 case IXGBE_PCI_LINK_SPEED_2500: 1036 hw->bus.speed = ixgbe_bus_speed_2500; 1037 break; 1038 case IXGBE_PCI_LINK_SPEED_5000: 1039 hw->bus.speed = ixgbe_bus_speed_5000; 1040 break; 1041 case IXGBE_PCI_LINK_SPEED_8000: 1042 hw->bus.speed = ixgbe_bus_speed_8000; 1043 break; 1044 default: 1045 hw->bus.speed = ixgbe_bus_speed_unknown; 1046 break; 1047 } 1048 1049 mac->ops.set_lan_id(hw); 1050 } 1051 1052 /** 1053 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1054 * @hw: pointer to hardware structure 1055 * 1056 * Gets the PCI bus info (speed, width, type) then calls helper function to 1057 * store this data within the ixgbe_hw structure. 1058 **/ 1059 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1060 { 1061 u16 link_status; 1062 1063 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1064 1065 /* Get the negotiated link width and speed from PCI config space */ 1066 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 1067 1068 ixgbe_set_pci_config_data_generic(hw, link_status); 1069 1070 return IXGBE_SUCCESS; 1071 } 1072 1073 /** 1074 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1075 * @hw: pointer to the HW structure 1076 * 1077 * Determines the LAN function id by reading memory-mapped registers and swaps 1078 * the port value if requested, and set MAC instance for devices that share 1079 * CS4227. 1080 **/ 1081 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1082 { 1083 struct ixgbe_bus_info *bus = &hw->bus; 1084 u32 reg; 1085 u16 ee_ctrl_4; 1086 1087 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1088 1089 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1090 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1091 bus->lan_id = (u8)bus->func; 1092 1093 /* check for a port swap */ 1094 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1095 if (reg & IXGBE_FACTPS_LFS) 1096 bus->func ^= 0x1; 1097 1098 /* Get MAC instance from EEPROM for configuring CS4227 */ 1099 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1100 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1101 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1102 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1103 } 1104 } 1105 1106 /** 1107 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1108 * @hw: pointer to hardware structure 1109 * 1110 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1111 * disables transmit and receive units. The adapter_stopped flag is used by 1112 * the shared code and drivers to determine if the adapter is in a stopped 1113 * state and should not touch the hardware. 1114 **/ 1115 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1116 { 1117 u32 reg_val; 1118 u16 i; 1119 1120 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1121 1122 /* 1123 * Set the adapter_stopped flag so other driver functions stop touching 1124 * the hardware 1125 */ 1126 hw->adapter_stopped = TRUE; 1127 1128 /* Disable the receive unit */ 1129 ixgbe_disable_rx(hw); 1130 1131 /* Clear interrupt mask to stop interrupts from being generated */ 1132 /* 1133 * XXX 1134 * This function is called in the state of both interrupt disabled 1135 * and interrupt enabled, e.g. 1136 * + interrupt disabled case: 1137 * - ixgbe_stop_locked() 1138 * - ixgbe_disable_intr() // interrupt disabled here 1139 * - ixgbe_stop_adapter() 1140 * - hw->mac.ops.stop_adapter() 1141 * == this function 1142 * + interrupt enabled case: 1143 * - ixgbe_local_timer1() 1144 * - ixgbe_init_locked() 1145 * - ixgbe_stop_adapter() 1146 * - hw->mac.ops.stop_adapter() 1147 * == this function 1148 * Therefore, it causes nest status breaking to nest the status 1149 * (that is, que->im_nest++) at all times. So, this function must 1150 * use ixgbe_ensure_disabled_intr() instead of ixgbe_disable_intr(). 1151 */ 1152 ixgbe_ensure_disabled_intr(hw->back); 1153 1154 /* Clear any pending interrupts, flush previous writes */ 1155 IXGBE_READ_REG(hw, IXGBE_EICR); 1156 1157 /* Disable the transmit unit. Each queue must be disabled. */ 1158 for (i = 0; i < hw->mac.max_tx_queues; i++) 1159 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1160 1161 /* Disable the receive unit by stopping each queue */ 1162 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1163 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1164 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1165 reg_val |= IXGBE_RXDCTL_SWFLSH; 1166 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1167 } 1168 1169 /* flush all queues disables */ 1170 IXGBE_WRITE_FLUSH(hw); 1171 msec_delay(2); 1172 1173 /* 1174 * Prevent the PCI-E bus from hanging by disabling PCI-E master 1175 * access and verify no pending requests 1176 */ 1177 return ixgbe_disable_pcie_master(hw); 1178 } 1179 1180 /** 1181 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1182 * @hw: pointer to hardware structure 1183 * 1184 * Store the index for the link active LED. This will be used to support 1185 * blinking the LED. 1186 **/ 1187 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1188 { 1189 struct ixgbe_mac_info *mac = &hw->mac; 1190 u32 led_reg, led_mode; 1191 u8 i; 1192 1193 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1194 1195 /* Get LED link active from the LEDCTL register */ 1196 for (i = 0; i < 4; i++) { 1197 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1198 1199 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1200 IXGBE_LED_LINK_ACTIVE) { 1201 mac->led_link_act = i; 1202 return IXGBE_SUCCESS; 1203 } 1204 } 1205 1206 /* 1207 * If LEDCTL register does not have the LED link active set, then use 1208 * known MAC defaults. 1209 */ 1210 switch (hw->mac.type) { 1211 case ixgbe_mac_X550EM_a: 1212 case ixgbe_mac_X550EM_x: 1213 mac->led_link_act = 1; 1214 break; 1215 default: 1216 mac->led_link_act = 2; 1217 } 1218 return IXGBE_SUCCESS; 1219 } 1220 1221 /** 1222 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1223 * @hw: pointer to hardware structure 1224 * @index: led number to turn on 1225 **/ 1226 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1227 { 1228 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1229 1230 DEBUGFUNC("ixgbe_led_on_generic"); 1231 1232 if (index > 3) 1233 return IXGBE_ERR_PARAM; 1234 1235 /* To turn on the LED, set mode to ON. */ 1236 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1237 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1238 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1239 IXGBE_WRITE_FLUSH(hw); 1240 1241 return IXGBE_SUCCESS; 1242 } 1243 1244 /** 1245 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1246 * @hw: pointer to hardware structure 1247 * @index: led number to turn off 1248 **/ 1249 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1250 { 1251 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1252 1253 DEBUGFUNC("ixgbe_led_off_generic"); 1254 1255 if (index > 3) 1256 return IXGBE_ERR_PARAM; 1257 1258 /* To turn off the LED, set mode to OFF. */ 1259 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1260 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1261 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1262 IXGBE_WRITE_FLUSH(hw); 1263 1264 return IXGBE_SUCCESS; 1265 } 1266 1267 /** 1268 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1269 * @hw: pointer to hardware structure 1270 * 1271 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1272 * ixgbe_hw struct in order to set up EEPROM access. 1273 **/ 1274 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1275 { 1276 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1277 u32 eec; 1278 u16 eeprom_size; 1279 1280 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1281 1282 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1283 eeprom->type = ixgbe_eeprom_none; 1284 /* Set default semaphore delay to 10ms which is a well 1285 * tested value */ 1286 eeprom->semaphore_delay = 10; 1287 /* Clear EEPROM page size, it will be initialized as needed */ 1288 eeprom->word_page_size = 0; 1289 1290 /* 1291 * Check for EEPROM present first. 1292 * If not present leave as none 1293 */ 1294 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1295 if (eec & IXGBE_EEC_PRES) { 1296 eeprom->type = ixgbe_eeprom_spi; 1297 1298 /* 1299 * SPI EEPROM is assumed here. This code would need to 1300 * change if a future EEPROM is not SPI. 1301 */ 1302 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1303 IXGBE_EEC_SIZE_SHIFT); 1304 eeprom->word_size = 1 << (eeprom_size + 1305 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1306 } 1307 1308 if (eec & IXGBE_EEC_ADDR_SIZE) 1309 eeprom->address_bits = 16; 1310 else 1311 eeprom->address_bits = 8; 1312 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1313 "%d\n", eeprom->type, eeprom->word_size, 1314 eeprom->address_bits); 1315 } 1316 1317 return IXGBE_SUCCESS; 1318 } 1319 1320 /** 1321 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1322 * @hw: pointer to hardware structure 1323 * @offset: offset within the EEPROM to write 1324 * @words: number of word(s) 1325 * @data: 16 bit word(s) to write to EEPROM 1326 * 1327 * Reads 16 bit word(s) from EEPROM through bit-bang method 1328 **/ 1329 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1330 u16 words, u16 *data) 1331 { 1332 s32 status = IXGBE_SUCCESS; 1333 u16 i, count; 1334 1335 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1336 1337 hw->eeprom.ops.init_params(hw); 1338 1339 if (words == 0) { 1340 status = IXGBE_ERR_INVALID_ARGUMENT; 1341 goto out; 1342 } 1343 1344 if (offset + words > hw->eeprom.word_size) { 1345 status = IXGBE_ERR_EEPROM; 1346 goto out; 1347 } 1348 1349 /* 1350 * The EEPROM page size cannot be queried from the chip. We do lazy 1351 * initialization. It is worth to do that when we write large buffer. 1352 */ 1353 if ((hw->eeprom.word_page_size == 0) && 1354 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1355 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1356 1357 /* 1358 * We cannot hold synchronization semaphores for too long 1359 * to avoid other entity starvation. However it is more efficient 1360 * to read in bursts than synchronizing access for each word. 1361 */ 1362 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1363 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1364 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1365 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1366 count, &data[i]); 1367 1368 if (status != IXGBE_SUCCESS) 1369 break; 1370 } 1371 1372 out: 1373 return status; 1374 } 1375 1376 /** 1377 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1378 * @hw: pointer to hardware structure 1379 * @offset: offset within the EEPROM to be written to 1380 * @words: number of word(s) 1381 * @data: 16 bit word(s) to be written to the EEPROM 1382 * 1383 * If ixgbe_eeprom_update_checksum is not called after this function, the 1384 * EEPROM will most likely contain an invalid checksum. 1385 **/ 1386 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1387 u16 words, u16 *data) 1388 { 1389 s32 status; 1390 u16 word; 1391 u16 page_size; 1392 u16 i; 1393 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1394 1395 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1396 1397 /* Prepare the EEPROM for writing */ 1398 status = ixgbe_acquire_eeprom(hw); 1399 1400 if (status == IXGBE_SUCCESS) { 1401 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1402 ixgbe_release_eeprom(hw); 1403 status = IXGBE_ERR_EEPROM; 1404 } 1405 } 1406 1407 if (status == IXGBE_SUCCESS) { 1408 for (i = 0; i < words; i++) { 1409 ixgbe_standby_eeprom(hw); 1410 1411 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1412 ixgbe_shift_out_eeprom_bits(hw, 1413 IXGBE_EEPROM_WREN_OPCODE_SPI, 1414 IXGBE_EEPROM_OPCODE_BITS); 1415 1416 ixgbe_standby_eeprom(hw); 1417 1418 /* 1419 * Some SPI eeproms use the 8th address bit embedded 1420 * in the opcode 1421 */ 1422 if ((hw->eeprom.address_bits == 8) && 1423 ((offset + i) >= 128)) 1424 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1425 1426 /* Send the Write command (8-bit opcode + addr) */ 1427 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1428 IXGBE_EEPROM_OPCODE_BITS); 1429 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1430 hw->eeprom.address_bits); 1431 1432 page_size = hw->eeprom.word_page_size; 1433 1434 /* Send the data in burst via SPI*/ 1435 do { 1436 word = data[i]; 1437 word = (word >> 8) | (word << 8); 1438 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1439 1440 if (page_size == 0) 1441 break; 1442 1443 /* do not wrap around page */ 1444 if (((offset + i) & (page_size - 1)) == 1445 (page_size - 1)) 1446 break; 1447 } while (++i < words); 1448 1449 ixgbe_standby_eeprom(hw); 1450 msec_delay(10); 1451 } 1452 /* Done with writing - release the EEPROM */ 1453 ixgbe_release_eeprom(hw); 1454 } 1455 1456 return status; 1457 } 1458 1459 /** 1460 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1461 * @hw: pointer to hardware structure 1462 * @offset: offset within the EEPROM to be written to 1463 * @data: 16 bit word to be written to the EEPROM 1464 * 1465 * If ixgbe_eeprom_update_checksum is not called after this function, the 1466 * EEPROM will most likely contain an invalid checksum. 1467 **/ 1468 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1469 { 1470 s32 status; 1471 1472 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1473 1474 hw->eeprom.ops.init_params(hw); 1475 1476 if (offset >= hw->eeprom.word_size) { 1477 status = IXGBE_ERR_EEPROM; 1478 goto out; 1479 } 1480 1481 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1482 1483 out: 1484 return status; 1485 } 1486 1487 /** 1488 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1489 * @hw: pointer to hardware structure 1490 * @offset: offset within the EEPROM to be read 1491 * @data: read 16 bit words(s) from EEPROM 1492 * @words: number of word(s) 1493 * 1494 * Reads 16 bit word(s) from EEPROM through bit-bang method 1495 **/ 1496 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1497 u16 words, u16 *data) 1498 { 1499 s32 status = IXGBE_SUCCESS; 1500 u16 i, count; 1501 1502 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1503 1504 hw->eeprom.ops.init_params(hw); 1505 1506 if (words == 0) { 1507 status = IXGBE_ERR_INVALID_ARGUMENT; 1508 goto out; 1509 } 1510 1511 if (offset + words > hw->eeprom.word_size) { 1512 status = IXGBE_ERR_EEPROM; 1513 goto out; 1514 } 1515 1516 /* 1517 * We cannot hold synchronization semaphores for too long 1518 * to avoid other entity starvation. However it is more efficient 1519 * to read in bursts than synchronizing access for each word. 1520 */ 1521 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1522 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1523 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1524 1525 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1526 count, &data[i]); 1527 1528 if (status != IXGBE_SUCCESS) 1529 break; 1530 } 1531 1532 out: 1533 return status; 1534 } 1535 1536 /** 1537 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1538 * @hw: pointer to hardware structure 1539 * @offset: offset within the EEPROM to be read 1540 * @words: number of word(s) 1541 * @data: read 16 bit word(s) from EEPROM 1542 * 1543 * Reads 16 bit word(s) from EEPROM through bit-bang method 1544 **/ 1545 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1546 u16 words, u16 *data) 1547 { 1548 s32 status; 1549 u16 word_in; 1550 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1551 u16 i; 1552 1553 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1554 1555 /* Prepare the EEPROM for reading */ 1556 status = ixgbe_acquire_eeprom(hw); 1557 1558 if (status == IXGBE_SUCCESS) { 1559 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1560 ixgbe_release_eeprom(hw); 1561 status = IXGBE_ERR_EEPROM; 1562 } 1563 } 1564 1565 if (status == IXGBE_SUCCESS) { 1566 for (i = 0; i < words; i++) { 1567 ixgbe_standby_eeprom(hw); 1568 /* 1569 * Some SPI eeproms use the 8th address bit embedded 1570 * in the opcode 1571 */ 1572 if ((hw->eeprom.address_bits == 8) && 1573 ((offset + i) >= 128)) 1574 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1575 1576 /* Send the READ command (opcode + addr) */ 1577 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1578 IXGBE_EEPROM_OPCODE_BITS); 1579 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1580 hw->eeprom.address_bits); 1581 1582 /* Read the data. */ 1583 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1584 data[i] = (word_in >> 8) | (word_in << 8); 1585 } 1586 1587 /* End this read operation */ 1588 ixgbe_release_eeprom(hw); 1589 } 1590 1591 return status; 1592 } 1593 1594 /** 1595 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1596 * @hw: pointer to hardware structure 1597 * @offset: offset within the EEPROM to be read 1598 * @data: read 16 bit value from EEPROM 1599 * 1600 * Reads 16 bit value from EEPROM through bit-bang method 1601 **/ 1602 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1603 u16 *data) 1604 { 1605 s32 status; 1606 1607 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1608 1609 hw->eeprom.ops.init_params(hw); 1610 1611 if (offset >= hw->eeprom.word_size) { 1612 status = IXGBE_ERR_EEPROM; 1613 goto out; 1614 } 1615 1616 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1617 1618 out: 1619 return status; 1620 } 1621 1622 /** 1623 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1624 * @hw: pointer to hardware structure 1625 * @offset: offset of word in the EEPROM to read 1626 * @words: number of word(s) 1627 * @data: 16 bit word(s) from the EEPROM 1628 * 1629 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1630 **/ 1631 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1632 u16 words, u16 *data) 1633 { 1634 u32 eerd; 1635 s32 status = IXGBE_SUCCESS; 1636 u32 i; 1637 1638 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1639 1640 hw->eeprom.ops.init_params(hw); 1641 1642 if (words == 0) { 1643 status = IXGBE_ERR_INVALID_ARGUMENT; 1644 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1645 goto out; 1646 } 1647 1648 if (offset >= hw->eeprom.word_size) { 1649 status = IXGBE_ERR_EEPROM; 1650 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1651 goto out; 1652 } 1653 1654 for (i = 0; i < words; i++) { 1655 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1656 IXGBE_EEPROM_RW_REG_START; 1657 1658 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1659 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1660 1661 if (status == IXGBE_SUCCESS) { 1662 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1663 IXGBE_EEPROM_RW_REG_DATA); 1664 } else { 1665 DEBUGOUT("Eeprom read timed out\n"); 1666 goto out; 1667 } 1668 } 1669 out: 1670 return status; 1671 } 1672 1673 /** 1674 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1675 * @hw: pointer to hardware structure 1676 * @offset: offset within the EEPROM to be used as a scratch pad 1677 * 1678 * Discover EEPROM page size by writing marching data at given offset. 1679 * This function is called only when we are writing a new large buffer 1680 * at given offset so the data would be overwritten anyway. 1681 **/ 1682 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1683 u16 offset) 1684 { 1685 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1686 s32 status = IXGBE_SUCCESS; 1687 u16 i; 1688 1689 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1690 1691 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1692 data[i] = i; 1693 1694 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1695 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1696 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1697 hw->eeprom.word_page_size = 0; 1698 if (status != IXGBE_SUCCESS) 1699 goto out; 1700 1701 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1702 if (status != IXGBE_SUCCESS) 1703 goto out; 1704 1705 /* 1706 * When writing in burst more than the actual page size 1707 * EEPROM address wraps around current page. 1708 */ 1709 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1710 1711 DEBUGOUT1("Detected EEPROM page size = %d words.", 1712 hw->eeprom.word_page_size); 1713 out: 1714 return status; 1715 } 1716 1717 /** 1718 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1719 * @hw: pointer to hardware structure 1720 * @offset: offset of word in the EEPROM to read 1721 * @data: word read from the EEPROM 1722 * 1723 * Reads a 16 bit word from the EEPROM using the EERD register. 1724 **/ 1725 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1726 { 1727 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1728 } 1729 1730 /** 1731 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1732 * @hw: pointer to hardware structure 1733 * @offset: offset of word in the EEPROM to write 1734 * @words: number of word(s) 1735 * @data: word(s) write to the EEPROM 1736 * 1737 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1738 **/ 1739 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1740 u16 words, u16 *data) 1741 { 1742 u32 eewr; 1743 s32 status = IXGBE_SUCCESS; 1744 u16 i; 1745 1746 DEBUGFUNC("ixgbe_write_eewr_generic"); 1747 1748 hw->eeprom.ops.init_params(hw); 1749 1750 if (words == 0) { 1751 status = IXGBE_ERR_INVALID_ARGUMENT; 1752 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1753 goto out; 1754 } 1755 1756 if (offset >= hw->eeprom.word_size) { 1757 status = IXGBE_ERR_EEPROM; 1758 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1759 goto out; 1760 } 1761 1762 for (i = 0; i < words; i++) { 1763 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1764 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1765 IXGBE_EEPROM_RW_REG_START; 1766 1767 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1768 if (status != IXGBE_SUCCESS) { 1769 DEBUGOUT("Eeprom write EEWR timed out\n"); 1770 goto out; 1771 } 1772 1773 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1774 1775 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1776 if (status != IXGBE_SUCCESS) { 1777 DEBUGOUT("Eeprom write EEWR timed out\n"); 1778 goto out; 1779 } 1780 } 1781 1782 out: 1783 return status; 1784 } 1785 1786 /** 1787 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1788 * @hw: pointer to hardware structure 1789 * @offset: offset of word in the EEPROM to write 1790 * @data: word write to the EEPROM 1791 * 1792 * Write a 16 bit word to the EEPROM using the EEWR register. 1793 **/ 1794 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1795 { 1796 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1797 } 1798 1799 /** 1800 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1801 * @hw: pointer to hardware structure 1802 * @ee_reg: EEPROM flag for polling 1803 * 1804 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1805 * read or write is done respectively. 1806 **/ 1807 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1808 { 1809 u32 i; 1810 u32 reg; 1811 s32 status = IXGBE_ERR_EEPROM; 1812 1813 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1814 1815 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1816 if (ee_reg == IXGBE_NVM_POLL_READ) 1817 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1818 else 1819 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1820 1821 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1822 status = IXGBE_SUCCESS; 1823 break; 1824 } 1825 usec_delay(5); 1826 } 1827 1828 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1829 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1830 "EEPROM read/write done polling timed out"); 1831 1832 return status; 1833 } 1834 1835 /** 1836 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1837 * @hw: pointer to hardware structure 1838 * 1839 * Prepares EEPROM for access using bit-bang method. This function should 1840 * be called before issuing a command to the EEPROM. 1841 **/ 1842 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1843 { 1844 s32 status = IXGBE_SUCCESS; 1845 u32 eec; 1846 u32 i; 1847 1848 DEBUGFUNC("ixgbe_acquire_eeprom"); 1849 1850 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1851 != IXGBE_SUCCESS) 1852 status = IXGBE_ERR_SWFW_SYNC; 1853 1854 if (status == IXGBE_SUCCESS) { 1855 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1856 1857 /* Request EEPROM Access */ 1858 eec |= IXGBE_EEC_REQ; 1859 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1860 1861 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1862 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1863 if (eec & IXGBE_EEC_GNT) 1864 break; 1865 usec_delay(5); 1866 } 1867 1868 /* Release if grant not acquired */ 1869 if (!(eec & IXGBE_EEC_GNT)) { 1870 eec &= ~IXGBE_EEC_REQ; 1871 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1872 DEBUGOUT("Could not acquire EEPROM grant\n"); 1873 1874 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1875 status = IXGBE_ERR_EEPROM; 1876 } 1877 1878 /* Setup EEPROM for Read/Write */ 1879 if (status == IXGBE_SUCCESS) { 1880 /* Clear CS and SK */ 1881 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1882 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1883 IXGBE_WRITE_FLUSH(hw); 1884 usec_delay(1); 1885 } 1886 } 1887 return status; 1888 } 1889 1890 /** 1891 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1892 * @hw: pointer to hardware structure 1893 * 1894 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1895 **/ 1896 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1897 { 1898 s32 status = IXGBE_ERR_EEPROM; 1899 u32 timeout = 2000; 1900 u32 i; 1901 u32 swsm; 1902 1903 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1904 1905 1906 /* Get SMBI software semaphore between device drivers first */ 1907 for (i = 0; i < timeout; i++) { 1908 /* 1909 * If the SMBI bit is 0 when we read it, then the bit will be 1910 * set and we have the semaphore 1911 */ 1912 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1913 if (!(swsm & IXGBE_SWSM_SMBI)) { 1914 status = IXGBE_SUCCESS; 1915 break; 1916 } 1917 usec_delay(50); 1918 } 1919 1920 if (i == timeout) { 1921 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1922 "not granted.\n"); 1923 /* 1924 * this release is particularly important because our attempts 1925 * above to get the semaphore may have succeeded, and if there 1926 * was a timeout, we should unconditionally clear the semaphore 1927 * bits to free the driver to make progress 1928 */ 1929 ixgbe_release_eeprom_semaphore(hw); 1930 1931 usec_delay(50); 1932 /* 1933 * one last try 1934 * If the SMBI bit is 0 when we read it, then the bit will be 1935 * set and we have the semaphore 1936 */ 1937 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1938 if (!(swsm & IXGBE_SWSM_SMBI)) 1939 status = IXGBE_SUCCESS; 1940 } 1941 1942 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1943 if (status == IXGBE_SUCCESS) { 1944 for (i = 0; i < timeout; i++) { 1945 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1946 1947 /* Set the SW EEPROM semaphore bit to request access */ 1948 swsm |= IXGBE_SWSM_SWESMBI; 1949 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1950 1951 /* 1952 * If we set the bit successfully then we got the 1953 * semaphore. 1954 */ 1955 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1956 if (swsm & IXGBE_SWSM_SWESMBI) 1957 break; 1958 1959 usec_delay(50); 1960 } 1961 1962 /* 1963 * Release semaphores and return error if SW EEPROM semaphore 1964 * was not granted because we don't have access to the EEPROM 1965 */ 1966 if (i >= timeout) { 1967 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1968 "SWESMBI Software EEPROM semaphore not granted.\n"); 1969 ixgbe_release_eeprom_semaphore(hw); 1970 status = IXGBE_ERR_EEPROM; 1971 } 1972 } else { 1973 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1974 "Software semaphore SMBI between device drivers " 1975 "not granted.\n"); 1976 } 1977 1978 return status; 1979 } 1980 1981 /** 1982 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1983 * @hw: pointer to hardware structure 1984 * 1985 * This function clears hardware semaphore bits. 1986 **/ 1987 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1988 { 1989 u32 swsm; 1990 1991 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1992 1993 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1994 1995 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1996 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1997 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1998 IXGBE_WRITE_FLUSH(hw); 1999 } 2000 2001 /** 2002 * ixgbe_ready_eeprom - Polls for EEPROM ready 2003 * @hw: pointer to hardware structure 2004 **/ 2005 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 2006 { 2007 s32 status = IXGBE_SUCCESS; 2008 u16 i; 2009 u8 spi_stat_reg; 2010 2011 DEBUGFUNC("ixgbe_ready_eeprom"); 2012 2013 /* 2014 * Read "Status Register" repeatedly until the LSB is cleared. The 2015 * EEPROM will signal that the command has been completed by clearing 2016 * bit 0 of the internal status register. If it's not cleared within 2017 * 5 milliseconds, then error out. 2018 */ 2019 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 2020 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 2021 IXGBE_EEPROM_OPCODE_BITS); 2022 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 2023 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 2024 break; 2025 2026 usec_delay(5); 2027 ixgbe_standby_eeprom(hw); 2028 } 2029 2030 /* 2031 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 2032 * devices (and only 0-5mSec on 5V devices) 2033 */ 2034 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 2035 DEBUGOUT("SPI EEPROM Status error\n"); 2036 status = IXGBE_ERR_EEPROM; 2037 } 2038 2039 return status; 2040 } 2041 2042 /** 2043 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 2044 * @hw: pointer to hardware structure 2045 **/ 2046 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 2047 { 2048 u32 eec; 2049 2050 DEBUGFUNC("ixgbe_standby_eeprom"); 2051 2052 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2053 2054 /* Toggle CS to flush commands */ 2055 eec |= IXGBE_EEC_CS; 2056 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2057 IXGBE_WRITE_FLUSH(hw); 2058 usec_delay(1); 2059 eec &= ~IXGBE_EEC_CS; 2060 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2061 IXGBE_WRITE_FLUSH(hw); 2062 usec_delay(1); 2063 } 2064 2065 /** 2066 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 2067 * @hw: pointer to hardware structure 2068 * @data: data to send to the EEPROM 2069 * @count: number of bits to shift out 2070 **/ 2071 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 2072 u16 count) 2073 { 2074 u32 eec; 2075 u32 mask; 2076 u32 i; 2077 2078 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 2079 2080 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2081 2082 /* 2083 * Mask is used to shift "count" bits of "data" out to the EEPROM 2084 * one bit at a time. Determine the starting bit based on count 2085 */ 2086 mask = 0x01 << (count - 1); 2087 2088 for (i = 0; i < count; i++) { 2089 /* 2090 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 2091 * "1", and then raising and then lowering the clock (the SK 2092 * bit controls the clock input to the EEPROM). A "0" is 2093 * shifted out to the EEPROM by setting "DI" to "0" and then 2094 * raising and then lowering the clock. 2095 */ 2096 if (data & mask) 2097 eec |= IXGBE_EEC_DI; 2098 else 2099 eec &= ~IXGBE_EEC_DI; 2100 2101 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2102 IXGBE_WRITE_FLUSH(hw); 2103 2104 usec_delay(1); 2105 2106 ixgbe_raise_eeprom_clk(hw, &eec); 2107 ixgbe_lower_eeprom_clk(hw, &eec); 2108 2109 /* 2110 * Shift mask to signify next bit of data to shift in to the 2111 * EEPROM 2112 */ 2113 mask = mask >> 1; 2114 } 2115 2116 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2117 eec &= ~IXGBE_EEC_DI; 2118 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2119 IXGBE_WRITE_FLUSH(hw); 2120 } 2121 2122 /** 2123 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2124 * @hw: pointer to hardware structure 2125 * @count: number of bits to shift 2126 **/ 2127 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2128 { 2129 u32 eec; 2130 u32 i; 2131 u16 data = 0; 2132 2133 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2134 2135 /* 2136 * In order to read a register from the EEPROM, we need to shift 2137 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2138 * the clock input to the EEPROM (setting the SK bit), and then reading 2139 * the value of the "DO" bit. During this "shifting in" process the 2140 * "DI" bit should always be clear. 2141 */ 2142 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2143 2144 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2145 2146 for (i = 0; i < count; i++) { 2147 data = data << 1; 2148 ixgbe_raise_eeprom_clk(hw, &eec); 2149 2150 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2151 2152 eec &= ~(IXGBE_EEC_DI); 2153 if (eec & IXGBE_EEC_DO) 2154 data |= 1; 2155 2156 ixgbe_lower_eeprom_clk(hw, &eec); 2157 } 2158 2159 return data; 2160 } 2161 2162 /** 2163 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2164 * @hw: pointer to hardware structure 2165 * @eec: EEC register's current value 2166 **/ 2167 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2168 { 2169 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2170 2171 /* 2172 * Raise the clock input to the EEPROM 2173 * (setting the SK bit), then delay 2174 */ 2175 *eec = *eec | IXGBE_EEC_SK; 2176 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2177 IXGBE_WRITE_FLUSH(hw); 2178 usec_delay(1); 2179 } 2180 2181 /** 2182 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2183 * @hw: pointer to hardware structure 2184 * @eec: EEC's current value 2185 **/ 2186 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2187 { 2188 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2189 2190 /* 2191 * Lower the clock input to the EEPROM (clearing the SK bit), then 2192 * delay 2193 */ 2194 *eec = *eec & ~IXGBE_EEC_SK; 2195 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2196 IXGBE_WRITE_FLUSH(hw); 2197 usec_delay(1); 2198 } 2199 2200 /** 2201 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2202 * @hw: pointer to hardware structure 2203 **/ 2204 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2205 { 2206 u32 eec; 2207 2208 DEBUGFUNC("ixgbe_release_eeprom"); 2209 2210 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2211 2212 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2213 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2214 2215 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2216 IXGBE_WRITE_FLUSH(hw); 2217 2218 usec_delay(1); 2219 2220 /* Stop requesting EEPROM access */ 2221 eec &= ~IXGBE_EEC_REQ; 2222 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2223 2224 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2225 2226 /* Delay before attempt to obtain semaphore again to allow FW access */ 2227 msec_delay(hw->eeprom.semaphore_delay); 2228 } 2229 2230 /** 2231 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2232 * @hw: pointer to hardware structure 2233 * 2234 * Returns a negative error code on error, or the 16-bit checksum 2235 **/ 2236 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2237 { 2238 u16 i; 2239 u16 j; 2240 u16 checksum = 0; 2241 u16 length = 0; 2242 u16 pointer = 0; 2243 u16 word = 0; 2244 2245 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2246 2247 /* Include 0x0-0x3F in the checksum */ 2248 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2249 if (hw->eeprom.ops.read(hw, i, &word)) { 2250 DEBUGOUT("EEPROM read failed\n"); 2251 return IXGBE_ERR_EEPROM; 2252 } 2253 checksum += word; 2254 } 2255 2256 /* Include all data from pointers except for the fw pointer */ 2257 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2258 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2259 DEBUGOUT("EEPROM read failed\n"); 2260 return IXGBE_ERR_EEPROM; 2261 } 2262 2263 /* If the pointer seems invalid */ 2264 if (pointer == 0xFFFF || pointer == 0) 2265 continue; 2266 2267 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2268 DEBUGOUT("EEPROM read failed\n"); 2269 return IXGBE_ERR_EEPROM; 2270 } 2271 2272 if (length == 0xFFFF || length == 0) 2273 continue; 2274 2275 for (j = pointer + 1; j <= pointer + length; j++) { 2276 if (hw->eeprom.ops.read(hw, j, &word)) { 2277 DEBUGOUT("EEPROM read failed\n"); 2278 return IXGBE_ERR_EEPROM; 2279 } 2280 checksum += word; 2281 } 2282 } 2283 2284 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2285 2286 return (s32)checksum; 2287 } 2288 2289 /** 2290 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2291 * @hw: pointer to hardware structure 2292 * @checksum_val: calculated checksum 2293 * 2294 * Performs checksum calculation and validates the EEPROM checksum. If the 2295 * caller does not need checksum_val, the value can be NULL. 2296 **/ 2297 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2298 u16 *checksum_val) 2299 { 2300 s32 status; 2301 u16 checksum; 2302 u16 read_checksum = 0; 2303 2304 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2305 2306 /* Read the first word from the EEPROM. If this times out or fails, do 2307 * not continue or we could be in for a very long wait while every 2308 * EEPROM read fails 2309 */ 2310 status = hw->eeprom.ops.read(hw, 0, &checksum); 2311 if (status) { 2312 DEBUGOUT("EEPROM read failed\n"); 2313 return status; 2314 } 2315 2316 status = hw->eeprom.ops.calc_checksum(hw); 2317 if (status < 0) 2318 return status; 2319 2320 checksum = (u16)(status & 0xffff); 2321 2322 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2323 if (status) { 2324 DEBUGOUT("EEPROM read failed\n"); 2325 return status; 2326 } 2327 2328 /* Verify read checksum from EEPROM is the same as 2329 * calculated checksum 2330 */ 2331 if (read_checksum != checksum) 2332 status = IXGBE_ERR_EEPROM_CHECKSUM; 2333 2334 /* If the user cares, return the calculated checksum */ 2335 if (checksum_val) 2336 *checksum_val = checksum; 2337 2338 return status; 2339 } 2340 2341 /** 2342 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2343 * @hw: pointer to hardware structure 2344 **/ 2345 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2346 { 2347 s32 status; 2348 u16 checksum; 2349 2350 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2351 2352 /* Read the first word from the EEPROM. If this times out or fails, do 2353 * not continue or we could be in for a very long wait while every 2354 * EEPROM read fails 2355 */ 2356 status = hw->eeprom.ops.read(hw, 0, &checksum); 2357 if (status) { 2358 DEBUGOUT("EEPROM read failed\n"); 2359 return status; 2360 } 2361 2362 status = hw->eeprom.ops.calc_checksum(hw); 2363 if (status < 0) 2364 return status; 2365 2366 checksum = (u16)(status & 0xffff); 2367 2368 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2369 2370 return status; 2371 } 2372 2373 /** 2374 * ixgbe_validate_mac_addr - Validate MAC address 2375 * @mac_addr: pointer to MAC address. 2376 * 2377 * Tests a MAC address to ensure it is a valid Individual Address. 2378 **/ 2379 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2380 { 2381 s32 status = IXGBE_SUCCESS; 2382 2383 DEBUGFUNC("ixgbe_validate_mac_addr"); 2384 2385 /* Make sure it is not a multicast address */ 2386 if (IXGBE_IS_MULTICAST(mac_addr)) { 2387 status = IXGBE_ERR_INVALID_MAC_ADDR; 2388 /* Not a broadcast address */ 2389 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2390 status = IXGBE_ERR_INVALID_MAC_ADDR; 2391 /* Reject the zero address */ 2392 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2393 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2394 status = IXGBE_ERR_INVALID_MAC_ADDR; 2395 } 2396 return status; 2397 } 2398 2399 /** 2400 * ixgbe_set_rar_generic - Set Rx address register 2401 * @hw: pointer to hardware structure 2402 * @index: Receive address register to write 2403 * @addr: Address to put into receive address register 2404 * @vmdq: VMDq "set" or "pool" index 2405 * @enable_addr: set flag that address is active 2406 * 2407 * Puts an ethernet address into a receive address register. 2408 **/ 2409 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2410 u32 enable_addr) 2411 { 2412 u32 rar_low, rar_high; 2413 u32 rar_entries = hw->mac.num_rar_entries; 2414 2415 DEBUGFUNC("ixgbe_set_rar_generic"); 2416 2417 /* Make sure we are using a valid rar index range */ 2418 if (index >= rar_entries) { 2419 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2420 "RAR index %d is out of range.\n", index); 2421 return IXGBE_ERR_INVALID_ARGUMENT; 2422 } 2423 2424 /* setup VMDq pool selection before this RAR gets enabled */ 2425 hw->mac.ops.set_vmdq(hw, index, vmdq); 2426 2427 /* 2428 * HW expects these in little endian so we reverse the byte 2429 * order from network order (big endian) to little endian 2430 */ 2431 rar_low = ((u32)addr[0] | 2432 ((u32)addr[1] << 8) | 2433 ((u32)addr[2] << 16) | 2434 ((u32)addr[3] << 24)); 2435 /* 2436 * Some parts put the VMDq setting in the extra RAH bits, 2437 * so save everything except the lower 16 bits that hold part 2438 * of the address and the address valid bit. 2439 */ 2440 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2441 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2442 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2443 2444 if (enable_addr != 0) 2445 rar_high |= IXGBE_RAH_AV; 2446 2447 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2448 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2449 2450 return IXGBE_SUCCESS; 2451 } 2452 2453 /** 2454 * ixgbe_clear_rar_generic - Remove Rx address register 2455 * @hw: pointer to hardware structure 2456 * @index: Receive address register to write 2457 * 2458 * Clears an ethernet address from a receive address register. 2459 **/ 2460 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2461 { 2462 u32 rar_high; 2463 u32 rar_entries = hw->mac.num_rar_entries; 2464 2465 DEBUGFUNC("ixgbe_clear_rar_generic"); 2466 2467 /* Make sure we are using a valid rar index range */ 2468 if (index >= rar_entries) { 2469 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2470 "RAR index %d is out of range.\n", index); 2471 return IXGBE_ERR_INVALID_ARGUMENT; 2472 } 2473 2474 /* 2475 * Some parts put the VMDq setting in the extra RAH bits, 2476 * so save everything except the lower 16 bits that hold part 2477 * of the address and the address valid bit. 2478 */ 2479 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2480 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2481 2482 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2483 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2484 2485 /* clear VMDq pool/queue selection for this RAR */ 2486 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2487 2488 return IXGBE_SUCCESS; 2489 } 2490 2491 /** 2492 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2493 * @hw: pointer to hardware structure 2494 * 2495 * Places the MAC address in receive address register 0 and clears the rest 2496 * of the receive address registers. Clears the multicast table. Assumes 2497 * the receiver is in reset when the routine is called. 2498 **/ 2499 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2500 { 2501 u32 i; 2502 u32 rar_entries = hw->mac.num_rar_entries; 2503 2504 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2505 2506 /* 2507 * If the current mac address is valid, assume it is a software override 2508 * to the permanent address. 2509 * Otherwise, use the permanent address from the eeprom. 2510 */ 2511 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2512 IXGBE_ERR_INVALID_MAC_ADDR) { 2513 /* Get the MAC address from the RAR0 for later reference */ 2514 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2515 2516 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2517 hw->mac.addr[0], hw->mac.addr[1], 2518 hw->mac.addr[2]); 2519 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2520 hw->mac.addr[4], hw->mac.addr[5]); 2521 } else { 2522 /* Setup the receive address. */ 2523 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2524 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2525 hw->mac.addr[0], hw->mac.addr[1], 2526 hw->mac.addr[2]); 2527 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2528 hw->mac.addr[4], hw->mac.addr[5]); 2529 2530 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2531 } 2532 2533 /* clear VMDq pool/queue selection for RAR 0 */ 2534 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2535 2536 hw->addr_ctrl.overflow_promisc = 0; 2537 2538 hw->addr_ctrl.rar_used_count = 1; 2539 2540 /* Zero out the other receive addresses. */ 2541 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2542 for (i = 1; i < rar_entries; i++) { 2543 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2544 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2545 } 2546 2547 /* Clear the MTA */ 2548 hw->addr_ctrl.mta_in_use = 0; 2549 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2550 2551 DEBUGOUT(" Clearing MTA\n"); 2552 for (i = 0; i < hw->mac.mcft_size; i++) 2553 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2554 2555 ixgbe_init_uta_tables(hw); 2556 2557 return IXGBE_SUCCESS; 2558 } 2559 2560 /** 2561 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2562 * @hw: pointer to hardware structure 2563 * @addr: new address 2564 * @vmdq: VMDq "set" or "pool" index 2565 * 2566 * Adds it to unused receive address register or goes into promiscuous mode. 2567 **/ 2568 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2569 { 2570 u32 rar_entries = hw->mac.num_rar_entries; 2571 u32 rar; 2572 2573 DEBUGFUNC("ixgbe_add_uc_addr"); 2574 2575 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2576 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2577 2578 /* 2579 * Place this address in the RAR if there is room, 2580 * else put the controller into promiscuous mode 2581 */ 2582 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2583 rar = hw->addr_ctrl.rar_used_count; 2584 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2585 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2586 hw->addr_ctrl.rar_used_count++; 2587 } else { 2588 hw->addr_ctrl.overflow_promisc++; 2589 } 2590 2591 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2592 } 2593 2594 /** 2595 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2596 * @hw: pointer to hardware structure 2597 * @addr_list: the list of new addresses 2598 * @addr_count: number of addresses 2599 * @next: iterator function to walk the address list 2600 * 2601 * The given list replaces any existing list. Clears the secondary addrs from 2602 * receive address registers. Uses unused receive address registers for the 2603 * first secondary addresses, and falls back to promiscuous mode as needed. 2604 * 2605 * Drivers using secondary unicast addresses must set user_set_promisc when 2606 * manually putting the device into promiscuous mode. 2607 **/ 2608 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2609 u32 addr_count, ixgbe_mc_addr_itr next) 2610 { 2611 u8 *addr; 2612 u32 i; 2613 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2614 u32 uc_addr_in_use; 2615 u32 fctrl; 2616 u32 vmdq; 2617 2618 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2619 2620 /* 2621 * Clear accounting of old secondary address list, 2622 * don't count RAR[0] 2623 */ 2624 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2625 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2626 hw->addr_ctrl.overflow_promisc = 0; 2627 2628 /* Zero out the other receive addresses */ 2629 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2630 for (i = 0; i < uc_addr_in_use; i++) { 2631 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2632 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2633 } 2634 2635 /* Add the new addresses */ 2636 for (i = 0; i < addr_count; i++) { 2637 DEBUGOUT(" Adding the secondary addresses:\n"); 2638 addr = next(hw, &addr_list, &vmdq); 2639 ixgbe_add_uc_addr(hw, addr, vmdq); 2640 } 2641 2642 if (hw->addr_ctrl.overflow_promisc) { 2643 /* enable promisc if not already in overflow or set by user */ 2644 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2645 DEBUGOUT(" Entering address overflow promisc mode\n"); 2646 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2647 fctrl |= IXGBE_FCTRL_UPE; 2648 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2649 } 2650 } else { 2651 /* only disable if set by overflow, not by user */ 2652 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2653 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2654 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2655 fctrl &= ~IXGBE_FCTRL_UPE; 2656 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2657 } 2658 } 2659 2660 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2661 return IXGBE_SUCCESS; 2662 } 2663 2664 /** 2665 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2666 * @hw: pointer to hardware structure 2667 * @mc_addr: the multicast address 2668 * 2669 * Extracts the 12 bits, from a multicast address, to determine which 2670 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2671 * incoming rx multicast addresses, to determine the bit-vector to check in 2672 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2673 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2674 * to mc_filter_type. 2675 **/ 2676 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2677 { 2678 u32 vector = 0; 2679 2680 DEBUGFUNC("ixgbe_mta_vector"); 2681 2682 switch (hw->mac.mc_filter_type) { 2683 case 0: /* use bits [47:36] of the address */ 2684 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2685 break; 2686 case 1: /* use bits [46:35] of the address */ 2687 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2688 break; 2689 case 2: /* use bits [45:34] of the address */ 2690 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2691 break; 2692 case 3: /* use bits [43:32] of the address */ 2693 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2694 break; 2695 default: /* Invalid mc_filter_type */ 2696 DEBUGOUT("MC filter type param set incorrectly\n"); 2697 ASSERT(0); 2698 break; 2699 } 2700 2701 /* vector can only be 12-bits or boundary will be exceeded */ 2702 vector &= 0xFFF; 2703 return vector; 2704 } 2705 2706 /** 2707 * ixgbe_set_mta - Set bit-vector in multicast table 2708 * @hw: pointer to hardware structure 2709 * @mc_addr: Multicast address 2710 * 2711 * Sets the bit-vector in the multicast table. 2712 **/ 2713 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2714 { 2715 u32 vector; 2716 u32 vector_bit; 2717 u32 vector_reg; 2718 2719 DEBUGFUNC("ixgbe_set_mta"); 2720 2721 hw->addr_ctrl.mta_in_use++; 2722 2723 vector = ixgbe_mta_vector(hw, mc_addr); 2724 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2725 2726 /* 2727 * The MTA is a register array of 128 32-bit registers. It is treated 2728 * like an array of 4096 bits. We want to set bit 2729 * BitArray[vector_value]. So we figure out what register the bit is 2730 * in, read it, OR in the new bit, then write back the new value. The 2731 * register is determined by the upper 7 bits of the vector value and 2732 * the bit within that register are determined by the lower 5 bits of 2733 * the value. 2734 */ 2735 vector_reg = (vector >> 5) & 0x7F; 2736 vector_bit = vector & 0x1F; 2737 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2738 } 2739 2740 /** 2741 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2742 * @hw: pointer to hardware structure 2743 * @mc_addr_list: the list of new multicast addresses 2744 * @mc_addr_count: number of addresses 2745 * @next: iterator function to walk the multicast address list 2746 * @clear: flag, when set clears the table beforehand 2747 * 2748 * When the clear flag is set, the given list replaces any existing list. 2749 * Hashes the given addresses into the multicast table. 2750 **/ 2751 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2752 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2753 bool clear) 2754 { 2755 u32 i; 2756 u32 vmdq; 2757 2758 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2759 2760 /* 2761 * Set the new number of MC addresses that we are being requested to 2762 * use. 2763 */ 2764 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2765 hw->addr_ctrl.mta_in_use = 0; 2766 2767 /* Clear mta_shadow */ 2768 if (clear) { 2769 DEBUGOUT(" Clearing MTA\n"); 2770 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2771 } 2772 2773 /* Update mta_shadow */ 2774 for (i = 0; i < mc_addr_count; i++) { 2775 DEBUGOUT(" Adding the multicast addresses:\n"); 2776 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2777 } 2778 2779 /* Enable mta */ 2780 for (i = 0; i < hw->mac.mcft_size; i++) 2781 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2782 hw->mac.mta_shadow[i]); 2783 2784 if (hw->addr_ctrl.mta_in_use > 0) 2785 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2786 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2787 2788 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2789 return IXGBE_SUCCESS; 2790 } 2791 2792 /** 2793 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2794 * @hw: pointer to hardware structure 2795 * 2796 * Enables multicast address in RAR and the use of the multicast hash table. 2797 **/ 2798 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2799 { 2800 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2801 2802 DEBUGFUNC("ixgbe_enable_mc_generic"); 2803 2804 if (a->mta_in_use > 0) 2805 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2806 hw->mac.mc_filter_type); 2807 2808 return IXGBE_SUCCESS; 2809 } 2810 2811 /** 2812 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2813 * @hw: pointer to hardware structure 2814 * 2815 * Disables multicast address in RAR and the use of the multicast hash table. 2816 **/ 2817 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2818 { 2819 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2820 2821 DEBUGFUNC("ixgbe_disable_mc_generic"); 2822 2823 if (a->mta_in_use > 0) 2824 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2825 2826 return IXGBE_SUCCESS; 2827 } 2828 2829 /** 2830 * ixgbe_fc_enable_generic - Enable flow control 2831 * @hw: pointer to hardware structure 2832 * 2833 * Enable flow control according to the current settings. 2834 **/ 2835 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2836 { 2837 s32 ret_val = IXGBE_SUCCESS; 2838 u32 mflcn_reg, fccfg_reg; 2839 u32 reg; 2840 u32 fcrtl, fcrth; 2841 int i; 2842 2843 DEBUGFUNC("ixgbe_fc_enable_generic"); 2844 2845 /* Validate the water mark configuration */ 2846 if (!hw->fc.pause_time) { 2847 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2848 goto out; 2849 } 2850 2851 /* Low water mark of zero causes XOFF floods */ 2852 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2853 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2854 hw->fc.high_water[i]) { 2855 if (!hw->fc.low_water[i] || 2856 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2857 DEBUGOUT("Invalid water mark configuration\n"); 2858 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2859 goto out; 2860 } 2861 } 2862 } 2863 2864 /* Negotiate the fc mode to use */ 2865 hw->mac.ops.fc_autoneg(hw); 2866 2867 /* Disable any previous flow control settings */ 2868 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2869 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2870 2871 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2872 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2873 2874 /* 2875 * The possible values of fc.current_mode are: 2876 * 0: Flow control is completely disabled 2877 * 1: Rx flow control is enabled (we can receive pause frames, 2878 * but not send pause frames). 2879 * 2: Tx flow control is enabled (we can send pause frames but 2880 * we do not support receiving pause frames). 2881 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2882 * other: Invalid. 2883 */ 2884 switch (hw->fc.current_mode) { 2885 case ixgbe_fc_none: 2886 /* 2887 * Flow control is disabled by software override or autoneg. 2888 * The code below will actually disable it in the HW. 2889 */ 2890 break; 2891 case ixgbe_fc_rx_pause: 2892 /* 2893 * Rx Flow control is enabled and Tx Flow control is 2894 * disabled by software override. Since there really 2895 * isn't a way to advertise that we are capable of RX 2896 * Pause ONLY, we will advertise that we support both 2897 * symmetric and asymmetric Rx PAUSE. Later, we will 2898 * disable the adapter's ability to send PAUSE frames. 2899 */ 2900 mflcn_reg |= IXGBE_MFLCN_RFCE; 2901 break; 2902 case ixgbe_fc_tx_pause: 2903 /* 2904 * Tx Flow control is enabled, and Rx Flow control is 2905 * disabled by software override. 2906 */ 2907 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2908 break; 2909 case ixgbe_fc_full: 2910 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2911 mflcn_reg |= IXGBE_MFLCN_RFCE; 2912 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2913 break; 2914 default: 2915 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2916 "Flow control param set incorrectly\n"); 2917 ret_val = IXGBE_ERR_CONFIG; 2918 goto out; 2919 break; 2920 } 2921 2922 /* Set 802.3x based flow control settings. */ 2923 mflcn_reg |= IXGBE_MFLCN_DPF; 2924 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2925 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2926 2927 2928 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2929 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2930 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2931 hw->fc.high_water[i]) { 2932 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2933 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2934 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2935 } else { 2936 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2937 /* 2938 * In order to prevent Tx hangs when the internal Tx 2939 * switch is enabled we must set the high water mark 2940 * to the Rx packet buffer size - 24KB. This allows 2941 * the Tx switch to function even under heavy Rx 2942 * workloads. 2943 */ 2944 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2945 } 2946 2947 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2948 } 2949 2950 /* Configure pause time (2 TCs per register) */ 2951 reg = (u32)hw->fc.pause_time * 0x00010001; 2952 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2953 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2954 2955 /* Configure flow control refresh threshold value */ 2956 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2957 2958 out: 2959 return ret_val; 2960 } 2961 2962 /** 2963 * ixgbe_negotiate_fc - Negotiate flow control 2964 * @hw: pointer to hardware structure 2965 * @adv_reg: flow control advertised settings 2966 * @lp_reg: link partner's flow control settings 2967 * @adv_sym: symmetric pause bit in advertisement 2968 * @adv_asm: asymmetric pause bit in advertisement 2969 * @lp_sym: symmetric pause bit in link partner advertisement 2970 * @lp_asm: asymmetric pause bit in link partner advertisement 2971 * 2972 * Find the intersection between advertised settings and link partner's 2973 * advertised settings 2974 **/ 2975 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2976 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2977 { 2978 if ((!(adv_reg)) || (!(lp_reg))) { 2979 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2980 "Local or link partner's advertised flow control " 2981 "settings are NULL. Local: %x, link partner: %x\n", 2982 adv_reg, lp_reg); 2983 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2984 } 2985 2986 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2987 /* 2988 * Now we need to check if the user selected Rx ONLY 2989 * of pause frames. In this case, we had to advertise 2990 * FULL flow control because we could not advertise RX 2991 * ONLY. Hence, we must now check to see if we need to 2992 * turn OFF the TRANSMISSION of PAUSE frames. 2993 */ 2994 if (hw->fc.requested_mode == ixgbe_fc_full) { 2995 hw->fc.current_mode = ixgbe_fc_full; 2996 DEBUGOUT("Flow Control = FULL.\n"); 2997 } else { 2998 hw->fc.current_mode = ixgbe_fc_rx_pause; 2999 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 3000 } 3001 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 3002 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 3003 hw->fc.current_mode = ixgbe_fc_tx_pause; 3004 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 3005 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 3006 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 3007 hw->fc.current_mode = ixgbe_fc_rx_pause; 3008 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 3009 } else { 3010 hw->fc.current_mode = ixgbe_fc_none; 3011 DEBUGOUT("Flow Control = NONE.\n"); 3012 } 3013 return IXGBE_SUCCESS; 3014 } 3015 3016 /** 3017 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 3018 * @hw: pointer to hardware structure 3019 * 3020 * Enable flow control according on 1 gig fiber. 3021 **/ 3022 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 3023 { 3024 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 3025 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3026 3027 /* 3028 * On multispeed fiber at 1g, bail out if 3029 * - link is up but AN did not complete, or if 3030 * - link is up and AN completed but timed out 3031 */ 3032 3033 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 3034 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 3035 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 3036 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 3037 goto out; 3038 } 3039 3040 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 3041 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 3042 3043 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 3044 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 3045 IXGBE_PCS1GANA_ASM_PAUSE, 3046 IXGBE_PCS1GANA_SYM_PAUSE, 3047 IXGBE_PCS1GANA_ASM_PAUSE); 3048 3049 out: 3050 return ret_val; 3051 } 3052 3053 /** 3054 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 3055 * @hw: pointer to hardware structure 3056 * 3057 * Enable flow control according to IEEE clause 37. 3058 **/ 3059 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 3060 { 3061 u32 links2, anlp1_reg, autoc_reg, links; 3062 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3063 3064 /* 3065 * On backplane, bail out if 3066 * - backplane autoneg was not completed, or if 3067 * - we are 82599 and link partner is not AN enabled 3068 */ 3069 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 3070 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 3071 DEBUGOUT("Auto-Negotiation did not complete\n"); 3072 goto out; 3073 } 3074 3075 if (hw->mac.type == ixgbe_mac_82599EB) { 3076 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 3077 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 3078 DEBUGOUT("Link partner is not AN enabled\n"); 3079 goto out; 3080 } 3081 } 3082 /* 3083 * Read the 10g AN autoc and LP ability registers and resolve 3084 * local flow control settings accordingly 3085 */ 3086 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3087 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 3088 3089 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 3090 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 3091 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 3092 3093 out: 3094 return ret_val; 3095 } 3096 3097 /** 3098 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 3099 * @hw: pointer to hardware structure 3100 * 3101 * Enable flow control according to IEEE clause 37. 3102 **/ 3103 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 3104 { 3105 u16 technology_ability_reg = 0; 3106 u16 lp_technology_ability_reg = 0; 3107 3108 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 3109 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3110 &technology_ability_reg); 3111 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 3112 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3113 &lp_technology_ability_reg); 3114 3115 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 3116 (u32)lp_technology_ability_reg, 3117 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 3118 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 3119 } 3120 3121 /** 3122 * ixgbe_fc_autoneg - Configure flow control 3123 * @hw: pointer to hardware structure 3124 * 3125 * Compares our advertised flow control capabilities to those advertised by 3126 * our link partner, and determines the proper flow control mode to use. 3127 **/ 3128 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3129 { 3130 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3131 ixgbe_link_speed speed; 3132 bool link_up; 3133 3134 DEBUGFUNC("ixgbe_fc_autoneg"); 3135 3136 /* 3137 * AN should have completed when the cable was plugged in. 3138 * Look for reasons to bail out. Bail out if: 3139 * - FC autoneg is disabled, or if 3140 * - link is not up. 3141 */ 3142 if (hw->fc.disable_fc_autoneg) { 3143 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 3144 "Flow control autoneg is disabled"); 3145 goto out; 3146 } 3147 3148 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3149 if (!link_up) { 3150 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3151 goto out; 3152 } 3153 3154 switch (hw->phy.media_type) { 3155 /* Autoneg flow control on fiber adapters */ 3156 case ixgbe_media_type_fiber_fixed: 3157 case ixgbe_media_type_fiber_qsfp: 3158 case ixgbe_media_type_fiber: 3159 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3160 ret_val = ixgbe_fc_autoneg_fiber(hw); 3161 break; 3162 3163 /* Autoneg flow control on backplane adapters */ 3164 case ixgbe_media_type_backplane: 3165 ret_val = ixgbe_fc_autoneg_backplane(hw); 3166 break; 3167 3168 /* Autoneg flow control on copper adapters */ 3169 case ixgbe_media_type_copper: 3170 if (ixgbe_device_supports_autoneg_fc(hw)) 3171 ret_val = ixgbe_fc_autoneg_copper(hw); 3172 break; 3173 3174 default: 3175 break; 3176 } 3177 3178 out: 3179 if (ret_val == IXGBE_SUCCESS) { 3180 hw->fc.fc_was_autonegged = TRUE; 3181 } else { 3182 hw->fc.fc_was_autonegged = FALSE; 3183 hw->fc.current_mode = hw->fc.requested_mode; 3184 } 3185 } 3186 3187 /* 3188 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3189 * @hw: pointer to hardware structure 3190 * 3191 * System-wide timeout range is encoded in PCIe Device Control2 register. 3192 * 3193 * Add 10% to specified maximum and return the number of times to poll for 3194 * completion timeout, in units of 100 microsec. Never return less than 3195 * 800 = 80 millisec. 3196 */ 3197 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3198 { 3199 s16 devctl2; 3200 u32 pollcnt; 3201 3202 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3203 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3204 3205 switch (devctl2) { 3206 case IXGBE_PCIDEVCTRL2_65_130ms: 3207 pollcnt = 1300; /* 130 millisec */ 3208 break; 3209 case IXGBE_PCIDEVCTRL2_260_520ms: 3210 pollcnt = 5200; /* 520 millisec */ 3211 break; 3212 case IXGBE_PCIDEVCTRL2_1_2s: 3213 pollcnt = 20000; /* 2 sec */ 3214 break; 3215 case IXGBE_PCIDEVCTRL2_4_8s: 3216 pollcnt = 80000; /* 8 sec */ 3217 break; 3218 case IXGBE_PCIDEVCTRL2_17_34s: 3219 pollcnt = 34000; /* 34 sec */ 3220 break; 3221 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3222 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3223 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3224 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3225 default: 3226 pollcnt = 800; /* 80 millisec minimum */ 3227 break; 3228 } 3229 3230 /* add 10% to spec maximum */ 3231 return (pollcnt * 11) / 10; 3232 } 3233 3234 /** 3235 * ixgbe_disable_pcie_master - Disable PCI-express master access 3236 * @hw: pointer to hardware structure 3237 * 3238 * Disables PCI-Express master access and verifies there are no pending 3239 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 3240 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 3241 * is returned signifying master requests disabled. 3242 **/ 3243 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 3244 { 3245 s32 status = IXGBE_SUCCESS; 3246 u32 i, poll; 3247 u16 value; 3248 3249 DEBUGFUNC("ixgbe_disable_pcie_master"); 3250 3251 /* Always set this bit to ensure any future transactions are blocked */ 3252 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3253 3254 /* Exit if master requests are blocked */ 3255 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3256 IXGBE_REMOVED(hw->hw_addr)) 3257 goto out; 3258 3259 /* Poll for master request bit to clear */ 3260 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 3261 usec_delay(100); 3262 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3263 goto out; 3264 } 3265 3266 /* 3267 * Two consecutive resets are required via CTRL.RST per datasheet 3268 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 3269 * of this need. The first reset prevents new master requests from 3270 * being issued by our device. We then must wait 1usec or more for any 3271 * remaining completions from the PCIe bus to trickle in, and then reset 3272 * again to clear out any effects they may have had on our device. 3273 */ 3274 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 3275 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3276 3277 if (hw->mac.type >= ixgbe_mac_X550) 3278 goto out; 3279 3280 /* 3281 * Before proceeding, make sure that the PCIe block does not have 3282 * transactions pending. 3283 */ 3284 poll = ixgbe_pcie_timeout_poll(hw); 3285 for (i = 0; i < poll; i++) { 3286 usec_delay(100); 3287 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3288 if (IXGBE_REMOVED(hw->hw_addr)) 3289 goto out; 3290 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3291 goto out; 3292 } 3293 3294 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3295 "PCIe transaction pending bit also did not clear.\n"); 3296 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 3297 3298 out: 3299 return status; 3300 } 3301 3302 /** 3303 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3304 * @hw: pointer to hardware structure 3305 * @mask: Mask to specify which semaphore to acquire 3306 * 3307 * Acquires the SWFW semaphore through the GSSR register for the specified 3308 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3309 **/ 3310 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3311 { 3312 u32 gssr = 0; 3313 u32 swmask = mask; 3314 u32 fwmask = mask << 5; 3315 u32 timeout = 200; 3316 u32 i; 3317 3318 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3319 3320 for (i = 0; i < timeout; i++) { 3321 /* 3322 * SW NVM semaphore bit is used for access to all 3323 * SW_FW_SYNC bits (not just NVM) 3324 */ 3325 if (ixgbe_get_eeprom_semaphore(hw)) 3326 return IXGBE_ERR_SWFW_SYNC; 3327 3328 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3329 if (!(gssr & (fwmask | swmask))) { 3330 gssr |= swmask; 3331 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3332 ixgbe_release_eeprom_semaphore(hw); 3333 return IXGBE_SUCCESS; 3334 } else { 3335 /* Resource is currently in use by FW or SW */ 3336 ixgbe_release_eeprom_semaphore(hw); 3337 msec_delay(5); 3338 } 3339 } 3340 3341 /* If time expired clear the bits holding the lock and retry */ 3342 if (gssr & (fwmask | swmask)) 3343 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3344 3345 msec_delay(5); 3346 return IXGBE_ERR_SWFW_SYNC; 3347 } 3348 3349 /** 3350 * ixgbe_release_swfw_sync - Release SWFW semaphore 3351 * @hw: pointer to hardware structure 3352 * @mask: Mask to specify which semaphore to release 3353 * 3354 * Releases the SWFW semaphore through the GSSR register for the specified 3355 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3356 **/ 3357 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3358 { 3359 u32 gssr; 3360 u32 swmask = mask; 3361 3362 DEBUGFUNC("ixgbe_release_swfw_sync"); 3363 3364 ixgbe_get_eeprom_semaphore(hw); 3365 3366 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3367 gssr &= ~swmask; 3368 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3369 3370 ixgbe_release_eeprom_semaphore(hw); 3371 } 3372 3373 /** 3374 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3375 * @hw: pointer to hardware structure 3376 * 3377 * Stops the receive data path and waits for the HW to internally empty 3378 * the Rx security block 3379 **/ 3380 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3381 { 3382 #define IXGBE_MAX_SECRX_POLL 4000 3383 3384 int i; 3385 int secrxreg; 3386 3387 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3388 3389 3390 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3391 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3392 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3393 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3394 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3395 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3396 break; 3397 else 3398 /* Use interrupt-safe sleep just in case */ 3399 usec_delay(10); 3400 } 3401 3402 /* For informational purposes only */ 3403 if (i >= IXGBE_MAX_SECRX_POLL) 3404 DEBUGOUT("Rx unit being enabled before security " 3405 "path fully disabled. Continuing with init.\n"); 3406 3407 return IXGBE_SUCCESS; 3408 } 3409 3410 /** 3411 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3412 * @hw: pointer to hardware structure 3413 * @locked: bool to indicate whether the SW/FW lock was taken 3414 * @reg_val: Value we read from AUTOC 3415 * 3416 * The default case requires no protection so just to the register read. 3417 */ 3418 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3419 { 3420 *locked = FALSE; 3421 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3422 return IXGBE_SUCCESS; 3423 } 3424 3425 /** 3426 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3427 * @hw: pointer to hardware structure 3428 * @reg_val: value to write to AUTOC 3429 * @locked: bool to indicate whether the SW/FW lock was already taken by 3430 * previous read. 3431 * 3432 * The default case requires no protection so just to the register write. 3433 */ 3434 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3435 { 3436 UNREFERENCED_1PARAMETER(locked); 3437 3438 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3439 return IXGBE_SUCCESS; 3440 } 3441 3442 /** 3443 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3444 * @hw: pointer to hardware structure 3445 * 3446 * Enables the receive data path. 3447 **/ 3448 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3449 { 3450 u32 secrxreg; 3451 3452 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3453 3454 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3455 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3456 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3457 IXGBE_WRITE_FLUSH(hw); 3458 3459 return IXGBE_SUCCESS; 3460 } 3461 3462 /** 3463 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3464 * @hw: pointer to hardware structure 3465 * @regval: register value to write to RXCTRL 3466 * 3467 * Enables the Rx DMA unit 3468 **/ 3469 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3470 { 3471 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3472 3473 if (regval & IXGBE_RXCTRL_RXEN) 3474 ixgbe_enable_rx(hw); 3475 else 3476 ixgbe_disable_rx(hw); 3477 3478 return IXGBE_SUCCESS; 3479 } 3480 3481 /** 3482 * ixgbe_blink_led_start_generic - Blink LED based on index. 3483 * @hw: pointer to hardware structure 3484 * @index: led number to blink 3485 **/ 3486 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3487 { 3488 ixgbe_link_speed speed = 0; 3489 bool link_up = 0; 3490 u32 autoc_reg = 0; 3491 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3492 s32 ret_val = IXGBE_SUCCESS; 3493 bool locked = FALSE; 3494 3495 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3496 3497 if (index > 3) 3498 return IXGBE_ERR_PARAM; 3499 3500 /* 3501 * Link must be up to auto-blink the LEDs; 3502 * Force it if link is down. 3503 */ 3504 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3505 3506 if (!link_up) { 3507 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3508 if (ret_val != IXGBE_SUCCESS) 3509 goto out; 3510 3511 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3512 autoc_reg |= IXGBE_AUTOC_FLU; 3513 3514 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3515 if (ret_val != IXGBE_SUCCESS) 3516 goto out; 3517 3518 IXGBE_WRITE_FLUSH(hw); 3519 msec_delay(10); 3520 } 3521 3522 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3523 led_reg |= IXGBE_LED_BLINK(index); 3524 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3525 IXGBE_WRITE_FLUSH(hw); 3526 3527 out: 3528 return ret_val; 3529 } 3530 3531 /** 3532 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3533 * @hw: pointer to hardware structure 3534 * @index: led number to stop blinking 3535 **/ 3536 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3537 { 3538 u32 autoc_reg = 0; 3539 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3540 s32 ret_val = IXGBE_SUCCESS; 3541 bool locked = FALSE; 3542 3543 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3544 3545 if (index > 3) 3546 return IXGBE_ERR_PARAM; 3547 3548 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3549 if (ret_val != IXGBE_SUCCESS) 3550 goto out; 3551 3552 autoc_reg &= ~IXGBE_AUTOC_FLU; 3553 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3554 3555 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3556 if (ret_val != IXGBE_SUCCESS) 3557 goto out; 3558 3559 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3560 led_reg &= ~IXGBE_LED_BLINK(index); 3561 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3562 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3563 IXGBE_WRITE_FLUSH(hw); 3564 3565 out: 3566 return ret_val; 3567 } 3568 3569 /** 3570 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3571 * @hw: pointer to hardware structure 3572 * @san_mac_offset: SAN MAC address offset 3573 * 3574 * This function will read the EEPROM location for the SAN MAC address 3575 * pointer, and returns the value at that location. This is used in both 3576 * get and set mac_addr routines. 3577 **/ 3578 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3579 u16 *san_mac_offset) 3580 { 3581 s32 ret_val; 3582 3583 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3584 3585 /* 3586 * First read the EEPROM pointer to see if the MAC addresses are 3587 * available. 3588 */ 3589 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3590 san_mac_offset); 3591 if (ret_val) { 3592 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3593 "eeprom at offset %d failed", 3594 IXGBE_SAN_MAC_ADDR_PTR); 3595 } 3596 3597 return ret_val; 3598 } 3599 3600 /** 3601 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3602 * @hw: pointer to hardware structure 3603 * @san_mac_addr: SAN MAC address 3604 * 3605 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3606 * per-port, so set_lan_id() must be called before reading the addresses. 3607 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3608 * upon for non-SFP connections, so we must call it here. 3609 **/ 3610 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3611 { 3612 u16 san_mac_data, san_mac_offset; 3613 u8 i; 3614 s32 ret_val; 3615 3616 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3617 3618 /* 3619 * First read the EEPROM pointer to see if the MAC addresses are 3620 * available. If they're not, no point in calling set_lan_id() here. 3621 */ 3622 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3623 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3624 goto san_mac_addr_out; 3625 3626 /* make sure we know which port we need to program */ 3627 hw->mac.ops.set_lan_id(hw); 3628 /* apply the port offset to the address offset */ 3629 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3630 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3631 for (i = 0; i < 3; i++) { 3632 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3633 &san_mac_data); 3634 if (ret_val) { 3635 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3636 "eeprom read at offset %d failed", 3637 san_mac_offset); 3638 goto san_mac_addr_out; 3639 } 3640 san_mac_addr[i * 2] = (u8)(san_mac_data); 3641 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3642 san_mac_offset++; 3643 } 3644 return IXGBE_SUCCESS; 3645 3646 san_mac_addr_out: 3647 /* 3648 * No addresses available in this EEPROM. It's not an 3649 * error though, so just wipe the local address and return. 3650 */ 3651 for (i = 0; i < 6; i++) 3652 san_mac_addr[i] = 0xFF; 3653 return IXGBE_SUCCESS; 3654 } 3655 3656 /** 3657 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3658 * @hw: pointer to hardware structure 3659 * @san_mac_addr: SAN MAC address 3660 * 3661 * Write a SAN MAC address to the EEPROM. 3662 **/ 3663 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3664 { 3665 s32 ret_val; 3666 u16 san_mac_data, san_mac_offset; 3667 u8 i; 3668 3669 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3670 3671 /* Look for SAN mac address pointer. If not defined, return */ 3672 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3673 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3674 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3675 3676 /* Make sure we know which port we need to write */ 3677 hw->mac.ops.set_lan_id(hw); 3678 /* Apply the port offset to the address offset */ 3679 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3680 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3681 3682 for (i = 0; i < 3; i++) { 3683 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3684 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3685 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3686 san_mac_offset++; 3687 } 3688 3689 return IXGBE_SUCCESS; 3690 } 3691 3692 /** 3693 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3694 * @hw: pointer to hardware structure 3695 * 3696 * Read PCIe configuration space, and get the MSI-X vector count from 3697 * the capabilities table. 3698 **/ 3699 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3700 { 3701 u16 msix_count = 1; 3702 u16 max_msix_count; 3703 u16 pcie_offset; 3704 3705 switch (hw->mac.type) { 3706 case ixgbe_mac_82598EB: 3707 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3708 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3709 break; 3710 case ixgbe_mac_82599EB: 3711 case ixgbe_mac_X540: 3712 case ixgbe_mac_X550: 3713 case ixgbe_mac_X550EM_x: 3714 case ixgbe_mac_X550EM_a: 3715 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3716 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3717 break; 3718 default: 3719 return msix_count; 3720 } 3721 3722 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3723 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3724 if (IXGBE_REMOVED(hw->hw_addr)) 3725 msix_count = 0; 3726 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3727 3728 /* MSI-X count is zero-based in HW */ 3729 msix_count++; 3730 3731 if (msix_count > max_msix_count) 3732 msix_count = max_msix_count; 3733 3734 return msix_count; 3735 } 3736 3737 /** 3738 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3739 * @hw: pointer to hardware structure 3740 * @addr: Address to put into receive address register 3741 * @vmdq: VMDq pool to assign 3742 * 3743 * Puts an ethernet address into a receive address register, or 3744 * finds the rar that it is already in; adds to the pool list 3745 **/ 3746 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3747 { 3748 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3749 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3750 u32 rar; 3751 u32 rar_low, rar_high; 3752 u32 addr_low, addr_high; 3753 3754 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3755 3756 /* swap bytes for HW little endian */ 3757 addr_low = addr[0] | (addr[1] << 8) 3758 | (addr[2] << 16) 3759 | (addr[3] << 24); 3760 addr_high = addr[4] | (addr[5] << 8); 3761 3762 /* 3763 * Either find the mac_id in rar or find the first empty space. 3764 * rar_highwater points to just after the highest currently used 3765 * rar in order to shorten the search. It grows when we add a new 3766 * rar to the top. 3767 */ 3768 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3769 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3770 3771 if (((IXGBE_RAH_AV & rar_high) == 0) 3772 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3773 first_empty_rar = rar; 3774 } else if ((rar_high & 0xFFFF) == addr_high) { 3775 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3776 if (rar_low == addr_low) 3777 break; /* found it already in the rars */ 3778 } 3779 } 3780 3781 if (rar < hw->mac.rar_highwater) { 3782 /* already there so just add to the pool bits */ 3783 ixgbe_set_vmdq(hw, rar, vmdq); 3784 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3785 /* stick it into first empty RAR slot we found */ 3786 rar = first_empty_rar; 3787 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3788 } else if (rar == hw->mac.rar_highwater) { 3789 /* add it to the top of the list and inc the highwater mark */ 3790 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3791 hw->mac.rar_highwater++; 3792 } else if (rar >= hw->mac.num_rar_entries) { 3793 return IXGBE_ERR_INVALID_MAC_ADDR; 3794 } 3795 3796 /* 3797 * If we found rar[0], make sure the default pool bit (we use pool 0) 3798 * remains cleared to be sure default pool packets will get delivered 3799 */ 3800 if (rar == 0) 3801 ixgbe_clear_vmdq(hw, rar, 0); 3802 3803 return rar; 3804 } 3805 3806 /** 3807 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3808 * @hw: pointer to hardware struct 3809 * @rar: receive address register index to disassociate 3810 * @vmdq: VMDq pool index to remove from the rar 3811 **/ 3812 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3813 { 3814 u32 mpsar_lo, mpsar_hi; 3815 u32 rar_entries = hw->mac.num_rar_entries; 3816 3817 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3818 3819 /* Make sure we are using a valid rar index range */ 3820 if (rar >= rar_entries) { 3821 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3822 "RAR index %d is out of range.\n", rar); 3823 return IXGBE_ERR_INVALID_ARGUMENT; 3824 } 3825 3826 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3827 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3828 3829 if (IXGBE_REMOVED(hw->hw_addr)) 3830 goto done; 3831 3832 if (!mpsar_lo && !mpsar_hi) 3833 goto done; 3834 3835 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3836 if (mpsar_lo) { 3837 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3838 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3839 } 3840 if (mpsar_hi) { 3841 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3842 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3843 } 3844 } else if (vmdq < 32) { 3845 mpsar_lo &= ~(1 << vmdq); 3846 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3847 } else { 3848 mpsar_hi &= ~(1 << (vmdq - 32)); 3849 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3850 } 3851 3852 /* was that the last pool using this rar? */ 3853 if (mpsar_lo == 0 && mpsar_hi == 0 && 3854 rar != 0 && rar != hw->mac.san_mac_rar_index) 3855 hw->mac.ops.clear_rar(hw, rar); 3856 done: 3857 return IXGBE_SUCCESS; 3858 } 3859 3860 /** 3861 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3862 * @hw: pointer to hardware struct 3863 * @rar: receive address register index to associate with a VMDq index 3864 * @vmdq: VMDq pool index 3865 **/ 3866 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3867 { 3868 u32 mpsar; 3869 u32 rar_entries = hw->mac.num_rar_entries; 3870 3871 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3872 3873 /* Make sure we are using a valid rar index range */ 3874 if (rar >= rar_entries) { 3875 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3876 "RAR index %d is out of range.\n", rar); 3877 return IXGBE_ERR_INVALID_ARGUMENT; 3878 } 3879 3880 if (vmdq < 32) { 3881 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3882 mpsar |= 1 << vmdq; 3883 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3884 } else { 3885 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3886 mpsar |= 1 << (vmdq - 32); 3887 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3888 } 3889 return IXGBE_SUCCESS; 3890 } 3891 3892 /** 3893 * This function should only be involved in the IOV mode. 3894 * In IOV mode, Default pool is next pool after the number of 3895 * VFs advertized and not 0. 3896 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3897 * 3898 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3899 * @hw: pointer to hardware struct 3900 * @vmdq: VMDq pool index 3901 **/ 3902 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3903 { 3904 u32 rar = hw->mac.san_mac_rar_index; 3905 3906 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3907 3908 if (vmdq < 32) { 3909 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3910 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3911 } else { 3912 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3913 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3914 } 3915 3916 return IXGBE_SUCCESS; 3917 } 3918 3919 /** 3920 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3921 * @hw: pointer to hardware structure 3922 **/ 3923 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3924 { 3925 int i; 3926 3927 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3928 DEBUGOUT(" Clearing UTA\n"); 3929 3930 for (i = 0; i < 128; i++) 3931 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3932 3933 return IXGBE_SUCCESS; 3934 } 3935 3936 /** 3937 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3938 * @hw: pointer to hardware structure 3939 * @vlan: VLAN id to write to VLAN filter 3940 * @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if 3941 * vlanid not found 3942 * 3943 * 3944 * return the VLVF index where this VLAN id should be placed 3945 * 3946 **/ 3947 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3948 { 3949 s32 regindex, first_empty_slot; 3950 u32 bits; 3951 3952 /* short cut the special case */ 3953 if (vlan == 0) 3954 return 0; 3955 3956 /* if vlvf_bypass is set we don't want to use an empty slot, we 3957 * will simply bypass the VLVF if there are no entries present in the 3958 * VLVF that contain our VLAN 3959 */ 3960 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3961 3962 /* add VLAN enable bit for comparison */ 3963 vlan |= IXGBE_VLVF_VIEN; 3964 3965 /* Search for the vlan id in the VLVF entries. Save off the first empty 3966 * slot found along the way. 3967 * 3968 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3969 */ 3970 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3971 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3972 if (bits == vlan) 3973 return regindex; 3974 if (!first_empty_slot && !bits) 3975 first_empty_slot = regindex; 3976 } 3977 3978 /* If we are here then we didn't find the VLAN. Return first empty 3979 * slot we found during our search, else error. 3980 */ 3981 if (!first_empty_slot) 3982 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); 3983 3984 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; 3985 } 3986 3987 /** 3988 * ixgbe_set_vfta_generic - Set VLAN filter table 3989 * @hw: pointer to hardware structure 3990 * @vlan: VLAN id to write to VLAN filter 3991 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3992 * @vlan_on: boolean flag to turn on/off VLAN 3993 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3994 * 3995 * Turn on/off specified VLAN in the VLAN filter table. 3996 **/ 3997 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3998 bool vlan_on, bool vlvf_bypass) 3999 { 4000 u32 regidx, vfta_delta, vfta; 4001 s32 ret_val; 4002 4003 DEBUGFUNC("ixgbe_set_vfta_generic"); 4004 4005 if (vlan > 4095 || vind > 63) 4006 return IXGBE_ERR_PARAM; 4007 4008 /* 4009 * this is a 2 part operation - first the VFTA, then the 4010 * VLVF and VLVFB if VT Mode is set 4011 * We don't write the VFTA until we know the VLVF part succeeded. 4012 */ 4013 4014 /* Part 1 4015 * The VFTA is a bitstring made up of 128 32-bit registers 4016 * that enable the particular VLAN id, much like the MTA: 4017 * bits[11-5]: which register 4018 * bits[4-0]: which bit in the register 4019 */ 4020 regidx = vlan / 32; 4021 vfta_delta = (u32)1 << (vlan % 32); 4022 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 4023 4024 /* 4025 * vfta_delta represents the difference between the current value 4026 * of vfta and the value we want in the register. Since the diff 4027 * is an XOR mask we can just update the vfta using an XOR 4028 */ 4029 vfta_delta &= vlan_on ? ~vfta : vfta; 4030 vfta ^= vfta_delta; 4031 4032 /* Part 2 4033 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 4034 */ 4035 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 4036 vfta, vlvf_bypass); 4037 if (ret_val != IXGBE_SUCCESS) { 4038 if (vlvf_bypass) 4039 goto vfta_update; 4040 return ret_val; 4041 } 4042 4043 vfta_update: 4044 /* Update VFTA now that we are ready for traffic */ 4045 if (vfta_delta) 4046 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 4047 4048 return IXGBE_SUCCESS; 4049 } 4050 4051 /** 4052 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 4053 * @hw: pointer to hardware structure 4054 * @vlan: VLAN id to write to VLAN filter 4055 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 4056 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 4057 * @vfta_delta: pointer to the difference between the current value of VFTA 4058 * and the desired value 4059 * @vfta: the desired value of the VFTA 4060 * @vlvf_bypass: boolean flag indicating updating default pool is okay 4061 * 4062 * Turn on/off specified bit in VLVF table. 4063 **/ 4064 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4065 bool vlan_on, u32 *vfta_delta, u32 vfta, 4066 bool vlvf_bypass) 4067 { 4068 u32 bits; 4069 s32 vlvf_index; 4070 4071 DEBUGFUNC("ixgbe_set_vlvf_generic"); 4072 4073 if (vlan > 4095 || vind > 63) 4074 return IXGBE_ERR_PARAM; 4075 4076 /* If VT Mode is set 4077 * Either vlan_on 4078 * make sure the vlan is in VLVF 4079 * set the vind bit in the matching VLVFB 4080 * Or !vlan_on 4081 * clear the pool bit and possibly the vind 4082 */ 4083 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4084 return IXGBE_SUCCESS; 4085 4086 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4087 if (vlvf_index < 0) 4088 return vlvf_index; 4089 4090 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 4091 4092 /* set the pool bit */ 4093 bits |= 1 << (vind % 32); 4094 if (vlan_on) 4095 goto vlvf_update; 4096 4097 /* clear the pool bit */ 4098 bits ^= 1 << (vind % 32); 4099 4100 if (!bits && 4101 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4102 /* Clear VFTA first, then disable VLVF. Otherwise 4103 * we run the risk of stray packets leaking into 4104 * the PF via the default pool 4105 */ 4106 if (*vfta_delta) 4107 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4108 4109 /* disable VLVF and clear remaining bit from pool */ 4110 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4111 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4112 4113 return IXGBE_SUCCESS; 4114 } 4115 4116 /* If there are still bits set in the VLVFB registers 4117 * for the VLAN ID indicated we need to see if the 4118 * caller is requesting that we clear the VFTA entry bit. 4119 * If the caller has requested that we clear the VFTA 4120 * entry bit but there are still pools/VFs using this VLAN 4121 * ID entry then ignore the request. We're not worried 4122 * about the case where we're turning the VFTA VLAN ID 4123 * entry bit on, only when requested to turn it off as 4124 * there may be multiple pools and/or VFs using the 4125 * VLAN ID entry. In that case we cannot clear the 4126 * VFTA bit until all pools/VFs using that VLAN ID have also 4127 * been cleared. This will be indicated by "bits" being 4128 * zero. 4129 */ 4130 *vfta_delta = 0; 4131 4132 vlvf_update: 4133 /* record pool change and enable VLAN ID if not already enabled */ 4134 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4135 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4136 4137 return IXGBE_SUCCESS; 4138 } 4139 4140 /** 4141 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4142 * @hw: pointer to hardware structure 4143 * 4144 * Clears the VLAN filer table, and the VMDq index associated with the filter 4145 **/ 4146 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4147 { 4148 u32 offset; 4149 4150 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4151 4152 for (offset = 0; offset < hw->mac.vft_size; offset++) 4153 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4154 4155 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4156 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4157 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4158 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); 4159 } 4160 4161 return IXGBE_SUCCESS; 4162 } 4163 4164 /** 4165 * ixgbe_toggle_txdctl_generic - Toggle VF's queues 4166 * @hw: pointer to hardware structure 4167 * @vf_number: VF index 4168 * 4169 * Enable and disable each queue in VF. 4170 */ 4171 s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number) 4172 { 4173 u8 queue_count, i; 4174 u32 offset, reg; 4175 4176 if (vf_number > 63) 4177 return IXGBE_ERR_PARAM; 4178 4179 /* 4180 * Determine number of queues by checking 4181 * number of virtual functions 4182 */ 4183 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4184 switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) { 4185 case IXGBE_GCR_EXT_VT_MODE_64: 4186 queue_count = 2; 4187 break; 4188 case IXGBE_GCR_EXT_VT_MODE_32: 4189 queue_count = 4; 4190 break; 4191 case IXGBE_GCR_EXT_VT_MODE_16: 4192 queue_count = 8; 4193 break; 4194 default: 4195 return IXGBE_ERR_CONFIG; 4196 } 4197 4198 /* Toggle queues */ 4199 for (i = 0; i < queue_count; ++i) { 4200 /* Calculate offset of current queue */ 4201 offset = queue_count * vf_number + i; 4202 4203 /* Enable queue */ 4204 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); 4205 reg |= IXGBE_TXDCTL_ENABLE; 4206 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); 4207 IXGBE_WRITE_FLUSH(hw); 4208 4209 /* Disable queue */ 4210 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); 4211 reg &= ~IXGBE_TXDCTL_ENABLE; 4212 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); 4213 IXGBE_WRITE_FLUSH(hw); 4214 } 4215 4216 return IXGBE_SUCCESS; 4217 } 4218 4219 /** 4220 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4221 * @hw: pointer to hardware structure 4222 * 4223 * Contains the logic to identify if we need to verify link for the 4224 * crosstalk fix 4225 **/ 4226 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4227 { 4228 4229 /* Does FW say we need the fix */ 4230 if (!hw->need_crosstalk_fix) 4231 return FALSE; 4232 4233 /* Only consider SFP+ PHYs i.e. media type fiber */ 4234 switch (hw->mac.ops.get_media_type(hw)) { 4235 case ixgbe_media_type_fiber: 4236 case ixgbe_media_type_fiber_qsfp: 4237 break; 4238 default: 4239 return FALSE; 4240 } 4241 4242 return TRUE; 4243 } 4244 4245 /** 4246 * ixgbe_check_mac_link_generic - Determine link and speed status 4247 * @hw: pointer to hardware structure 4248 * @speed: pointer to link speed 4249 * @link_up: TRUE when link is up 4250 * @link_up_wait_to_complete: bool used to wait for link up or not 4251 * 4252 * Reads the links register to determine if link is up and the current speed 4253 **/ 4254 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4255 bool *link_up, bool link_up_wait_to_complete) 4256 { 4257 u32 links_reg, links_orig; 4258 u32 i; 4259 4260 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4261 4262 /* If Crosstalk fix enabled do the sanity check of making sure 4263 * the SFP+ cage is full. 4264 */ 4265 if (ixgbe_need_crosstalk_fix(hw)) { 4266 if ((hw->mac.type != ixgbe_mac_82598EB) && 4267 !ixgbe_sfp_cage_full(hw)) { 4268 *link_up = FALSE; 4269 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4270 return IXGBE_SUCCESS; 4271 } 4272 } 4273 4274 /* clear the old state */ 4275 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4276 4277 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4278 4279 if (links_orig != links_reg) { 4280 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4281 links_orig, links_reg); 4282 } 4283 4284 if (link_up_wait_to_complete) { 4285 for (i = 0; i < hw->mac.max_link_up_time; i++) { 4286 if (links_reg & IXGBE_LINKS_UP) { 4287 *link_up = TRUE; 4288 break; 4289 } else { 4290 *link_up = FALSE; 4291 } 4292 msec_delay(100); 4293 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4294 } 4295 } else { 4296 if (links_reg & IXGBE_LINKS_UP) 4297 *link_up = TRUE; 4298 else 4299 *link_up = FALSE; 4300 } 4301 4302 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4303 case IXGBE_LINKS_SPEED_10G_82599: 4304 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4305 if (hw->mac.type >= ixgbe_mac_X550) { 4306 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4307 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4308 } 4309 break; 4310 case IXGBE_LINKS_SPEED_1G_82599: 4311 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4312 break; 4313 case IXGBE_LINKS_SPEED_100_82599: 4314 *speed = IXGBE_LINK_SPEED_100_FULL; 4315 if (hw->mac.type >= ixgbe_mac_X550) { 4316 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4317 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4318 } 4319 break; 4320 case IXGBE_LINKS_SPEED_10_X550EM_A: 4321 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4322 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4323 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4324 *speed = IXGBE_LINK_SPEED_10_FULL; 4325 break; 4326 default: 4327 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4328 } 4329 4330 return IXGBE_SUCCESS; 4331 } 4332 4333 /** 4334 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4335 * the EEPROM 4336 * @hw: pointer to hardware structure 4337 * @wwnn_prefix: the alternative WWNN prefix 4338 * @wwpn_prefix: the alternative WWPN prefix 4339 * 4340 * This function will read the EEPROM from the alternative SAN MAC address 4341 * block to check the support for the alternative WWNN/WWPN prefix support. 4342 **/ 4343 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4344 u16 *wwpn_prefix) 4345 { 4346 u16 offset, caps; 4347 u16 alt_san_mac_blk_offset; 4348 4349 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4350 4351 /* clear output first */ 4352 *wwnn_prefix = 0xFFFF; 4353 *wwpn_prefix = 0xFFFF; 4354 4355 /* check if alternative SAN MAC is supported */ 4356 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4357 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4358 goto wwn_prefix_err; 4359 4360 if ((alt_san_mac_blk_offset == 0) || 4361 (alt_san_mac_blk_offset == 0xFFFF)) 4362 goto wwn_prefix_out; 4363 4364 /* check capability in alternative san mac address block */ 4365 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4366 if (hw->eeprom.ops.read(hw, offset, &caps)) 4367 goto wwn_prefix_err; 4368 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4369 goto wwn_prefix_out; 4370 4371 /* get the corresponding prefix for WWNN/WWPN */ 4372 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4373 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4374 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4375 "eeprom read at offset %d failed", offset); 4376 } 4377 4378 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4379 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4380 goto wwn_prefix_err; 4381 4382 wwn_prefix_out: 4383 return IXGBE_SUCCESS; 4384 4385 wwn_prefix_err: 4386 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4387 "eeprom read at offset %d failed", offset); 4388 return IXGBE_SUCCESS; 4389 } 4390 4391 /** 4392 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4393 * @hw: pointer to hardware structure 4394 * @bs: the fcoe boot status 4395 * 4396 * This function will read the FCOE boot status from the iSCSI FCOE block 4397 **/ 4398 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4399 { 4400 u16 offset, caps, flags; 4401 s32 status; 4402 4403 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4404 4405 /* clear output first */ 4406 *bs = ixgbe_fcoe_bootstatus_unavailable; 4407 4408 /* check if FCOE IBA block is present */ 4409 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4410 status = hw->eeprom.ops.read(hw, offset, &caps); 4411 if (status != IXGBE_SUCCESS) 4412 goto out; 4413 4414 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4415 goto out; 4416 4417 /* check if iSCSI FCOE block is populated */ 4418 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4419 if (status != IXGBE_SUCCESS) 4420 goto out; 4421 4422 if ((offset == 0) || (offset == 0xFFFF)) 4423 goto out; 4424 4425 /* read fcoe flags in iSCSI FCOE block */ 4426 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4427 status = hw->eeprom.ops.read(hw, offset, &flags); 4428 if (status != IXGBE_SUCCESS) 4429 goto out; 4430 4431 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4432 *bs = ixgbe_fcoe_bootstatus_enabled; 4433 else 4434 *bs = ixgbe_fcoe_bootstatus_disabled; 4435 4436 out: 4437 return status; 4438 } 4439 4440 /** 4441 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4442 * @hw: pointer to hardware structure 4443 * @enable: enable or disable switch for MAC anti-spoofing 4444 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 4445 * 4446 **/ 4447 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4448 { 4449 int vf_target_reg = vf >> 3; 4450 int vf_target_shift = vf % 8; 4451 u32 pfvfspoof; 4452 4453 if (hw->mac.type == ixgbe_mac_82598EB) 4454 return; 4455 4456 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4457 if (enable) 4458 pfvfspoof |= (1 << vf_target_shift); 4459 else 4460 pfvfspoof &= ~(1 << vf_target_shift); 4461 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4462 } 4463 4464 /** 4465 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4466 * @hw: pointer to hardware structure 4467 * @enable: enable or disable switch for VLAN anti-spoofing 4468 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4469 * 4470 **/ 4471 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4472 { 4473 int vf_target_reg = vf >> 3; 4474 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4475 u32 pfvfspoof; 4476 4477 if (hw->mac.type == ixgbe_mac_82598EB) 4478 return; 4479 4480 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4481 if (enable) 4482 pfvfspoof |= (1 << vf_target_shift); 4483 else 4484 pfvfspoof &= ~(1 << vf_target_shift); 4485 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4486 } 4487 4488 /** 4489 * ixgbe_get_device_caps_generic - Get additional device capabilities 4490 * @hw: pointer to hardware structure 4491 * @device_caps: the EEPROM word with the extra device capabilities 4492 * 4493 * This function will read the EEPROM location for the device capabilities, 4494 * and return the word through device_caps. 4495 **/ 4496 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4497 { 4498 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4499 4500 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4501 4502 return IXGBE_SUCCESS; 4503 } 4504 4505 /** 4506 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4507 * @hw: pointer to hardware structure 4508 * 4509 **/ 4510 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4511 { 4512 u32 regval; 4513 u32 i; 4514 4515 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4516 4517 /* Enable relaxed ordering */ 4518 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4519 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4520 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4521 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4522 } 4523 4524 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4525 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4526 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4527 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4528 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4529 } 4530 4531 } 4532 4533 /** 4534 * ixgbe_calculate_checksum - Calculate checksum for buffer 4535 * @buffer: pointer to EEPROM 4536 * @length: size of EEPROM to calculate a checksum for 4537 * Calculates the checksum for some buffer on a specified length. The 4538 * checksum calculated is returned. 4539 **/ 4540 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4541 { 4542 u32 i; 4543 u8 sum = 0; 4544 4545 DEBUGFUNC("ixgbe_calculate_checksum"); 4546 4547 if (!buffer) 4548 return 0; 4549 4550 for (i = 0; i < length; i++) 4551 sum += buffer[i]; 4552 4553 return (u8) (0 - sum); 4554 } 4555 4556 /** 4557 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 4558 * @hw: pointer to the HW structure 4559 * @buffer: command to write and where the return status will be placed 4560 * @length: length of buffer, must be multiple of 4 bytes 4561 * @timeout: time in ms to wait for command completion 4562 * 4563 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4564 * else returns semaphore error when encountering an error acquiring 4565 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4566 * 4567 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4568 * by the caller. 4569 **/ 4570 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4571 u32 timeout) 4572 { 4573 u32 hicr, i, fwsts; 4574 u16 dword_len; 4575 4576 DEBUGFUNC("ixgbe_hic_unlocked"); 4577 4578 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4579 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4580 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4581 } 4582 4583 /* Set bit 9 of FWSTS clearing FW reset indication */ 4584 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4585 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4586 4587 /* Check that the host interface is enabled. */ 4588 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4589 if (!(hicr & IXGBE_HICR_EN)) { 4590 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4591 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4592 } 4593 4594 /* Calculate length in DWORDs. We must be DWORD aligned */ 4595 if (length % sizeof(u32)) { 4596 DEBUGOUT("Buffer length failure, not aligned to dword"); 4597 return IXGBE_ERR_INVALID_ARGUMENT; 4598 } 4599 4600 dword_len = length >> 2; 4601 4602 /* The device driver writes the relevant command block 4603 * into the ram area. 4604 */ 4605 for (i = 0; i < dword_len; i++) 4606 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4607 i, IXGBE_CPU_TO_LE32(buffer[i])); 4608 4609 /* Setting this bit tells the ARC that a new command is pending. */ 4610 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4611 4612 for (i = 0; i < timeout; i++) { 4613 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4614 if (!(hicr & IXGBE_HICR_C)) 4615 break; 4616 msec_delay(1); 4617 } 4618 4619 /* For each command except "Apply Update" perform 4620 * status checks in the HICR registry. 4621 */ 4622 if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) == 4623 IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD) 4624 return IXGBE_SUCCESS; 4625 4626 /* Check command completion */ 4627 if ((timeout && i == timeout) || 4628 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4629 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4630 "Command has failed with no status valid.\n"); 4631 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4632 } 4633 4634 return IXGBE_SUCCESS; 4635 } 4636 4637 /** 4638 * ixgbe_host_interface_command - Issue command to manageability block 4639 * @hw: pointer to the HW structure 4640 * @buffer: contains the command to write and where the return status will 4641 * be placed 4642 * @length: length of buffer, must be multiple of 4 bytes 4643 * @timeout: time in ms to wait for command completion 4644 * @return_data: read and return data from the buffer (TRUE) or not (FALSE) 4645 * Needed because FW structures are big endian and decoding of 4646 * these fields can be 8 bit or 16 bit based on command. Decoding 4647 * is not easily understood without making a table of commands. 4648 * So we will leave this up to the caller to read back the data 4649 * in these cases. 4650 * 4651 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4652 * else returns semaphore error when encountering an error acquiring 4653 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4654 **/ 4655 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4656 u32 length, u32 timeout, bool return_data) 4657 { 4658 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4659 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer; 4660 u16 buf_len; 4661 s32 status; 4662 u32 bi; 4663 u32 dword_len; 4664 4665 DEBUGFUNC("ixgbe_host_interface_command"); 4666 4667 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4668 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4669 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4670 } 4671 4672 /* Take management host interface semaphore */ 4673 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4674 if (status) 4675 return status; 4676 4677 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4678 if (status) 4679 goto rel_out; 4680 4681 if (!return_data) 4682 goto rel_out; 4683 4684 /* Calculate length in DWORDs */ 4685 dword_len = hdr_size >> 2; 4686 4687 /* first pull in the header so we know the buffer length */ 4688 for (bi = 0; bi < dword_len; bi++) { 4689 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4690 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4691 } 4692 4693 /* 4694 * If there is any thing in data position pull it in 4695 * Read Flash command requires reading buffer length from 4696 * two byes instead of one byte 4697 */ 4698 if (resp->cmd == 0x30 || resp->cmd == 0x31) { 4699 for (; bi < dword_len + 2; bi++) { 4700 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4701 bi); 4702 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4703 } 4704 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3) 4705 & 0xF00) | resp->buf_len; 4706 hdr_size += (2 << 2); 4707 } else { 4708 buf_len = resp->buf_len; 4709 } 4710 if (!buf_len) 4711 goto rel_out; 4712 4713 if (length < buf_len + hdr_size) { 4714 DEBUGOUT("Buffer not large enough for reply message.\n"); 4715 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4716 goto rel_out; 4717 } 4718 4719 /* Calculate length in DWORDs, add 3 for odd lengths */ 4720 dword_len = (buf_len + 3) >> 2; 4721 4722 /* Pull in the rest of the buffer (bi is where we left off) */ 4723 for (; bi <= dword_len; bi++) { 4724 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4725 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4726 } 4727 4728 rel_out: 4729 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4730 4731 return status; 4732 } 4733 4734 /** 4735 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4736 * @hw: pointer to the HW structure 4737 * @maj: driver version major number 4738 * @minr: driver version minor number 4739 * @build: driver version build number 4740 * @sub: driver version sub build number 4741 * @len: unused 4742 * @driver_ver: unused 4743 * 4744 * Sends driver version number to firmware through the manageability 4745 * block. On success return IXGBE_SUCCESS 4746 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4747 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4748 **/ 4749 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 minr, 4750 u8 build, u8 sub, u16 len, 4751 const char *driver_ver) 4752 { 4753 struct ixgbe_hic_drv_info fw_cmd; 4754 int i; 4755 s32 ret_val = IXGBE_SUCCESS; 4756 4757 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4758 UNREFERENCED_2PARAMETER(len, driver_ver); 4759 4760 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4761 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4762 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4763 fw_cmd.port_num = (u8)hw->bus.func; 4764 fw_cmd.ver_maj = maj; 4765 fw_cmd.ver_min = minr; 4766 fw_cmd.ver_build = build; 4767 fw_cmd.ver_sub = sub; 4768 fw_cmd.hdr.checksum = 0; 4769 fw_cmd.pad = 0; 4770 fw_cmd.pad2 = 0; 4771 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4772 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4773 4774 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4775 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4776 sizeof(fw_cmd), 4777 IXGBE_HI_COMMAND_TIMEOUT, 4778 TRUE); 4779 if (ret_val != IXGBE_SUCCESS) 4780 continue; 4781 4782 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4783 FW_CEM_RESP_STATUS_SUCCESS) 4784 ret_val = IXGBE_SUCCESS; 4785 else 4786 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4787 4788 break; 4789 } 4790 4791 return ret_val; 4792 } 4793 4794 /** 4795 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4796 * @hw: pointer to hardware structure 4797 * @num_pb: number of packet buffers to allocate 4798 * @headroom: reserve n KB of headroom 4799 * @strategy: packet buffer allocation strategy 4800 **/ 4801 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4802 int strategy) 4803 { 4804 u32 pbsize = hw->mac.rx_pb_size; 4805 int i = 0; 4806 u32 rxpktsize, txpktsize, txpbthresh; 4807 4808 /* Reserve headroom */ 4809 pbsize -= headroom; 4810 4811 if (!num_pb) 4812 num_pb = 1; 4813 4814 /* Divide remaining packet buffer space amongst the number of packet 4815 * buffers requested using supplied strategy. 4816 */ 4817 switch (strategy) { 4818 case PBA_STRATEGY_WEIGHTED: 4819 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4820 * buffer with 5/8 of the packet buffer space. 4821 */ 4822 rxpktsize = (pbsize * 5) / (num_pb * 4); 4823 pbsize -= rxpktsize * (num_pb / 2); 4824 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4825 for (; i < (num_pb / 2); i++) 4826 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4827 /* fall through - configure remaining packet buffers */ 4828 case PBA_STRATEGY_EQUAL: 4829 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4830 for (; i < num_pb; i++) 4831 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4832 break; 4833 default: 4834 break; 4835 } 4836 4837 /* Only support an equally distributed Tx packet buffer strategy. */ 4838 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4839 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4840 for (i = 0; i < num_pb; i++) { 4841 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4842 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4843 } 4844 4845 /* Clear unused TCs, if any, to zero buffer size*/ 4846 for (; i < IXGBE_MAX_PB; i++) { 4847 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4848 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4849 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4850 } 4851 } 4852 4853 /** 4854 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4855 * @hw: pointer to the hardware structure 4856 * 4857 * The 82599 and x540 MACs can experience issues if TX work is still pending 4858 * when a reset occurs. This function prevents this by flushing the PCIe 4859 * buffers on the system. 4860 **/ 4861 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4862 { 4863 u32 gcr_ext, hlreg0, i, poll; 4864 u16 value; 4865 4866 /* 4867 * If double reset is not requested then all transactions should 4868 * already be clear and as such there is no work to do 4869 */ 4870 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4871 return; 4872 4873 /* 4874 * Set loopback enable to prevent any transmits from being sent 4875 * should the link come up. This assumes that the RXCTRL.RXEN bit 4876 * has already been cleared. 4877 */ 4878 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4879 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4880 4881 /* Wait for a last completion before clearing buffers */ 4882 IXGBE_WRITE_FLUSH(hw); 4883 msec_delay(3); 4884 4885 /* 4886 * Before proceeding, make sure that the PCIe block does not have 4887 * transactions pending. 4888 */ 4889 poll = ixgbe_pcie_timeout_poll(hw); 4890 for (i = 0; i < poll; i++) { 4891 usec_delay(100); 4892 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4893 if (IXGBE_REMOVED(hw->hw_addr)) 4894 goto out; 4895 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4896 goto out; 4897 } 4898 4899 out: 4900 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4901 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4902 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4903 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4904 4905 /* Flush all writes and allow 20usec for all transactions to clear */ 4906 IXGBE_WRITE_FLUSH(hw); 4907 usec_delay(20); 4908 4909 /* restore previous register values */ 4910 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4911 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4912 } 4913 4914 /** 4915 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW 4916 * 4917 * @hw: pointer to hardware structure 4918 * @cmd: Command we send to the FW 4919 * @status: The reply from the FW 4920 * 4921 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 4922 **/ 4923 #define IXGBE_BYPASS_BB_WAIT 1 4924 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) 4925 { 4926 int i; 4927 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; 4928 u32 esdp; 4929 4930 if (!status) 4931 return IXGBE_ERR_PARAM; 4932 4933 *status = 0; 4934 4935 /* SDP vary by MAC type */ 4936 switch (hw->mac.type) { 4937 case ixgbe_mac_82599EB: 4938 sck = IXGBE_ESDP_SDP7; 4939 sdi = IXGBE_ESDP_SDP0; 4940 sdo = IXGBE_ESDP_SDP6; 4941 dir_sck = IXGBE_ESDP_SDP7_DIR; 4942 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4943 dir_sdo = IXGBE_ESDP_SDP6_DIR; 4944 break; 4945 case ixgbe_mac_X540: 4946 sck = IXGBE_ESDP_SDP2; 4947 sdi = IXGBE_ESDP_SDP0; 4948 sdo = IXGBE_ESDP_SDP1; 4949 dir_sck = IXGBE_ESDP_SDP2_DIR; 4950 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4951 dir_sdo = IXGBE_ESDP_SDP1_DIR; 4952 break; 4953 default: 4954 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 4955 } 4956 4957 /* Set SDP pins direction */ 4958 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4959 esdp |= dir_sck; /* SCK as output */ 4960 esdp |= dir_sdi; /* SDI as output */ 4961 esdp &= ~dir_sdo; /* SDO as input */ 4962 esdp |= sck; 4963 esdp |= sdi; 4964 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4965 IXGBE_WRITE_FLUSH(hw); 4966 msec_delay(IXGBE_BYPASS_BB_WAIT); 4967 4968 /* Generate start condition */ 4969 esdp &= ~sdi; 4970 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4971 IXGBE_WRITE_FLUSH(hw); 4972 msec_delay(IXGBE_BYPASS_BB_WAIT); 4973 4974 esdp &= ~sck; 4975 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4976 IXGBE_WRITE_FLUSH(hw); 4977 msec_delay(IXGBE_BYPASS_BB_WAIT); 4978 4979 /* Clock out the new control word and clock in the status */ 4980 for (i = 0; i < 32; i++) { 4981 if ((cmd >> (31 - i)) & 0x01) { 4982 esdp |= sdi; 4983 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4984 } else { 4985 esdp &= ~sdi; 4986 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4987 } 4988 IXGBE_WRITE_FLUSH(hw); 4989 msec_delay(IXGBE_BYPASS_BB_WAIT); 4990 4991 esdp |= sck; 4992 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4993 IXGBE_WRITE_FLUSH(hw); 4994 msec_delay(IXGBE_BYPASS_BB_WAIT); 4995 4996 esdp &= ~sck; 4997 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4998 IXGBE_WRITE_FLUSH(hw); 4999 msec_delay(IXGBE_BYPASS_BB_WAIT); 5000 5001 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5002 if (esdp & sdo) 5003 *status = (*status << 1) | 0x01; 5004 else 5005 *status = (*status << 1) | 0x00; 5006 msec_delay(IXGBE_BYPASS_BB_WAIT); 5007 } 5008 5009 /* stop condition */ 5010 esdp |= sck; 5011 esdp &= ~sdi; 5012 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5013 IXGBE_WRITE_FLUSH(hw); 5014 msec_delay(IXGBE_BYPASS_BB_WAIT); 5015 5016 esdp |= sdi; 5017 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 5018 IXGBE_WRITE_FLUSH(hw); 5019 5020 /* set the page bits to match the cmd that the status it belongs to */ 5021 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); 5022 5023 return IXGBE_SUCCESS; 5024 } 5025 5026 /** 5027 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. 5028 * 5029 * If we send a write we can't be sure it took until we can read back 5030 * that same register. It can be a problem as some of the fields may 5031 * for valid reasons change in-between the time wrote the register and 5032 * we read it again to verify. So this function check everything we 5033 * can check and then assumes it worked. 5034 * 5035 * @u32 in_reg - The register cmd for the bit-bang read. 5036 * @u32 out_reg - The register returned from a bit-bang read. 5037 **/ 5038 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) 5039 { 5040 u32 mask; 5041 5042 /* Page must match for all control pages */ 5043 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) 5044 return FALSE; 5045 5046 switch (in_reg & BYPASS_PAGE_M) { 5047 case BYPASS_PAGE_CTL0: 5048 /* All the following can't change since the last write 5049 * - All the event actions 5050 * - The timeout value 5051 */ 5052 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | 5053 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | 5054 BYPASS_WDTIMEOUT_M | 5055 BYPASS_WDT_VALUE_M; 5056 if ((out_reg & mask) != (in_reg & mask)) 5057 return FALSE; 5058 5059 /* 0x0 is never a valid value for bypass status */ 5060 if (!(out_reg & BYPASS_STATUS_OFF_M)) 5061 return FALSE; 5062 break; 5063 case BYPASS_PAGE_CTL1: 5064 /* All the following can't change since the last write 5065 * - time valid bit 5066 * - time we last sent 5067 */ 5068 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; 5069 if ((out_reg & mask) != (in_reg & mask)) 5070 return FALSE; 5071 break; 5072 case BYPASS_PAGE_CTL2: 5073 /* All we can check in this page is control number 5074 * which is already done above. 5075 */ 5076 break; 5077 } 5078 5079 /* We are as sure as we can be return TRUE */ 5080 return TRUE; 5081 } 5082 5083 /** 5084 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Register. 5085 * 5086 * @hw: pointer to hardware structure 5087 * @cmd: The control word we are setting. 5088 * @event: The event we are setting in the FW. This also happens to 5089 * be the mask for the event we are setting (handy) 5090 * @action: The action we set the event to in the FW. This is in a 5091 * bit field that happens to be what we want to put in 5092 * the event spot (also handy) 5093 **/ 5094 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 5095 u32 action) 5096 { 5097 u32 by_ctl = 0; 5098 u32 cmd, verify; 5099 u32 count = 0; 5100 5101 /* Get current values */ 5102 cmd = ctrl; /* just reading only need control number */ 5103 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5104 return IXGBE_ERR_INVALID_ARGUMENT; 5105 5106 /* Set to new action */ 5107 cmd = (by_ctl & ~event) | BYPASS_WE | action; 5108 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5109 return IXGBE_ERR_INVALID_ARGUMENT; 5110 5111 /* Page 0 force a FW eeprom write which is slow so verify */ 5112 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { 5113 verify = BYPASS_PAGE_CTL0; 5114 do { 5115 if (count++ > 5) 5116 return IXGBE_BYPASS_FW_WRITE_FAILURE; 5117 5118 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) 5119 return IXGBE_ERR_INVALID_ARGUMENT; 5120 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); 5121 } else { 5122 /* We have give the FW time for the write to stick */ 5123 msec_delay(100); 5124 } 5125 5126 return IXGBE_SUCCESS; 5127 } 5128 5129 /** 5130 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom address. 5131 * 5132 * @hw: pointer to hardware structure 5133 * @addr: The bypass eeprom address to read. 5134 * @value: The 8b of data at the address above. 5135 **/ 5136 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) 5137 { 5138 u32 cmd; 5139 u32 status; 5140 5141 5142 /* send the request */ 5143 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; 5144 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; 5145 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5146 return IXGBE_ERR_INVALID_ARGUMENT; 5147 5148 /* We have give the FW time for the write to stick */ 5149 msec_delay(100); 5150 5151 /* now read the results */ 5152 cmd &= ~BYPASS_WE; 5153 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5154 return IXGBE_ERR_INVALID_ARGUMENT; 5155 5156 *value = status & BYPASS_CTL2_DATA_M; 5157 5158 return IXGBE_SUCCESS; 5159 } 5160 5161 /** 5162 * ixgbe_get_orom_version - Return option ROM from EEPROM 5163 * 5164 * @hw: pointer to hardware structure 5165 * @nvm_ver: pointer to output structure 5166 * 5167 * if valid option ROM version, nvm_ver->or_valid set to TRUE 5168 * else nvm_ver->or_valid is FALSE. 5169 **/ 5170 void ixgbe_get_orom_version(struct ixgbe_hw *hw, 5171 struct ixgbe_nvm_version *nvm_ver) 5172 { 5173 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 5174 5175 nvm_ver->or_valid = FALSE; 5176 /* Option Rom may or may not be present. Start with pointer */ 5177 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 5178 5179 /* make sure offset is valid */ 5180 if ((offset == 0x0) || (offset == NVM_INVALID_PTR)) 5181 return; 5182 5183 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 5184 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 5185 5186 /* option rom exists and is valid */ 5187 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 5188 eeprom_cfg_blkl == NVM_VER_INVALID || 5189 eeprom_cfg_blkh == NVM_VER_INVALID) 5190 return; 5191 5192 nvm_ver->or_valid = TRUE; 5193 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 5194 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 5195 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 5196 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 5197 } 5198 5199 /** 5200 * ixgbe_get_oem_prod_version - Return OEM Product version 5201 * 5202 * @hw: pointer to hardware structure 5203 * @nvm_ver: pointer to output structure 5204 * 5205 * if valid OEM product version, nvm_ver->oem_valid set to TRUE 5206 * else nvm_ver->oem_valid is FALSE. 5207 **/ 5208 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 5209 struct ixgbe_nvm_version *nvm_ver) 5210 { 5211 u16 rel_num, prod_ver, mod_len, cap, offset; 5212 5213 nvm_ver->oem_valid = FALSE; 5214 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 5215 5216 /* Return if offset to OEM Product Version block is invalid */ 5217 if (offset == 0x0 || offset == NVM_INVALID_PTR) 5218 return; 5219 5220 /* Read product version block */ 5221 hw->eeprom.ops.read(hw, offset, &mod_len); 5222 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 5223 5224 /* Return if OEM product version block is invalid */ 5225 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 5226 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 5227 return; 5228 5229 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 5230 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 5231 5232 /* Return if version is invalid */ 5233 if ((rel_num | prod_ver) == 0x0 || 5234 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 5235 return; 5236 5237 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 5238 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 5239 nvm_ver->oem_release = rel_num; 5240 nvm_ver->oem_valid = TRUE; 5241 } 5242 5243 /** 5244 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 5245 * 5246 * @hw: pointer to hardware structure 5247 * @nvm_ver: pointer to output structure 5248 * 5249 * word read errors will return 0xFFFF 5250 **/ 5251 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) 5252 { 5253 u16 etk_id_l, etk_id_h; 5254 5255 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 5256 etk_id_l = NVM_VER_INVALID; 5257 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 5258 etk_id_h = NVM_VER_INVALID; 5259 5260 /* The word order for the version format is determined by high order 5261 * word bit 15. 5262 */ 5263 if ((etk_id_h & NVM_ETK_VALID) == 0) { 5264 nvm_ver->etk_id = etk_id_h; 5265 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); 5266 } else { 5267 nvm_ver->etk_id = etk_id_l; 5268 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); 5269 } 5270 } 5271 5272 5273 /** 5274 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5275 * @hw: pointer to hardware structure 5276 * @map: pointer to u8 arr for returning map 5277 * 5278 * Read the rtrup2tc HW register and resolve its content into map 5279 **/ 5280 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5281 { 5282 u32 reg, i; 5283 5284 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 5285 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 5286 map[i] = IXGBE_RTRUP2TC_UP_MASK & 5287 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 5288 return; 5289 } 5290 5291 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 5292 { 5293 u32 pfdtxgswc; 5294 u32 rxctrl; 5295 5296 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5297 if (rxctrl & IXGBE_RXCTRL_RXEN) { 5298 if (hw->mac.type != ixgbe_mac_82598EB) { 5299 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5300 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 5301 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 5302 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5303 hw->mac.set_lben = TRUE; 5304 } else { 5305 hw->mac.set_lben = FALSE; 5306 } 5307 } 5308 rxctrl &= ~IXGBE_RXCTRL_RXEN; 5309 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 5310 } 5311 } 5312 5313 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 5314 { 5315 u32 pfdtxgswc; 5316 u32 rxctrl; 5317 5318 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5319 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 5320 5321 if (hw->mac.type != ixgbe_mac_82598EB) { 5322 if (hw->mac.set_lben) { 5323 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5324 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 5325 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5326 hw->mac.set_lben = FALSE; 5327 } 5328 } 5329 } 5330 5331 /** 5332 * ixgbe_mng_present - returns TRUE when management capability is present 5333 * @hw: pointer to hardware structure 5334 */ 5335 bool ixgbe_mng_present(struct ixgbe_hw *hw) 5336 { 5337 u32 fwsm; 5338 5339 if (hw->mac.type < ixgbe_mac_82599EB) 5340 return FALSE; 5341 5342 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5343 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 5344 } 5345 5346 /** 5347 * ixgbe_mng_enabled - Is the manageability engine enabled? 5348 * @hw: pointer to hardware structure 5349 * 5350 * Returns TRUE if the manageability engine is enabled. 5351 **/ 5352 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 5353 { 5354 u32 fwsm, manc, factps; 5355 5356 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5357 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 5358 return FALSE; 5359 5360 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 5361 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 5362 return FALSE; 5363 5364 if (hw->mac.type <= ixgbe_mac_X540) { 5365 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 5366 if (factps & IXGBE_FACTPS_MNGCG) 5367 return FALSE; 5368 } 5369 5370 return TRUE; 5371 } 5372 5373 /** 5374 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 5375 * @hw: pointer to hardware structure 5376 * @speed: new link speed 5377 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 5378 * 5379 * Set the link speed in the MAC and/or PHY register and restarts link. 5380 **/ 5381 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 5382 ixgbe_link_speed speed, 5383 bool autoneg_wait_to_complete) 5384 { 5385 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5386 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5387 s32 status = IXGBE_SUCCESS; 5388 u32 speedcnt = 0; 5389 u32 i = 0; 5390 bool autoneg, link_up = FALSE; 5391 5392 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 5393 5394 /* Mask off requested but non-supported speeds */ 5395 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 5396 if (status != IXGBE_SUCCESS) 5397 return status; 5398 5399 speed &= link_speed; 5400 5401 /* Try each speed one by one, highest priority first. We do this in 5402 * software because 10Gb fiber doesn't support speed autonegotiation. 5403 */ 5404 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5405 speedcnt++; 5406 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5407 5408 /* Set the module link speed */ 5409 switch (hw->phy.media_type) { 5410 case ixgbe_media_type_fiber_fixed: 5411 case ixgbe_media_type_fiber: 5412 ixgbe_set_rate_select_speed(hw, 5413 IXGBE_LINK_SPEED_10GB_FULL); 5414 break; 5415 case ixgbe_media_type_fiber_qsfp: 5416 /* QSFP module automatically detects MAC link speed */ 5417 break; 5418 default: 5419 DEBUGOUT("Unexpected media type.\n"); 5420 break; 5421 } 5422 5423 /* Allow module to change analog characteristics (1G->10G) */ 5424 msec_delay(40); 5425 5426 status = ixgbe_setup_mac_link(hw, 5427 IXGBE_LINK_SPEED_10GB_FULL, 5428 autoneg_wait_to_complete); 5429 if (status != IXGBE_SUCCESS) 5430 return status; 5431 5432 /* Flap the Tx laser if it has not already been done */ 5433 ixgbe_flap_tx_laser(hw); 5434 5435 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 5436 * Section 73.10.2, we may have to wait up to 500ms if KR is 5437 * attempted. 82599 uses the same timing for 10g SFI. 5438 */ 5439 for (i = 0; i < 5; i++) { 5440 /* Wait for the link partner to also set speed */ 5441 msec_delay(100); 5442 5443 /* If we have link, just jump out */ 5444 status = ixgbe_check_link(hw, &link_speed, 5445 &link_up, FALSE); 5446 if (status != IXGBE_SUCCESS) 5447 return status; 5448 5449 if (link_up) 5450 goto out; 5451 } 5452 } 5453 5454 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5455 speedcnt++; 5456 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5457 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5458 5459 /* Set the module link speed */ 5460 switch (hw->phy.media_type) { 5461 case ixgbe_media_type_fiber_fixed: 5462 case ixgbe_media_type_fiber: 5463 ixgbe_set_rate_select_speed(hw, 5464 IXGBE_LINK_SPEED_1GB_FULL); 5465 break; 5466 case ixgbe_media_type_fiber_qsfp: 5467 /* QSFP module automatically detects link speed */ 5468 break; 5469 default: 5470 DEBUGOUT("Unexpected media type.\n"); 5471 break; 5472 } 5473 5474 /* Allow module to change analog characteristics (10G->1G) */ 5475 msec_delay(40); 5476 5477 status = ixgbe_setup_mac_link(hw, 5478 IXGBE_LINK_SPEED_1GB_FULL, 5479 autoneg_wait_to_complete); 5480 if (status != IXGBE_SUCCESS) 5481 return status; 5482 5483 /* Flap the Tx laser if it has not already been done */ 5484 ixgbe_flap_tx_laser(hw); 5485 5486 /* Wait for the link partner to also set speed */ 5487 msec_delay(100); 5488 5489 /* If we have link, just jump out */ 5490 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 5491 if (status != IXGBE_SUCCESS) 5492 return status; 5493 5494 if (link_up) 5495 goto out; 5496 } 5497 5498 if (speed == 0) { 5499 /* Disable the Tx laser for media none */ 5500 ixgbe_disable_tx_laser(hw); 5501 5502 goto out; 5503 } 5504 5505 /* We didn't get link. Configure back to the highest speed we tried, 5506 * (if there was more than one). We call ourselves back with just the 5507 * single highest speed that the user requested. 5508 */ 5509 if (speedcnt > 1) 5510 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 5511 highest_link_speed, 5512 autoneg_wait_to_complete); 5513 5514 out: 5515 /* Set autoneg_advertised value based on input link speed */ 5516 hw->phy.autoneg_advertised = 0; 5517 5518 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 5519 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 5520 5521 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 5522 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 5523 5524 return status; 5525 } 5526 5527 /** 5528 * ixgbe_set_soft_rate_select_speed - Set module link speed 5529 * @hw: pointer to hardware structure 5530 * @speed: link speed to set 5531 * 5532 * Set module link speed via the soft rate select. 5533 */ 5534 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 5535 ixgbe_link_speed speed) 5536 { 5537 s32 status; 5538 u8 rs, eeprom_data; 5539 5540 switch (speed) { 5541 case IXGBE_LINK_SPEED_10GB_FULL: 5542 /* one bit mask same as setting on */ 5543 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 5544 break; 5545 case IXGBE_LINK_SPEED_1GB_FULL: 5546 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 5547 break; 5548 default: 5549 DEBUGOUT("Invalid fixed module speed\n"); 5550 return; 5551 } 5552 5553 /* Set RS0 */ 5554 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5555 IXGBE_I2C_EEPROM_DEV_ADDR2, 5556 &eeprom_data); 5557 if (status) { 5558 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 5559 goto out; 5560 } 5561 5562 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5563 5564 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5565 IXGBE_I2C_EEPROM_DEV_ADDR2, 5566 eeprom_data); 5567 if (status) { 5568 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 5569 goto out; 5570 } 5571 5572 /* Set RS1 */ 5573 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5574 IXGBE_I2C_EEPROM_DEV_ADDR2, 5575 &eeprom_data); 5576 if (status) { 5577 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 5578 goto out; 5579 } 5580 5581 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5582 5583 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5584 IXGBE_I2C_EEPROM_DEV_ADDR2, 5585 eeprom_data); 5586 if (status) { 5587 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 5588 goto out; 5589 } 5590 out: 5591 return; 5592 } 5593
Indexes created Wed Sep 24 02:09:48 GMT 2025