ixgbe_common.c revision 1.9
1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 282289 2015-04-30 22:53:27Z erj $*/ 34 /*$NetBSD: ixgbe_common.c,v 1.9 2016/12/01 06:56:28 msaitoh Exp $*/ 35 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 #include "ixgbe_dcb.h" 39 #include "ixgbe_dcb_82599.h" 40 #include "ixgbe_api.h" 41 42 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 43 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 44 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 45 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 46 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 47 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 48 u16 count); 49 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 50 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 51 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 52 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 53 54 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 55 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 56 u16 *san_mac_offset); 57 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 58 u16 words, u16 *data); 59 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 60 u16 words, u16 *data); 61 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 62 u16 offset); 63 64 /** 65 * ixgbe_init_ops_generic - Inits function ptrs 66 * @hw: pointer to the hardware structure 67 * 68 * Initialize the function pointers. 69 **/ 70 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 71 { 72 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 73 struct ixgbe_mac_info *mac = &hw->mac; 74 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 75 76 DEBUGFUNC("ixgbe_init_ops_generic"); 77 78 /* EEPROM */ 79 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 80 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 81 if (eec & IXGBE_EEC_PRES) { 82 eeprom->ops.read = ixgbe_read_eerd_generic; 83 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 84 } else { 85 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 86 eeprom->ops.read_buffer = 87 ixgbe_read_eeprom_buffer_bit_bang_generic; 88 } 89 eeprom->ops.write = ixgbe_write_eeprom_generic; 90 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 91 eeprom->ops.validate_checksum = 92 ixgbe_validate_eeprom_checksum_generic; 93 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 94 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 95 96 /* MAC */ 97 mac->ops.init_hw = ixgbe_init_hw_generic; 98 mac->ops.reset_hw = NULL; 99 mac->ops.start_hw = ixgbe_start_hw_generic; 100 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 101 mac->ops.get_media_type = NULL; 102 mac->ops.get_supported_physical_layer = NULL; 103 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 104 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 105 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 106 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 107 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 108 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 109 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 110 mac->ops.prot_autoc_read = prot_autoc_read_generic; 111 mac->ops.prot_autoc_write = prot_autoc_write_generic; 112 113 /* LEDs */ 114 mac->ops.led_on = ixgbe_led_on_generic; 115 mac->ops.led_off = ixgbe_led_off_generic; 116 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 117 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 118 119 /* RAR, Multicast, VLAN */ 120 mac->ops.set_rar = ixgbe_set_rar_generic; 121 mac->ops.clear_rar = ixgbe_clear_rar_generic; 122 mac->ops.insert_mac_addr = NULL; 123 mac->ops.set_vmdq = NULL; 124 mac->ops.clear_vmdq = NULL; 125 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 126 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 127 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 128 mac->ops.enable_mc = ixgbe_enable_mc_generic; 129 mac->ops.disable_mc = ixgbe_disable_mc_generic; 130 mac->ops.clear_vfta = NULL; 131 mac->ops.set_vfta = NULL; 132 mac->ops.set_vlvf = NULL; 133 mac->ops.init_uta_tables = NULL; 134 mac->ops.enable_rx = ixgbe_enable_rx_generic; 135 mac->ops.disable_rx = ixgbe_disable_rx_generic; 136 137 /* Flow Control */ 138 mac->ops.fc_enable = ixgbe_fc_enable_generic; 139 mac->ops.setup_fc = ixgbe_setup_fc_generic; 140 141 /* Link */ 142 mac->ops.get_link_capabilities = NULL; 143 mac->ops.setup_link = NULL; 144 mac->ops.check_link = NULL; 145 mac->ops.dmac_config = NULL; 146 mac->ops.dmac_update_tcs = NULL; 147 mac->ops.dmac_config_tcs = NULL; 148 149 return IXGBE_SUCCESS; 150 } 151 152 /** 153 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 154 * of flow control 155 * @hw: pointer to hardware structure 156 * 157 * This function returns TRUE if the device supports flow control 158 * autonegotiation, and FALSE if it does not. 159 * 160 **/ 161 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 162 { 163 bool supported = FALSE; 164 ixgbe_link_speed speed; 165 bool link_up; 166 167 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 168 169 switch (hw->phy.media_type) { 170 case ixgbe_media_type_fiber_fixed: 171 case ixgbe_media_type_fiber_qsfp: 172 case ixgbe_media_type_fiber: 173 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 174 /* if link is down, assume supported */ 175 if (link_up) 176 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 177 TRUE : FALSE; 178 else 179 supported = TRUE; 180 break; 181 case ixgbe_media_type_backplane: 182 supported = TRUE; 183 break; 184 case ixgbe_media_type_copper: 185 /* only some copper devices support flow control autoneg */ 186 switch (hw->device_id) { 187 case IXGBE_DEV_ID_82599_T3_LOM: 188 case IXGBE_DEV_ID_X540T: 189 case IXGBE_DEV_ID_X540T1: 190 case IXGBE_DEV_ID_X540_BYPASS: 191 case IXGBE_DEV_ID_X550T: 192 case IXGBE_DEV_ID_X550EM_X_10G_T: 193 supported = TRUE; 194 break; 195 default: 196 supported = FALSE; 197 } 198 default: 199 break; 200 } 201 202 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 203 "Device %x does not support flow control autoneg", 204 hw->device_id); 205 return supported; 206 } 207 208 /** 209 * ixgbe_setup_fc_generic - Set up flow control 210 * @hw: pointer to hardware structure 211 * 212 * Called at init time to set up flow control. 213 **/ 214 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 215 { 216 s32 ret_val = IXGBE_SUCCESS; 217 u32 reg = 0, reg_bp = 0; 218 u16 reg_cu = 0; 219 bool locked = FALSE; 220 221 DEBUGFUNC("ixgbe_setup_fc_generic"); 222 223 /* Validate the requested mode */ 224 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 225 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 226 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 227 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 228 goto out; 229 } 230 231 /* 232 * 10gig parts do not have a word in the EEPROM to determine the 233 * default flow control setting, so we explicitly set it to full. 234 */ 235 if (hw->fc.requested_mode == ixgbe_fc_default) 236 hw->fc.requested_mode = ixgbe_fc_full; 237 238 /* 239 * Set up the 1G and 10G flow control advertisement registers so the 240 * HW will be able to do fc autoneg once the cable is plugged in. If 241 * we link at 10G, the 1G advertisement is harmless and vice versa. 242 */ 243 switch (hw->phy.media_type) { 244 case ixgbe_media_type_backplane: 245 /* some MAC's need RMW protection on AUTOC */ 246 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 247 if (ret_val != IXGBE_SUCCESS) 248 goto out; 249 250 /* only backplane uses autoc so fall though */ 251 case ixgbe_media_type_fiber_fixed: 252 case ixgbe_media_type_fiber_qsfp: 253 case ixgbe_media_type_fiber: 254 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 255 256 break; 257 case ixgbe_media_type_copper: 258 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 259 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 260 break; 261 default: 262 break; 263 } 264 265 /* 266 * The possible values of fc.requested_mode are: 267 * 0: Flow control is completely disabled 268 * 1: Rx flow control is enabled (we can receive pause frames, 269 * but not send pause frames). 270 * 2: Tx flow control is enabled (we can send pause frames but 271 * we do not support receiving pause frames). 272 * 3: Both Rx and Tx flow control (symmetric) are enabled. 273 * other: Invalid. 274 */ 275 switch (hw->fc.requested_mode) { 276 case ixgbe_fc_none: 277 /* Flow control completely disabled by software override. */ 278 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 279 if (hw->phy.media_type == ixgbe_media_type_backplane) 280 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 281 IXGBE_AUTOC_ASM_PAUSE); 282 else if (hw->phy.media_type == ixgbe_media_type_copper) 283 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 284 break; 285 case ixgbe_fc_tx_pause: 286 /* 287 * Tx Flow control is enabled, and Rx Flow control is 288 * disabled by software override. 289 */ 290 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 291 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 292 if (hw->phy.media_type == ixgbe_media_type_backplane) { 293 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 294 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 295 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 296 reg_cu |= IXGBE_TAF_ASM_PAUSE; 297 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 298 } 299 break; 300 case ixgbe_fc_rx_pause: 301 /* 302 * Rx Flow control is enabled and Tx Flow control is 303 * disabled by software override. Since there really 304 * isn't a way to advertise that we are capable of RX 305 * Pause ONLY, we will advertise that we support both 306 * symmetric and asymmetric Rx PAUSE, as such we fall 307 * through to the fc_full statement. Later, we will 308 * disable the adapter's ability to send PAUSE frames. 309 */ 310 case ixgbe_fc_full: 311 /* Flow control (both Rx and Tx) is enabled by SW override. */ 312 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 313 if (hw->phy.media_type == ixgbe_media_type_backplane) 314 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 315 IXGBE_AUTOC_ASM_PAUSE; 316 else if (hw->phy.media_type == ixgbe_media_type_copper) 317 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 318 break; 319 default: 320 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 321 "Flow control param set incorrectly\n"); 322 ret_val = IXGBE_ERR_CONFIG; 323 goto out; 324 break; 325 } 326 327 if (hw->mac.type < ixgbe_mac_X540) { 328 /* 329 * Enable auto-negotiation between the MAC & PHY; 330 * the MAC will advertise clause 37 flow control. 331 */ 332 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 333 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 334 335 /* Disable AN timeout */ 336 if (hw->fc.strict_ieee) 337 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 338 339 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 340 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 341 } 342 343 /* 344 * AUTOC restart handles negotiation of 1G and 10G on backplane 345 * and copper. There is no need to set the PCS1GCTL register. 346 * 347 */ 348 if (hw->phy.media_type == ixgbe_media_type_backplane) { 349 reg_bp |= IXGBE_AUTOC_AN_RESTART; 350 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 351 if (ret_val) 352 goto out; 353 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 354 (ixgbe_device_supports_autoneg_fc(hw))) { 355 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 356 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 357 } 358 359 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 360 out: 361 return ret_val; 362 } 363 364 /** 365 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 366 * @hw: pointer to hardware structure 367 * 368 * Starts the hardware by filling the bus info structure and media type, clears 369 * all on chip counters, initializes receive address registers, multicast 370 * table, VLAN filter table, calls routine to set up link and flow control 371 * settings, and leaves transmit and receive units disabled and uninitialized 372 **/ 373 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 374 { 375 s32 ret_val; 376 u32 ctrl_ext; 377 378 DEBUGFUNC("ixgbe_start_hw_generic"); 379 380 /* Set the media type */ 381 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 382 383 /* PHY ops initialization must be done in reset_hw() */ 384 385 /* Clear the VLAN filter table */ 386 hw->mac.ops.clear_vfta(hw); 387 388 /* Clear statistics registers */ 389 hw->mac.ops.clear_hw_cntrs(hw); 390 391 /* Set No Snoop Disable */ 392 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 393 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 394 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 395 IXGBE_WRITE_FLUSH(hw); 396 397 /* Setup flow control */ 398 ret_val = ixgbe_setup_fc(hw); 399 if (ret_val != IXGBE_SUCCESS) 400 goto out; 401 402 /* Clear adapter stopped flag */ 403 hw->adapter_stopped = FALSE; 404 405 out: 406 return ret_val; 407 } 408 409 /** 410 * ixgbe_start_hw_gen2 - Init sequence for common device family 411 * @hw: pointer to hw structure 412 * 413 * Performs the init sequence common to the second generation 414 * of 10 GbE devices. 415 * Devices in the second generation: 416 * 82599 417 * X540 418 **/ 419 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 420 { 421 u32 i; 422 u32 regval; 423 424 /* Clear the rate limiters */ 425 for (i = 0; i < hw->mac.max_tx_queues; i++) { 426 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 427 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 428 } 429 IXGBE_WRITE_FLUSH(hw); 430 431 /* Disable relaxed ordering */ 432 for (i = 0; i < hw->mac.max_tx_queues; i++) { 433 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 434 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 435 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 436 } 437 438 for (i = 0; i < hw->mac.max_rx_queues; i++) { 439 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 440 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 441 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 442 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 443 } 444 445 return IXGBE_SUCCESS; 446 } 447 448 /** 449 * ixgbe_init_hw_generic - Generic hardware initialization 450 * @hw: pointer to hardware structure 451 * 452 * Initialize the hardware by resetting the hardware, filling the bus info 453 * structure and media type, clears all on chip counters, initializes receive 454 * address registers, multicast table, VLAN filter table, calls routine to set 455 * up link and flow control settings, and leaves transmit and receive units 456 * disabled and uninitialized 457 **/ 458 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 459 { 460 s32 status; 461 462 DEBUGFUNC("ixgbe_init_hw_generic"); 463 464 /* Reset the hardware */ 465 status = hw->mac.ops.reset_hw(hw); 466 467 if (status == IXGBE_SUCCESS) { 468 /* Start the HW */ 469 status = hw->mac.ops.start_hw(hw); 470 } 471 472 return status; 473 } 474 475 /** 476 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 477 * @hw: pointer to hardware structure 478 * 479 * Clears all hardware statistics counters by reading them from the hardware 480 * Statistics counters are clear on read. 481 **/ 482 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 483 { 484 u16 i = 0; 485 486 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 487 488 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 489 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 490 IXGBE_READ_REG(hw, IXGBE_ERRBC); 491 IXGBE_READ_REG(hw, IXGBE_MSPDC); 492 for (i = 0; i < 8; i++) 493 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 494 495 IXGBE_READ_REG(hw, IXGBE_MLFC); 496 IXGBE_READ_REG(hw, IXGBE_MRFC); 497 IXGBE_READ_REG(hw, IXGBE_RLEC); 498 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 499 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 500 if (hw->mac.type >= ixgbe_mac_82599EB) { 501 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 502 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 503 } else { 504 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 505 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 506 } 507 508 for (i = 0; i < 8; i++) { 509 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 510 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 511 if (hw->mac.type >= ixgbe_mac_82599EB) { 512 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 513 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 514 } else { 515 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 516 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 517 } 518 } 519 if (hw->mac.type >= ixgbe_mac_82599EB) 520 for (i = 0; i < 8; i++) 521 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 522 IXGBE_READ_REG(hw, IXGBE_PRC64); 523 IXGBE_READ_REG(hw, IXGBE_PRC127); 524 IXGBE_READ_REG(hw, IXGBE_PRC255); 525 IXGBE_READ_REG(hw, IXGBE_PRC511); 526 IXGBE_READ_REG(hw, IXGBE_PRC1023); 527 IXGBE_READ_REG(hw, IXGBE_PRC1522); 528 IXGBE_READ_REG(hw, IXGBE_GPRC); 529 IXGBE_READ_REG(hw, IXGBE_BPRC); 530 IXGBE_READ_REG(hw, IXGBE_MPRC); 531 IXGBE_READ_REG(hw, IXGBE_GPTC); 532 IXGBE_READ_REG(hw, IXGBE_GORCL); 533 IXGBE_READ_REG(hw, IXGBE_GORCH); 534 IXGBE_READ_REG(hw, IXGBE_GOTCL); 535 IXGBE_READ_REG(hw, IXGBE_GOTCH); 536 if (hw->mac.type == ixgbe_mac_82598EB) 537 for (i = 0; i < 8; i++) 538 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 539 IXGBE_READ_REG(hw, IXGBE_RUC); 540 IXGBE_READ_REG(hw, IXGBE_RFC); 541 IXGBE_READ_REG(hw, IXGBE_ROC); 542 IXGBE_READ_REG(hw, IXGBE_RJC); 543 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 544 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 545 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 546 IXGBE_READ_REG(hw, IXGBE_TORL); 547 IXGBE_READ_REG(hw, IXGBE_TORH); 548 IXGBE_READ_REG(hw, IXGBE_TPR); 549 IXGBE_READ_REG(hw, IXGBE_TPT); 550 IXGBE_READ_REG(hw, IXGBE_PTC64); 551 IXGBE_READ_REG(hw, IXGBE_PTC127); 552 IXGBE_READ_REG(hw, IXGBE_PTC255); 553 IXGBE_READ_REG(hw, IXGBE_PTC511); 554 IXGBE_READ_REG(hw, IXGBE_PTC1023); 555 IXGBE_READ_REG(hw, IXGBE_PTC1522); 556 IXGBE_READ_REG(hw, IXGBE_MPTC); 557 IXGBE_READ_REG(hw, IXGBE_BPTC); 558 for (i = 0; i < 16; i++) { 559 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 560 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 561 if (hw->mac.type >= ixgbe_mac_82599EB) { 562 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 563 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 564 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 565 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 566 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 567 } else { 568 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 569 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 570 } 571 } 572 573 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 574 if (hw->phy.id == 0) 575 ixgbe_identify_phy(hw); 576 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 577 IXGBE_MDIO_PCS_DEV_TYPE, &i); 578 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 579 IXGBE_MDIO_PCS_DEV_TYPE, &i); 580 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 581 IXGBE_MDIO_PCS_DEV_TYPE, &i); 582 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 583 IXGBE_MDIO_PCS_DEV_TYPE, &i); 584 } 585 586 return IXGBE_SUCCESS; 587 } 588 589 /** 590 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 591 * @hw: pointer to hardware structure 592 * @pba_num: stores the part number string from the EEPROM 593 * @pba_num_size: part number string buffer length 594 * 595 * Reads the part number string from the EEPROM. 596 **/ 597 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 598 u32 pba_num_size) 599 { 600 s32 ret_val; 601 u16 data; 602 u16 pba_ptr; 603 u16 offset; 604 u16 length; 605 606 DEBUGFUNC("ixgbe_read_pba_string_generic"); 607 608 if (pba_num == NULL) { 609 DEBUGOUT("PBA string buffer was null\n"); 610 return IXGBE_ERR_INVALID_ARGUMENT; 611 } 612 613 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 614 if (ret_val) { 615 DEBUGOUT("NVM Read Error\n"); 616 return ret_val; 617 } 618 619 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 620 if (ret_val) { 621 DEBUGOUT("NVM Read Error\n"); 622 return ret_val; 623 } 624 625 /* 626 * if data is not ptr guard the PBA must be in legacy format which 627 * means pba_ptr is actually our second data word for the PBA number 628 * and we can decode it into an ascii string 629 */ 630 if (data != IXGBE_PBANUM_PTR_GUARD) { 631 DEBUGOUT("NVM PBA number is not stored as string\n"); 632 633 /* we will need 11 characters to store the PBA */ 634 if (pba_num_size < 11) { 635 DEBUGOUT("PBA string buffer too small\n"); 636 return IXGBE_ERR_NO_SPACE; 637 } 638 639 /* extract hex string from data and pba_ptr */ 640 pba_num[0] = (data >> 12) & 0xF; 641 pba_num[1] = (data >> 8) & 0xF; 642 pba_num[2] = (data >> 4) & 0xF; 643 pba_num[3] = data & 0xF; 644 pba_num[4] = (pba_ptr >> 12) & 0xF; 645 pba_num[5] = (pba_ptr >> 8) & 0xF; 646 pba_num[6] = '-'; 647 pba_num[7] = 0; 648 pba_num[8] = (pba_ptr >> 4) & 0xF; 649 pba_num[9] = pba_ptr & 0xF; 650 651 /* put a null character on the end of our string */ 652 pba_num[10] = '\0'; 653 654 /* switch all the data but the '-' to hex char */ 655 for (offset = 0; offset < 10; offset++) { 656 if (pba_num[offset] < 0xA) 657 pba_num[offset] += '0'; 658 else if (pba_num[offset] < 0x10) 659 pba_num[offset] += 'A' - 0xA; 660 } 661 662 return IXGBE_SUCCESS; 663 } 664 665 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 666 if (ret_val) { 667 DEBUGOUT("NVM Read Error\n"); 668 return ret_val; 669 } 670 671 if (length == 0xFFFF || length == 0) { 672 DEBUGOUT("NVM PBA number section invalid length\n"); 673 return IXGBE_ERR_PBA_SECTION; 674 } 675 676 /* check if pba_num buffer is big enough */ 677 if (pba_num_size < (((u32)length * 2) - 1)) { 678 DEBUGOUT("PBA string buffer too small\n"); 679 return IXGBE_ERR_NO_SPACE; 680 } 681 682 /* trim pba length from start of string */ 683 pba_ptr++; 684 length--; 685 686 for (offset = 0; offset < length; offset++) { 687 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 688 if (ret_val) { 689 DEBUGOUT("NVM Read Error\n"); 690 return ret_val; 691 } 692 pba_num[offset * 2] = (u8)(data >> 8); 693 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 694 } 695 pba_num[offset * 2] = '\0'; 696 697 return IXGBE_SUCCESS; 698 } 699 700 /** 701 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 702 * @hw: pointer to hardware structure 703 * @pba_num: stores the part number from the EEPROM 704 * 705 * Reads the part number from the EEPROM. 706 **/ 707 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 708 { 709 s32 ret_val; 710 u16 data; 711 712 DEBUGFUNC("ixgbe_read_pba_num_generic"); 713 714 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 715 if (ret_val) { 716 DEBUGOUT("NVM Read Error\n"); 717 return ret_val; 718 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 719 DEBUGOUT("NVM Not supported\n"); 720 return IXGBE_NOT_IMPLEMENTED; 721 } 722 *pba_num = (u32)(data << 16); 723 724 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 725 if (ret_val) { 726 DEBUGOUT("NVM Read Error\n"); 727 return ret_val; 728 } 729 *pba_num |= data; 730 731 return IXGBE_SUCCESS; 732 } 733 734 /** 735 * ixgbe_read_pba_raw 736 * @hw: pointer to the HW structure 737 * @eeprom_buf: optional pointer to EEPROM image 738 * @eeprom_buf_size: size of EEPROM image in words 739 * @max_pba_block_size: PBA block size limit 740 * @pba: pointer to output PBA structure 741 * 742 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 743 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 744 * 745 **/ 746 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 747 u32 eeprom_buf_size, u16 max_pba_block_size, 748 struct ixgbe_pba *pba) 749 { 750 s32 ret_val; 751 u16 pba_block_size; 752 753 if (pba == NULL) 754 return IXGBE_ERR_PARAM; 755 756 if (eeprom_buf == NULL) { 757 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 758 &pba->word[0]); 759 if (ret_val) 760 return ret_val; 761 } else { 762 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 763 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 764 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 765 } else { 766 return IXGBE_ERR_PARAM; 767 } 768 } 769 770 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 771 if (pba->pba_block == NULL) 772 return IXGBE_ERR_PARAM; 773 774 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 775 eeprom_buf_size, 776 &pba_block_size); 777 if (ret_val) 778 return ret_val; 779 780 if (pba_block_size > max_pba_block_size) 781 return IXGBE_ERR_PARAM; 782 783 if (eeprom_buf == NULL) { 784 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 785 pba_block_size, 786 pba->pba_block); 787 if (ret_val) 788 return ret_val; 789 } else { 790 if (eeprom_buf_size > (u32)(pba->word[1] + 791 pba_block_size)) { 792 memcpy(pba->pba_block, 793 &eeprom_buf[pba->word[1]], 794 pba_block_size * sizeof(u16)); 795 } else { 796 return IXGBE_ERR_PARAM; 797 } 798 } 799 } 800 801 return IXGBE_SUCCESS; 802 } 803 804 /** 805 * ixgbe_write_pba_raw 806 * @hw: pointer to the HW structure 807 * @eeprom_buf: optional pointer to EEPROM image 808 * @eeprom_buf_size: size of EEPROM image in words 809 * @pba: pointer to PBA structure 810 * 811 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 812 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 813 * 814 **/ 815 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 816 u32 eeprom_buf_size, struct ixgbe_pba *pba) 817 { 818 s32 ret_val; 819 820 if (pba == NULL) 821 return IXGBE_ERR_PARAM; 822 823 if (eeprom_buf == NULL) { 824 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 825 &pba->word[0]); 826 if (ret_val) 827 return ret_val; 828 } else { 829 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 830 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 831 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 832 } else { 833 return IXGBE_ERR_PARAM; 834 } 835 } 836 837 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 838 if (pba->pba_block == NULL) 839 return IXGBE_ERR_PARAM; 840 841 if (eeprom_buf == NULL) { 842 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 843 pba->pba_block[0], 844 pba->pba_block); 845 if (ret_val) 846 return ret_val; 847 } else { 848 if (eeprom_buf_size > (u32)(pba->word[1] + 849 pba->pba_block[0])) { 850 memcpy(&eeprom_buf[pba->word[1]], 851 pba->pba_block, 852 pba->pba_block[0] * sizeof(u16)); 853 } else { 854 return IXGBE_ERR_PARAM; 855 } 856 } 857 } 858 859 return IXGBE_SUCCESS; 860 } 861 862 /** 863 * ixgbe_get_pba_block_size 864 * @hw: pointer to the HW structure 865 * @eeprom_buf: optional pointer to EEPROM image 866 * @eeprom_buf_size: size of EEPROM image in words 867 * @pba_data_size: pointer to output variable 868 * 869 * Returns the size of the PBA block in words. Function operates on EEPROM 870 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 871 * EEPROM device. 872 * 873 **/ 874 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 875 u32 eeprom_buf_size, u16 *pba_block_size) 876 { 877 s32 ret_val; 878 u16 pba_word[2]; 879 u16 length; 880 881 DEBUGFUNC("ixgbe_get_pba_block_size"); 882 883 if (eeprom_buf == NULL) { 884 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 885 &pba_word[0]); 886 if (ret_val) 887 return ret_val; 888 } else { 889 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 890 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 891 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 892 } else { 893 return IXGBE_ERR_PARAM; 894 } 895 } 896 897 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 898 if (eeprom_buf == NULL) { 899 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 900 &length); 901 if (ret_val) 902 return ret_val; 903 } else { 904 if (eeprom_buf_size > pba_word[1]) 905 length = eeprom_buf[pba_word[1] + 0]; 906 else 907 return IXGBE_ERR_PARAM; 908 } 909 910 if (length == 0xFFFF || length == 0) 911 return IXGBE_ERR_PBA_SECTION; 912 } else { 913 /* PBA number in legacy format, there is no PBA Block. */ 914 length = 0; 915 } 916 917 if (pba_block_size != NULL) 918 *pba_block_size = length; 919 920 return IXGBE_SUCCESS; 921 } 922 923 /** 924 * ixgbe_get_mac_addr_generic - Generic get MAC address 925 * @hw: pointer to hardware structure 926 * @mac_addr: Adapter MAC address 927 * 928 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 929 * A reset of the adapter must be performed prior to calling this function 930 * in order for the MAC address to have been loaded from the EEPROM into RAR0 931 **/ 932 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 933 { 934 u32 rar_high; 935 u32 rar_low; 936 u16 i; 937 938 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 939 940 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 941 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 942 943 for (i = 0; i < 4; i++) 944 mac_addr[i] = (u8)(rar_low >> (i*8)); 945 946 for (i = 0; i < 2; i++) 947 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 948 949 return IXGBE_SUCCESS; 950 } 951 952 /** 953 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 954 * @hw: pointer to hardware structure 955 * @link_status: the link status returned by the PCI config space 956 * 957 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 958 **/ 959 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 960 { 961 struct ixgbe_mac_info *mac = &hw->mac; 962 963 if (hw->bus.type == ixgbe_bus_type_unknown) 964 hw->bus.type = ixgbe_bus_type_pci_express; 965 966 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 967 case IXGBE_PCI_LINK_WIDTH_1: 968 hw->bus.width = ixgbe_bus_width_pcie_x1; 969 break; 970 case IXGBE_PCI_LINK_WIDTH_2: 971 hw->bus.width = ixgbe_bus_width_pcie_x2; 972 break; 973 case IXGBE_PCI_LINK_WIDTH_4: 974 hw->bus.width = ixgbe_bus_width_pcie_x4; 975 break; 976 case IXGBE_PCI_LINK_WIDTH_8: 977 hw->bus.width = ixgbe_bus_width_pcie_x8; 978 break; 979 default: 980 hw->bus.width = ixgbe_bus_width_unknown; 981 break; 982 } 983 984 switch (link_status & IXGBE_PCI_LINK_SPEED) { 985 case IXGBE_PCI_LINK_SPEED_2500: 986 hw->bus.speed = ixgbe_bus_speed_2500; 987 break; 988 case IXGBE_PCI_LINK_SPEED_5000: 989 hw->bus.speed = ixgbe_bus_speed_5000; 990 break; 991 case IXGBE_PCI_LINK_SPEED_8000: 992 hw->bus.speed = ixgbe_bus_speed_8000; 993 break; 994 default: 995 hw->bus.speed = ixgbe_bus_speed_unknown; 996 break; 997 } 998 999 mac->ops.set_lan_id(hw); 1000 } 1001 1002 /** 1003 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1004 * @hw: pointer to hardware structure 1005 * 1006 * Gets the PCI bus info (speed, width, type) then calls helper function to 1007 * store this data within the ixgbe_hw structure. 1008 **/ 1009 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1010 { 1011 u16 link_status; 1012 1013 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1014 1015 /* Get the negotiated link width and speed from PCI config space */ 1016 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 1017 1018 ixgbe_set_pci_config_data_generic(hw, link_status); 1019 1020 return IXGBE_SUCCESS; 1021 } 1022 1023 /** 1024 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1025 * @hw: pointer to the HW structure 1026 * 1027 * Determines the LAN function id by reading memory-mapped registers 1028 * and swaps the port value if requested. 1029 **/ 1030 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1031 { 1032 struct ixgbe_bus_info *bus = &hw->bus; 1033 u32 reg; 1034 1035 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1036 1037 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1038 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1039 bus->lan_id = bus->func; 1040 1041 /* check for a port swap */ 1042 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 1043 if (reg & IXGBE_FACTPS_LFS) 1044 bus->func ^= 0x1; 1045 } 1046 1047 /** 1048 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1049 * @hw: pointer to hardware structure 1050 * 1051 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1052 * disables transmit and receive units. The adapter_stopped flag is used by 1053 * the shared code and drivers to determine if the adapter is in a stopped 1054 * state and should not touch the hardware. 1055 **/ 1056 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1057 { 1058 u32 reg_val; 1059 u16 i; 1060 1061 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1062 1063 /* 1064 * Set the adapter_stopped flag so other driver functions stop touching 1065 * the hardware 1066 */ 1067 hw->adapter_stopped = TRUE; 1068 1069 /* Disable the receive unit */ 1070 ixgbe_disable_rx(hw); 1071 1072 /* Clear interrupt mask to stop interrupts from being generated */ 1073 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 1074 1075 /* Clear any pending interrupts, flush previous writes */ 1076 IXGBE_READ_REG(hw, IXGBE_EICR); 1077 1078 /* Disable the transmit unit. Each queue must be disabled. */ 1079 for (i = 0; i < hw->mac.max_tx_queues; i++) 1080 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1081 1082 /* Disable the receive unit by stopping each queue */ 1083 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1084 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1085 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1086 reg_val |= IXGBE_RXDCTL_SWFLSH; 1087 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1088 } 1089 1090 /* flush all queues disables */ 1091 IXGBE_WRITE_FLUSH(hw); 1092 msec_delay(2); 1093 1094 /* 1095 * Prevent the PCI-E bus from hanging by disabling PCI-E master 1096 * access and verify no pending requests 1097 */ 1098 return ixgbe_disable_pcie_master(hw); 1099 } 1100 1101 /** 1102 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1103 * @hw: pointer to hardware structure 1104 * @index: led number to turn on 1105 **/ 1106 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1107 { 1108 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1109 1110 DEBUGFUNC("ixgbe_led_on_generic"); 1111 1112 /* To turn on the LED, set mode to ON. */ 1113 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1114 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1115 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1116 IXGBE_WRITE_FLUSH(hw); 1117 1118 return IXGBE_SUCCESS; 1119 } 1120 1121 /** 1122 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1123 * @hw: pointer to hardware structure 1124 * @index: led number to turn off 1125 **/ 1126 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1127 { 1128 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1129 1130 DEBUGFUNC("ixgbe_led_off_generic"); 1131 1132 /* To turn off the LED, set mode to OFF. */ 1133 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1134 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1135 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1136 IXGBE_WRITE_FLUSH(hw); 1137 1138 return IXGBE_SUCCESS; 1139 } 1140 1141 /** 1142 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1143 * @hw: pointer to hardware structure 1144 * 1145 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1146 * ixgbe_hw struct in order to set up EEPROM access. 1147 **/ 1148 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1149 { 1150 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1151 u32 eec; 1152 u16 eeprom_size; 1153 1154 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1155 1156 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1157 eeprom->type = ixgbe_eeprom_none; 1158 /* Set default semaphore delay to 10ms which is a well 1159 * tested value */ 1160 eeprom->semaphore_delay = 10; 1161 /* Clear EEPROM page size, it will be initialized as needed */ 1162 eeprom->word_page_size = 0; 1163 1164 /* 1165 * Check for EEPROM present first. 1166 * If not present leave as none 1167 */ 1168 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1169 if (eec & IXGBE_EEC_PRES) { 1170 eeprom->type = ixgbe_eeprom_spi; 1171 1172 /* 1173 * SPI EEPROM is assumed here. This code would need to 1174 * change if a future EEPROM is not SPI. 1175 */ 1176 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1177 IXGBE_EEC_SIZE_SHIFT); 1178 eeprom->word_size = 1 << (eeprom_size + 1179 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1180 } 1181 1182 if (eec & IXGBE_EEC_ADDR_SIZE) 1183 eeprom->address_bits = 16; 1184 else 1185 eeprom->address_bits = 8; 1186 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1187 "%d\n", eeprom->type, eeprom->word_size, 1188 eeprom->address_bits); 1189 } 1190 1191 return IXGBE_SUCCESS; 1192 } 1193 1194 /** 1195 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1196 * @hw: pointer to hardware structure 1197 * @offset: offset within the EEPROM to write 1198 * @words: number of word(s) 1199 * @data: 16 bit word(s) to write to EEPROM 1200 * 1201 * Reads 16 bit word(s) from EEPROM through bit-bang method 1202 **/ 1203 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1204 u16 words, u16 *data) 1205 { 1206 s32 status = IXGBE_SUCCESS; 1207 u16 i, count; 1208 1209 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1210 1211 hw->eeprom.ops.init_params(hw); 1212 1213 if (words == 0) { 1214 status = IXGBE_ERR_INVALID_ARGUMENT; 1215 goto out; 1216 } 1217 1218 if (offset + words > hw->eeprom.word_size) { 1219 status = IXGBE_ERR_EEPROM; 1220 goto out; 1221 } 1222 1223 /* 1224 * The EEPROM page size cannot be queried from the chip. We do lazy 1225 * initialization. It is worth to do that when we write large buffer. 1226 */ 1227 if ((hw->eeprom.word_page_size == 0) && 1228 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1229 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1230 1231 /* 1232 * We cannot hold synchronization semaphores for too long 1233 * to avoid other entity starvation. However it is more efficient 1234 * to read in bursts than synchronizing access for each word. 1235 */ 1236 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1237 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1238 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1239 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1240 count, &data[i]); 1241 1242 if (status != IXGBE_SUCCESS) 1243 break; 1244 } 1245 1246 out: 1247 return status; 1248 } 1249 1250 /** 1251 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1252 * @hw: pointer to hardware structure 1253 * @offset: offset within the EEPROM to be written to 1254 * @words: number of word(s) 1255 * @data: 16 bit word(s) to be written to the EEPROM 1256 * 1257 * If ixgbe_eeprom_update_checksum is not called after this function, the 1258 * EEPROM will most likely contain an invalid checksum. 1259 **/ 1260 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1261 u16 words, u16 *data) 1262 { 1263 s32 status; 1264 u16 word; 1265 u16 page_size; 1266 u16 i; 1267 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1268 1269 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1270 1271 /* Prepare the EEPROM for writing */ 1272 status = ixgbe_acquire_eeprom(hw); 1273 1274 if (status == IXGBE_SUCCESS) { 1275 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1276 ixgbe_release_eeprom(hw); 1277 status = IXGBE_ERR_EEPROM; 1278 } 1279 } 1280 1281 if (status == IXGBE_SUCCESS) { 1282 for (i = 0; i < words; i++) { 1283 ixgbe_standby_eeprom(hw); 1284 1285 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1286 ixgbe_shift_out_eeprom_bits(hw, 1287 IXGBE_EEPROM_WREN_OPCODE_SPI, 1288 IXGBE_EEPROM_OPCODE_BITS); 1289 1290 ixgbe_standby_eeprom(hw); 1291 1292 /* 1293 * Some SPI eeproms use the 8th address bit embedded 1294 * in the opcode 1295 */ 1296 if ((hw->eeprom.address_bits == 8) && 1297 ((offset + i) >= 128)) 1298 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1299 1300 /* Send the Write command (8-bit opcode + addr) */ 1301 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1302 IXGBE_EEPROM_OPCODE_BITS); 1303 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1304 hw->eeprom.address_bits); 1305 1306 page_size = hw->eeprom.word_page_size; 1307 1308 /* Send the data in burst via SPI*/ 1309 do { 1310 word = data[i]; 1311 word = (word >> 8) | (word << 8); 1312 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1313 1314 if (page_size == 0) 1315 break; 1316 1317 /* do not wrap around page */ 1318 if (((offset + i) & (page_size - 1)) == 1319 (page_size - 1)) 1320 break; 1321 } while (++i < words); 1322 1323 ixgbe_standby_eeprom(hw); 1324 msec_delay(10); 1325 } 1326 /* Done with writing - release the EEPROM */ 1327 ixgbe_release_eeprom(hw); 1328 } 1329 1330 return status; 1331 } 1332 1333 /** 1334 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1335 * @hw: pointer to hardware structure 1336 * @offset: offset within the EEPROM to be written to 1337 * @data: 16 bit word to be written to the EEPROM 1338 * 1339 * If ixgbe_eeprom_update_checksum is not called after this function, the 1340 * EEPROM will most likely contain an invalid checksum. 1341 **/ 1342 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1343 { 1344 s32 status; 1345 1346 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1347 1348 hw->eeprom.ops.init_params(hw); 1349 1350 if (offset >= hw->eeprom.word_size) { 1351 status = IXGBE_ERR_EEPROM; 1352 goto out; 1353 } 1354 1355 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1356 1357 out: 1358 return status; 1359 } 1360 1361 /** 1362 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1363 * @hw: pointer to hardware structure 1364 * @offset: offset within the EEPROM to be read 1365 * @data: read 16 bit words(s) from EEPROM 1366 * @words: number of word(s) 1367 * 1368 * Reads 16 bit word(s) from EEPROM through bit-bang method 1369 **/ 1370 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1371 u16 words, u16 *data) 1372 { 1373 s32 status = IXGBE_SUCCESS; 1374 u16 i, count; 1375 1376 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1377 1378 hw->eeprom.ops.init_params(hw); 1379 1380 if (words == 0) { 1381 status = IXGBE_ERR_INVALID_ARGUMENT; 1382 goto out; 1383 } 1384 1385 if (offset + words > hw->eeprom.word_size) { 1386 status = IXGBE_ERR_EEPROM; 1387 goto out; 1388 } 1389 1390 /* 1391 * We cannot hold synchronization semaphores for too long 1392 * to avoid other entity starvation. However it is more efficient 1393 * to read in bursts than synchronizing access for each word. 1394 */ 1395 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1396 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1397 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1398 1399 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1400 count, &data[i]); 1401 1402 if (status != IXGBE_SUCCESS) 1403 break; 1404 } 1405 1406 out: 1407 return status; 1408 } 1409 1410 /** 1411 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1412 * @hw: pointer to hardware structure 1413 * @offset: offset within the EEPROM to be read 1414 * @words: number of word(s) 1415 * @data: read 16 bit word(s) from EEPROM 1416 * 1417 * Reads 16 bit word(s) from EEPROM through bit-bang method 1418 **/ 1419 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1420 u16 words, u16 *data) 1421 { 1422 s32 status; 1423 u16 word_in; 1424 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1425 u16 i; 1426 1427 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1428 1429 /* Prepare the EEPROM for reading */ 1430 status = ixgbe_acquire_eeprom(hw); 1431 1432 if (status == IXGBE_SUCCESS) { 1433 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1434 ixgbe_release_eeprom(hw); 1435 status = IXGBE_ERR_EEPROM; 1436 } 1437 } 1438 1439 if (status == IXGBE_SUCCESS) { 1440 for (i = 0; i < words; i++) { 1441 ixgbe_standby_eeprom(hw); 1442 /* 1443 * Some SPI eeproms use the 8th address bit embedded 1444 * in the opcode 1445 */ 1446 if ((hw->eeprom.address_bits == 8) && 1447 ((offset + i) >= 128)) 1448 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1449 1450 /* Send the READ command (opcode + addr) */ 1451 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1452 IXGBE_EEPROM_OPCODE_BITS); 1453 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1454 hw->eeprom.address_bits); 1455 1456 /* Read the data. */ 1457 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1458 data[i] = (word_in >> 8) | (word_in << 8); 1459 } 1460 1461 /* End this read operation */ 1462 ixgbe_release_eeprom(hw); 1463 } 1464 1465 return status; 1466 } 1467 1468 /** 1469 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1470 * @hw: pointer to hardware structure 1471 * @offset: offset within the EEPROM to be read 1472 * @data: read 16 bit value from EEPROM 1473 * 1474 * Reads 16 bit value from EEPROM through bit-bang method 1475 **/ 1476 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1477 u16 *data) 1478 { 1479 s32 status; 1480 1481 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1482 1483 hw->eeprom.ops.init_params(hw); 1484 1485 if (offset >= hw->eeprom.word_size) { 1486 status = IXGBE_ERR_EEPROM; 1487 goto out; 1488 } 1489 1490 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1491 1492 out: 1493 return status; 1494 } 1495 1496 /** 1497 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1498 * @hw: pointer to hardware structure 1499 * @offset: offset of word in the EEPROM to read 1500 * @words: number of word(s) 1501 * @data: 16 bit word(s) from the EEPROM 1502 * 1503 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1504 **/ 1505 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1506 u16 words, u16 *data) 1507 { 1508 u32 eerd; 1509 s32 status = IXGBE_SUCCESS; 1510 u32 i; 1511 1512 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1513 1514 hw->eeprom.ops.init_params(hw); 1515 1516 if (words == 0) { 1517 status = IXGBE_ERR_INVALID_ARGUMENT; 1518 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1519 goto out; 1520 } 1521 1522 if (offset >= hw->eeprom.word_size) { 1523 status = IXGBE_ERR_EEPROM; 1524 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1525 goto out; 1526 } 1527 1528 for (i = 0; i < words; i++) { 1529 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1530 IXGBE_EEPROM_RW_REG_START; 1531 1532 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1533 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1534 1535 if (status == IXGBE_SUCCESS) { 1536 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1537 IXGBE_EEPROM_RW_REG_DATA); 1538 } else { 1539 DEBUGOUT("Eeprom read timed out\n"); 1540 goto out; 1541 } 1542 } 1543 out: 1544 return status; 1545 } 1546 1547 /** 1548 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1549 * @hw: pointer to hardware structure 1550 * @offset: offset within the EEPROM to be used as a scratch pad 1551 * 1552 * Discover EEPROM page size by writing marching data at given offset. 1553 * This function is called only when we are writing a new large buffer 1554 * at given offset so the data would be overwritten anyway. 1555 **/ 1556 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1557 u16 offset) 1558 { 1559 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1560 s32 status = IXGBE_SUCCESS; 1561 u16 i; 1562 1563 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1564 1565 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1566 data[i] = i; 1567 1568 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1569 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1570 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1571 hw->eeprom.word_page_size = 0; 1572 if (status != IXGBE_SUCCESS) 1573 goto out; 1574 1575 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1576 if (status != IXGBE_SUCCESS) 1577 goto out; 1578 1579 /* 1580 * When writing in burst more than the actual page size 1581 * EEPROM address wraps around current page. 1582 */ 1583 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1584 1585 DEBUGOUT1("Detected EEPROM page size = %d words.", 1586 hw->eeprom.word_page_size); 1587 out: 1588 return status; 1589 } 1590 1591 /** 1592 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1593 * @hw: pointer to hardware structure 1594 * @offset: offset of word in the EEPROM to read 1595 * @data: word read from the EEPROM 1596 * 1597 * Reads a 16 bit word from the EEPROM using the EERD register. 1598 **/ 1599 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1600 { 1601 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1602 } 1603 1604 /** 1605 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1606 * @hw: pointer to hardware structure 1607 * @offset: offset of word in the EEPROM to write 1608 * @words: number of word(s) 1609 * @data: word(s) write to the EEPROM 1610 * 1611 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1612 **/ 1613 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1614 u16 words, u16 *data) 1615 { 1616 u32 eewr; 1617 s32 status = IXGBE_SUCCESS; 1618 u16 i; 1619 1620 DEBUGFUNC("ixgbe_write_eewr_generic"); 1621 1622 hw->eeprom.ops.init_params(hw); 1623 1624 if (words == 0) { 1625 status = IXGBE_ERR_INVALID_ARGUMENT; 1626 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1627 goto out; 1628 } 1629 1630 if (offset >= hw->eeprom.word_size) { 1631 status = IXGBE_ERR_EEPROM; 1632 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1633 goto out; 1634 } 1635 1636 for (i = 0; i < words; i++) { 1637 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1638 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1639 IXGBE_EEPROM_RW_REG_START; 1640 1641 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1642 if (status != IXGBE_SUCCESS) { 1643 DEBUGOUT("Eeprom write EEWR timed out\n"); 1644 goto out; 1645 } 1646 1647 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1648 1649 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1650 if (status != IXGBE_SUCCESS) { 1651 DEBUGOUT("Eeprom write EEWR timed out\n"); 1652 goto out; 1653 } 1654 } 1655 1656 out: 1657 return status; 1658 } 1659 1660 /** 1661 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1662 * @hw: pointer to hardware structure 1663 * @offset: offset of word in the EEPROM to write 1664 * @data: word write to the EEPROM 1665 * 1666 * Write a 16 bit word to the EEPROM using the EEWR register. 1667 **/ 1668 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1669 { 1670 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1671 } 1672 1673 /** 1674 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1675 * @hw: pointer to hardware structure 1676 * @ee_reg: EEPROM flag for polling 1677 * 1678 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1679 * read or write is done respectively. 1680 **/ 1681 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1682 { 1683 u32 i; 1684 u32 reg; 1685 s32 status = IXGBE_ERR_EEPROM; 1686 1687 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1688 1689 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1690 if (ee_reg == IXGBE_NVM_POLL_READ) 1691 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1692 else 1693 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1694 1695 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1696 status = IXGBE_SUCCESS; 1697 break; 1698 } 1699 usec_delay(5); 1700 } 1701 1702 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1703 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1704 "EEPROM read/write done polling timed out"); 1705 1706 return status; 1707 } 1708 1709 /** 1710 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1711 * @hw: pointer to hardware structure 1712 * 1713 * Prepares EEPROM for access using bit-bang method. This function should 1714 * be called before issuing a command to the EEPROM. 1715 **/ 1716 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1717 { 1718 s32 status = IXGBE_SUCCESS; 1719 u32 eec; 1720 u32 i; 1721 1722 DEBUGFUNC("ixgbe_acquire_eeprom"); 1723 1724 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1725 != IXGBE_SUCCESS) 1726 status = IXGBE_ERR_SWFW_SYNC; 1727 1728 if (status == IXGBE_SUCCESS) { 1729 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1730 1731 /* Request EEPROM Access */ 1732 eec |= IXGBE_EEC_REQ; 1733 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1734 1735 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1736 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1737 if (eec & IXGBE_EEC_GNT) 1738 break; 1739 usec_delay(5); 1740 } 1741 1742 /* Release if grant not acquired */ 1743 if (!(eec & IXGBE_EEC_GNT)) { 1744 eec &= ~IXGBE_EEC_REQ; 1745 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1746 DEBUGOUT("Could not acquire EEPROM grant\n"); 1747 1748 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1749 status = IXGBE_ERR_EEPROM; 1750 } 1751 1752 /* Setup EEPROM for Read/Write */ 1753 if (status == IXGBE_SUCCESS) { 1754 /* Clear CS and SK */ 1755 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1756 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1757 IXGBE_WRITE_FLUSH(hw); 1758 usec_delay(1); 1759 } 1760 } 1761 return status; 1762 } 1763 1764 /** 1765 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1766 * @hw: pointer to hardware structure 1767 * 1768 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1769 **/ 1770 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1771 { 1772 s32 status = IXGBE_ERR_EEPROM; 1773 u32 timeout = 2000; 1774 u32 i; 1775 u32 swsm; 1776 1777 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1778 1779 1780 /* Get SMBI software semaphore between device drivers first */ 1781 for (i = 0; i < timeout; i++) { 1782 /* 1783 * If the SMBI bit is 0 when we read it, then the bit will be 1784 * set and we have the semaphore 1785 */ 1786 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1787 if (!(swsm & IXGBE_SWSM_SMBI)) { 1788 status = IXGBE_SUCCESS; 1789 break; 1790 } 1791 usec_delay(50); 1792 } 1793 1794 if (i == timeout) { 1795 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1796 "not granted.\n"); 1797 /* 1798 * this release is particularly important because our attempts 1799 * above to get the semaphore may have succeeded, and if there 1800 * was a timeout, we should unconditionally clear the semaphore 1801 * bits to free the driver to make progress 1802 */ 1803 ixgbe_release_eeprom_semaphore(hw); 1804 1805 usec_delay(50); 1806 /* 1807 * one last try 1808 * If the SMBI bit is 0 when we read it, then the bit will be 1809 * set and we have the semaphore 1810 */ 1811 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1812 if (!(swsm & IXGBE_SWSM_SMBI)) 1813 status = IXGBE_SUCCESS; 1814 } 1815 1816 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1817 if (status == IXGBE_SUCCESS) { 1818 for (i = 0; i < timeout; i++) { 1819 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1820 1821 /* Set the SW EEPROM semaphore bit to request access */ 1822 swsm |= IXGBE_SWSM_SWESMBI; 1823 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1824 1825 /* 1826 * If we set the bit successfully then we got the 1827 * semaphore. 1828 */ 1829 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1830 if (swsm & IXGBE_SWSM_SWESMBI) 1831 break; 1832 1833 usec_delay(50); 1834 } 1835 1836 /* 1837 * Release semaphores and return error if SW EEPROM semaphore 1838 * was not granted because we don't have access to the EEPROM 1839 */ 1840 if (i >= timeout) { 1841 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1842 "SWESMBI Software EEPROM semaphore not granted.\n"); 1843 ixgbe_release_eeprom_semaphore(hw); 1844 status = IXGBE_ERR_EEPROM; 1845 } 1846 } else { 1847 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1848 "Software semaphore SMBI between device drivers " 1849 "not granted.\n"); 1850 } 1851 1852 return status; 1853 } 1854 1855 /** 1856 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1857 * @hw: pointer to hardware structure 1858 * 1859 * This function clears hardware semaphore bits. 1860 **/ 1861 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1862 { 1863 u32 swsm; 1864 1865 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1866 1867 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1868 1869 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1870 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1871 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1872 IXGBE_WRITE_FLUSH(hw); 1873 } 1874 1875 /** 1876 * ixgbe_ready_eeprom - Polls for EEPROM ready 1877 * @hw: pointer to hardware structure 1878 **/ 1879 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1880 { 1881 s32 status = IXGBE_SUCCESS; 1882 u16 i; 1883 u8 spi_stat_reg; 1884 1885 DEBUGFUNC("ixgbe_ready_eeprom"); 1886 1887 /* 1888 * Read "Status Register" repeatedly until the LSB is cleared. The 1889 * EEPROM will signal that the command has been completed by clearing 1890 * bit 0 of the internal status register. If it's not cleared within 1891 * 5 milliseconds, then error out. 1892 */ 1893 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1894 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1895 IXGBE_EEPROM_OPCODE_BITS); 1896 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1897 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1898 break; 1899 1900 usec_delay(5); 1901 ixgbe_standby_eeprom(hw); 1902 }; 1903 1904 /* 1905 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1906 * devices (and only 0-5mSec on 5V devices) 1907 */ 1908 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1909 DEBUGOUT("SPI EEPROM Status error\n"); 1910 status = IXGBE_ERR_EEPROM; 1911 } 1912 1913 return status; 1914 } 1915 1916 /** 1917 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1918 * @hw: pointer to hardware structure 1919 **/ 1920 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1921 { 1922 u32 eec; 1923 1924 DEBUGFUNC("ixgbe_standby_eeprom"); 1925 1926 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1927 1928 /* Toggle CS to flush commands */ 1929 eec |= IXGBE_EEC_CS; 1930 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1931 IXGBE_WRITE_FLUSH(hw); 1932 usec_delay(1); 1933 eec &= ~IXGBE_EEC_CS; 1934 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1935 IXGBE_WRITE_FLUSH(hw); 1936 usec_delay(1); 1937 } 1938 1939 /** 1940 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1941 * @hw: pointer to hardware structure 1942 * @data: data to send to the EEPROM 1943 * @count: number of bits to shift out 1944 **/ 1945 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1946 u16 count) 1947 { 1948 u32 eec; 1949 u32 mask; 1950 u32 i; 1951 1952 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 1953 1954 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1955 1956 /* 1957 * Mask is used to shift "count" bits of "data" out to the EEPROM 1958 * one bit at a time. Determine the starting bit based on count 1959 */ 1960 mask = 0x01 << (count - 1); 1961 1962 for (i = 0; i < count; i++) { 1963 /* 1964 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1965 * "1", and then raising and then lowering the clock (the SK 1966 * bit controls the clock input to the EEPROM). A "0" is 1967 * shifted out to the EEPROM by setting "DI" to "0" and then 1968 * raising and then lowering the clock. 1969 */ 1970 if (data & mask) 1971 eec |= IXGBE_EEC_DI; 1972 else 1973 eec &= ~IXGBE_EEC_DI; 1974 1975 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1976 IXGBE_WRITE_FLUSH(hw); 1977 1978 usec_delay(1); 1979 1980 ixgbe_raise_eeprom_clk(hw, &eec); 1981 ixgbe_lower_eeprom_clk(hw, &eec); 1982 1983 /* 1984 * Shift mask to signify next bit of data to shift in to the 1985 * EEPROM 1986 */ 1987 mask = mask >> 1; 1988 }; 1989 1990 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1991 eec &= ~IXGBE_EEC_DI; 1992 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1993 IXGBE_WRITE_FLUSH(hw); 1994 } 1995 1996 /** 1997 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1998 * @hw: pointer to hardware structure 1999 **/ 2000 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2001 { 2002 u32 eec; 2003 u32 i; 2004 u16 data = 0; 2005 2006 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2007 2008 /* 2009 * In order to read a register from the EEPROM, we need to shift 2010 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2011 * the clock input to the EEPROM (setting the SK bit), and then reading 2012 * the value of the "DO" bit. During this "shifting in" process the 2013 * "DI" bit should always be clear. 2014 */ 2015 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 2016 2017 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2018 2019 for (i = 0; i < count; i++) { 2020 data = data << 1; 2021 ixgbe_raise_eeprom_clk(hw, &eec); 2022 2023 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 2024 2025 eec &= ~(IXGBE_EEC_DI); 2026 if (eec & IXGBE_EEC_DO) 2027 data |= 1; 2028 2029 ixgbe_lower_eeprom_clk(hw, &eec); 2030 } 2031 2032 return data; 2033 } 2034 2035 /** 2036 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2037 * @hw: pointer to hardware structure 2038 * @eec: EEC register's current value 2039 **/ 2040 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2041 { 2042 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2043 2044 /* 2045 * Raise the clock input to the EEPROM 2046 * (setting the SK bit), then delay 2047 */ 2048 *eec = *eec | IXGBE_EEC_SK; 2049 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 2050 IXGBE_WRITE_FLUSH(hw); 2051 usec_delay(1); 2052 } 2053 2054 /** 2055 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2056 * @hw: pointer to hardware structure 2057 * @eecd: EECD's current value 2058 **/ 2059 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2060 { 2061 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2062 2063 /* 2064 * Lower the clock input to the EEPROM (clearing the SK bit), then 2065 * delay 2066 */ 2067 *eec = *eec & ~IXGBE_EEC_SK; 2068 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 2069 IXGBE_WRITE_FLUSH(hw); 2070 usec_delay(1); 2071 } 2072 2073 /** 2074 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2075 * @hw: pointer to hardware structure 2076 **/ 2077 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2078 { 2079 u32 eec; 2080 2081 DEBUGFUNC("ixgbe_release_eeprom"); 2082 2083 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 2084 2085 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2086 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2087 2088 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 2089 IXGBE_WRITE_FLUSH(hw); 2090 2091 usec_delay(1); 2092 2093 /* Stop requesting EEPROM access */ 2094 eec &= ~IXGBE_EEC_REQ; 2095 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 2096 2097 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2098 2099 /* Delay before attempt to obtain semaphore again to allow FW access */ 2100 msec_delay(hw->eeprom.semaphore_delay); 2101 } 2102 2103 /** 2104 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2105 * @hw: pointer to hardware structure 2106 * 2107 * Returns a negative error code on error, or the 16-bit checksum 2108 **/ 2109 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2110 { 2111 u16 i; 2112 u16 j; 2113 u16 checksum = 0; 2114 u16 length = 0; 2115 u16 pointer = 0; 2116 u16 word = 0; 2117 2118 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2119 2120 /* Include 0x0-0x3F in the checksum */ 2121 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2122 if (hw->eeprom.ops.read(hw, i, &word)) { 2123 DEBUGOUT("EEPROM read failed\n"); 2124 return IXGBE_ERR_EEPROM; 2125 } 2126 checksum += word; 2127 } 2128 2129 /* Include all data from pointers except for the fw pointer */ 2130 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2131 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2132 DEBUGOUT("EEPROM read failed\n"); 2133 return IXGBE_ERR_EEPROM; 2134 } 2135 2136 /* If the pointer seems invalid */ 2137 if (pointer == 0xFFFF || pointer == 0) 2138 continue; 2139 2140 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2141 DEBUGOUT("EEPROM read failed\n"); 2142 return IXGBE_ERR_EEPROM; 2143 } 2144 2145 if (length == 0xFFFF || length == 0) 2146 continue; 2147 2148 for (j = pointer + 1; j <= pointer + length; j++) { 2149 if (hw->eeprom.ops.read(hw, j, &word)) { 2150 DEBUGOUT("EEPROM read failed\n"); 2151 return IXGBE_ERR_EEPROM; 2152 } 2153 checksum += word; 2154 } 2155 } 2156 2157 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2158 2159 return (s32)checksum; 2160 } 2161 2162 /** 2163 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2164 * @hw: pointer to hardware structure 2165 * @checksum_val: calculated checksum 2166 * 2167 * Performs checksum calculation and validates the EEPROM checksum. If the 2168 * caller does not need checksum_val, the value can be NULL. 2169 **/ 2170 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2171 u16 *checksum_val) 2172 { 2173 s32 status; 2174 u16 checksum; 2175 u16 read_checksum = 0; 2176 2177 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2178 2179 /* Read the first word from the EEPROM. If this times out or fails, do 2180 * not continue or we could be in for a very long wait while every 2181 * EEPROM read fails 2182 */ 2183 status = hw->eeprom.ops.read(hw, 0, &checksum); 2184 if (status) { 2185 DEBUGOUT("EEPROM read failed\n"); 2186 return status; 2187 } 2188 2189 status = hw->eeprom.ops.calc_checksum(hw); 2190 if (status < 0) 2191 return status; 2192 2193 checksum = (u16)(status & 0xffff); 2194 2195 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2196 if (status) { 2197 DEBUGOUT("EEPROM read failed\n"); 2198 return status; 2199 } 2200 2201 /* Verify read checksum from EEPROM is the same as 2202 * calculated checksum 2203 */ 2204 if (read_checksum != checksum) 2205 status = IXGBE_ERR_EEPROM_CHECKSUM; 2206 2207 /* If the user cares, return the calculated checksum */ 2208 if (checksum_val) 2209 *checksum_val = checksum; 2210 2211 return status; 2212 } 2213 2214 /** 2215 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2216 * @hw: pointer to hardware structure 2217 **/ 2218 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2219 { 2220 s32 status; 2221 u16 checksum; 2222 2223 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2224 2225 /* Read the first word from the EEPROM. If this times out or fails, do 2226 * not continue or we could be in for a very long wait while every 2227 * EEPROM read fails 2228 */ 2229 status = hw->eeprom.ops.read(hw, 0, &checksum); 2230 if (status) { 2231 DEBUGOUT("EEPROM read failed\n"); 2232 return status; 2233 } 2234 2235 status = hw->eeprom.ops.calc_checksum(hw); 2236 if (status < 0) 2237 return status; 2238 2239 checksum = (u16)(status & 0xffff); 2240 2241 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2242 2243 return status; 2244 } 2245 2246 /** 2247 * ixgbe_validate_mac_addr - Validate MAC address 2248 * @mac_addr: pointer to MAC address. 2249 * 2250 * Tests a MAC address to ensure it is a valid Individual Address 2251 **/ 2252 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2253 { 2254 s32 status = IXGBE_SUCCESS; 2255 2256 DEBUGFUNC("ixgbe_validate_mac_addr"); 2257 2258 /* Make sure it is not a multicast address */ 2259 if (IXGBE_IS_MULTICAST(mac_addr)) { 2260 DEBUGOUT("MAC address is multicast\n"); 2261 status = IXGBE_ERR_INVALID_MAC_ADDR; 2262 /* Not a broadcast address */ 2263 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2264 DEBUGOUT("MAC address is broadcast\n"); 2265 status = IXGBE_ERR_INVALID_MAC_ADDR; 2266 /* Reject the zero address */ 2267 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2268 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2269 DEBUGOUT("MAC address is all zeros\n"); 2270 status = IXGBE_ERR_INVALID_MAC_ADDR; 2271 } 2272 return status; 2273 } 2274 2275 /** 2276 * ixgbe_set_rar_generic - Set Rx address register 2277 * @hw: pointer to hardware structure 2278 * @index: Receive address register to write 2279 * @addr: Address to put into receive address register 2280 * @vmdq: VMDq "set" or "pool" index 2281 * @enable_addr: set flag that address is active 2282 * 2283 * Puts an ethernet address into a receive address register. 2284 **/ 2285 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2286 u32 enable_addr) 2287 { 2288 u32 rar_low, rar_high; 2289 u32 rar_entries = hw->mac.num_rar_entries; 2290 2291 DEBUGFUNC("ixgbe_set_rar_generic"); 2292 2293 /* Make sure we are using a valid rar index range */ 2294 if (index >= rar_entries) { 2295 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2296 "RAR index %d is out of range.\n", index); 2297 return IXGBE_ERR_INVALID_ARGUMENT; 2298 } 2299 2300 /* setup VMDq pool selection before this RAR gets enabled */ 2301 hw->mac.ops.set_vmdq(hw, index, vmdq); 2302 2303 /* 2304 * HW expects these in little endian so we reverse the byte 2305 * order from network order (big endian) to little endian 2306 */ 2307 rar_low = ((u32)addr[0] | 2308 ((u32)addr[1] << 8) | 2309 ((u32)addr[2] << 16) | 2310 ((u32)addr[3] << 24)); 2311 /* 2312 * Some parts put the VMDq setting in the extra RAH bits, 2313 * so save everything except the lower 16 bits that hold part 2314 * of the address and the address valid bit. 2315 */ 2316 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2317 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2318 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2319 2320 if (enable_addr != 0) 2321 rar_high |= IXGBE_RAH_AV; 2322 2323 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2324 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2325 2326 return IXGBE_SUCCESS; 2327 } 2328 2329 /** 2330 * ixgbe_clear_rar_generic - Remove Rx address register 2331 * @hw: pointer to hardware structure 2332 * @index: Receive address register to write 2333 * 2334 * Clears an ethernet address from a receive address register. 2335 **/ 2336 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2337 { 2338 u32 rar_high; 2339 u32 rar_entries = hw->mac.num_rar_entries; 2340 2341 DEBUGFUNC("ixgbe_clear_rar_generic"); 2342 2343 /* Make sure we are using a valid rar index range */ 2344 if (index >= rar_entries) { 2345 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2346 "RAR index %d is out of range.\n", index); 2347 return IXGBE_ERR_INVALID_ARGUMENT; 2348 } 2349 2350 /* 2351 * Some parts put the VMDq setting in the extra RAH bits, 2352 * so save everything except the lower 16 bits that hold part 2353 * of the address and the address valid bit. 2354 */ 2355 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2356 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2357 2358 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2359 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2360 2361 /* clear VMDq pool/queue selection for this RAR */ 2362 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2363 2364 return IXGBE_SUCCESS; 2365 } 2366 2367 /** 2368 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2369 * @hw: pointer to hardware structure 2370 * 2371 * Places the MAC address in receive address register 0 and clears the rest 2372 * of the receive address registers. Clears the multicast table. Assumes 2373 * the receiver is in reset when the routine is called. 2374 **/ 2375 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2376 { 2377 u32 i; 2378 u32 rar_entries = hw->mac.num_rar_entries; 2379 2380 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2381 2382 /* 2383 * If the current mac address is valid, assume it is a software override 2384 * to the permanent address. 2385 * Otherwise, use the permanent address from the eeprom. 2386 */ 2387 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2388 IXGBE_ERR_INVALID_MAC_ADDR) { 2389 /* Get the MAC address from the RAR0 for later reference */ 2390 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2391 2392 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2393 hw->mac.addr[0], hw->mac.addr[1], 2394 hw->mac.addr[2]); 2395 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2396 hw->mac.addr[4], hw->mac.addr[5]); 2397 } else { 2398 /* Setup the receive address. */ 2399 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2400 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2401 hw->mac.addr[0], hw->mac.addr[1], 2402 hw->mac.addr[2]); 2403 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2404 hw->mac.addr[4], hw->mac.addr[5]); 2405 2406 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2407 2408 /* clear VMDq pool/queue selection for RAR 0 */ 2409 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2410 } 2411 hw->addr_ctrl.overflow_promisc = 0; 2412 2413 hw->addr_ctrl.rar_used_count = 1; 2414 2415 /* Zero out the other receive addresses. */ 2416 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2417 for (i = 1; i < rar_entries; i++) { 2418 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2419 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2420 } 2421 2422 /* Clear the MTA */ 2423 hw->addr_ctrl.mta_in_use = 0; 2424 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2425 2426 DEBUGOUT(" Clearing MTA\n"); 2427 for (i = 0; i < hw->mac.mcft_size; i++) 2428 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2429 2430 ixgbe_init_uta_tables(hw); 2431 2432 return IXGBE_SUCCESS; 2433 } 2434 2435 /** 2436 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2437 * @hw: pointer to hardware structure 2438 * @addr: new address 2439 * 2440 * Adds it to unused receive address register or goes into promiscuous mode. 2441 **/ 2442 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2443 { 2444 u32 rar_entries = hw->mac.num_rar_entries; 2445 u32 rar; 2446 2447 DEBUGFUNC("ixgbe_add_uc_addr"); 2448 2449 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2450 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2451 2452 /* 2453 * Place this address in the RAR if there is room, 2454 * else put the controller into promiscuous mode 2455 */ 2456 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2457 rar = hw->addr_ctrl.rar_used_count; 2458 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2459 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2460 hw->addr_ctrl.rar_used_count++; 2461 } else { 2462 hw->addr_ctrl.overflow_promisc++; 2463 } 2464 2465 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2466 } 2467 2468 /** 2469 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2470 * @hw: pointer to hardware structure 2471 * @addr_list: the list of new addresses 2472 * @addr_count: number of addresses 2473 * @next: iterator function to walk the address list 2474 * 2475 * The given list replaces any existing list. Clears the secondary addrs from 2476 * receive address registers. Uses unused receive address registers for the 2477 * first secondary addresses, and falls back to promiscuous mode as needed. 2478 * 2479 * Drivers using secondary unicast addresses must set user_set_promisc when 2480 * manually putting the device into promiscuous mode. 2481 **/ 2482 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2483 u32 addr_count, ixgbe_mc_addr_itr next) 2484 { 2485 u8 *addr; 2486 u32 i; 2487 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2488 u32 uc_addr_in_use; 2489 u32 fctrl; 2490 u32 vmdq; 2491 2492 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2493 2494 /* 2495 * Clear accounting of old secondary address list, 2496 * don't count RAR[0] 2497 */ 2498 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2499 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2500 hw->addr_ctrl.overflow_promisc = 0; 2501 2502 /* Zero out the other receive addresses */ 2503 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2504 for (i = 0; i < uc_addr_in_use; i++) { 2505 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2506 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2507 } 2508 2509 /* Add the new addresses */ 2510 for (i = 0; i < addr_count; i++) { 2511 DEBUGOUT(" Adding the secondary addresses:\n"); 2512 addr = next(hw, &addr_list, &vmdq); 2513 ixgbe_add_uc_addr(hw, addr, vmdq); 2514 } 2515 2516 if (hw->addr_ctrl.overflow_promisc) { 2517 /* enable promisc if not already in overflow or set by user */ 2518 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2519 DEBUGOUT(" Entering address overflow promisc mode\n"); 2520 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2521 fctrl |= IXGBE_FCTRL_UPE; 2522 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2523 } 2524 } else { 2525 /* only disable if set by overflow, not by user */ 2526 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2527 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2528 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2529 fctrl &= ~IXGBE_FCTRL_UPE; 2530 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2531 } 2532 } 2533 2534 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2535 return IXGBE_SUCCESS; 2536 } 2537 2538 /** 2539 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2540 * @hw: pointer to hardware structure 2541 * @mc_addr: the multicast address 2542 * 2543 * Extracts the 12 bits, from a multicast address, to determine which 2544 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2545 * incoming rx multicast addresses, to determine the bit-vector to check in 2546 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2547 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2548 * to mc_filter_type. 2549 **/ 2550 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2551 { 2552 u32 vector = 0; 2553 2554 DEBUGFUNC("ixgbe_mta_vector"); 2555 2556 switch (hw->mac.mc_filter_type) { 2557 case 0: /* use bits [47:36] of the address */ 2558 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2559 break; 2560 case 1: /* use bits [46:35] of the address */ 2561 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2562 break; 2563 case 2: /* use bits [45:34] of the address */ 2564 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2565 break; 2566 case 3: /* use bits [43:32] of the address */ 2567 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2568 break; 2569 default: /* Invalid mc_filter_type */ 2570 DEBUGOUT("MC filter type param set incorrectly\n"); 2571 ASSERT(0); 2572 break; 2573 } 2574 2575 /* vector can only be 12-bits or boundary will be exceeded */ 2576 vector &= 0xFFF; 2577 return vector; 2578 } 2579 2580 /** 2581 * ixgbe_set_mta - Set bit-vector in multicast table 2582 * @hw: pointer to hardware structure 2583 * @hash_value: Multicast address hash value 2584 * 2585 * Sets the bit-vector in the multicast table. 2586 **/ 2587 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2588 { 2589 u32 vector; 2590 u32 vector_bit; 2591 u32 vector_reg; 2592 2593 DEBUGFUNC("ixgbe_set_mta"); 2594 2595 hw->addr_ctrl.mta_in_use++; 2596 2597 vector = ixgbe_mta_vector(hw, mc_addr); 2598 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2599 2600 /* 2601 * The MTA is a register array of 128 32-bit registers. It is treated 2602 * like an array of 4096 bits. We want to set bit 2603 * BitArray[vector_value]. So we figure out what register the bit is 2604 * in, read it, OR in the new bit, then write back the new value. The 2605 * register is determined by the upper 7 bits of the vector value and 2606 * the bit within that register are determined by the lower 5 bits of 2607 * the value. 2608 */ 2609 vector_reg = (vector >> 5) & 0x7F; 2610 vector_bit = vector & 0x1F; 2611 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2612 } 2613 2614 /** 2615 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2616 * @hw: pointer to hardware structure 2617 * @mc_addr_list: the list of new multicast addresses 2618 * @mc_addr_count: number of addresses 2619 * @next: iterator function to walk the multicast address list 2620 * @clear: flag, when set clears the table beforehand 2621 * 2622 * When the clear flag is set, the given list replaces any existing list. 2623 * Hashes the given addresses into the multicast table. 2624 **/ 2625 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2626 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2627 bool clear) 2628 { 2629 u32 i; 2630 u32 vmdq; 2631 2632 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2633 2634 /* 2635 * Set the new number of MC addresses that we are being requested to 2636 * use. 2637 */ 2638 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2639 hw->addr_ctrl.mta_in_use = 0; 2640 2641 /* Clear mta_shadow */ 2642 if (clear) { 2643 DEBUGOUT(" Clearing MTA\n"); 2644 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2645 } 2646 2647 /* Update mta_shadow */ 2648 for (i = 0; i < mc_addr_count; i++) { 2649 DEBUGOUT(" Adding the multicast addresses:\n"); 2650 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2651 } 2652 2653 /* Enable mta */ 2654 for (i = 0; i < hw->mac.mcft_size; i++) 2655 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2656 hw->mac.mta_shadow[i]); 2657 2658 if (hw->addr_ctrl.mta_in_use > 0) 2659 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2660 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2661 2662 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2663 return IXGBE_SUCCESS; 2664 } 2665 2666 /** 2667 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2668 * @hw: pointer to hardware structure 2669 * 2670 * Enables multicast address in RAR and the use of the multicast hash table. 2671 **/ 2672 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2673 { 2674 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2675 2676 DEBUGFUNC("ixgbe_enable_mc_generic"); 2677 2678 if (a->mta_in_use > 0) 2679 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2680 hw->mac.mc_filter_type); 2681 2682 return IXGBE_SUCCESS; 2683 } 2684 2685 /** 2686 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2687 * @hw: pointer to hardware structure 2688 * 2689 * Disables multicast address in RAR and the use of the multicast hash table. 2690 **/ 2691 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2692 { 2693 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2694 2695 DEBUGFUNC("ixgbe_disable_mc_generic"); 2696 2697 if (a->mta_in_use > 0) 2698 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2699 2700 return IXGBE_SUCCESS; 2701 } 2702 2703 /** 2704 * ixgbe_fc_enable_generic - Enable flow control 2705 * @hw: pointer to hardware structure 2706 * 2707 * Enable flow control according to the current settings. 2708 **/ 2709 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2710 { 2711 s32 ret_val = IXGBE_SUCCESS; 2712 u32 mflcn_reg, fccfg_reg; 2713 u32 reg; 2714 u32 fcrtl, fcrth; 2715 int i; 2716 2717 DEBUGFUNC("ixgbe_fc_enable_generic"); 2718 2719 /* Validate the water mark configuration */ 2720 if (!hw->fc.pause_time) { 2721 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2722 goto out; 2723 } 2724 2725 /* Low water mark of zero causes XOFF floods */ 2726 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2727 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2728 hw->fc.high_water[i]) { 2729 if (!hw->fc.low_water[i] || 2730 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2731 DEBUGOUT("Invalid water mark configuration\n"); 2732 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2733 goto out; 2734 } 2735 } 2736 } 2737 2738 /* Negotiate the fc mode to use */ 2739 ixgbe_fc_autoneg(hw); 2740 2741 /* Disable any previous flow control settings */ 2742 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2743 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2744 2745 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2746 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2747 2748 /* 2749 * The possible values of fc.current_mode are: 2750 * 0: Flow control is completely disabled 2751 * 1: Rx flow control is enabled (we can receive pause frames, 2752 * but not send pause frames). 2753 * 2: Tx flow control is enabled (we can send pause frames but 2754 * we do not support receiving pause frames). 2755 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2756 * other: Invalid. 2757 */ 2758 switch (hw->fc.current_mode) { 2759 case ixgbe_fc_none: 2760 /* 2761 * Flow control is disabled by software override or autoneg. 2762 * The code below will actually disable it in the HW. 2763 */ 2764 break; 2765 case ixgbe_fc_rx_pause: 2766 /* 2767 * Rx Flow control is enabled and Tx Flow control is 2768 * disabled by software override. Since there really 2769 * isn't a way to advertise that we are capable of RX 2770 * Pause ONLY, we will advertise that we support both 2771 * symmetric and asymmetric Rx PAUSE. Later, we will 2772 * disable the adapter's ability to send PAUSE frames. 2773 */ 2774 mflcn_reg |= IXGBE_MFLCN_RFCE; 2775 break; 2776 case ixgbe_fc_tx_pause: 2777 /* 2778 * Tx Flow control is enabled, and Rx Flow control is 2779 * disabled by software override. 2780 */ 2781 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2782 break; 2783 case ixgbe_fc_full: 2784 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2785 mflcn_reg |= IXGBE_MFLCN_RFCE; 2786 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2787 break; 2788 default: 2789 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2790 "Flow control param set incorrectly\n"); 2791 ret_val = IXGBE_ERR_CONFIG; 2792 goto out; 2793 break; 2794 } 2795 2796 /* Set 802.3x based flow control settings. */ 2797 mflcn_reg |= IXGBE_MFLCN_DPF; 2798 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2799 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2800 2801 2802 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2803 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2804 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2805 hw->fc.high_water[i]) { 2806 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2807 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2808 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2809 } else { 2810 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2811 /* 2812 * In order to prevent Tx hangs when the internal Tx 2813 * switch is enabled we must set the high water mark 2814 * to the Rx packet buffer size - 24KB. This allows 2815 * the Tx switch to function even under heavy Rx 2816 * workloads. 2817 */ 2818 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2819 } 2820 2821 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2822 } 2823 2824 /* Configure pause time (2 TCs per register) */ 2825 reg = hw->fc.pause_time * 0x00010001; 2826 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2827 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2828 2829 /* Configure flow control refresh threshold value */ 2830 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2831 2832 out: 2833 return ret_val; 2834 } 2835 2836 /** 2837 * ixgbe_negotiate_fc - Negotiate flow control 2838 * @hw: pointer to hardware structure 2839 * @adv_reg: flow control advertised settings 2840 * @lp_reg: link partner's flow control settings 2841 * @adv_sym: symmetric pause bit in advertisement 2842 * @adv_asm: asymmetric pause bit in advertisement 2843 * @lp_sym: symmetric pause bit in link partner advertisement 2844 * @lp_asm: asymmetric pause bit in link partner advertisement 2845 * 2846 * Find the intersection between advertised settings and link partner's 2847 * advertised settings 2848 **/ 2849 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2850 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2851 { 2852 if ((!(adv_reg)) || (!(lp_reg))) { 2853 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2854 "Local or link partner's advertised flow control " 2855 "settings are NULL. Local: %x, link partner: %x\n", 2856 adv_reg, lp_reg); 2857 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2858 } 2859 2860 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2861 /* 2862 * Now we need to check if the user selected Rx ONLY 2863 * of pause frames. In this case, we had to advertise 2864 * FULL flow control because we could not advertise RX 2865 * ONLY. Hence, we must now check to see if we need to 2866 * turn OFF the TRANSMISSION of PAUSE frames. 2867 */ 2868 if (hw->fc.requested_mode == ixgbe_fc_full) { 2869 hw->fc.current_mode = ixgbe_fc_full; 2870 DEBUGOUT("Flow Control = FULL.\n"); 2871 } else { 2872 hw->fc.current_mode = ixgbe_fc_rx_pause; 2873 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2874 } 2875 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2876 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2877 hw->fc.current_mode = ixgbe_fc_tx_pause; 2878 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2879 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2880 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2881 hw->fc.current_mode = ixgbe_fc_rx_pause; 2882 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2883 } else { 2884 hw->fc.current_mode = ixgbe_fc_none; 2885 DEBUGOUT("Flow Control = NONE.\n"); 2886 } 2887 return IXGBE_SUCCESS; 2888 } 2889 2890 /** 2891 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2892 * @hw: pointer to hardware structure 2893 * 2894 * Enable flow control according on 1 gig fiber. 2895 **/ 2896 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2897 { 2898 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2899 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2900 2901 /* 2902 * On multispeed fiber at 1g, bail out if 2903 * - link is up but AN did not complete, or if 2904 * - link is up and AN completed but timed out 2905 */ 2906 2907 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2908 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2909 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 2910 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 2911 goto out; 2912 } 2913 2914 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2915 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2916 2917 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2918 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2919 IXGBE_PCS1GANA_ASM_PAUSE, 2920 IXGBE_PCS1GANA_SYM_PAUSE, 2921 IXGBE_PCS1GANA_ASM_PAUSE); 2922 2923 out: 2924 return ret_val; 2925 } 2926 2927 /** 2928 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2929 * @hw: pointer to hardware structure 2930 * 2931 * Enable flow control according to IEEE clause 37. 2932 **/ 2933 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2934 { 2935 u32 links2, anlp1_reg, autoc_reg, links; 2936 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2937 2938 /* 2939 * On backplane, bail out if 2940 * - backplane autoneg was not completed, or if 2941 * - we are 82599 and link partner is not AN enabled 2942 */ 2943 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2944 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 2945 DEBUGOUT("Auto-Negotiation did not complete\n"); 2946 goto out; 2947 } 2948 2949 if (hw->mac.type == ixgbe_mac_82599EB) { 2950 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2951 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 2952 DEBUGOUT("Link partner is not AN enabled\n"); 2953 goto out; 2954 } 2955 } 2956 /* 2957 * Read the 10g AN autoc and LP ability registers and resolve 2958 * local flow control settings accordingly 2959 */ 2960 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2961 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2962 2963 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2964 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2965 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2966 2967 out: 2968 return ret_val; 2969 } 2970 2971 /** 2972 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2973 * @hw: pointer to hardware structure 2974 * 2975 * Enable flow control according to IEEE clause 37. 2976 **/ 2977 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2978 { 2979 u16 technology_ability_reg = 0; 2980 u16 lp_technology_ability_reg = 0; 2981 2982 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 2983 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2984 &technology_ability_reg); 2985 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 2986 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2987 &lp_technology_ability_reg); 2988 2989 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2990 (u32)lp_technology_ability_reg, 2991 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2992 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2993 } 2994 2995 /** 2996 * ixgbe_fc_autoneg - Configure flow control 2997 * @hw: pointer to hardware structure 2998 * 2999 * Compares our advertised flow control capabilities to those advertised by 3000 * our link partner, and determines the proper flow control mode to use. 3001 **/ 3002 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3003 { 3004 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3005 ixgbe_link_speed speed; 3006 bool link_up; 3007 3008 DEBUGFUNC("ixgbe_fc_autoneg"); 3009 3010 /* 3011 * AN should have completed when the cable was plugged in. 3012 * Look for reasons to bail out. Bail out if: 3013 * - FC autoneg is disabled, or if 3014 * - link is not up. 3015 */ 3016 if (hw->fc.disable_fc_autoneg) { 3017 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 3018 "Flow control autoneg is disabled"); 3019 goto out; 3020 } 3021 3022 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3023 if (!link_up) { 3024 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3025 goto out; 3026 } 3027 3028 switch (hw->phy.media_type) { 3029 /* Autoneg flow control on fiber adapters */ 3030 case ixgbe_media_type_fiber_fixed: 3031 case ixgbe_media_type_fiber_qsfp: 3032 case ixgbe_media_type_fiber: 3033 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3034 ret_val = ixgbe_fc_autoneg_fiber(hw); 3035 break; 3036 3037 /* Autoneg flow control on backplane adapters */ 3038 case ixgbe_media_type_backplane: 3039 ret_val = ixgbe_fc_autoneg_backplane(hw); 3040 break; 3041 3042 /* Autoneg flow control on copper adapters */ 3043 case ixgbe_media_type_copper: 3044 if (ixgbe_device_supports_autoneg_fc(hw)) 3045 ret_val = ixgbe_fc_autoneg_copper(hw); 3046 break; 3047 3048 default: 3049 break; 3050 } 3051 3052 out: 3053 if (ret_val == IXGBE_SUCCESS) { 3054 hw->fc.fc_was_autonegged = TRUE; 3055 } else { 3056 hw->fc.fc_was_autonegged = FALSE; 3057 hw->fc.current_mode = hw->fc.requested_mode; 3058 } 3059 } 3060 3061 /* 3062 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3063 * @hw: pointer to hardware structure 3064 * 3065 * System-wide timeout range is encoded in PCIe Device Control2 register. 3066 * 3067 * Add 10% to specified maximum and return the number of times to poll for 3068 * completion timeout, in units of 100 microsec. Never return less than 3069 * 800 = 80 millisec. 3070 */ 3071 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3072 { 3073 s16 devctl2; 3074 u32 pollcnt; 3075 3076 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3077 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3078 3079 switch (devctl2) { 3080 case IXGBE_PCIDEVCTRL2_65_130ms: 3081 pollcnt = 1300; /* 130 millisec */ 3082 break; 3083 case IXGBE_PCIDEVCTRL2_260_520ms: 3084 pollcnt = 5200; /* 520 millisec */ 3085 break; 3086 case IXGBE_PCIDEVCTRL2_1_2s: 3087 pollcnt = 20000; /* 2 sec */ 3088 break; 3089 case IXGBE_PCIDEVCTRL2_4_8s: 3090 pollcnt = 80000; /* 8 sec */ 3091 break; 3092 case IXGBE_PCIDEVCTRL2_17_34s: 3093 pollcnt = 34000; /* 34 sec */ 3094 break; 3095 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3096 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3097 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3098 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3099 default: 3100 pollcnt = 800; /* 80 millisec minimum */ 3101 break; 3102 } 3103 3104 /* add 10% to spec maximum */ 3105 return (pollcnt * 11) / 10; 3106 } 3107 3108 /** 3109 * ixgbe_disable_pcie_master - Disable PCI-express master access 3110 * @hw: pointer to hardware structure 3111 * 3112 * Disables PCI-Express master access and verifies there are no pending 3113 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 3114 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 3115 * is returned signifying master requests disabled. 3116 **/ 3117 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 3118 { 3119 s32 status = IXGBE_SUCCESS; 3120 u32 i, poll; 3121 u16 value; 3122 3123 DEBUGFUNC("ixgbe_disable_pcie_master"); 3124 3125 /* Always set this bit to ensure any future transactions are blocked */ 3126 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3127 3128 /* Exit if master requests are blocked */ 3129 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3130 IXGBE_REMOVED(hw->hw_addr)) 3131 goto out; 3132 3133 /* Poll for master request bit to clear */ 3134 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 3135 usec_delay(100); 3136 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3137 goto out; 3138 } 3139 3140 /* 3141 * Two consecutive resets are required via CTRL.RST per datasheet 3142 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 3143 * of this need. The first reset prevents new master requests from 3144 * being issued by our device. We then must wait 1usec or more for any 3145 * remaining completions from the PCIe bus to trickle in, and then reset 3146 * again to clear out any effects they may have had on our device. 3147 */ 3148 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 3149 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3150 3151 /* 3152 * Before proceeding, make sure that the PCIe block does not have 3153 * transactions pending. 3154 */ 3155 poll = ixgbe_pcie_timeout_poll(hw); 3156 for (i = 0; i < poll; i++) { 3157 usec_delay(100); 3158 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3159 if (IXGBE_REMOVED(hw->hw_addr)) 3160 goto out; 3161 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3162 goto out; 3163 } 3164 3165 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3166 "PCIe transaction pending bit also did not clear.\n"); 3167 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 3168 3169 out: 3170 return status; 3171 } 3172 3173 /** 3174 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3175 * @hw: pointer to hardware structure 3176 * @mask: Mask to specify which semaphore to acquire 3177 * 3178 * Acquires the SWFW semaphore through the GSSR register for the specified 3179 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3180 **/ 3181 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3182 { 3183 u32 gssr = 0; 3184 u32 swmask = mask; 3185 u32 fwmask = mask << 5; 3186 u32 timeout = 200; 3187 u32 i; 3188 3189 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3190 3191 for (i = 0; i < timeout; i++) { 3192 /* 3193 * SW NVM semaphore bit is used for access to all 3194 * SW_FW_SYNC bits (not just NVM) 3195 */ 3196 if (ixgbe_get_eeprom_semaphore(hw)) 3197 return IXGBE_ERR_SWFW_SYNC; 3198 3199 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3200 if (!(gssr & (fwmask | swmask))) { 3201 gssr |= swmask; 3202 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3203 ixgbe_release_eeprom_semaphore(hw); 3204 return IXGBE_SUCCESS; 3205 } else { 3206 /* Resource is currently in use by FW or SW */ 3207 ixgbe_release_eeprom_semaphore(hw); 3208 msec_delay(5); 3209 } 3210 } 3211 3212 /* If time expired clear the bits holding the lock and retry */ 3213 if (gssr & (fwmask | swmask)) 3214 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3215 3216 msec_delay(5); 3217 return IXGBE_ERR_SWFW_SYNC; 3218 } 3219 3220 /** 3221 * ixgbe_release_swfw_sync - Release SWFW semaphore 3222 * @hw: pointer to hardware structure 3223 * @mask: Mask to specify which semaphore to release 3224 * 3225 * Releases the SWFW semaphore through the GSSR register for the specified 3226 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3227 **/ 3228 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3229 { 3230 u32 gssr; 3231 u32 swmask = mask; 3232 3233 DEBUGFUNC("ixgbe_release_swfw_sync"); 3234 3235 ixgbe_get_eeprom_semaphore(hw); 3236 3237 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3238 gssr &= ~swmask; 3239 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3240 3241 ixgbe_release_eeprom_semaphore(hw); 3242 } 3243 3244 /** 3245 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3246 * @hw: pointer to hardware structure 3247 * 3248 * Stops the receive data path and waits for the HW to internally empty 3249 * the Rx security block 3250 **/ 3251 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3252 { 3253 #define IXGBE_MAX_SECRX_POLL 40 3254 3255 int i; 3256 int secrxreg; 3257 3258 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3259 3260 3261 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3262 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3263 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3264 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3265 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3266 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3267 break; 3268 else 3269 /* Use interrupt-safe sleep just in case */ 3270 usec_delay(1000); 3271 } 3272 3273 /* For informational purposes only */ 3274 if (i >= IXGBE_MAX_SECRX_POLL) 3275 DEBUGOUT("Rx unit being enabled before security " 3276 "path fully disabled. Continuing with init.\n"); 3277 3278 return IXGBE_SUCCESS; 3279 } 3280 3281 /** 3282 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3283 * @hw: pointer to hardware structure 3284 * @reg_val: Value we read from AUTOC 3285 * 3286 * The default case requires no protection so just to the register read. 3287 */ 3288 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3289 { 3290 *locked = FALSE; 3291 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3292 return IXGBE_SUCCESS; 3293 } 3294 3295 /** 3296 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3297 * @hw: pointer to hardware structure 3298 * @reg_val: value to write to AUTOC 3299 * @locked: bool to indicate whether the SW/FW lock was already taken by 3300 * previous read. 3301 * 3302 * The default case requires no protection so just to the register write. 3303 */ 3304 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3305 { 3306 UNREFERENCED_1PARAMETER(locked); 3307 3308 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3309 return IXGBE_SUCCESS; 3310 } 3311 3312 /** 3313 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3314 * @hw: pointer to hardware structure 3315 * 3316 * Enables the receive data path. 3317 **/ 3318 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3319 { 3320 int secrxreg; 3321 3322 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3323 3324 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3325 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3326 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3327 IXGBE_WRITE_FLUSH(hw); 3328 3329 return IXGBE_SUCCESS; 3330 } 3331 3332 /** 3333 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3334 * @hw: pointer to hardware structure 3335 * @regval: register value to write to RXCTRL 3336 * 3337 * Enables the Rx DMA unit 3338 **/ 3339 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3340 { 3341 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3342 3343 if (regval & IXGBE_RXCTRL_RXEN) 3344 ixgbe_enable_rx(hw); 3345 else 3346 ixgbe_disable_rx(hw); 3347 3348 return IXGBE_SUCCESS; 3349 } 3350 3351 /** 3352 * ixgbe_blink_led_start_generic - Blink LED based on index. 3353 * @hw: pointer to hardware structure 3354 * @index: led number to blink 3355 **/ 3356 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3357 { 3358 ixgbe_link_speed speed = 0; 3359 bool link_up = 0; 3360 u32 autoc_reg = 0; 3361 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3362 s32 ret_val = IXGBE_SUCCESS; 3363 bool locked = FALSE; 3364 3365 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3366 3367 /* 3368 * Link must be up to auto-blink the LEDs; 3369 * Force it if link is down. 3370 */ 3371 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3372 3373 if (!link_up) { 3374 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3375 if (ret_val != IXGBE_SUCCESS) 3376 goto out; 3377 3378 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3379 autoc_reg |= IXGBE_AUTOC_FLU; 3380 3381 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3382 if (ret_val != IXGBE_SUCCESS) 3383 goto out; 3384 3385 IXGBE_WRITE_FLUSH(hw); 3386 msec_delay(10); 3387 } 3388 3389 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3390 led_reg |= IXGBE_LED_BLINK(index); 3391 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3392 IXGBE_WRITE_FLUSH(hw); 3393 3394 out: 3395 return ret_val; 3396 } 3397 3398 /** 3399 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3400 * @hw: pointer to hardware structure 3401 * @index: led number to stop blinking 3402 **/ 3403 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3404 { 3405 u32 autoc_reg = 0; 3406 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3407 s32 ret_val = IXGBE_SUCCESS; 3408 bool locked = FALSE; 3409 3410 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3411 3412 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3413 if (ret_val != IXGBE_SUCCESS) 3414 goto out; 3415 3416 autoc_reg &= ~IXGBE_AUTOC_FLU; 3417 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3418 3419 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3420 if (ret_val != IXGBE_SUCCESS) 3421 goto out; 3422 3423 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3424 led_reg &= ~IXGBE_LED_BLINK(index); 3425 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3426 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3427 IXGBE_WRITE_FLUSH(hw); 3428 3429 out: 3430 return ret_val; 3431 } 3432 3433 /** 3434 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3435 * @hw: pointer to hardware structure 3436 * @san_mac_offset: SAN MAC address offset 3437 * 3438 * This function will read the EEPROM location for the SAN MAC address 3439 * pointer, and returns the value at that location. This is used in both 3440 * get and set mac_addr routines. 3441 **/ 3442 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3443 u16 *san_mac_offset) 3444 { 3445 s32 ret_val; 3446 3447 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3448 3449 /* 3450 * First read the EEPROM pointer to see if the MAC addresses are 3451 * available. 3452 */ 3453 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3454 san_mac_offset); 3455 if (ret_val) { 3456 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3457 "eeprom at offset %d failed", 3458 IXGBE_SAN_MAC_ADDR_PTR); 3459 } 3460 3461 return ret_val; 3462 } 3463 3464 /** 3465 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3466 * @hw: pointer to hardware structure 3467 * @san_mac_addr: SAN MAC address 3468 * 3469 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3470 * per-port, so set_lan_id() must be called before reading the addresses. 3471 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3472 * upon for non-SFP connections, so we must call it here. 3473 **/ 3474 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3475 { 3476 u16 san_mac_data, san_mac_offset; 3477 u8 i; 3478 s32 ret_val; 3479 3480 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3481 3482 /* 3483 * First read the EEPROM pointer to see if the MAC addresses are 3484 * available. If they're not, no point in calling set_lan_id() here. 3485 */ 3486 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3487 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3488 goto san_mac_addr_out; 3489 3490 /* make sure we know which port we need to program */ 3491 hw->mac.ops.set_lan_id(hw); 3492 /* apply the port offset to the address offset */ 3493 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3494 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3495 for (i = 0; i < 3; i++) { 3496 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3497 &san_mac_data); 3498 if (ret_val) { 3499 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3500 "eeprom read at offset %d failed", 3501 san_mac_offset); 3502 goto san_mac_addr_out; 3503 } 3504 san_mac_addr[i * 2] = (u8)(san_mac_data); 3505 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3506 san_mac_offset++; 3507 } 3508 return IXGBE_SUCCESS; 3509 3510 san_mac_addr_out: 3511 /* 3512 * No addresses available in this EEPROM. It's not an 3513 * error though, so just wipe the local address and return. 3514 */ 3515 for (i = 0; i < 6; i++) 3516 san_mac_addr[i] = 0xFF; 3517 return IXGBE_SUCCESS; 3518 } 3519 3520 /** 3521 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3522 * @hw: pointer to hardware structure 3523 * @san_mac_addr: SAN MAC address 3524 * 3525 * Write a SAN MAC address to the EEPROM. 3526 **/ 3527 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3528 { 3529 s32 ret_val; 3530 u16 san_mac_data, san_mac_offset; 3531 u8 i; 3532 3533 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3534 3535 /* Look for SAN mac address pointer. If not defined, return */ 3536 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3537 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3538 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3539 3540 /* Make sure we know which port we need to write */ 3541 hw->mac.ops.set_lan_id(hw); 3542 /* Apply the port offset to the address offset */ 3543 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3544 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3545 3546 for (i = 0; i < 3; i++) { 3547 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3548 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3549 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3550 san_mac_offset++; 3551 } 3552 3553 return IXGBE_SUCCESS; 3554 } 3555 3556 /** 3557 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3558 * @hw: pointer to hardware structure 3559 * 3560 * Read PCIe configuration space, and get the MSI-X vector count from 3561 * the capabilities table. 3562 **/ 3563 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3564 { 3565 u16 msix_count = 1; 3566 u16 max_msix_count; 3567 u16 pcie_offset; 3568 3569 switch (hw->mac.type) { 3570 case ixgbe_mac_82598EB: 3571 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3572 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3573 break; 3574 case ixgbe_mac_82599EB: 3575 case ixgbe_mac_X540: 3576 case ixgbe_mac_X550: 3577 case ixgbe_mac_X550EM_x: 3578 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3579 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3580 break; 3581 default: 3582 return msix_count; 3583 } 3584 3585 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3586 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3587 if (IXGBE_REMOVED(hw->hw_addr)) 3588 msix_count = 0; 3589 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3590 3591 /* MSI-X count is zero-based in HW */ 3592 msix_count++; 3593 3594 if (msix_count > max_msix_count) 3595 msix_count = max_msix_count; 3596 3597 return msix_count; 3598 } 3599 3600 /** 3601 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3602 * @hw: pointer to hardware structure 3603 * @addr: Address to put into receive address register 3604 * @vmdq: VMDq pool to assign 3605 * 3606 * Puts an ethernet address into a receive address register, or 3607 * finds the rar that it is aleady in; adds to the pool list 3608 **/ 3609 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3610 { 3611 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3612 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3613 u32 rar; 3614 u32 rar_low, rar_high; 3615 u32 addr_low, addr_high; 3616 3617 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3618 3619 /* swap bytes for HW little endian */ 3620 addr_low = addr[0] | (addr[1] << 8) 3621 | (addr[2] << 16) 3622 | (addr[3] << 24); 3623 addr_high = addr[4] | (addr[5] << 8); 3624 3625 /* 3626 * Either find the mac_id in rar or find the first empty space. 3627 * rar_highwater points to just after the highest currently used 3628 * rar in order to shorten the search. It grows when we add a new 3629 * rar to the top. 3630 */ 3631 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3632 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3633 3634 if (((IXGBE_RAH_AV & rar_high) == 0) 3635 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3636 first_empty_rar = rar; 3637 } else if ((rar_high & 0xFFFF) == addr_high) { 3638 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3639 if (rar_low == addr_low) 3640 break; /* found it already in the rars */ 3641 } 3642 } 3643 3644 if (rar < hw->mac.rar_highwater) { 3645 /* already there so just add to the pool bits */ 3646 ixgbe_set_vmdq(hw, rar, vmdq); 3647 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3648 /* stick it into first empty RAR slot we found */ 3649 rar = first_empty_rar; 3650 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3651 } else if (rar == hw->mac.rar_highwater) { 3652 /* add it to the top of the list and inc the highwater mark */ 3653 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3654 hw->mac.rar_highwater++; 3655 } else if (rar >= hw->mac.num_rar_entries) { 3656 return IXGBE_ERR_INVALID_MAC_ADDR; 3657 } 3658 3659 /* 3660 * If we found rar[0], make sure the default pool bit (we use pool 0) 3661 * remains cleared to be sure default pool packets will get delivered 3662 */ 3663 if (rar == 0) 3664 ixgbe_clear_vmdq(hw, rar, 0); 3665 3666 return rar; 3667 } 3668 3669 /** 3670 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3671 * @hw: pointer to hardware struct 3672 * @rar: receive address register index to disassociate 3673 * @vmdq: VMDq pool index to remove from the rar 3674 **/ 3675 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3676 { 3677 u32 mpsar_lo, mpsar_hi; 3678 u32 rar_entries = hw->mac.num_rar_entries; 3679 3680 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3681 3682 /* Make sure we are using a valid rar index range */ 3683 if (rar >= rar_entries) { 3684 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3685 "RAR index %d is out of range.\n", rar); 3686 return IXGBE_ERR_INVALID_ARGUMENT; 3687 } 3688 3689 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3690 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3691 3692 if (IXGBE_REMOVED(hw->hw_addr)) 3693 goto done; 3694 3695 if (!mpsar_lo && !mpsar_hi) 3696 goto done; 3697 3698 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3699 if (mpsar_lo) { 3700 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3701 mpsar_lo = 0; 3702 } 3703 if (mpsar_hi) { 3704 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3705 mpsar_hi = 0; 3706 } 3707 } else if (vmdq < 32) { 3708 mpsar_lo &= ~(1 << vmdq); 3709 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3710 } else { 3711 mpsar_hi &= ~(1 << (vmdq - 32)); 3712 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3713 } 3714 3715 /* was that the last pool using this rar? */ 3716 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 3717 hw->mac.ops.clear_rar(hw, rar); 3718 done: 3719 return IXGBE_SUCCESS; 3720 } 3721 3722 /** 3723 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3724 * @hw: pointer to hardware struct 3725 * @rar: receive address register index to associate with a VMDq index 3726 * @vmdq: VMDq pool index 3727 **/ 3728 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3729 { 3730 u32 mpsar; 3731 u32 rar_entries = hw->mac.num_rar_entries; 3732 3733 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3734 3735 /* Make sure we are using a valid rar index range */ 3736 if (rar >= rar_entries) { 3737 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3738 "RAR index %d is out of range.\n", rar); 3739 return IXGBE_ERR_INVALID_ARGUMENT; 3740 } 3741 3742 if (vmdq < 32) { 3743 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3744 mpsar |= 1 << vmdq; 3745 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3746 } else { 3747 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3748 mpsar |= 1 << (vmdq - 32); 3749 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3750 } 3751 return IXGBE_SUCCESS; 3752 } 3753 3754 /** 3755 * This function should only be involved in the IOV mode. 3756 * In IOV mode, Default pool is next pool after the number of 3757 * VFs advertized and not 0. 3758 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3759 * 3760 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3761 * @hw: pointer to hardware struct 3762 * @vmdq: VMDq pool index 3763 **/ 3764 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3765 { 3766 u32 rar = hw->mac.san_mac_rar_index; 3767 3768 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3769 3770 if (vmdq < 32) { 3771 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3772 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3773 } else { 3774 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3775 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3776 } 3777 3778 return IXGBE_SUCCESS; 3779 } 3780 3781 /** 3782 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3783 * @hw: pointer to hardware structure 3784 **/ 3785 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3786 { 3787 int i; 3788 3789 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3790 DEBUGOUT(" Clearing UTA\n"); 3791 3792 for (i = 0; i < 128; i++) 3793 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3794 3795 return IXGBE_SUCCESS; 3796 } 3797 3798 /** 3799 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3800 * @hw: pointer to hardware structure 3801 * @vlan: VLAN id to write to VLAN filter 3802 * 3803 * return the VLVF index where this VLAN id should be placed 3804 * 3805 **/ 3806 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 3807 { 3808 u32 bits = 0; 3809 u32 first_empty_slot = 0; 3810 s32 regindex; 3811 3812 /* short cut the special case */ 3813 if (vlan == 0) 3814 return 0; 3815 3816 /* 3817 * Search for the vlan id in the VLVF entries. Save off the first empty 3818 * slot found along the way 3819 */ 3820 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 3821 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3822 if (!bits && !(first_empty_slot)) 3823 first_empty_slot = regindex; 3824 else if ((bits & 0x0FFF) == vlan) 3825 break; 3826 } 3827 3828 /* 3829 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 3830 * in the VLVF. Else use the first empty VLVF register for this 3831 * vlan id. 3832 */ 3833 if (regindex >= IXGBE_VLVF_ENTRIES) { 3834 if (first_empty_slot) 3835 regindex = first_empty_slot; 3836 else { 3837 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 3838 "No space in VLVF.\n"); 3839 regindex = IXGBE_ERR_NO_SPACE; 3840 } 3841 } 3842 3843 return regindex; 3844 } 3845 3846 /** 3847 * ixgbe_set_vfta_generic - Set VLAN filter table 3848 * @hw: pointer to hardware structure 3849 * @vlan: VLAN id to write to VLAN filter 3850 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3851 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3852 * 3853 * Turn on/off specified VLAN in the VLAN filter table. 3854 **/ 3855 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3856 bool vlan_on) 3857 { 3858 s32 regindex; 3859 u32 bitindex; 3860 u32 vfta; 3861 u32 targetbit; 3862 s32 ret_val = IXGBE_SUCCESS; 3863 bool vfta_changed = FALSE; 3864 3865 DEBUGFUNC("ixgbe_set_vfta_generic"); 3866 3867 if (vlan > 4095) 3868 return IXGBE_ERR_PARAM; 3869 3870 /* 3871 * this is a 2 part operation - first the VFTA, then the 3872 * VLVF and VLVFB if VT Mode is set 3873 * We don't write the VFTA until we know the VLVF part succeeded. 3874 */ 3875 3876 /* Part 1 3877 * The VFTA is a bitstring made up of 128 32-bit registers 3878 * that enable the particular VLAN id, much like the MTA: 3879 * bits[11-5]: which register 3880 * bits[4-0]: which bit in the register 3881 */ 3882 regindex = (vlan >> 5) & 0x7F; 3883 bitindex = vlan & 0x1F; 3884 targetbit = (1 << bitindex); 3885 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 3886 3887 if (vlan_on) { 3888 if (!(vfta & targetbit)) { 3889 vfta |= targetbit; 3890 vfta_changed = TRUE; 3891 } 3892 } else { 3893 if ((vfta & targetbit)) { 3894 vfta &= ~targetbit; 3895 vfta_changed = TRUE; 3896 } 3897 } 3898 3899 /* Part 2 3900 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 3901 */ 3902 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, 3903 &vfta_changed); 3904 if (ret_val != IXGBE_SUCCESS) 3905 return ret_val; 3906 3907 if (vfta_changed) 3908 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); 3909 3910 return IXGBE_SUCCESS; 3911 } 3912 3913 /** 3914 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 3915 * @hw: pointer to hardware structure 3916 * @vlan: VLAN id to write to VLAN filter 3917 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3918 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3919 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 3920 * should be changed 3921 * 3922 * Turn on/off specified bit in VLVF table. 3923 **/ 3924 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3925 bool vlan_on, bool *vfta_changed) 3926 { 3927 u32 vt; 3928 3929 DEBUGFUNC("ixgbe_set_vlvf_generic"); 3930 3931 if (vlan > 4095) 3932 return IXGBE_ERR_PARAM; 3933 3934 /* If VT Mode is set 3935 * Either vlan_on 3936 * make sure the vlan is in VLVF 3937 * set the vind bit in the matching VLVFB 3938 * Or !vlan_on 3939 * clear the pool bit and possibly the vind 3940 */ 3941 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3942 if (vt & IXGBE_VT_CTL_VT_ENABLE) { 3943 s32 vlvf_index; 3944 u32 bits; 3945 3946 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); 3947 if (vlvf_index < 0) 3948 return vlvf_index; 3949 3950 if (vlan_on) { 3951 /* set the pool bit */ 3952 if (vind < 32) { 3953 bits = IXGBE_READ_REG(hw, 3954 IXGBE_VLVFB(vlvf_index * 2)); 3955 bits |= (1 << vind); 3956 IXGBE_WRITE_REG(hw, 3957 IXGBE_VLVFB(vlvf_index * 2), 3958 bits); 3959 } else { 3960 bits = IXGBE_READ_REG(hw, 3961 IXGBE_VLVFB((vlvf_index * 2) + 1)); 3962 bits |= (1 << (vind - 32)); 3963 IXGBE_WRITE_REG(hw, 3964 IXGBE_VLVFB((vlvf_index * 2) + 1), 3965 bits); 3966 } 3967 } else { 3968 /* clear the pool bit */ 3969 if (vind < 32) { 3970 bits = IXGBE_READ_REG(hw, 3971 IXGBE_VLVFB(vlvf_index * 2)); 3972 bits &= ~(1 << vind); 3973 IXGBE_WRITE_REG(hw, 3974 IXGBE_VLVFB(vlvf_index * 2), 3975 bits); 3976 bits |= IXGBE_READ_REG(hw, 3977 IXGBE_VLVFB((vlvf_index * 2) + 1)); 3978 } else { 3979 bits = IXGBE_READ_REG(hw, 3980 IXGBE_VLVFB((vlvf_index * 2) + 1)); 3981 bits &= ~(1 << (vind - 32)); 3982 IXGBE_WRITE_REG(hw, 3983 IXGBE_VLVFB((vlvf_index * 2) + 1), 3984 bits); 3985 bits |= IXGBE_READ_REG(hw, 3986 IXGBE_VLVFB(vlvf_index * 2)); 3987 } 3988 } 3989 3990 /* 3991 * If there are still bits set in the VLVFB registers 3992 * for the VLAN ID indicated we need to see if the 3993 * caller is requesting that we clear the VFTA entry bit. 3994 * If the caller has requested that we clear the VFTA 3995 * entry bit but there are still pools/VFs using this VLAN 3996 * ID entry then ignore the request. We're not worried 3997 * about the case where we're turning the VFTA VLAN ID 3998 * entry bit on, only when requested to turn it off as 3999 * there may be multiple pools and/or VFs using the 4000 * VLAN ID entry. In that case we cannot clear the 4001 * VFTA bit until all pools/VFs using that VLAN ID have also 4002 * been cleared. This will be indicated by "bits" being 4003 * zero. 4004 */ 4005 if (bits) { 4006 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 4007 (IXGBE_VLVF_VIEN | vlan)); 4008 if ((!vlan_on) && (vfta_changed != NULL)) { 4009 /* someone wants to clear the vfta entry 4010 * but some pools/VFs are still using it. 4011 * Ignore it. */ 4012 *vfta_changed = FALSE; 4013 } 4014 } else 4015 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4016 } 4017 4018 return IXGBE_SUCCESS; 4019 } 4020 4021 /** 4022 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4023 * @hw: pointer to hardware structure 4024 * 4025 * Clears the VLAN filer table, and the VMDq index associated with the filter 4026 **/ 4027 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4028 { 4029 u32 offset; 4030 4031 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4032 4033 for (offset = 0; offset < hw->mac.vft_size; offset++) 4034 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4035 4036 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4037 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4038 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4039 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); 4040 } 4041 4042 return IXGBE_SUCCESS; 4043 } 4044 4045 /** 4046 * ixgbe_check_mac_link_generic - Determine link and speed status 4047 * @hw: pointer to hardware structure 4048 * @speed: pointer to link speed 4049 * @link_up: TRUE when link is up 4050 * @link_up_wait_to_complete: bool used to wait for link up or not 4051 * 4052 * Reads the links register to determine if link is up and the current speed 4053 **/ 4054 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4055 bool *link_up, bool link_up_wait_to_complete) 4056 { 4057 u32 links_reg, links_orig; 4058 u32 i; 4059 4060 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4061 4062 /* clear the old state */ 4063 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4064 4065 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4066 4067 if (links_orig != links_reg) { 4068 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4069 links_orig, links_reg); 4070 } 4071 4072 if (link_up_wait_to_complete) { 4073 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 4074 if (links_reg & IXGBE_LINKS_UP) { 4075 *link_up = TRUE; 4076 break; 4077 } else { 4078 *link_up = FALSE; 4079 } 4080 msec_delay(100); 4081 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4082 } 4083 } else { 4084 if (links_reg & IXGBE_LINKS_UP) 4085 *link_up = TRUE; 4086 else 4087 *link_up = FALSE; 4088 } 4089 4090 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4091 case IXGBE_LINKS_SPEED_10G_82599: 4092 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4093 if (hw->mac.type >= ixgbe_mac_X550) { 4094 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4095 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4096 } 4097 break; 4098 case IXGBE_LINKS_SPEED_1G_82599: 4099 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4100 break; 4101 case IXGBE_LINKS_SPEED_100_82599: 4102 *speed = IXGBE_LINK_SPEED_100_FULL; 4103 if (hw->mac.type >= ixgbe_mac_X550) { 4104 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4105 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4106 } 4107 break; 4108 default: 4109 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4110 } 4111 4112 return IXGBE_SUCCESS; 4113 } 4114 4115 /** 4116 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4117 * the EEPROM 4118 * @hw: pointer to hardware structure 4119 * @wwnn_prefix: the alternative WWNN prefix 4120 * @wwpn_prefix: the alternative WWPN prefix 4121 * 4122 * This function will read the EEPROM from the alternative SAN MAC address 4123 * block to check the support for the alternative WWNN/WWPN prefix support. 4124 **/ 4125 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4126 u16 *wwpn_prefix) 4127 { 4128 u16 offset, caps; 4129 u16 alt_san_mac_blk_offset; 4130 4131 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4132 4133 /* clear output first */ 4134 *wwnn_prefix = 0xFFFF; 4135 *wwpn_prefix = 0xFFFF; 4136 4137 /* check if alternative SAN MAC is supported */ 4138 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4139 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4140 goto wwn_prefix_err; 4141 4142 if ((alt_san_mac_blk_offset == 0) || 4143 (alt_san_mac_blk_offset == 0xFFFF)) 4144 goto wwn_prefix_out; 4145 4146 /* check capability in alternative san mac address block */ 4147 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4148 if (hw->eeprom.ops.read(hw, offset, &caps)) 4149 goto wwn_prefix_err; 4150 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4151 goto wwn_prefix_out; 4152 4153 /* get the corresponding prefix for WWNN/WWPN */ 4154 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4155 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4156 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4157 "eeprom read at offset %d failed", offset); 4158 } 4159 4160 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4161 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4162 goto wwn_prefix_err; 4163 4164 wwn_prefix_out: 4165 return IXGBE_SUCCESS; 4166 4167 wwn_prefix_err: 4168 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4169 "eeprom read at offset %d failed", offset); 4170 return IXGBE_SUCCESS; 4171 } 4172 4173 /** 4174 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4175 * @hw: pointer to hardware structure 4176 * @bs: the fcoe boot status 4177 * 4178 * This function will read the FCOE boot status from the iSCSI FCOE block 4179 **/ 4180 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4181 { 4182 u16 offset, caps, flags; 4183 s32 status; 4184 4185 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4186 4187 /* clear output first */ 4188 *bs = ixgbe_fcoe_bootstatus_unavailable; 4189 4190 /* check if FCOE IBA block is present */ 4191 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4192 status = hw->eeprom.ops.read(hw, offset, &caps); 4193 if (status != IXGBE_SUCCESS) 4194 goto out; 4195 4196 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4197 goto out; 4198 4199 /* check if iSCSI FCOE block is populated */ 4200 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4201 if (status != IXGBE_SUCCESS) 4202 goto out; 4203 4204 if ((offset == 0) || (offset == 0xFFFF)) 4205 goto out; 4206 4207 /* read fcoe flags in iSCSI FCOE block */ 4208 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4209 status = hw->eeprom.ops.read(hw, offset, &flags); 4210 if (status != IXGBE_SUCCESS) 4211 goto out; 4212 4213 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4214 *bs = ixgbe_fcoe_bootstatus_enabled; 4215 else 4216 *bs = ixgbe_fcoe_bootstatus_disabled; 4217 4218 out: 4219 return status; 4220 } 4221 4222 /** 4223 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4224 * @hw: pointer to hardware structure 4225 * @enable: enable or disable switch for anti-spoofing 4226 * @pf: Physical Function pool - do not enable anti-spoofing for the PF 4227 * 4228 **/ 4229 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) 4230 { 4231 int j; 4232 int pf_target_reg = pf >> 3; 4233 int pf_target_shift = pf % 8; 4234 u32 pfvfspoof = 0; 4235 4236 if (hw->mac.type == ixgbe_mac_82598EB) 4237 return; 4238 4239 if (enable) 4240 pfvfspoof = IXGBE_SPOOF_MACAS_MASK; 4241 4242 /* 4243 * PFVFSPOOF register array is size 8 with 8 bits assigned to 4244 * MAC anti-spoof enables in each register array element. 4245 */ 4246 for (j = 0; j < pf_target_reg; j++) 4247 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 4248 4249 /* 4250 * The PF should be allowed to spoof so that it can support 4251 * emulation mode NICs. Do not set the bits assigned to the PF 4252 */ 4253 pfvfspoof &= (1 << pf_target_shift) - 1; 4254 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 4255 4256 /* 4257 * Remaining pools belong to the PF so they do not need to have 4258 * anti-spoofing enabled. 4259 */ 4260 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++) 4261 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0); 4262 } 4263 4264 /** 4265 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4266 * @hw: pointer to hardware structure 4267 * @enable: enable or disable switch for VLAN anti-spoofing 4268 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4269 * 4270 **/ 4271 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4272 { 4273 int vf_target_reg = vf >> 3; 4274 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4275 u32 pfvfspoof; 4276 4277 if (hw->mac.type == ixgbe_mac_82598EB) 4278 return; 4279 4280 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4281 if (enable) 4282 pfvfspoof |= (1 << vf_target_shift); 4283 else 4284 pfvfspoof &= ~(1 << vf_target_shift); 4285 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4286 } 4287 4288 /** 4289 * ixgbe_get_device_caps_generic - Get additional device capabilities 4290 * @hw: pointer to hardware structure 4291 * @device_caps: the EEPROM word with the extra device capabilities 4292 * 4293 * This function will read the EEPROM location for the device capabilities, 4294 * and return the word through device_caps. 4295 **/ 4296 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4297 { 4298 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4299 4300 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4301 4302 return IXGBE_SUCCESS; 4303 } 4304 4305 /** 4306 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4307 * @hw: pointer to hardware structure 4308 * 4309 **/ 4310 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4311 { 4312 u32 regval; 4313 u32 i; 4314 4315 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4316 4317 /* Enable relaxed ordering */ 4318 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4319 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4320 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4321 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4322 } 4323 4324 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4325 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4326 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4327 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4328 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4329 } 4330 4331 } 4332 4333 /** 4334 * ixgbe_calculate_checksum - Calculate checksum for buffer 4335 * @buffer: pointer to EEPROM 4336 * @length: size of EEPROM to calculate a checksum for 4337 * Calculates the checksum for some buffer on a specified length. The 4338 * checksum calculated is returned. 4339 **/ 4340 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4341 { 4342 u32 i; 4343 u8 sum = 0; 4344 4345 DEBUGFUNC("ixgbe_calculate_checksum"); 4346 4347 if (!buffer) 4348 return 0; 4349 4350 for (i = 0; i < length; i++) 4351 sum += buffer[i]; 4352 4353 return (u8) (0 - sum); 4354 } 4355 4356 /** 4357 * ixgbe_host_interface_command - Issue command to manageability block 4358 * @hw: pointer to the HW structure 4359 * @buffer: contains the command to write and where the return status will 4360 * be placed 4361 * @length: length of buffer, must be multiple of 4 bytes 4362 * @timeout: time in ms to wait for command completion 4363 * @return_data: read and return data from the buffer (TRUE) or not (FALSE) 4364 * Needed because FW structures are big endian and decoding of 4365 * these fields can be 8 bit or 16 bit based on command. Decoding 4366 * is not easily understood without making a table of commands. 4367 * So we will leave this up to the caller to read back the data 4368 * in these cases. 4369 * 4370 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4371 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 4372 **/ 4373 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4374 u32 length, u32 timeout, bool return_data) 4375 { 4376 u32 hicr, i, bi, fwsts; 4377 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4378 u16 buf_len; 4379 u16 dword_len; 4380 4381 DEBUGFUNC("ixgbe_host_interface_command"); 4382 4383 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4384 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4385 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4386 } 4387 /* Set bit 9 of FWSTS clearing FW reset indication */ 4388 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4389 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4390 4391 /* Check that the host interface is enabled. */ 4392 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4393 if ((hicr & IXGBE_HICR_EN) == 0) { 4394 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4395 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4396 } 4397 4398 /* Calculate length in DWORDs. We must be DWORD aligned */ 4399 if ((length % (sizeof(u32))) != 0) { 4400 DEBUGOUT("Buffer length failure, not aligned to dword"); 4401 return IXGBE_ERR_INVALID_ARGUMENT; 4402 } 4403 4404 dword_len = length >> 2; 4405 4406 /* The device driver writes the relevant command block 4407 * into the ram area. 4408 */ 4409 for (i = 0; i < dword_len; i++) 4410 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4411 i, IXGBE_CPU_TO_LE32(buffer[i])); 4412 4413 /* Setting this bit tells the ARC that a new command is pending. */ 4414 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4415 4416 for (i = 0; i < timeout; i++) { 4417 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4418 if (!(hicr & IXGBE_HICR_C)) 4419 break; 4420 msec_delay(1); 4421 } 4422 4423 /* Check command completion */ 4424 if ((timeout != 0 && i == timeout) || 4425 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4426 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4427 "Command has failed with no status valid.\n"); 4428 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4429 } 4430 4431 if (!return_data) 4432 return 0; 4433 4434 /* Calculate length in DWORDs */ 4435 dword_len = hdr_size >> 2; 4436 4437 /* first pull in the header so we know the buffer length */ 4438 for (bi = 0; bi < dword_len; bi++) { 4439 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4440 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4441 } 4442 4443 /* If there is any thing in data position pull it in */ 4444 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; 4445 if (buf_len == 0) 4446 return 0; 4447 4448 if (length < buf_len + hdr_size) { 4449 DEBUGOUT("Buffer not large enough for reply message.\n"); 4450 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4451 } 4452 4453 /* Calculate length in DWORDs, add 3 for odd lengths */ 4454 dword_len = (buf_len + 3) >> 2; 4455 4456 /* Pull in the rest of the buffer (bi is where we left off) */ 4457 for (; bi <= dword_len; bi++) { 4458 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4459 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4460 } 4461 4462 return 0; 4463 } 4464 4465 /** 4466 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4467 * @hw: pointer to the HW structure 4468 * @maj: driver version major number 4469 * @minr: driver version minor number 4470 * @build: driver version build number 4471 * @sub: driver version sub build number 4472 * 4473 * Sends driver version number to firmware through the manageability 4474 * block. On success return IXGBE_SUCCESS 4475 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4476 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4477 **/ 4478 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 minr, 4479 u8 build, u8 sub) 4480 { 4481 struct ixgbe_hic_drv_info fw_cmd; 4482 int i; 4483 s32 ret_val = IXGBE_SUCCESS; 4484 4485 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4486 4487 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) 4488 != IXGBE_SUCCESS) { 4489 ret_val = IXGBE_ERR_SWFW_SYNC; 4490 goto out; 4491 } 4492 4493 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4494 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4495 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4496 fw_cmd.port_num = (u8)hw->bus.func; 4497 fw_cmd.ver_maj = maj; 4498 fw_cmd.ver_min = minr; 4499 fw_cmd.ver_build = build; 4500 fw_cmd.ver_sub = sub; 4501 fw_cmd.hdr.checksum = 0; 4502 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4503 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4504 fw_cmd.pad = 0; 4505 fw_cmd.pad2 = 0; 4506 4507 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4508 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4509 sizeof(fw_cmd), 4510 IXGBE_HI_COMMAND_TIMEOUT, 4511 TRUE); 4512 if (ret_val != IXGBE_SUCCESS) 4513 continue; 4514 4515 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4516 FW_CEM_RESP_STATUS_SUCCESS) 4517 ret_val = IXGBE_SUCCESS; 4518 else 4519 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4520 4521 break; 4522 } 4523 4524 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4525 out: 4526 return ret_val; 4527 } 4528 4529 /** 4530 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4531 * @hw: pointer to hardware structure 4532 * @num_pb: number of packet buffers to allocate 4533 * @headroom: reserve n KB of headroom 4534 * @strategy: packet buffer allocation strategy 4535 **/ 4536 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4537 int strategy) 4538 { 4539 u32 pbsize = hw->mac.rx_pb_size; 4540 int i = 0; 4541 u32 rxpktsize, txpktsize, txpbthresh; 4542 4543 /* Reserve headroom */ 4544 pbsize -= headroom; 4545 4546 if (!num_pb) 4547 num_pb = 1; 4548 4549 /* Divide remaining packet buffer space amongst the number of packet 4550 * buffers requested using supplied strategy. 4551 */ 4552 switch (strategy) { 4553 case PBA_STRATEGY_WEIGHTED: 4554 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4555 * buffer with 5/8 of the packet buffer space. 4556 */ 4557 rxpktsize = (pbsize * 5) / (num_pb * 4); 4558 pbsize -= rxpktsize * (num_pb / 2); 4559 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4560 for (; i < (num_pb / 2); i++) 4561 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4562 /* Fall through to configure remaining packet buffers */ 4563 case PBA_STRATEGY_EQUAL: 4564 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4565 for (; i < num_pb; i++) 4566 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4567 break; 4568 default: 4569 break; 4570 } 4571 4572 /* Only support an equally distributed Tx packet buffer strategy. */ 4573 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4574 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4575 for (i = 0; i < num_pb; i++) { 4576 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4577 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4578 } 4579 4580 /* Clear unused TCs, if any, to zero buffer size*/ 4581 for (; i < IXGBE_MAX_PB; i++) { 4582 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4583 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4584 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4585 } 4586 } 4587 4588 /** 4589 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4590 * @hw: pointer to the hardware structure 4591 * 4592 * The 82599 and x540 MACs can experience issues if TX work is still pending 4593 * when a reset occurs. This function prevents this by flushing the PCIe 4594 * buffers on the system. 4595 **/ 4596 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4597 { 4598 u32 gcr_ext, hlreg0, i, poll; 4599 u16 value; 4600 4601 /* 4602 * If double reset is not requested then all transactions should 4603 * already be clear and as such there is no work to do 4604 */ 4605 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4606 return; 4607 4608 /* 4609 * Set loopback enable to prevent any transmits from being sent 4610 * should the link come up. This assumes that the RXCTRL.RXEN bit 4611 * has already been cleared. 4612 */ 4613 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4614 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4615 4616 /* Wait for a last completion before clearing buffers */ 4617 IXGBE_WRITE_FLUSH(hw); 4618 msec_delay(3); 4619 4620 /* 4621 * Before proceeding, make sure that the PCIe block does not have 4622 * transactions pending. 4623 */ 4624 poll = ixgbe_pcie_timeout_poll(hw); 4625 for (i = 0; i < poll; i++) { 4626 usec_delay(100); 4627 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4628 if (IXGBE_REMOVED(hw->hw_addr)) 4629 goto out; 4630 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4631 goto out; 4632 } 4633 4634 out: 4635 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4636 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4637 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4638 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4639 4640 /* Flush all writes and allow 20usec for all transactions to clear */ 4641 IXGBE_WRITE_FLUSH(hw); 4642 usec_delay(20); 4643 4644 /* restore previous register values */ 4645 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4646 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4647 } 4648 4649 4650 /** 4651 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 4652 * @hw: pointer to hardware structure 4653 * @map: pointer to u8 arr for returning map 4654 * 4655 * Read the rtrup2tc HW register and resolve its content into map 4656 **/ 4657 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 4658 { 4659 u32 reg, i; 4660 4661 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 4662 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 4663 map[i] = IXGBE_RTRUP2TC_UP_MASK & 4664 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 4665 return; 4666 } 4667 4668 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 4669 { 4670 u32 pfdtxgswc; 4671 u32 rxctrl; 4672 4673 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4674 if (rxctrl & IXGBE_RXCTRL_RXEN) { 4675 if (hw->mac.type != ixgbe_mac_82598EB) { 4676 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4677 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 4678 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 4679 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4680 hw->mac.set_lben = TRUE; 4681 } else { 4682 hw->mac.set_lben = FALSE; 4683 } 4684 } 4685 rxctrl &= ~IXGBE_RXCTRL_RXEN; 4686 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 4687 } 4688 } 4689 4690 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 4691 { 4692 u32 pfdtxgswc; 4693 u32 rxctrl; 4694 4695 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4696 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 4697 4698 if (hw->mac.type != ixgbe_mac_82598EB) { 4699 if (hw->mac.set_lben) { 4700 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4701 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 4702 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4703 hw->mac.set_lben = FALSE; 4704 } 4705 } 4706 } 4707 4708 /** 4709 * ixgbe_mng_present - returns TRUE when management capability is present 4710 * @hw: pointer to hardware structure 4711 */ 4712 bool ixgbe_mng_present(struct ixgbe_hw *hw) 4713 { 4714 u32 fwsm; 4715 4716 if (hw->mac.type < ixgbe_mac_82599EB) 4717 return FALSE; 4718 4719 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 4720 fwsm &= IXGBE_FWSM_MODE_MASK; 4721 return fwsm == IXGBE_FWSM_FW_MODE_PT; 4722 } 4723 4724 /** 4725 * ixgbe_mng_enabled - Is the manageability engine enabled? 4726 * @hw: pointer to hardware structure 4727 * 4728 * Returns TRUE if the manageability engine is enabled. 4729 **/ 4730 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 4731 { 4732 u32 fwsm, manc, factps; 4733 4734 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 4735 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 4736 return FALSE; 4737 4738 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 4739 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 4740 return FALSE; 4741 4742 if (hw->mac.type <= ixgbe_mac_X540) { 4743 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS); 4744 if (factps & IXGBE_FACTPS_MNGCG) 4745 return FALSE; 4746 } 4747 4748 return TRUE; 4749 } 4750 4751 /** 4752 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 4753 * @hw: pointer to hardware structure 4754 * @speed: new link speed 4755 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 4756 * 4757 * Set the link speed in the MAC and/or PHY register and restarts link. 4758 **/ 4759 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 4760 ixgbe_link_speed speed, 4761 bool autoneg_wait_to_complete) 4762 { 4763 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4764 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4765 s32 status = IXGBE_SUCCESS; 4766 u32 speedcnt = 0; 4767 u32 i = 0; 4768 bool autoneg, link_up = FALSE; 4769 4770 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 4771 4772 /* Mask off requested but non-supported speeds */ 4773 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 4774 if (status != IXGBE_SUCCESS) 4775 return status; 4776 4777 speed &= link_speed; 4778 4779 /* Try each speed one by one, highest priority first. We do this in 4780 * software because 10Gb fiber doesn't support speed autonegotiation. 4781 */ 4782 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 4783 speedcnt++; 4784 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 4785 4786 /* If we already have link at this speed, just jump out */ 4787 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 4788 if (status != IXGBE_SUCCESS) 4789 return status; 4790 4791 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 4792 goto out; 4793 4794 /* Set the module link speed */ 4795 switch (hw->phy.media_type) { 4796 case ixgbe_media_type_fiber_fixed: 4797 case ixgbe_media_type_fiber: 4798 ixgbe_set_rate_select_speed(hw, 4799 IXGBE_LINK_SPEED_10GB_FULL); 4800 break; 4801 case ixgbe_media_type_fiber_qsfp: 4802 /* QSFP module automatically detects MAC link speed */ 4803 break; 4804 default: 4805 DEBUGOUT("Unexpected media type.\n"); 4806 break; 4807 } 4808 4809 /* Allow module to change analog characteristics (1G->10G) */ 4810 msec_delay(40); 4811 4812 status = ixgbe_setup_mac_link(hw, 4813 IXGBE_LINK_SPEED_10GB_FULL, 4814 autoneg_wait_to_complete); 4815 if (status != IXGBE_SUCCESS) 4816 return status; 4817 4818 /* Flap the Tx laser if it has not already been done */ 4819 ixgbe_flap_tx_laser(hw); 4820 4821 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 4822 * Section 73.10.2, we may have to wait up to 500ms if KR is 4823 * attempted. 82599 uses the same timing for 10g SFI. 4824 */ 4825 for (i = 0; i < 5; i++) { 4826 /* Wait for the link partner to also set speed */ 4827 msec_delay(100); 4828 4829 /* If we have link, just jump out */ 4830 status = ixgbe_check_link(hw, &link_speed, 4831 &link_up, FALSE); 4832 if (status != IXGBE_SUCCESS) 4833 return status; 4834 4835 if (link_up) 4836 goto out; 4837 } 4838 } 4839 4840 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 4841 speedcnt++; 4842 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 4843 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 4844 4845 /* If we already have link at this speed, just jump out */ 4846 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 4847 if (status != IXGBE_SUCCESS) 4848 return status; 4849 4850 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 4851 goto out; 4852 4853 /* Set the module link speed */ 4854 switch (hw->phy.media_type) { 4855 case ixgbe_media_type_fiber_fixed: 4856 case ixgbe_media_type_fiber: 4857 ixgbe_set_rate_select_speed(hw, 4858 IXGBE_LINK_SPEED_1GB_FULL); 4859 break; 4860 case ixgbe_media_type_fiber_qsfp: 4861 /* QSFP module automatically detects link speed */ 4862 break; 4863 default: 4864 DEBUGOUT("Unexpected media type.\n"); 4865 break; 4866 } 4867 4868 /* Allow module to change analog characteristics (10G->1G) */ 4869 msec_delay(40); 4870 4871 status = ixgbe_setup_mac_link(hw, 4872 IXGBE_LINK_SPEED_1GB_FULL, 4873 autoneg_wait_to_complete); 4874 if (status != IXGBE_SUCCESS) 4875 return status; 4876 4877 /* Flap the Tx laser if it has not already been done */ 4878 ixgbe_flap_tx_laser(hw); 4879 4880 /* Wait for the link partner to also set speed */ 4881 msec_delay(100); 4882 4883 /* If we have link, just jump out */ 4884 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 4885 if (status != IXGBE_SUCCESS) 4886 return status; 4887 4888 if (link_up) 4889 goto out; 4890 } 4891 4892 /* We didn't get link. Configure back to the highest speed we tried, 4893 * (if there was more than one). We call ourselves back with just the 4894 * single highest speed that the user requested. 4895 */ 4896 if (speedcnt > 1) 4897 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 4898 highest_link_speed, 4899 autoneg_wait_to_complete); 4900 4901 out: 4902 /* Set autoneg_advertised value based on input link speed */ 4903 hw->phy.autoneg_advertised = 0; 4904 4905 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 4907 4908 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 4909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 4910 4911 return status; 4912 } 4913 4914 /** 4915 * ixgbe_set_soft_rate_select_speed - Set module link speed 4916 * @hw: pointer to hardware structure 4917 * @speed: link speed to set 4918 * 4919 * Set module link speed via the soft rate select. 4920 */ 4921 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 4922 ixgbe_link_speed speed) 4923 { 4924 s32 status; 4925 u8 rs, eeprom_data; 4926 4927 switch (speed) { 4928 case IXGBE_LINK_SPEED_10GB_FULL: 4929 /* one bit mask same as setting on */ 4930 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 4931 break; 4932 case IXGBE_LINK_SPEED_1GB_FULL: 4933 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 4934 break; 4935 default: 4936 DEBUGOUT("Invalid fixed module speed\n"); 4937 return; 4938 } 4939 4940 /* Set RS0 */ 4941 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4942 IXGBE_I2C_EEPROM_DEV_ADDR2, 4943 &eeprom_data); 4944 if (status) { 4945 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 4946 goto out; 4947 } 4948 4949 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4950 4951 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4952 IXGBE_I2C_EEPROM_DEV_ADDR2, 4953 eeprom_data); 4954 if (status) { 4955 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 4956 goto out; 4957 } 4958 4959 /* Set RS1 */ 4960 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4961 IXGBE_I2C_EEPROM_DEV_ADDR2, 4962 &eeprom_data); 4963 if (status) { 4964 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 4965 goto out; 4966 } 4967 4968 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4969 4970 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4971 IXGBE_I2C_EEPROM_DEV_ADDR2, 4972 eeprom_data); 4973 if (status) { 4974 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 4975 goto out; 4976 } 4977 out: 4978 return; 4979 } 4980
Indexes created Thu Sep 25 16:09:42 GMT 2025